A digital synchronization system

Abstract

This application provides a digital synchronization system that can achieve a single digital synchronization signal, SYSREF, to match the connection establishment status of the JESD204B in automatic mode. When the connection is lost, it continuously sends synchronization signals to synchronize the RF chip with the FPGA or baseband data chip. In manual mode, the occurrence of the SYSREF digital synchronization signal can be selected based on the enable high / low level. Finally, this SYSREF digital synchronization signal is fully phase controllable, allowing for flexible adaptation to different application scenarios. In normal use, it simplifies synchronization between multiple chips and devices, eliminating the need for an additional clock chip to send the digital synchronization signal. Furthermore, the SYSREF digital synchronization signal, custom-generated internally by the RF transceiver chip, resides in the same clock domain as the chip, eliminating the need for additional hardware resources for cross-clock domain synchronization and resulting in better timing performance.

Description

Technical Field

[0001] This application relates to the field of signal synchronization technology, and in particular to a digital synchronization system. Background Technology

[0002] In modern communication systems, radio frequency transceiver chips play a crucial role, responsible for processing and transmitting wireless signals. High-speed data transmission and synchronization are core issues in the design and application of these chips. SerDes technology, or serialization and deserialization technology, is a key means to achieve this goal. By converting parallel data into high-speed serial data, SerDes technology significantly increases the data transmission rate while reducing the physical size of the signal, which is particularly important for space-constrained devices.

[0003] However, high-speed data transmission requires precise clock synchronization to ensure data integrity and accuracy. In the absence of an independent clock chip providing digital synchronization, the SerDes_Tx and SerDes_Rx modules need to output the SYSREF signal to the baseband chip via specific pins. The SYSREF signal is a special synchronization reference signal that provides a common clock reference for the FPGA or baseband data chip in the system. In this way, even at different power-on times, the devices can synchronize via the SYSREF signal, ensuring data transmission consistency and latency consistency.

[0004] This synchronization mechanism is crucial for the link establishment process. Link establishment refers to ensuring that all relevant devices or chips are in a synchronized state before data transmission begins. By using the SYSREF signal, even if devices are powered on at different times, they can be guaranteed to remain synchronized during data transmission, thus avoiding synchronization problems caused by clock skew.

[0005] Therefore, there is an urgent need in this field for a technical solution that can simplify the synchronization between multiple chips and multiple devices without requiring an additional clock chip to send digital synchronization signals. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a digital synchronization system to solve the problem of how to make the synchronization between multiple chips and multiple devices simpler and without the need for an additional clock chip to send digital synchronization signals.

[0007] To achieve the above and other related objectives, a first aspect of this application provides a digital synchronization system, comprising: a transmitter and a receiver; a digital synchronization signal is connected between the transmitter's transmit interface and a system reference pin on the receiver, the digital synchronization signal being used to align frame boundaries and multi-frame boundaries; the transmitter and receiver communicate based on the JESD204B communication protocol; wherein the digital synchronization signal is configured to be turned on and off based on automatic or manual mode; if configured in automatic mode, the transmitter automatically sends a digital synchronization signal to synchronize with the receiver when the link is lost; if configured in manual mode, the transmitter selects whether to send a digital synchronization signal based on the level of a manual enable signal.

[0008] In some embodiments of the first aspect of this application, the digital synchronization signal is controlled via a serial peripheral interface.

[0009] In some embodiments of the first aspect of this application, the system controls automatic mode or manual mode via a 1-bit serial peripheral interface signal; wherein, in automatic mode, the enabling and disabling of the digital synchronization signal is controlled by a synchronization input signal; the synchronization input signal is sent from the receiving end to the transmitting end; in manual mode, the enabling and disabling of the digital synchronization signal is controlled by a manual enable level.

[0010] In some embodiments of the first aspect of this application, in automatic mode, the transmitting end automatically shuts down the digital synchronization signal after recognizing the link establishment identifier.

[0011] In some embodiments of the first aspect of this application, in automatic mode, the transmitting end automatically turns on the digital synchronization signal after recognizing a broken link identifier.

[0012] In some embodiments of the first aspect of this application, the link establishment identifier is a synchronization input signal identifier sent from the receiving end to the transmitting end, and a link establishment is indicated when the synchronization input signal is high.

[0013] In some embodiments of the first aspect of this application, the transmitting end is configured with a counter for recording the duration of a link break, the counter having a reserved upper limit value for counting, the upper limit value for counting being greater than the threshold; the counter stops counting when the number of consecutive low-level beats of the synchronization input signal recorded by the counter reaches the threshold.

[0014] In some embodiments of the first aspect of this application, the transmitting end is configured with a counter for recording the duration of a link break, the counter having a reserved upper limit value for counting, the upper limit value for counting being greater than the threshold; the counter stops counting when the number of consecutive low-level beats of the synchronization input signal recorded by the counter reaches the threshold.

[0015] In some embodiments of the first aspect of this application, in manual mode, if the manual enable signal is detected to be high, the digital synchronization signal is turned on; if the manual enable signal is detected to be low, the digital synchronization signal is turned off.

[0016] In some embodiments of the first aspect of this application, the delay control signal is used to control the phase of the digital synchronization signal; when the JESD204B communication protocol operates in subclass 0 operation mode, the delay control signal is an n-bit signal, and the square wave period of the digital synchronization signal is 2 times the system clock period. n The phase shift is (0 to 2 times) and the phase shift range is (0 to 2 n -1).

[0017] As described above, the digital synchronization system of this application has the following beneficial effects: This application can truly achieve a single digital synchronization signal SYSREF, enabling automatic mode matching of the JESD204B's link establishment status, and continuously emitting synchronization signals to synchronize the RF chip with the FPGA or baseband data chip when the link is lost. In manual mode, the occurrence of the digital synchronization signal SYSREF can be selected based on the enable high / low level. Finally, this digital synchronization signal SYSREF satisfies full phase controllability, allowing for flexible adaptation to different application scenarios. In normal use, it simplifies synchronization between multiple chips and devices, eliminating the need for an additional clock chip to generate the digital synchronization signal. Furthermore, the SYSREF digital synchronization signal, custom-generated internally by the RF transceiver chip, resides in the same clock domain as the chip, eliminating the need for additional hardware resources for cross-clock domain synchronization and resulting in better timing performance. Attached Figure Description

[0018] Figure 1 The diagram shown is a structural schematic of a digital synchronization system according to an embodiment of this application.

[0019] Figure 2 The diagram shown is a timing waveform diagram of the automatic mode operation in one embodiment of this application.

[0020] Figure 3 The diagram shown is a timing waveform in manual mode operation according to an embodiment of this application.

[0021] Figure 4 The diagram shown is a schematic representation of the fully phase-controllable operation in one embodiment of this application.

[0022] Figure 5 The diagram shown is a simplified simulation waveform in automatic mode according to one embodiment of this application.

[0023] Figure 6 The diagram shown is a relatively complex simulation waveform in automatic mode according to one embodiment of this application.

[0024] Figure 7 The diagram shown is a simulation waveform in manual mode according to one embodiment of this application.

[0025] Figure 8 The results shown are simulation results of full phase controllability in one embodiment of this application (phase relationship when sys_pha_ctr = 0).

[0026] Figure 9 The results shown are simulation results of full phase controllability in one embodiment of this application (phase relationship when sys_pha_ctr = 15).

[0027] Figure 10 The results shown are simulation results of full phase controllability in one embodiment of this application (phase relationship when sys_pha_ctr = 31). Detailed Implementation

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0029] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0030] <1> The JESD204B communication protocol is a high-speed serial data converter interface standard developed by the JEDEC committee. It is mainly used for data transmission between ADCs / DACs and logic devices such as FPGAs. It supports data transmission rates up to 12.5Gbps. By simplifying connections and supporting smaller solutions, it ensures system performance and is suitable for high-speed data conversion applications.

[0031] <2> The LMFC (Local Multi-Frame Clock) signal is a clock signal used in the JESD204B standard to synchronize data transmission between high-speed data converters and logic devices. It achieves deterministic delay and multi-chip synchronization by ensuring that data is correctly aligned and decoded at the receiving end.

[0032] <3> A radio frequency (RF) transceiver chip is an integrated circuit used in wireless communication systems to receive and transmit signals. It typically includes a receive link (containing low-noise amplifiers, filters, analog-to-digital converters, etc.) and a transmit link (containing digital-to-analog converters, power amplifiers, filters, etc.), and is capable of processing analog signals at radio frequency (RF) frequencies.

[0033] <4> FPGA, or Field-Programmable Gate Array, is a programmable semiconductor device that allows for the implementation of custom hardware logic without the need for manufacturing dedicated chips. An FPGA contains configurable logic blocks and programmable interconnect resources, allowing developers to configure hardware circuitry as needed.

[0034] <5> PCLK (Peripheral Clock) is the source clock that provides synchronization clock signals for various peripheral devices. The PCLK period refers to one complete cycle of this clock signal, that is, the time interval from one rising edge of the clock to the next rising edge.

[0035] <6> The SYSREF (System Reference) signal is a digital signal used to synchronize multiple components in a system. In some communication protocols (such as JESD204B), the SYSREF signal is used to ensure that data is aligned at deterministic points in time, thereby achieving precise synchronization.

[0036] <7> Link establishment is the process of setting up a data link, where the sending and receiving ends establish a connection for data transmission through some synchronization mechanism. In digital communication or data transmission protocols, link establishment is a prerequisite for ensuring that data can be transmitted correctly and orderly between the sending and receiving ends.

[0037] <8> A broken link is the disconnection of an established data link connection. This can be due to communication errors, physical connection interruptions, or other reasons causing link failure. After the link is broken, a re-establishment process may be required to restore data transmission.

[0038] The technical solutions of this application embodiment can be applied to various application systems, including but not limited to the following:

[0039] a. Wireless communication infrastructure: The combination of radio frequency transceiver chips and FPGA IP cores can be used to implement complex wireless communication systems, such as base stations, which need to handle high-speed data transmission and multi-user access.

[0040] b. Defense Electronic Systems: In the military and defense fields, the combination of radio frequency transceiver chips and FPGAs can be used in electronic warfare, signals intelligence and communications systems, which typically require high-performance signal processing and flexible hardware configuration.

[0041] c. RF Test Equipment and Instruments: In the field of test and measurement, the synchronization of RF transceiver chips and FPGA IP cores can be used to realize high-performance test equipment that can perform accurate signal analysis and generation.

[0042] d. Software-defined radio platform: Combining RF transceiver chips with FPGAs can build flexible software-defined radio (SDR) platforms that can adapt to different communication standards and protocols.

[0043] e. Medical devices: In the medical field, radio frequency transceiver chips can be used in implantable medical devices such as pacemakers and neurostimulators. They are synchronized with FPGA IP cores to realize the design of in vivo communication systems.

[0044] f. Wearable medical systems: Radio frequency transceiver chips are integrated into wearable medical devices for wireless transmission of physiological data, and FPGA IP cores provide necessary signal processing and data transmission control in this process.

[0045] g. 5G communication system: The combination of radio frequency transceiver chip and FPGA IP core can be used to implement MASSIVEMIMO technology in 5G base stations, providing high-speed data transmission and increasing bandwidth.

[0046] h. Satellite communication: The radio frequency transceiver chip is synchronized with the FPGA IP core and can be used in satellite communication systems to realize data transmission between earth stations and satellites.

[0047] i. Low-cost on-chip radar: In on-chip radar applications, the combination of RF transceiver chips and FPGA IP cores can be used to realize low-cost, high-efficiency radar systems, suitable for a variety of monitoring and detection scenarios.

[0048] j. Airborne video wireless transmission: In the field of UAVs, RF transceiver chips synchronized with FPGA IP cores can be used to realize wireless transmission of airborne video and remote control and telemetry, meeting the requirements of small UAVs for data link size, weight, power consumption and low cost.

[0049] The foregoing has described the nouns and terms used in the embodiments of this application and explained the application fields of the technical solutions in this application. The following will provide a detailed explanation of the principles and implementation process of the technical solutions of this application in conjunction with specific embodiments.

[0050] Figure 1A schematic diagram of a digital synchronization system according to an embodiment of the present invention is shown. The digital synchronization system in this embodiment mainly includes a transmitter and a receiver. A digital synchronization signal is connected between the transmitter's transmit interface and a system reference pin on the receiver. The digital synchronization signal is used to align frame boundaries and multi-frame boundaries. The transmitter and receiver communicate based on the JESD204B communication protocol. The digital synchronization signal is configured to be turned on and off in either automatic or manual mode. If configured in automatic mode, the transmitter automatically sends a digital synchronization signal to synchronize with the receiver when the link is lost. If configured in manual mode, the transmission mode is selected based on the level of the manual enable signal.

[0051] It should be understood that the ESD204B communication protocol is a high-speed serial data converter interface standard developed by the JEDEC committee. The transmitting end (TX) and receiving end (RX) work together to achieve synchronous data transmission. The transmitting end (TX) is responsible for encapsulating data into the format specified by the JESD204B protocol, including frame and multi-frame structures; ensuring data transmission synchronization through Code Group Synchronization (CGS) and Initialization Channel Alignment Sequence (ILAS); and using a digital synchronization signal (SYSREF) to align the local multi-frame clock (LMFC) for synchronization with the receiving end. The digital synchronization signal (SYSREF) can be periodic or a single pulse, used to indicate the Device Clock edge of different converters or logic devices. The receiving end (RX) receives data from the transmitting end and decodes it using the physical layer's serializer / deserializer (SERDES) module; it identifies specific patterns in the data stream, such as K28.5 code, by detecting the SYNC signal to achieve code group synchronization; and it uses a flexible buffer to absorb data propagation delay in the link and releases data simultaneously at well-defined times to ensure data synchronization.

[0052] The LMFC (Local Multi-Frame Clock) signal is used to ensure the synchronization of data transmission. The LMFC is a local clock generated by the link clock and counted according to parameters F and K. The K parameter ranges from 1 to 32, and the F parameter determines the number of bytes in each multi-frame. The periodic pulses of the LMFC are used to synchronize data transmission, ensuring that data can be correctly aligned and decoded at the receiving end. The period of the LMFC can be calculated using the following formula:

[0053] LMFC period = Link rate / (10 × F × K); Formula (1)

[0054] For example, if the link rate is 10Gbps, F=2, and K=32, then the LMFC period is 64ns.

[0055] The following section uses an RF transceiver chip as the transmitter of the JESD204B communication protocol and an FPGA IP core as the receiver to provide a detailed explanation of the technical solution of this application. For ease of description, the digital synchronization signal between the transmitter and receiver will be referred to as the SYSREF signal. Figure 1 In this document, it is named lmfc_to_fpga, the system reference pin is simply referred to as the SYSREF pin, and the synchronization input signal is simply referred to as the sync_in signal.

[0056] It should be understood that RF transceiver chips are core components of wireless communication systems, responsible for converting baseband signals into RF signals for transmission, and simultaneously converting received RF signals back into baseband signals for processing. The functions of RF transceiver chips include, but are not limited to, frequency conversion, frequency synthesis, signal amplification, filtering, and switching. FPGA IP cores, or intellectual property cores, are pre-designed circuit functional modules, which are generally categorized into three types based on design complexity and application: soft cores, hard cores, and solid cores. Soft cores provide hardware description language source code, offering high flexibility and reusability; solid cores are synthesized modules provided as netlists; and hard cores are the final mask product, providing a fully place-and-route netlist, offering high predictability and optimization.

[0057] The signal transmission process between the RF transceiver chip and the FPGA IP core is roughly as follows: The RF transceiver chip's analog-to-digital converter (ADC) acquires the analog signal and converts it into a digital signal. Then, it transmits the data through the JESD204B TX interface according to the specifications of the transport layer, data link layer, and physical layer defined by the protocol. At the data link layer, code group synchronization (CGS) and initial channel alignment sequence (ILAS) ensure the synchronization of data transmission. Subsequently, user data is transmitted at high speed serially to the FPGA IP core's 204B RX interface at the physical layer. After receiving the data, the FPGA processes it through the corresponding JESD204B RX IP core, completing the synchronous reception and deserialization operations. The FPGA IP core transmits the processed data through its 204B TX interface to the RF transceiver chip's 204B RX interface, and then further transmits it to the digital transmit channel (tx_ch) for digital-to-analog conversion to obtain the corresponding analog signal for use in the analog domain.

[0058] In the embodiments of this application, the system controls automatic or manual mode through a 1-bit serial peripheral interface signal. For example, a high level indicates automatic mode and a low level indicates manual mode, or vice versa. This embodiment does not limit this. In automatic mode, the enabling and disabling of the digital synchronization signal is controlled by a synchronization input signal (sync_in); the synchronization input signal is sent from the receiving end to the transmitting end.

[0059] In the embodiments of this application, when the digital synchronization signal is configured as an automatic mode switch, the digital synchronization signal is automatically turned off after the transmitting end detects a link establishment identifier, and automatically turned on after the transmitting end detects a link loss identifier.

[0060] Preferably, the link establishment indicator is represented by a synchronization input signal sent from the receiving end to the transmitting end; a high-level synchronization input signal indicates that a link has been established. The link termination indicator is a low-level synchronization input signal for a duration reaching a threshold. The transmitting end is configured with a counter for recording the duration of the link termination. The counter has a reserved upper limit value, which is greater than the threshold. The counter stops counting when the number of consecutive low-level beats of the synchronization input signal recorded reaches the threshold.

[0061] In the specific implementation, the transmitting end is configured with a counter to record the duration of the link break. When the count value of the counter reaches a preset threshold, the link break identifier is confirmed and the digital synchronization signal is automatically turned on. For example, the counter records the number of consecutive low-level beats of the sync_in signal. When the count reaches the threshold in a specific clock domain (such as the pclk clock domain), the counting stops and the SYSREF signal is pulled low.

[0062] Figure 2 The timing waveform diagram for automatic mode operation is shown. It is generated based on the characteristics of automatic mode: it automatically shuts down when a link establishment signal is detected and reopens when a link loss occurs. A counter (cnt_sync_low) records the duration of the low level of the sync_in signal, stopping when it counts to M in the pclk clock domain and pulling the SYSREF signal low. If the counter (cnt_sync_low) value is small, even though the sync_in signal is low, it is still considered a link establishment state, and there is no need to pull SYSREF low.

[0063] It's worth noting that the JESD204B communication protocol uses a synchronization input signal (hereinafter referred to as the sync_in signal) to indicate link establishment and disconnection. The sync_in signal is a control signal used to request the transmitting end to start sending synchronization data. The state of the sync_in signal usually indicates whether the receiving end is ready to establish a data link synchronization with the transmitting end. If the sync_in signal is high, it means that the link has been established, because the sync_in signal is usually active low, meaning that when the sync_in signal is pulled low, it means that the receiving end is requesting synchronization or establishing a link. However, due to possible alarm modes of the RF transceiver chip (e.g., protection mechanisms triggered by certain abnormal or error states) or minor interference, the low level of the sync_in signal may not be immediately cleared. This requires allowing a certain margin for the low level of the sync_in signal to ensure that the system can synchronize stably. Therefore, if the disconnection time is short, it is not necessary to resend the SYSREF signal; the SYSREF signal needs to be resent only if the disconnection time exceeds a certain limit.

[0064] Explained, when a link establishment signal is detected, i.e., the receiver sends a sync_in signal, the transmitter automatically closes the data stream and begins sending a specific synchronization sequence (such as a K28.5 code) to help the receiver align and identify the boundaries of the data stream. This process is called Code Group Synchronization (CGS). Once the receiver successfully identifies and aligns the data stream, it stops sending the sync_in signal, allowing the transmitter to continue sending subsequent data, including the Initial Channel Alignment Sequence (ILAS) and user data. When a link failure occurs, i.e., data transmission is interrupted or an error occurs, the receiver resends the sync_in signal to notify the transmitter that the link is broken and resynchronization is required. At this time, the transmitter stops sending the current data stream and restarts sending the synchronization sequence to re-establish link synchronization.

[0065] In the embodiments of this application, when the digital synchronization signal is configured as a manual mode switch, a high level of manual enable turns on the digital synchronization signal, and a low level of manual enable turns off the digital synchronization signal.

[0066] In a specific implementation, users can read and write specific registers (such as the square wave register) through software programming to change the state of the SYSREF signal. For example, if the manual enable signal (sys_man_en) is high, a square wave signal is output; if the manual enable signal (sys_man_en) is low, no square wave signal is output. This allows us to obtain... Figure 3 The timing waveform diagram is shown below.

[0067] In the embodiments of this application, the system includes a delay control signal for controlling the phase of the SYSREF signal; when the JESD204B communication protocol operates in subclass 0 mode, the delay control signal is an n-bit signal, and the square wave period of the SYSREF signal is 2 times the system clock period. n The phase shift range of the SYSREF signal is (0 to 2 times). n -1).

[0068] It should be understood that in the JESD204B interface, the SYSREF signal is a critical timing signal used to ensure synchronization between the data converter and the logic device. When the SYSREF signal serves as a system-level reference signal, it allows for deterministic latency, meaning that data transmission from the sender to the receiver has a known and consistent delay. The phase of the SYSREF signal can be controlled by a delay control signal (hereinafter referred to as the sys_pha_ctr signal), which determines the delay of the SYSREF signal. When the JESD204B interface operates in mode 0, the square wave period of the SYSREF signal is 32 times the device clock period, therefore the phase shift range is 0 to 31. Thus, the sys_pha_ctr signal should be a 5-bit signal, sufficient to provide the required phase control.

[0069] For example, in implementation, the delay time of SYSREF can be adjusted via the AXI4-LITE interface configuration register. This allows the phase of SYSREF to be adjusted programmatically to meet the synchronization requirements between different devices in the system. In some FPGA design examples, the SYSREF generator can generate periodic or intermittently periodic SYSREF signals, and the period and duty cycle of SYSREF can be precisely controlled by configuring the multiplier and duty cycle.

[0070] Figure 4 This demonstrates the fully phase-controllable operation, where the phase shift is determined by the value of the sys_pha_ctr signal and can be shifted from 0 to 31 pclk cycles (pclk is the master clock of the JESD204B communication protocol). Three typical cases are shown in the figure:

[0071] (1) When sys_pha_ctr = 0, the SYSREF signal has no phase shift.

[0072] (2) When sys_pha_ctr=16, the phase shift of the SYSREF signal is 16 pclk cycles. Combined with the fact that the entire SYSREF cycle is 32 pclk cycles, it is equivalent to being inverted at this time.

[0073] (3) When sys_pha_ctr = 31, the phase shift of the SYSREF signal is at its maximum. When the sys_pha_ctr signal increases to 32, it is equivalent to the phase of the SYSREF signal having shifted by a full cycle. At this point, further increasing the value of the sys_pha_ctr signal will have no additional meaning, because from the perspective of phase, it has returned to its original state. Therefore, the design in this mode is relatively simple. The shift control of the sys_pha_ctr signal can be implemented by setting a 32-bit register to adapt to different phase adjustment requirements.

[0074] The structure of a digital synchronization system provided by an embodiment of the present invention has been explained above. The following will, in conjunction with... Figures 5-10 The simulation results of the digital synchronization system of the present invention are presented here.

[0075] Figure 5 This demonstrates a simpler scenario in automatic mode. When `rst_n` goes high, the `sync_in` signal is 0, indicating no connection establishment, so the `lmfc_to_fpga` signal (i.e., the `SYSREF` signal in the modification requirements) is emitted. When the `sync_in` signal is 1, the 204B interface has established a connection, so the `lmfc_to_fpga` signal goes low. In the diagram, the `pclk` period is 23.04 ns, while the `lmfc_to_fpga` signal period is 737.28 ns, exactly 32 times, consistent with the operating state of mode 0.

[0076] Figure 6 This illustrates a more complex scenario in automatic mode. If the sync_in signal is pulled low intermittently due to alarm mode or other interference, the cnt_sync_low variable is used to count the number of low-level pulses of the sync_in signal in the pclk clock domain. In the first few segments of the diagram, the intervals where the sync_in signal is pulled low are too short, causing the sync_in signal to not reach its maximum value of 6. Therefore, it is considered that the connection is still established, and no lmfc_to_fpga (i.e., the SYSREF signal) will be emitted. In the subsequent segments, the intervals where the sync_in signal is pulled low become longer, and the value of cnt_sync_low reaches 6, so the lmfc_to_fpga signal will be output intermittently. In the last segment, the sync_in signal remains low for a long time, indicating a complete disconnection, so the output lmfc_to_fpga signal is a continuous square wave.

[0077] Figure 7The simulation results shown are for manual mode. In the figure, sys_mode = 1, indicating the chip is operating in manual mode. When the manual enable signal sys_man_en is low, the output lmfc_to_fpga is 0. When the manual enable signal sys_man_en is high, the output lmfc_to_fpga is 1. The simulation results are consistent with the design requirements.

[0078] Figure 8 , 9 Figure 10 shows the simulation results for full phase controllability. In mode 0, the period of the SYSREF signal is 32 times that of pclk. Since the value of sys_pha_ctr can be 0-31, it is only necessary to verify a few typical cases. Figure 8 The diagram shows the phase relationship when sys_pha_ctr = 0. It can be observed that the lmfc_to_fpga signal is sampling the lmfc_to_fpga_temp signal at this time, which means it is in phase with the d[0] signal. Figure 9 The diagram shows the phase relationship when sys_pha_ctr = 15 (0F). At this time, the lmfc_to_fpga signal is in phase with d

[15] and out of phase with the temp signal. Figure 10 The diagram shows the phase relationship when sys_pha_ctr = 31 (1F). At this time, the lmfc_to_fpga signal and the temp signal are in phase, and the signal and d

[15] are out of phase.

[0079] The technical solution provided in this application enables a single digital synchronization signal, SYSREF, to match the JESD204B's link establishment in automatic mode. When the link is lost, it continuously sends synchronization signals to synchronize the RF chip with the FPGA or baseband data chip. In manual mode, the SYSREF signal can be selectively activated based on the enable / disable level. Finally, the SYSREF signal is fully phase-controllable, allowing for flexible adaptation to different application scenarios. In normal use, it simplifies synchronization between multiple chips and devices, eliminating the need for an additional clock chip to send the digital synchronization signal. Furthermore, the SYSREF signal, custom-generated within the RF transceiver chip, operates in the same clock domain as the chip, eliminating the need for additional hardware resources for cross-clock domain synchronization and resulting in better timing performance.

[0080] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first XX" and "second XX" are merely used to distinguish different XXs and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily imply that they are different.

[0081] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0082] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0084] In summary, this application provides a digital synchronization system with the following advantages: This application can truly achieve a single digital synchronization signal SYSREF, enabling automatic mode matching of the JESD204B's link establishment status and continuously emitting synchronization signals to synchronize the RF chip with the FPGA or baseband data chip when the link is lost. In manual mode, the occurrence of the digital synchronization signal SYSREF can be selected based on the enable high / low level. Finally, this digital synchronization signal SYSREF is fully phase controllable, allowing for flexible adaptation to different application scenarios. In normal use, it simplifies synchronization between multiple chips and devices, eliminating the need for an additional clock chip to generate the digital synchronization signal. Furthermore, the SYSREF digital synchronization signal, custom-generated internally by the RF transceiver chip, resides in the same clock domain as the chip, eliminating the need for additional hardware resources for cross-clock domain synchronization and resulting in better timing performance. Therefore, this application effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0085] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A digital synchronization system, characterized in that, include: Sender and receiver; The transmitting end and the receiving end communicate based on the JESD204B communication protocol; The transmitting end internally generates a digital synchronization signal, and the digital synchronization signal is in the same clock domain as the transmitting end. The digital synchronization signal is connected between the transmitting interface of the transmitting end and the system reference pin set on the receiving end, and is used to transmit the digital synchronization signal from the transmitting end to the receiving end to align frame boundaries and multi-frame boundaries. The digital synchronization signal is configured to be turned on and off based on automatic or manual mode. If configured in automatic mode, the receiving end sends a synchronization input signal to the transmitting end, which is used to control the enabling and disabling of the digital synchronization signal. Furthermore, the transmitting end automatically turns off the digital synchronization signal after recognizing a link establishment identifier represented by the synchronization input signal, and automatically turns on the digital synchronization signal after recognizing a link loss identifier represented by the synchronization input signal, so as to synchronize with the receiving end. If configured for manual mode, the digital synchronization signal is selected based on the level of the manual enable signal.

2. The digital synchronization system according to claim 1, characterized in that, The digital synchronization signal is controlled via a serial peripheral interface.

3. The digital synchronization system according to claim 2, characterized in that, The system controls automatic or manual mode via a 1-bit serial peripheral interface signal; in manual mode, the enabling and disabling of the digital synchronization signal is controlled by the manual enable level.

4. The digital synchronization system according to claim 1, characterized in that, The link establishment identifier is represented by a synchronization input signal sent from the receiving end to the sending end. When the synchronization input signal is high, it indicates that the link has been established.

5. The digital synchronization system according to claim 4, characterized in that, The chain break indicator is when the synchronization input signal is at a low level for a duration that reaches a threshold.

6. The digital synchronization system according to claim 5, characterized in that, The transmitting end is configured with a counter for recording the duration of the link break. The counter has a reserved upper limit value for counting, which is greater than the threshold. The counter stops counting when the number of consecutive low-level beats of the synchronization input signal recorded by the counter reaches the threshold.

7. The digital synchronization system according to claim 1, characterized in that, In manual mode, if the manual enable signal is detected to be high, the digital synchronization signal is enabled; if the manual enable signal is detected to be low, the digital synchronization signal is disabled.

8. The digital synchronization system according to claim 1, characterized in that, The system is provided with a delay control signal for controlling the phase of the digital synchronization signal; when the JESD204B communication protocol works in the operation mode of subclass 0, the delay control signal is an n-bit signal, the square wave period of the digital synchronization signal is 2 n times of the system clock period, and the phase shift range is (0~2 n -1).

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