Motor simulation device and simulation method thereof

Abstract

The motor simulation device and the simulation method provided by the motor simulation device can improve the universality of the motor simulation device and reduce the interference of other signals on the sensor signal.

Description

Technical Field

[0001] This disclosure relates to the field of real-time power electronics simulation, and in particular to a motor simulation device and simulation method thereof. Background Technology

[0002] As a typical electromechanical energy conversion device, electric motors are widely used in many traditional industries such as industrial control, transportation, water conservancy projects, medical and health care, and consumer electronics. According to authoritative statistics at home and abroad, electric motor systems account for more than 60% of the total electricity generated. Energy conservation in electric motor systems has a significant impact on my country's national policy of promoting energy conservation and emission reduction. Furthermore, with the rapid development of emerging application areas and technologies for electric motors, such as new energy vehicles, wind power generation, locomotive traction, and ship electric propulsion, more and more new challenges are being posed to the performance testing technologies of various electric motors and their drive controllers.

[0003] The motor simulator, based on a constructed dynamic mathematical model of the motor, achieves accurate simulation of the motor's motoring and generating states. It combines the advantages of hardware-in-the-loop (HiL) simulation and bench testing, filling the gap between signal-level hardware-in-the-loop (HiL) simulation and power-level motor bench testing. It simulates various load conditions of the motor based on the motor drive controller, realizing power hardware-in-the-loop testing (MCU Power-HiL) of the motor drive controller.

[0004] However, when the motor simulator and the drive controller of the motor under test communicate, the signals transmitted between them are easily interfered with by the power devices in the motor simulator. Summary of the Invention

[0005] This disclosure provides a motor simulation device and simulation method thereof, which at least helps to improve the versatility of the motor simulation device and reduce the interference of other signals in the motor simulation device on the sensing signals.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a motor simulation device, including: a motor simulator, the motor simulator including a core control unit, the core control unit including a first FPGA chip; an interface expansion box located outside the motor simulator, the interface expansion box including a second FPGA chip; an interface expansion communication unit configured to realize optical fiber communication between the core control unit and the interface expansion box; and a motor under test and sensor signal transmission unit, the sensor signal transmission unit being configured to realize the interaction of sensor signals between the interface expansion box and the motor under test; wherein, the first FPGA chip is configured to implement a sensor signal simulation algorithm, and the optical fiber user layer protocol and physical layer protocol on the core control unit side; the second FPGA chip is configured to implement sensor signal interface logic, and the optical fiber user layer protocol and physical layer protocol on the interface expansion box side.

[0007] In some embodiments, the core control unit is provided with a first high-speed serial interface, and the interface expansion box is provided with a second high-speed serial interface. The first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock. The interface expansion communication unit includes a first high-speed optical module, a transceiver optical fiber, and a second high-speed optical module. The first high-speed optical module is connected to the first high-speed serial interface, the second high-speed optical module is connected to the second high-speed serial interface, and the transceiver optical fiber connects the first high-speed optical module and the second high-speed optical module.

[0008] In some embodiments, the first FPGA chip includes a sensor signal simulation algorithm module, a first user layer protocol transmission module, a first user layer protocol reception module, and a first physical layer communication module; wherein, the first physical layer communication module is configured to receive a first signal transmitted by the interface expansion box based on the interface expansion communication unit; the first user layer protocol reception module is configured to receive the first signal from the first physical layer communication module and transmit the first signal to the sensor signal simulation algorithm module; the sensor signal simulation algorithm module is configured to perform sensor signal simulation based on the first signal and output a second signal to the first user layer protocol transmission module; the first user layer protocol transmission module is configured to receive the second signal from the sensor signal simulation algorithm module and transmit it to the first physical layer communication module; the first physical layer communication module is further configured to transmit the second signal to the interface expansion box based on the interface expansion communication unit.

[0009] In some embodiments, the sensor signal simulation algorithm module is further configured to receive a control signal and perform sensor signal simulation based on the control signal and the first signal.

[0010] In some embodiments, the second FPGA chip includes a sensor signal hardware interface design module, a second user layer protocol sending module, a second user layer protocol receiving module, and a second physical layer communication module; wherein, the second physical layer communication module is configured to receive a second signal transmitted by the core control unit based on the interface extended communication unit; the second user layer protocol receiving module is configured to receive the second signal from the second physical layer communication module and transmit the second signal to the sensor signal hardware interface design module; the sensor signal hardware interface design module is configured to receive the second signal from the second user layer protocol receiving module and receive a first signal transmitted by the motor under test; the second user layer protocol sending module is configured to receive the first signal from the sensor signal hardware interface design module and transmit it to the second physical layer communication module; the second physical layer communication module is further configured to transmit the first signal to the core control unit based on the interface extended communication unit.

[0011] In some embodiments, the sensing signal hardware interface design module is further configured to design different sensing signal interfaces for sensing signal interaction with the motor under test based on the different types of sensing signals, receive the first signal transmitted by the motor under test from some of the sensing signal interfaces, and transmit the received second signal to the remaining sensing signal interfaces.

[0012] In some embodiments, the sensing signal hardware interface design module includes an interface timing logic design unit and a signal conditioning unit; the interface timing logic design unit is configured to design different interface timing logics based on the different types of sensing signals; the signal conditioning unit is configured to condition the first signal and the second signal.

[0013] In some embodiments, the interface timing logic design unit includes a first timing logic design subunit and a second timing logic design subunit; the signal conditioning unit includes a first conditioning subunit and a second conditioning subunit; wherein, the first signal is transmitted sequentially from a portion of the sensor signal interface, the first conditioning subunit, and the first timing logic design subunit to the second user layer protocol sending module; the second signal is transmitted sequentially from the second user layer protocol receiving module, the second timing logic design subunit, and the second conditioning subunit to the remaining sensor signal interface.

[0014] In some embodiments, the sensing signal includes a position sensing signal or a temperature sensing signal.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure also provides a motor simulation method, applied to the motor simulation device described in any of the above claims. The motor simulation method includes: realizing the interaction of sensor signals between the interface expansion box and the motor under test through the sensor signal transmission unit; realizing optical fiber communication between the core control unit and the interface expansion box through the interface expansion communication unit; and realizing the simulation of the motor under test through information interaction between the motor simulator and the motor under test.

[0016] The technical solutions provided in this disclosure have at least the following advantages:

[0017] On the one hand, the interface that needs to communicate with the motor under test is designed in the interface expansion box, rather than on the core control unit. This physically extends the sensor signal interface, reducing the types and number of interfaces required on the core control unit, thus reducing the interface design burden on the core control unit. On the other hand, an interface expansion communication unit is designed to achieve fiber optic communication between the core control unit and the interface expansion box. Since the transmission distance of the sensor signal between the interface expansion box and the core control unit is relatively long, the high speed, low latency, and low jitter characteristics of fiber optic communication mean that the physical extension of the sensor signal interface implemented by the interface expansion box has a negligible impact on the performance of the motor simulation device. This ensures low latency and low jitter of the sensor signal over long distances, guarantees the synchronization of the sensor signal, and effectively reduces the interference of wiring of other devices in the motor simulator (excluding the core control unit) on the sensor signal transmitted in the interface expansion communication unit, further improving the accuracy of the sensor signal transmitted between the core control unit and the interface expansion box. On the other hand, the sensor signal simulation algorithm is implemented using the first FPGA chip in the core control unit, and the sensor signal interface logic is implemented using the second FPGA chip in the interface expansion box. That is, the module implementing the sensor signal simulation algorithm and the module implementing the sensor signal interface logic are distributed across two FPGA chips, further reducing the design burden on the core control unit. Furthermore, designing the second FPGA chip to implement the sensor signal interface logic allows for the design of interfaces compatible with various types of motors under test, especially when there are many types of sensor signals. This improves the versatility of the motor simulation device. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a motor simulation device provided in an embodiment of the present disclosure;

[0020] Figure 2 A partial structural schematic diagram of a motor simulation device provided in an embodiment of this disclosure;

[0021] Figure 3 A schematic diagram of the structure of a first FPGA chip in a motor simulation device provided in an embodiment of this disclosure;

[0022] Figure 4 This is another partial structural schematic diagram of a motor simulation device provided in an embodiment of the present disclosure;

[0023] Figure 5 This is another schematic diagram of the structure of the motor simulation device provided in one embodiment of the present disclosure;

[0024] Figure 6 This is a schematic diagram of the structure of a second FPGA chip in a motor simulation device provided in an embodiment of the present disclosure. Detailed Implementation

[0025] As is known from the background art, it is necessary to reduce interference with the signals transmitted between the motor simulator and the drive controller of the motor under test.

[0026] Analysis revealed that the motor simulator mainly consists of a host computer, a core control unit, a bidirectional DC source, a power conversion unit, and a filtering unit. The core control unit communicates with the motor under test. The host computer constructs a motor model and sends parameters and displays relevant statuses to the core control unit. The core control unit performs parameter parsing and status reporting from the host computer, bidirectional DC source control, motor model algorithms, three-phase current tracking, and power conversion control. The core control unit needs to acquire the bidirectional DC source voltage output, three-phase line voltage, and three-phase line current as signal inputs for the motor model and three-phase current tracking.

[0027] As can be seen, the core control unit not only communicates with the power conversion unit, the two-phase DC source, and the host computer, but also needs to acquire the bidirectional DC source voltage output, three-phase line voltage, and three-phase line current. Furthermore, it needs to communicate with the motor under test (MUT) to implement sensor signal simulation algorithms related to the MUT within the core control unit. Therefore, the core control unit requires numerous communication interfaces to meet the communication needs with these devices and to acquire current and voltage, resulting in significant interface design challenges. In addition, the core control unit and the MUT controller typically connect via physical wiring for sensor signal input and output. Since the core control unit is an internal component of the motor simulator, the physical wiring between the core control unit and the MUT controller is relatively long. Moreover, this physical wiring, along with the wiring between the core control unit and other devices within the motor simulator, is located within the simulator itself. The close proximity of these wirings makes the communication between the core control unit and the MUT controller susceptible to interference from other devices within the motor simulator, thus affecting the acquisition of sensor signals from the MUT controller.

[0028] This disclosure provides a motor simulation device and method. In the motor simulation device, on one hand, the interface requiring communication with the motor under test is designed in an interface expansion box, rather than on the core control unit. This physically extends the sensor signal interface, reducing the types and number of interfaces required on the core control unit, thus reducing the interface design burden on the core control unit. On the other hand, an interface expansion communication unit is designed to achieve fiber optic communication between the core control unit and the interface expansion box. Since the transmission distance of the sensor signal between the interface expansion box and the core control unit is relatively long, the high speed, low latency, and low jitter characteristics of fiber optic communication mean that the physical extension of the sensor signal interface implemented by the interface expansion box has negligible impact on the performance of the motor simulation device. This ensures low latency and low jitter of the sensor signal over long distances, guarantees sensor signal synchronization, and effectively reduces interference from wiring of other devices besides the core control unit within the motor simulator on the sensor signal transmitted in the interface expansion communication unit, further improving the accuracy of the sensor signal transmitted between the core control unit and the interface expansion box. On the other hand, the sensor signal simulation algorithm is implemented using the first FPGA chip in the core control unit, and the sensor signal interface logic is implemented using the second FPGA chip in the interface expansion box. That is, the module implementing the sensor signal simulation algorithm and the module implementing the sensor signal interface logic are distributed across two FPGA chips, further reducing the design burden on the core control unit. Furthermore, designing the second FPGA chip to implement the sensor signal interface logic allows for the design of interfaces compatible with various types of motors under test, especially when there are many types of sensor signals. This improves the versatility of the motor simulation device.

[0029] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] This disclosure provides an embodiment of a motor simulation device, which will be described in detail below with reference to the accompanying drawings.

[0034] refer to Figure 1 , Figure 1This is a schematic diagram of a module structure of a motor simulation device provided in an embodiment of the present disclosure. The motor simulation device includes: a motor simulator 100, which includes a core control unit 101, and the core control unit 101 includes a first FPGA chip 111; an interface expansion box 102 located outside the motor simulator 100, which includes a second FPGA chip 112; an interface expansion communication unit 103 configured to realize optical fiber communication between the core control unit 101 and the interface expansion box 102; a motor under test 104 and a sensing signal transmission unit 105 configured to realize the interaction of sensing signals between the interface expansion box 102 and the motor under test 104; wherein, the first FPGA chip 111 is configured to implement a sensing signal simulation algorithm, as well as the optical fiber user layer protocol and physical layer protocol on the core control unit 101 side; the second FPGA chip 112 is configured to implement the sensing signal interface logic, as well as the optical fiber user layer protocol and physical layer protocol on the interface expansion box 102 side.

[0035] It is worth noting that an interface expansion box 102 is designed outside the motor simulator 100, and an interface expansion communication unit 103 is designed to realize fiber optic communication between the core control unit 101 and the interface expansion box 102. A sensor signal transmission unit 105 is also designed to realize the interaction of sensor signals between the interface expansion box 102 and the motor under test 104. Real-time interaction of sensor signals between the core control unit 101 and the motor under test 104 is achieved through the sensor signal transmission unit 105, the interface expansion box 102, and the interface expansion communication unit 103.

[0036] On the one hand, the interface that needs to communicate with the motor under test 104 is designed on the interface expansion box 102 instead of the core control unit 101, thereby realizing the physical extension of the sensing signal interface and reducing the types and number of interfaces that need to be designed on the core control unit 101, which helps to reduce the interface design pressure on the core control unit 101.

[0037] On the other hand, based on the design of the interface expansion box 102, an interface expansion communication unit 103 is designed to realize fiber optic communication between the core control unit 101 and the interface expansion box 102. Since the transmission distance of the sensing signals between the interface expansion box 102 and the core control unit 101 is relatively long, the high speed, low latency, and low jitter characteristics of the fiber optic communication of the interface expansion communication unit 103 are advantageous for achieving real-time interaction of sensing signals between the core control unit 101 and the interface expansion box 102. In other words, based on the high speed, low latency, and low jitter characteristics of fiber optic communication, the physical extension of the sensing signal interface implemented by the interface expansion box 102 has a negligible impact on the performance of the motor simulation device, ensuring low latency and low jitter of the sensing signals over long distances and guaranteeing the synchronization of the sensing signals.

[0038] Furthermore, since the core control unit 101 and the interface expansion box 102 exchange sensing signals via high-speed, low-latency, and low-jitter optical fibers, rather than transmitting signals through physical connections, the interference of connections of other devices in the motor simulator 100 other than the core control unit 101 on the sensing signals transmitted in the interface expansion communication unit 103 is effectively reduced, further improving the accuracy of the sensing signals transmitted between the core control unit 101 and the interface expansion box 102.

[0039] On the other hand, the interface that works with the motor under test is transferred from the core control unit 101 to the interface expansion box 102. The first FPGA chip 111 in the core control unit 101 is used to implement the sensor signal simulation algorithm, and the second FPGA chip 112 in the interface expansion box 102 is used to implement the sensor signal interface logic. That is, the module that implements the sensor signal simulation algorithm function and the module that implements the sensor signal interface logic are distributed on two FPGA chips, which further reduces the design pressure on the core control unit 101.

[0040] On the other hand, the second FPGA chip 112 is designed to implement the sensing signal interface logic. In cases where there are many types of sensing signals, the second FPGA chip 112 can be used to design interfaces that match various types of motors under test 104. This not only effectively reduces the design pressure of the peripheral interface of the core control unit 101, but also helps the motor simulation device to match various types of motors under test 104, thereby improving the versatility of the motor simulation device.

[0041] In some cases, the interface expansion box 102 is located outside the motor simulator 100. Compared to the core control unit 101, the interface expansion box 102 can be designed to be closer to the motor under test 104, reducing the distance between the interface expansion box 102 and the motor under test 104. This reduces the wiring length of the sensor signal transmission unit 105, thereby reducing the delay caused by the transmission of sensor signals in the sensor signal transmission unit 105, and further ensuring real-time interaction of sensor signals between the core control unit 101 and the interface expansion box 102. In one example, the sensor signal transmission unit 105 can be a physical connection.

[0042] In some cases, the core control unit 101 is connected to other devices in the motor simulator 100 via power lines. Based on this, an interface expansion communication unit 103 is designed to realize fiber optic communication between the core control unit 101 and the interface expansion box 102. This helps to avoid the existence of signal lines located inside the motor simulator 100 between the core control unit 101 and the motor under test 104. This also helps to avoid the signal lines transmitting sensing signals being too close to the power lines inside the motor simulator 100, thus avoiding significant interference from the power lines to the signal lines.

[0043] In some cases, depending on the type of the motor under test 104, the types and quantities of sensor signals that need to be exchanged between the core control unit 101 and the motor under test 104 are different. All kinds of sensor signals can be transmitted through the interface expansion communication unit 103, without the need to design multiple signal lines for transmitting sensor signals between the core control unit 101 and the interface expansion box 102.

[0044] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0045] In some embodiments, reference Figure 2 , Figure 2 This is a partial structural diagram of a motor simulation device provided in an embodiment of the present disclosure. The core control unit 101 is provided with a first high-speed serial interface, and the interface expansion box 102 is provided with a second high-speed serial interface. The first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock clk. The interface expansion communication unit 103 includes a first high-speed optical module 113, a transceiver optical fiber 123, and a second high-speed optical module 133. The first high-speed optical module 113 is connected to the first high-speed serial interface, the second high-speed optical module 133 is connected to the second high-speed serial interface, and the transceiver optical fiber 123 is connected to the first high-speed optical module 113 and the second high-speed optical module 133.

[0046] In some examples, the same parameter clock crystal is connected to the first high-speed serial interface and the second high-speed serial interface, so that the core control unit 101 and the interface extension communication unit 103 receive the same reference clock clk.

[0047] In some examples, the first high-speed optical module 113 and the second high-speed optical module 133 are of the same model to further ensure real-time interaction of sensing signals between the core control unit 101 and the motor under test 104.

[0048] In some embodiments, the sensing signal includes a position sensing signal or a temperature sensing signal.

[0049] It is worth noting that, depending on the type of motor under test 104, the type of sensing signal to be transmitted between the core control unit 101 and the motor under test 104 may also differ. Based on the various types of motors under test 104 currently available, the sensing signals fall into two main categories: position sensing signals and temperature sensing signals. Position sensing signals include, but are not limited to, resolver signals, incremental coded signals, or Hall coded signals; temperature sensing signals are primarily signals simulated by thermistors.

[0050] Based on this, the interface connected to the motor under test 104 is placed outside the motor simulator 100, and a second FPGA chip 112 is designed to implement the sensing signal interface logic. Even if there are many types of sensing signals, the second FPGA chip 112 can be used to design interfaces that match various types of motors under test 104. This not only effectively reduces the design pressure of the peripheral interface of the core control unit 101, but also helps the motor simulation device to match various types of motors under test 104, thereby improving the versatility of the motor simulation device.

[0051] In some embodiments, reference Figure 3 , Figure 3 This is a schematic diagram of the structure of a first FPGA chip in a motor simulation device provided in an embodiment of the present disclosure. The first FPGA chip 111 may include a sensor signal simulation algorithm module 211, a first user layer protocol sending module 311, a first user layer protocol receiving module 411, and a first physical layer communication module 511.

[0052] Reference Figure 1 and Figure 3The first physical layer communication module 511 is configured to receive a first signal signal1 transmitted by the interface expansion box 102 based on the interface expansion communication unit 103. The first user layer protocol receiving module 411 is configured to receive the first signal signal1 from the first physical layer communication module 511 and transmit the first signal signal1 to the sensor signal simulation algorithm module 211. The sensor signal simulation algorithm module 211 is configured to perform sensor signal simulation based on the first signal signal1 and output a second signal signal2 to the first user layer protocol sending module 311. The first user layer protocol sending module 311 is configured to receive the second signal signal2 from the sensor signal simulation algorithm module 211 and transmit it to the first physical layer communication module 511. The first physical layer communication module 511 is also configured to transmit the second signal signal2 to the interface expansion box 102 based on the interface expansion communication unit 103.

[0053] The following detailed explanation uses a resolver signal as an example of the type of sensing signal transmitted between the motor under test 104 and the core control unit 101. (Refer to the reference...) Figure 3 and Figure 4 , Figure 4 This is a partial structural diagram of a motor simulation device provided in an embodiment of the present disclosure. The first signal signal1 may include an excitation acquisition signal signal11, and the second signal signal2 may include an in-phase signal signal21 and a quadrature signal signal22.

[0054] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The sensor signal simulation algorithm module 211 can also be configured to receive a control signal control and perform sensor signal simulation based on the control signal control and the first signal signal1.

[0055] In some cases, refer to Figure 5 , Figure 5This is another schematic diagram of the motor simulation device provided in one embodiment of the present disclosure. The motor simulator 100 may further include a host computer 106, a bidirectional DC source 107, a power conversion unit 108, and a filter unit 109. The host computer 106 and the core control unit 101 are communicatively connected. The host computer 106 constructs a motor model and sends parameters and displays relevant statuses to the core control unit 101. The core control unit 101 is also communicatively connected to the bidirectional DC source 107 and the power conversion unit 108. The core control unit 101 performs power control on the power conversion unit 108. The core control unit 101 also collects the bidirectional DC source voltage output Udc, the three-phase line voltages Uab and Ubc, and the three-phase line currents Ia, Ib, and Ic.

[0056] In addition, the control signal received by the sensor signal simulation algorithm module 211 is sent by the host computer 106. The host computer 106 can send different types of control signals to the sensor signal simulation algorithm module 211 based on the different types of motors under test 104.

[0057] In some cases, refer to Figure 5 The bidirectional DC power source 107 is electrically connected to the power grid 119.

[0058] The following detailed explanation uses the example of a resolver signal as the type of sensing signal transmitted between the motor under test 104 and the core control unit 101.

[0059] Reference Figure 3 and Figure 4 The control signal 'control' can be the resolver pole pair number 'control1', resolver amplitude control 'control2', and motor mechanical speed control 'control3'. The sensor signal simulation algorithm module 211 simulates the sensor signal based on the received excitation acquisition signal 'singal11', resolver pole pair number 'control1', resolver amplitude control 'control2', and motor mechanical speed control 'control3', and outputs the in-phase signal 'singal21' and the quadrature signal 'singal22' to the first user layer protocol sending module 311.

[0060] Reference Figure 4 and Figure 5It is worth noting that the transmission lines in the core control unit 101 used to acquire the bidirectional DC source voltage output Udc, three-phase line voltages Uab and Ubc, and three-phase line currents Ia, Ib, and Ic are power lines. The power signals transmitted in these power lines can easily cause significant interference to the signal lines transmitting sensor signals. Therefore, an interface expansion communication unit 103 is designed to enable fiber optic communication between the core control unit 101 and the interface expansion box 102. This helps avoid the presence of signal lines located inside the motor simulator 100 between the core control unit 101 and the motor under test 104. This also helps prevent the signal lines transmitting sensor signals from being too close to the various power lines within the motor simulator 100, thus avoiding significant interference from the power lines to the signal lines.

[0061] In some embodiments, reference Figure 6 , Figure 6 This is a schematic diagram of the structure of a second FPGA chip in a motor simulation device provided in an embodiment of the present disclosure. The second FPGA chip 112 may include a sensor signal hardware interface design module 212, a second user layer protocol sending module 312, a second user layer protocol receiving module 412, and a second physical layer communication module 512.

[0062] Reference Figure 1 and Figure 3 The second physical layer communication module 512 is configured to receive the second signal signal2 transmitted by the core control unit 101 based on the interface extension communication unit 103. The second user layer protocol receiving module 412 is configured to receive the second signal signal2 from the second physical layer communication module 512 and transmit the second signal signal2 to the sensor signal hardware interface design module 212. The sensor signal hardware interface design module 212 is configured to receive the second signal signal2 from the second user layer protocol receiving module 412 and receive the first signal signal1 transmitted by the motor under test 104. The second user layer protocol sending module 312 is configured to receive the first signal signal1 from the sensor signal hardware interface design module 212 and transmit it to the second physical layer communication module 512. The second physical layer communication module 512 is also configured to transmit the first signal signal1 to the core control unit 101 based on the interface extension communication unit 103.

[0063] In some embodiments, in conjunction with reference Figure 5 and Figure 6The sensor signal hardware interface design module 212 can also be configured to design different sensor signal interfaces for sensor signal interaction with the motor under test 104 based on the different types of sensor signals, receive the first signal signal1 transmitted by the motor under test 104 from some sensor signal interfaces, and transmit the received second signal signal2 to the remaining sensor signal interfaces.

[0064] It is worth noting that the type of sensing signal may be different for different types of motors under test 104. Based on this, the sensing signal hardware interface design module 212 can change the interface type for interacting with the motor under test 104, so that the interface extension communication unit 103 can be adapted to multiple types of motors under test 104, so that the motor simulator 100 can simulate multiple types of motors under test 104, thereby improving the versatility of the motor simulator 100.

[0065] The following detailed explanation uses the example of a resolver signal as the type of sensing signal transmitted between the motor under test 104 and the core control unit 101.

[0066] In some cases, in conjunction with references Figure 4 and Figure 5 Based on the fact that the sensing signal is a resolver signal, the sensing signal hardware interface design module 212 designs different sensing signal interfaces for interacting with the motor under test 104, including an excitation signal interface 212a, a non-in-phase signal interface 212b, and a quadrature signal interface 212c. The excitation signal interface 212a serves as an input interface, receiving the excitation acquisition signal signal11 transmitted from the motor under test 104; the non-in-phase signal interface 212b and the quadrature signal interface 212c serve as output interfaces, with the non-in-phase signal interface 212b providing the non-in-phase signal signal21 to the motor under test 104, and the quadrature signal interface 212c providing the quadrature signal signal22 to the motor under test 104.

[0067] In some embodiments, in conjunction with reference Figure 4 and Figure 6 The sensor signal hardware interface design module 212 includes an interface timing logic design unit 222 and a signal conditioning unit 232. The interface timing logic design unit 222 is configured to design different interface timing logics based on the different types of sensor signals. The signal conditioning unit 232 is configured to condition the first signal signal1 and the second signal signal2.

[0068] It is worth noting that, based on the fact that the types of sensing signals may be different, different interface timing logic can be designed with the help of the interface timing logic design unit 222, so that the interface extension communication unit 103 has an interface adapted to the motor under test, thereby achieving the purpose that the interface extension communication unit 103 can be adapted to various types of motors under test 104.

[0069] In some cases, in conjunction with references Figure 4 and Figure 5 The interface timing logic design unit 222 and the signal conditioning unit 232 are in one-to-one correspondence, and the signal conditioning unit 232 and the sensing signal interface on the interface expansion communication unit 103 that interacts with the motor under test 104 are in one-to-one correspondence.

[0070] In some embodiments, in conjunction with reference Figure 4 and Figure 6 The interface timing logic design unit 222 includes a first timing logic design subunit 222a and a second timing logic design subunit 222b; the signal conditioning unit 232 includes a first conditioning subunit 232a and a second conditioning subunit 232b; wherein, the first signal signal1 is transmitted sequentially from a portion of the sensor signal interface, the first conditioning subunit 232a and the first timing logic design subunit 222a to the second user layer protocol sending module 312; the second signal signal2 is transmitted sequentially from the second user layer protocol receiving module 412, the second timing logic design subunit 222b and the second conditioning subunit 232b to the remaining sensor signal interface.

[0071] The following detailed explanation uses the example of a resolver signal as the type of sensing signal transmitted between the motor under test 104 and the core control unit 101.

[0072] In some cases, refer to Figure 4 The excitation acquisition signal signal11 is transmitted sequentially via the excitation signal interface 212a to the first conditioning subunit 232a and the first timing logic design subunit 222a, and then to the second user layer protocol transmission module 312. The first conditioning subunit 232a can be considered as an input signal conditioning unit, and the first timing logic design subunit 222a is used to implement the timing logic of the ADC interface, converting the acquired analog signal into a digital signal.

[0073] The second signal, signal2, includes an in-phase signal, signal21, and a quadrature signal, signal22. The second sequential logic design subunit 222b includes an in-phase sequential logic design subunit 322b corresponding to the in-phase signal, signal21, and a quadrature sequential logic design subunit 422b corresponding to the quadrature signal, signal22. The second conditioning subunit 232b includes an in-phase conditioning subunit 332b corresponding to the in-phase signal, signal21, and a quadrature conditioning subunit 432b corresponding to the quadrature signal, signal22. The second conditioning subunit 232b can be considered an output signal conditioning unit, and the second sequential logic design subunit 222b is used to implement the DAC interface timing logic, converting digital signals into analog signals.

[0074] Specifically, the in-phase signal singal21 is transmitted sequentially from the second user layer protocol receiving module 412, the in-phase timing logic design subunit 322b, and the in-phase conditioning subunit 332b to the in-phase signal interface 212b; the quadrature signal singal22 is transmitted sequentially from the second user layer protocol receiving module 412, the quadrature timing logic design subunit 422b, and the quadrature conditioning subunit 432b to the quadrature signal interface 212c.

[0075] In summary, on the one hand, designing the interface that needs to establish communication with the motor under test 104 on the interface expansion box 102, rather than on the core control unit 101, physically extends the sensing signal interface, which helps reduce the interface design pressure on the core control unit 101. On the other hand, designing the interface expansion communication unit 103 to realize fiber optic communication between the core control unit 101 and the interface expansion box 102 is beneficial for leveraging the high speed, low latency, and low latency jitter characteristics of the fiber optic communication of the interface expansion communication unit 103 to achieve real-time interaction of sensing signals between the core control unit 101 and the interface expansion box 102. Moreover, it effectively reduces the interference of the wiring of other devices in the motor simulator 100 other than the core control unit 101 on the sensing signals transmitted in the interface expansion communication unit 103, further improving the accuracy of the sensing signals transmitted between the core control unit 101 and the interface expansion box 102. Furthermore, distributing the module that implements the sensing signal simulation algorithm function and the module that implements the sensing signal interface logic on two FPGA chips further reduces the design pressure on the core control unit 101. On the other hand, the second FPGA chip 112 is designed to implement the sensing signal interface logic. In cases where there are many types of sensing signals, the second FPGA chip 112 can be used to design interfaces that match various types of motors under test 104, which is beneficial to improving the versatility of the motor simulation device.

[0076] Another embodiment of this disclosure also provides a motor simulation method, which can be implemented by the above-mentioned motor simulation device. The motor simulation method provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0077] refer to Figure 1 The motor simulation method is applied to the motor simulation device provided in the aforementioned embodiment. The motor simulation method includes: realizing the interaction of sensor signals between the interface expansion box 102 and the motor under test 104 by means of the sensor signal transmission unit 105; realizing optical fiber communication between the core control unit 101 and the interface expansion box 102 by means of the interface expansion communication unit 103; and realizing the simulation of the motor under test 104 by means of information interaction between the motor simulator and the motor under test 104.

[0078] By leveraging the high speed, low latency, and low jitter characteristics of fiber optic communication in the interface expansion communication unit 103, low latency and low jitter of the sensing signals over long distances are ensured, guaranteeing the synchronization of the sensing signals. This, in turn, improves the simulation accuracy of the motor under test 104 using the motor simulation method. Furthermore, the interface expansion box 102, located outside the motor simulator 100, effectively reduces interference from wiring of other devices within the motor simulator 100 (excluding the core control unit 101) on the sensing signals transmitted in the interface expansion communication unit 103. This further improves the accuracy of the sensing signals transmitted between the core control unit 101 and the interface expansion box 102, thereby further enhancing the simulation accuracy of the motor under test 104 using the motor simulation method.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A motor simulation device, characterized in that, include: A motor simulator, the motor simulator including a core control unit, the core control unit including a first FPGA chip; An interface expansion box, located outside the motor simulator, includes a second FPGA chip; An interface expansion communication unit is configured to enable fiber optic communication between the core control unit and the interface expansion box. The motor under test and the sensor signal transmission unit are configured to enable the interaction of sensor signals between the interface expansion box and the motor under test. The first FPGA chip is configured to implement a sensor signal simulation algorithm, as well as the fiber optic user layer protocol and physical layer protocol on the core control unit side; the second FPGA chip is configured to implement sensor signal interface logic, as well as the fiber optic user layer protocol and physical layer protocol on the interface expansion box side. The core control unit is provided with a first high-speed serial interface, and the interface expansion box is provided with a second high-speed serial interface. The first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock. The interface extension communication unit includes a first high-speed optical module, a transceiver optical fiber, and a second high-speed optical module. The first high-speed optical module is connected to the first high-speed serial interface, the second high-speed optical module is connected to the second high-speed serial interface, and the transceiver optical fiber connects the first high-speed optical module and the second high-speed optical module.

2. The motor simulation device according to claim 1, characterized in that, The first FPGA chip includes a sensor signal simulation algorithm module, a first user layer protocol transmission module, a first user layer protocol reception module, and a first physical layer communication module; The first physical layer communication module is configured to receive a first signal transmitted by the interface expansion box based on the interface expansion communication unit. The first user layer protocol receiving module is configured to receive the first signal from the first physical layer communication module and transmit the first signal to the sensor signal simulation algorithm module; The sensor signal simulation algorithm module is configured to simulate a sensor signal based on the first signal and output a second signal to the first user layer protocol sending module. The first user layer protocol sending module is configured to receive the second signal from the sensor signal simulation algorithm module and transmit it to the first physical layer communication module; The first physical layer communication module is also configured to transmit the second signal to the interface expansion box based on the interface expansion communication unit.

3. The motor simulation device according to claim 2, characterized in that, The sensor signal simulation algorithm module is further configured to receive a control signal and perform sensor signal simulation based on the control signal and the first signal.

4. The motor simulation device according to claim 1, characterized in that, The second FPGA chip includes a sensor signal hardware interface design module, a second user layer protocol transmission module, a second user layer protocol reception module, and a second physical layer communication module; The second physical layer communication module is configured to receive a second signal transmitted by the core control unit based on the interface extended communication unit. The second user layer protocol receiving module is configured to receive the second signal from the second physical layer communication module and transmit the second signal to the sensor signal hardware interface design module. The sensing signal hardware interface design module is configured to receive the second signal from the second user layer protocol receiving module and receive the first signal transmitted by the motor under test. The second user layer protocol sending module is configured to receive the first signal from the sensor signal hardware interface design module and transmit it to the second physical layer communication module. The second physical layer communication module is also configured to transmit the first signal to the core control unit based on the interface extension communication unit.

5. The motor simulation device according to claim 4, characterized in that, The sensor signal hardware interface design module is further configured to design different sensor signal interfaces for sensor signal interaction with the motor under test based on the different types of the sensor signals, receive the first signal transmitted by the motor under test from some of the sensor signal interfaces, and transmit the received second signal to the remaining sensor signal interfaces.

6. The motor simulation device according to claim 5, characterized in that, The sensing signal hardware interface design module includes an interface timing logic design unit and a signal conditioning unit; The interface timing logic design unit is configured to design different interface timing logic based on the different types of the sensing signals. The signal conditioning unit is configured to condition the first signal and the second signal.

7. The motor simulation device according to claim 6, characterized in that, The interface timing logic design unit includes a first timing logic design subunit and a second timing logic design subunit; the signal conditioning unit includes a first conditioning subunit and a second conditioning subunit; The first signal is transmitted sequentially from a portion of the sensor signal interface, the first conditioning subunit, and the first timing logic design subunit to the second user layer protocol transmission module; the second signal is transmitted sequentially from the second user layer protocol receiving module, the second timing logic design subunit, and the second conditioning subunit to the remaining sensor signal interface.

8. The motor simulation device according to claim 1, characterized in that, The sensing signals include position sensing signals or temperature sensing signals.

9. A method for simulating an electric motor, characterized in that, The motor simulation device applied to any one of claims 1 to 8, the motor simulation method comprising: The sensor signal transmission unit is used to realize the interaction of sensor signals between the interface expansion box and the motor under test; The interface expansion communication unit is used to achieve optical fiber communication between the core control unit and the interface expansion box. The simulation of the motor under test is achieved through information interaction between the motor simulator and the motor under test.

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