Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure comprises: forming a substrate; forming a drift region inside the substrate; forming a body region in the drift region, wherein the body region and the drift region have different doping types; forming a side gate structure in the body region; forming a source region in the body region, wherein the source region is adjacent to the side gate structure and is located on a side of the side gate structure adjacent to the drift region, wherein the depth of the bottom surface of the source region is less than the depth of the bottom surface of the side gate structure; and forming a drain region in the drift region. By adopting the above technical solution, a conducting channel can be formed below the source region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] A voltage-controlled power device refers to a semiconductor device whose conduction state and power output can be controlled by a voltage signal. Voltage-controlled power devices are widely used in power electronics and automatic control systems.

[0003] How to design voltage-controlled power devices is an issue worth discussing. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can form a conducting channel below a source region.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes:

[0006] forming a base;

[0007] forming a drift region within the substrate;

[0008] A body region is formed in the drift region, and the doping type of the body region is different from that of the drift region;

[0009] forming a side gate structure in the body region;

[0010] forming a source region in the body region, the source region being adjacent to the side gate structure and being located on a side of the side gate structure adjacent to the drift region, wherein a depth of a bottom surface of the source region is less than a depth of a bottom surface of the side gate structure;

[0011] A drain region is formed in the drift region.

[0012] Optionally, a side gate structure is formed in the body region, comprising:

[0013] forming a side gate trench on the surface of the body region;

[0014] A side gate dielectric layer covering the side gate structure on the side wall surface and the bottom surface of the side gate trench;

[0015] The side gate trench is filled to form a side gate body of the side gate structure.

[0016] Optionally, forming a substrate comprises:

[0017] providing a first substrate;

[0018] forming a bottom gate material layer of a bottom gate structure in the first substrate;

[0019] A bottom gate dielectric layer of a bottom gate structure is formed, wherein the bottom gate dielectric layer covers the bottom gate material layer;

[0020] A second substrate is formed, the second substrate covers the bottom gate dielectric layer, wherein the drift region and the body region are located in the second substrate.

[0021] Optionally, before forming the source region in the body region, the forming method further includes:

[0022] Forming a plug hole on the surface of the second substrate, wherein the plug hole is spaced apart from the drift region and exposes the surface of the bottom gate material layer;

[0023] The plug hole is filled to obtain a bottom gate plug of a bottom gate structure.

[0024] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the drift region and the body region belong to the semiconductor unit;

[0025] Before forming the source region in the body region, the forming method further includes:

[0026] An isolation ring groove is formed on the surface of the second substrate, wherein the isolation ring groove is arranged around the semiconductor unit;

[0027] The isolation ring groove is filled to obtain the isolation ring.

[0028] Optionally, the forming method further comprises:

[0029] A plug hole is formed on the surface of the isolating ring.

[0030] Optionally, forming a bottom gate material layer in the first substrate includes:

[0031] forming a bottom gate trench on the surface of the first substrate;

[0032] The bottom gate trench is filled to obtain a bottom gate material layer.

[0033] Optionally, before forming the body region in the drift region, the forming method further includes:

[0034] forming a top gate dielectric layer of a top gate structure on the drift region;

[0035] forming a top gate body of a top gate structure on the top gate dielectric layer;

[0036] The top gate structure covers the body region and is spaced apart from the side gate structure.

[0037] Optionally, the forming method further comprises:

[0038] forming an extraction region in the source region, wherein the bottom surface of the extraction region covers the body region;

[0039] The extraction region and the body region have the same doping type, and the doping concentration of the extraction region is higher than that of the body region.

[0040] Optionally, the semiconductor structure is a symmetrical LDMOS device, the symmetrical LDMOS device includes two symmetrical semiconductor units, the side gate structure belongs to the semiconductor unit, and the two semiconductor units share the same side gate structure.

[0041] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes:

[0042] substrate;

[0043] a drift region, the drift region being located within the substrate;

[0044] a body region, the body region being located in the drift region and having a doping type different from that of the drift region;

[0045] a side gate structure, the side gate structure being located within the body region;

[0046] A source region, the source region is located in the body region, the source region is adjacent to the side gate structure, and is located on a side of the side gate structure adjacent to the drift region, wherein a depth of a bottom surface of the source region is less than a depth of a bottom surface of the side gate structure;

[0047] A drain region is located in the drift region.

[0048] Optionally, the surface of the body region has a side gate trench;

[0049] The side gate structure comprises:

[0050] A side gate dielectric layer covering the side wall surface and the bottom surface of the side gate trench;

[0051] A side gate body is located in the side gate trench.

[0052] Optionally, the semiconductor structure further includes:

[0053] A bottom gate structure, the bottom gate structure comprising a bottom gate material layer and a bottom gate dielectric layer;

[0054] The substrate comprises:

[0055] A first substrate, wherein the bottom gate material layer is located in the first substrate, and the bottom gate dielectric layer covers the bottom gate material layer;

[0056] A second substrate covers the bottom gate dielectric layer.

[0057] Optionally, a plug hole is provided on the surface of the second substrate, wherein the plug hole is spaced apart from the drift region and exposes the surface of the bottom gate material layer;

[0058] The bottom gate structure further includes a bottom gate plug, which is located in the plug hole and connected to the bottom gate material layer.

[0059] Optionally, the bottom gate plug is made of the same material as the bottom gate material layer.

[0060] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the drift region and the body region belong to the semiconductor unit;

[0061] The first substrate surface has an isolation ring groove, and the isolation ring groove is arranged around the semiconductor unit;

[0062] An isolation ring is arranged in the isolation ring groove.

[0063] Optionally, the bottom gate structure further comprises:

[0064] A bottom gate plug passes through the isolation ring.

[0065] Optionally, the semiconductor structure further includes a top gate structure, wherein the top gate structure includes:

[0066] A top gate dielectric layer, wherein the top gate dielectric layer covers the drift region and the body region, and the top gate structure and the side gate structure are spaced apart;

[0067] A top gate body covers the top gate dielectric layer.

[0068] Optionally, the semiconductor structure further includes:

[0069] an extraction region, wherein the extraction region is located in the source region and a bottom surface of the extraction region covers the body region;

[0070] The extraction region and the body region have the same doping type, and the doping concentration of the extraction region is higher than that of the body region.

[0071] Optionally, the semiconductor structure is a symmetrical LDMOS device, the symmetrical LDMOS device includes two symmetrical semiconductor units, the side gate structure belongs to the semiconductor unit, and the two semiconductor units share the same side gate structure.

[0072] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0073] By arranging the source region adjacent to the side gate structure and the depth of the bottom surface of the source region being less than the depth of the bottom surface of the side gate dielectric layer of the side gate structure, the side wall of the side gate structure located below the source region can be exposed, thereby forming a conducting channel in the body region adjacent to the side gate structure below the source region.

[0074] Furthermore, the bottom gate structure can increase the concentration of the first type of carriers in the body region between the bottom gate dielectric layer and the side gate dielectric layer, and reduce the on-resistance of the conduction channel controlled by the side gate structure and located below the source region; at the same time, the bottom gate structure can also increase the concentration of the first type of carriers in the drift region on the adjacent side of the bottom gate dielectric layer, and reduce the on-resistance in the drift region on the adjacent side of the bottom gate dielectric layer, as well as the on-resistance of the conduction path corresponding to the side gate structure, thereby further reducing the on-resistance of the semiconductor structure.

[0075] Furthermore, by adjusting the position of the external voltage terminal of the bottom gate structure through the bottom gate plug, the external voltage terminals of the bottom gate structure and the top gate structure can be located on the same side.

[0076] Furthermore, a plug hole is formed on the surface of the isolation ring, so that the isolation ring can achieve electrical isolation between the bottom gate plug and the drift region along a direction parallel to the surface of the second substrate.

[0077] Furthermore, the extraction region can extract the second type of carriers accumulated in the body region, reduce the probability of recombination of the second type of carriers with the first type of carriers in the body region, increase the cross-sectional area of ​​the conduction channel controlled by the side gate structure and the concentration of the first type of carriers in the conduction channel, thereby further reducing the on-resistance of the conduction channel corresponding to the side gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0079] Figure 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0080] Figures 2 to 4 is a schematic diagram of a cross-sectional structure of a first part of devices corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention;

[0081] Figure 5 yes Figure 4 A top view of a semiconductor structure is shown;

[0082] Figure 6 is along Figure 5 A schematic diagram of the cross-sectional structure in the B1-B2 direction is shown;

[0083] Figure 7 It is a schematic diagram of the cross-sectional structure of the second part of the device corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0084] Description of reference numerals:

[0085] Substrate 100, first substrate 110, second substrate 120, drift region 121, body region 122, source region 123, drain region 124, extraction region 125, isolation ring 130; bottom gate structure 200, bottom gate material layer 210, bottom gate dielectric layer 220, bottom gate plug 230, bottom plug extension 240; top gate structure 300, top gate dielectric layer 310, top field dielectric layer 320, top gate body 330; side gate structure 400, side gate dielectric layer 410, side gate body 420. DETAILED DESCRIPTION

[0086] As mentioned earlier, how to design voltage-controlled power devices is an issue worth discussing.

[0087] In a specific application scenario, taking LDMOS as an example, LDMOS has a drift region, a body region, a source region and a drain region. A gate structure is arranged on the surface of the drift region and the surface of the body region. The gate structure can form a conductive channel on the surface of the body region on one side of the source region, which is the side of the source region close to the drift region.

[0088] In an embodiment of the present invention, by setting a source region adjacent to the side gate structure and the depth of the bottom surface of the source region being less than the depth of the bottom surface of the side gate dielectric layer of the side gate structure, the side wall of the side gate structure located below the source region can be exposed, thereby forming a conductive channel in the body region adjacent to the side gate structure below the source region.

[0089] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0090] Reference Figure 1 , Figure 1 1 is a flow chart of a method for forming a semiconductor device in an embodiment of the present invention. The method for forming a semiconductor device may include steps S11 to S16:

[0091] Step S11: forming a substrate;

[0092] Step S12: forming a drift region inside the substrate;

[0093] Step S13: forming a body region in the drift region, wherein the body region and the drift region have different doping types;

[0094] Step S14: forming a side gate structure in the body region;

[0095] Step S15: forming a source region in the body region, the source region is adjacent to the side gate structure and is located on a side of the side gate structure adjacent to the drift region, wherein a depth of a bottom surface of the source region is less than a depth of a bottom surface of the side gate structure;

[0096] Step S16: forming a drain region in the drift region.

[0097] The following combination Figures 2 to 7 The above-mentioned formation method is explained.

[0098] Figures 2 to 4 is a schematic diagram of a cross-sectional structure of a first part of devices corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention; Figure 5 yes Figure 4 A top view of a semiconductor structure is shown, wherein Figure 4 is along Figure 5 A schematic diagram of the cross-sectional structure in the direction A1-A2 is shown; Figure 6 is along Figure 5 A schematic diagram of the cross-sectional structure in the B1-B2 direction is shown; Figure 7 It is a schematic diagram of the cross-sectional structure of the second part of the device corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0099] Reference Figure 2 , forming a substrate 100.

[0100] Specifically, the substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0101] Specifically, the steps of forming the substrate 100 may include: providing a first substrate 110; forming a bottom gate material layer 210 of a bottom gate structure 200 in the first substrate 110; forming a bottom gate dielectric layer 220 of the bottom gate structure 200, wherein the bottom gate dielectric layer 220 covers the bottom gate material layer 210; and forming a second substrate 120, wherein the second substrate 120 covers the bottom gate dielectric layer 220.

[0102] In some embodiments, the first substrate 110 may be a silicon substrate, or the material of the first substrate 110 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The first substrate 110 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0103] Specifically, the step of forming the bottom gate material layer 210 may include: etching on the surface of the first substrate 110 to form a bottom gate trench (not shown); and filling the bottom gate trench to form the bottom gate material layer 210 .

[0104] In some embodiments, the material of the bottom gate dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, or aluminum oxide.

[0105] In some embodiments, the bottom gate dielectric layer 220 and the second substrate 120 may be implemented in a variety of ways, such as Silicon Direct Bonding (SDB) or Separation by Implantation of Oxygen (SIMOX).

[0106] In some embodiments, the second substrate 120 may be a silicon substrate, or the material of the second substrate 120 may further include germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0107] In some embodiments, the doping type of the second substrate 120 may be P-type doping or N-type doping.

[0108] It should be noted that in the following description, P-type doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used for the second substrate 120 .

[0109] Continue to refer to Figure 2 , an isolation ring 130 is formed on the second substrate 120 .

[0110] Specifically, the isolation ring 130 is a ring structure, which can achieve electrical isolation between the inside and outside of the ring.

[0111] In some embodiments, the material of the isolation ring 130 may be silicon dioxide.

[0112] Furthermore, the step of forming the isolation ring 130 may include: etching the surface of the second substrate 120 to obtain a groove for the isolation ring 130 ; and filling the groove for the isolation ring 130 to obtain the isolation ring 130 .

[0113] Reference Figure 3 , a drift region 121 is formed in the second substrate 120 .

[0114] In some embodiments, the drift region 121 may be formed in the groove of the isolation ring 130 by using an ion implantation process.

[0115] In some embodiments, the doping type of the drift region 121 may be N-type doping or P-type doping.

[0116] It should be noted that, in the following description, N-type trench doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used in the drift region 121 .

[0117] Continue to refer to Figure 3 , a top gate dielectric layer 310 and a top field dielectric layer 320 of the top gate structure 300 are formed on the drift region 121 ; and a top gate body 330 of the top gate structure 300 is formed on the top gate dielectric layer 310 and the top field dielectric layer 320 .

[0118] Specifically, the top gate structure 300 is adapted to receive an external control voltage.

[0119] Continue to refer to Figure 3 , a body region 122 is formed in the drift region 121 .

[0120] The body region 122 and the drift region 121 have different doping types. The body region 122 is located on one side of the top field dielectric layer 320 , and the side is adjacent to the top gate dielectric layer 310 .

[0121] Specifically, the top gate structure 300 can form a conductive channel on the surface of the body region 122 .

[0122] Specifically, the step of forming the body region 122 may include: forming the body region 122 in the drift region 121 exposed on the side of the top gate dielectric layer 310 away from the top field dielectric layer 320 ; and performing annealing treatment on the body region 122 .

[0123] Specifically, a portion of the formed body region 122 is located below the top gate structure 300 , and the top gate structure 300 is suitable for forming a conducting channel on the surface of the body region 122 covered by the top gate structure 300 .

[0124] Reference Figure 4 , a side gate structure 400 is formed in the body region 122 .

[0125] Specifically, the side gate structure 400 is located in the body region 122 and can form a conducting channel in the body region 122 .

[0126] Specifically, forming the side gate structure 400 may include: forming a side gate trench (not shown) on the surface of the body region 122; covering the side gate dielectric layer 410 of the side gate structure 400 on the side wall surface and bottom surface of the side gate trench; and filling the side gate trench to form a side gate body 420 of the side gate structure 400.

[0127] Combined with reference Figures 4 to 6 , forming a bottom gate plug 230 of the bottom gate structure 200 .

[0128] One end of the bottom gate plug 230 penetrates the second substrate 120 and the bottom gate dielectric layer 220 and is connected to the bottom gate material layer 210 , and the other end is exposed to the surface of the second substrate 120 on the same side as the top gate structure 300 .

[0129] Specifically, by adjusting the position of the external voltage terminal of the bottom gate structure 200 through the bottom gate plug 230 , the external voltage terminals of the bottom gate structure 200 and the top gate structure 300 can be located on the same side.

[0130] In some embodiments, the side gate structure 400 is spaced apart from the top gate structure 300 .

[0131] Specifically, the spacing arrangement can reduce the impact between the side gate structure 400 and the top gate structure 300 .

[0132] Specifically, the step of forming the bottom gate plug 230 may include: forming a plug hole (not shown) on the surface of the second substrate 120 , the plug hole exposing the surface of the bottom gate material layer 210 ; and filling the plug hole to obtain the bottom gate plug 230 .

[0133] In some embodiments, the plug hole is spaced apart from the drift region 121 .

[0134] Specifically, in this way, a gap can be provided between the bottom gate plug 230 to be formed subsequently and the drift region 121 , thereby reducing the influence of the bottom gate plug 230 on the drift region 121 .

[0135] In some embodiments, plug holes are formed on the surface of the isolation ring 130 .

[0136] Specifically, a plug hole is formed on the surface of the isolation ring 130 , so that the isolation ring 130 can achieve electrical isolation between the bottom gate plug 230 and the drift region 121 along a direction parallel to the surface of the second substrate 120 .

[0137] In some embodiments, the material of the bottom gate plug 230 and the material of the bottom gate material layer 210 may be the same or different.

[0138] In some embodiments, there may be a plurality of bottom gate plugs 230 , and the plurality of bottom gate plugs 230 are spaced apart and distributed along the extending direction of the isolation ring 130 .

[0139] In some embodiments, the bottom gate structure 200 further has a bottom plug extension 240 . The bottom plug extension 240 is located on the surface of the second substrate 120 . The bottom plug extension 240 is connected to the bottom gate plug 230 and has a larger cross-sectional area than the bottom gate plug 230 .

[0140] Reference Figure 7, a source region 123 is formed in the body region 122 exposed by the top gate structure 300 ; and a drain region 124 is formed in the drift region 121 exposed by the top gate structure 300 .

[0141] The source region 123 and the body region 122 have different doping types, the drain region 124 and the source region 123 have the same doping type, and the doping concentration of the drain region 124 is higher than that of the drift region 121 .

[0142] In some embodiments, the source region 123 and the drain region 124 may be formed in various orders. For example, the drain region 124 may be formed during the process of forming the source region 123. For example, the source region 123 may be formed after the drain region 124. For example, the source region 123 may be formed before the drain region 124.

[0143] In some embodiments, the source region 123 is adjacent to the side gate structure 400 and is located on a side of the side gate structure 400 adjacent to the drift region 121 , wherein the depth of the bottom surface of the source region 123 is less than the depth of the bottom surface of the side gate structure 400 , and the top surface of the source region 123 is flush with the top surface of the side gate structure 400 .

[0144] Specifically, the depth of the bottom surface of the source region 123 is less than the depth of the bottom surface of the side gate dielectric layer 410, which can expose the side wall of the side gate structure 400 located below the source region 123, so that a conductive channel C2 can be formed in the body region 122 adjacent to the side gate structure 400 below the source region 123, which means that the semiconductor structure has at least a conductive channel C1 controlled by the top gate structure 300 and located on the side of the source region 123 close to the drift region 121, and a conductive channel C2 controlled by the side gate structure 400 and located below the source region 123. By setting a plurality of conductive channels, the on-resistance of the semiconductor structure can be reduced.

[0145] It should be noted that the conduction path corresponding to the side gate structure 400 includes the conduction channel C2 controlled by the side gate structure 400 and located below the source region 123 , and the drift region 121 adjacent to the bottom gate dielectric layer 220 , which is located on the side of the bottom gate dielectric layer 220 adjacent to the side gate structure 400 .

[0146] In some embodiments, the bottom gate material layer 210 and the bottom gate dielectric layer 220 are both located below the side gate structure 400 .

[0147] The bottom gate structure 200 can increase the concentration of the first type of carriers in the body region 122 between the bottom gate dielectric layer 220 and the side gate dielectric layer 410, and reduce the on-resistance of the conduction channel C2 controlled by the side gate structure 400 and located below the source region 123; at the same time, the bottom gate structure 200 can also increase the concentration of the first type of carriers in the drift region 121 adjacent to the bottom gate dielectric layer 220, and reduce the on-resistance in the drift region 121 adjacent to the bottom gate dielectric layer 220, as well as the on-resistance of the conduction path corresponding to the side gate structure 400, thereby further reducing the on-resistance of the semiconductor structure.

[0148] Continue to refer to Figure 7 , an extraction region 125 is formed in the source region 123.

[0149] The bottom surface of the extraction region 125 covers the body region 122 . The extraction region 125 and the body region 122 have the same doping type, and the doping concentration is higher than that of the body region 122 .

[0150] Specifically, the extraction region 125 can extract the second type of carriers accumulated in the body region 122, reduce the probability of the second type of carriers in the body region 122 to recombine with the first type of carriers, increase the cross-sectional area of ​​the conduction channel C2 controlled by the side gate structure 400 and the concentration of the first type of carriers in the conduction channel C2, thereby further reducing the on-resistance of the conduction channel C2 corresponding to the side gate structure 400.

[0151] It should be noted that the first type of carriers and the second type of carriers are of different types. For example, the first type of carriers may be electrons, and the second type of carriers may be holes.

[0152] In some embodiments, ion implantation may be performed on the source region 123 to obtain an extraction region 125 within the source region 123 .

[0153] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 121 , a body region 122 , a source region 123 , a drain region 124 , an extraction region 125 , a bottom gate structure 200 , a top gate structure 300 , and a side gate structure 400 .

[0154] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units, and the two symmetrical semiconductor units share the same side gate structure 400 and bottom gate structure 200 .

[0155] Specifically, sharing the same side gate structure 400 and the bottom gate structure 200 can improve the current driving capability of the LDMOS device, and can also simplify the layout and improve the integration of the device.

[0156] It should be noted that, in addition to the shared side gate structure 400 and the bottom gate structure 200, each semiconductor unit in the symmetric LDMOS device may have its own drift region 121, body region 122, source region 123, drain region 124, extraction region 125 and top gate structure 300, and the above-mentioned parts may be completely consistent or not completely consistent.

[0157] Furthermore, the semiconductor unit is located inside the isolation ring 130 .

[0158] Specifically, the isolation ring 130 is disposed around the semiconductor unit, and can achieve electrical isolation between semiconductor units of adjacent semiconductor structures.

[0159] In an embodiment of the present invention, a semiconductor structure may also be provided. Figures 2 to 7 The semiconductor structure may include: a substrate 100; a drift region 121, wherein the drift region 121 is located in the substrate; a body region 122, wherein the body region 122 is located in the drift region 121 and has a doping type different from that of the drift region 121; a side gate structure 400, wherein the side gate structure 400 is located in the body region 122; a source region 123, wherein the source region 123 is located in the body region 122, the source region 123 is adjacent to the side gate structure 400, and is located on a side of the side gate structure 400 adjacent to the drift region 121, wherein a depth of a bottom surface of the source region 123 is less than a depth of a bottom surface of a side gate dielectric layer 410; and a drain region 124, wherein the drain region 124 is located in the drift region 121.

[0160] In some embodiments, the surface of the body region 122 may have a side gate trench (not shown); the side gate structure 400 may include: a side gate dielectric layer 410 covering the sidewall surface and the bottom surface of the side gate trench; and a side gate body 420 located in the side gate trench.

[0161] In some embodiments, the semiconductor structure may further include: a bottom gate structure 200, the bottom gate structure 200 including a bottom gate material layer 210 and a bottom gate dielectric layer 220; the substrate 100 may include: a first substrate 110, the bottom gate material layer 210 is located in the first substrate 110, and the bottom gate dielectric layer 220 covers the bottom gate material layer 210; and a second substrate 120, the second substrate 120 covers the bottom gate dielectric layer 220.

[0162] In some embodiments, the surface of the second substrate 120 may have a plug hole (not shown), which is spaced apart from the drift region 121 and exposes the surface of the bottom gate material layer 210; the bottom gate structure 200 also includes a bottom gate plug 230, which is located in the plug hole and connected to the bottom gate material layer 210.

[0163] In some embodiments, the bottom gate plug 230 is made of the same material as the bottom gate material layer 210 .

[0164] In some embodiments, the semiconductor structure can be an LDMOS device, which includes a semiconductor unit, and the drift region 121 and the body region 122 belong to the semiconductor unit; the surface of the first substrate 110 has an isolation ring 130 groove, and the isolation ring 130 groove is arranged around the semiconductor unit; the isolation ring 130 groove has an isolation ring 130.

[0165] In some embodiments, the bottom gate structure 200 may further include: a bottom gate plug 230 , wherein the bottom gate plug 230 passes through the isolation ring 130 .

[0166] In some embodiments, the semiconductor structure may further include: a top gate structure 300, the top gate structure 300 includes: a top gate dielectric layer 310, the top gate dielectric layer 310 covers the drift region 121 and the body region 122, and the top gate structure 300 is spaced apart from the side gate structure 400; a top gate body 330, the top gate body 330 covers the top gate dielectric layer 310.

[0167] In some embodiments, the semiconductor structure may further include: an extraction region 125 , the extraction region 125 is located in the source region 123 and the bottom surface of the extraction region 125 covers the body region 122 ; wherein the extraction region 125 and the body region 122 have the same doping type and the doping concentration of the extraction region 125 is higher than that of the body region 122 .

[0168] In some embodiments, the semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The side gate structure 400 belongs to the semiconductor unit, and the two semiconductor units share the same side gate structure 400 .

[0169] It should be noted that for the principle, specific implementation and beneficial effects of the semiconductor structure, please refer to the previous article and Figures 2 to 7 The description related to the method for forming the semiconductor structure shown is not repeated here.

[0170] It should be noted that the semiconductor structure in the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0171] It will be understood that the terms "bottom, top, side" herein are only used to indicate the relative positions of the gate structures in the cross-sectional structural diagram shown in the accompanying drawings, for illustration in the embodiments of the present invention, and do not constitute limitations on the actual positions of the gate structures.

[0172] It is understandable that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0173] It is understood that the "multiple" mentioned herein refers to two or more than two. The first, second, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0174] It can be understood that the above describes multiple implementation schemes provided by the embodiments of the present invention, and the various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as the implementation schemes disclosed and open to the public by the present invention.

[0175] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Forming a substrate, wherein forming the substrate comprises: providing a first substrate; forming a bottom gate material layer of a bottom gate structure in the first substrate; forming a bottom gate dielectric layer of the bottom gate structure, wherein the bottom gate dielectric layer covers the bottom gate material layer; forming a second substrate, wherein the second substrate covers the bottom gate dielectric layer; forming a drift region inside the substrate; forming a body region in the drift region, wherein the body region has a different doping type from that of the drift region, wherein the drift region and the body region are located in the second substrate; forming a side gate structure in the body region; forming a source region in the body region, the source region being adjacent to the side gate structure and being located on a side of the side gate structure adjacent to the drift region, wherein a depth of a bottom surface of the source region is less than a depth of a bottom surface of the side gate structure; forming a drain region in the drift region; Before forming the source region in the body region, the method further includes: forming a plug hole on the surface of the second substrate, wherein the plug hole is spaced apart from the drift region and exposes the surface of the bottom gate material layer; and filling the plug hole to obtain a bottom gate plug of the bottom gate structure.

2. The forming method according to claim 1, characterized in that: forming a side gate structure in the body region, comprising: forming a side gate trench on the surface of the body region; A side gate dielectric layer covering the side gate structure on the side wall surface and the bottom surface of the side gate trench; The side gate trench is filled to form a side gate body of the side gate structure.

3. The forming method according to claim 1, characterized in that: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the drift region and the body region belong to the semiconductor unit; Before forming the source region in the body region, the method further includes: An isolation ring groove is formed on the surface of the second substrate, wherein the isolation ring groove is arranged around the semiconductor unit; The isolation ring groove is filled to obtain an isolation ring.

4. The forming method according to claim 3, characterized in that: The method further comprises: A plug hole is formed on the surface of the isolation ring.

5. The forming method according to claim 1, characterized in that: Forming a bottom gate material layer in the first substrate, comprising: forming a bottom gate trench on the surface of the first substrate; The bottom gate trench is filled to obtain the bottom gate material layer.

6. The forming method according to claim 1, characterized in that: Before forming a body region in the drift region, the method further includes: forming a top gate dielectric layer of a top gate structure on the drift region; forming a top gate body of the top gate structure on the top gate dielectric layer; The top gate structure covers the body region and is spaced apart from the side gate structure.

7. The forming method according to claim 1, characterized in that: The method further comprises: forming an extraction region in the source region, wherein the bottom surface of the extraction region covers the body region; The extraction region and the body region have the same doping type, and the doping concentration of the extraction region is higher than that of the body region.

8. The forming method according to claim 1, characterized in that: The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The side gate structure belongs to the semiconductor unit, and the two semiconductor units share the same side gate structure.

9. A semiconductor structure, characterized in that: include: substrate; a drift region, the drift region being located within the substrate; a body region, the body region being located in the drift region and having a doping type different from that of the drift region; a side gate structure, the side gate structure being located within the body region; A source region, the source region is located in the body region, the source region is adjacent to the side gate structure, and is located on a side of the side gate structure adjacent to the drift region, wherein a depth of a bottom surface of the source region is less than a depth of a bottom surface of the side gate structure; a drain region, the drain region being located in the drift region; A bottom gate structure, wherein the bottom gate structure comprises a bottom gate material layer, a bottom gate dielectric layer and a bottom gate plug; Wherein, the substrate comprises: a first substrate, the bottom gate material layer is located in the first substrate, the bottom gate dielectric layer covers the bottom gate material layer; a second substrate, the second substrate covers the bottom gate dielectric layer; The second substrate surface has a plug hole, the plug hole is spaced apart from the drift region and exposes the surface of the bottom gate material layer; the bottom gate plug is located in the plug hole and connected to the bottom gate material layer.

10. The semiconductor structure according to claim 9, characterized in that: The surface of the body region has a side gate trench; The side gate structure comprises: A side gate dielectric layer covering the side wall surface and the bottom surface of the side gate trench; A side gate body is located in the side gate trench.

11. The semiconductor structure according to claim 9, characterized in that: The bottom gate plug is made of the same material as the bottom gate material layer.

12. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the drift region and the body region belong to the semiconductor unit; The first substrate surface has an isolation ring groove, and the isolation ring groove is arranged around the semiconductor unit; An isolation ring is arranged in the isolation ring groove.

13. The semiconductor structure according to claim 12, characterized in that: The bottom gate plug passes through the isolation ring.

14. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further includes a top gate structure, wherein the top gate structure includes: A top gate dielectric layer, wherein the top gate dielectric layer covers the drift region and the body region, and the top gate structure and the side gate structure are spaced apart; A top gate body covers the top gate dielectric layer.

15. The semiconductor structure according to claim 9, characterized in that The semiconductor structure further comprises: an extraction region, wherein the extraction region is located in the source region and a bottom surface of the extraction region covers the body region; The extraction region and the body region have the same doping type, and the doping concentration of the extraction region is higher than that of the body region.

16. The semiconductor structure according to claim 9, characterized in that The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The side gate structure belongs to the semiconductor unit, and the two semiconductor units share the same side gate structure.

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