Method, apparatus and computer readable storage medium for processing a video

Abstract

The present disclosure relates to a method, apparatus and computer readable storage medium for processing a video. The method comprises: parsing a bitstream of the video to determine information indicating whether at least one image frame is referenced by a subsequent image frame; decoding the bitstream to obtain the at least one image frame when the information indicates that the at least one image frame is not referenced by the subsequent image frame; and transmitting the at least one image frame to a display module for displaying the at least one image frame without storing the at least one image frame to an off-chip memory. According to the above scheme, power consumption of a processing device in a video processing process can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of video processing technology, and more specifically to a method, apparatus, and computer-readable storage medium for processing video. Background Technology

[0002] As the performance of smart terminal devices such as mobile phones and tablets gradually improves, people can watch local videos or online videos anytime, anywhere through these devices. With increasingly sophisticated video quality, high-resolution, high-frame-rate, and high-bitrate videos are constantly emerging, providing users with a better video viewing experience while also placing higher demands on the performance of terminal devices.

[0003] Currently, due to limitations in terminal device size and battery technology, terminal devices face extremely stringent requirements regarding power consumption and battery life. Prolonged video viewing leads to rapid battery drain and shortened battery life, causing significant anxiety for users. Therefore, reducing power consumption for video playback and improving battery life is a key technical challenge for enhancing the user experience of smart terminal devices. Summary of the Invention

[0004] In view of the above problems, at least in order to reduce the impact of video processing on the battery life of terminal devices, embodiments of this disclosure provide a method, apparatus, and computer-readable storage medium for processing video.

[0005] In a first aspect of this disclosure, a method for processing video is provided. The method includes: parsing a video bitstream to determine information indicating whether at least one image frame is referenced by subsequent image frames; when the information indicates that at least one image frame is not referenced by subsequent image frames, decoding the bitstream to obtain at least one image frame; and transmitting the at least one image frame to a display module for displaying the at least one image frame without storing the at least one image frame in off-chip memory.

[0006] According to embodiments of this disclosure, image frames are differentiated based on whether they will be referenced by subsequent image frames. For image frames that will not be referenced by subsequent image frames, they can be directly transmitted online to the display module without going through the slower and more power-consuming off-chip memory, thereby reducing the power consumption of the terminal device.

[0007] In one implementation of the first aspect, the method further includes: decoding the bitstream to obtain at least one image frame when the information indicates that at least one image frame is referenced by subsequent image frames; transmitting the at least one image frame to off-chip memory; and reading the at least one image frame from the off-chip memory to a display module to display the at least one image frame. In this way, stable video output can be ensured by using off-chip memory with a larger storage capacity for image frames that will be referenced by subsequent image frames.

[0008] In one implementation of the first aspect, when the information indicates that the at least one image frame is not referenced by the subsequent image frames, the method further includes: pre-synchronizing the image frames and audio before decoding the bitstream. This avoids a deterioration in user experience due to audio and video desynchronization.

[0009] In one implementation of the first aspect, at least one image frame is stored in on-chip memory without requiring it to be stored in off-chip memory. In this way, direct transmission of video data is achieved via on-chip memory.

[0010] In one implementation of the first aspect, image frames are stored in on-chip memory in the form of blocks or stripes. Since on-chip memory space is relatively limited, this method reduces the space requirements for on-chip memory.

[0011] In one implementation of the first aspect, the method further includes synchronizing the image frame and audio after storing the image frame in off-chip memory. This improves the user's viewing experience.

[0012] In a second aspect of this disclosure, an apparatus for processing video is provided. The apparatus includes a video decoding module, a display module, and a central processing unit, wherein the central processing unit is configured to: parse a video bitstream to determine information indicating whether at least one image frame is referenced by subsequent image frames; when the information indicates that at least one image frame is not referenced by subsequent image frames, decode the bitstream to obtain at least one image frame; and transmit the at least one image frame to the display module for displaying the at least one image frame without storing it in off-chip memory.

[0013] In one implementation of the second aspect, the apparatus further includes off-chip memory, wherein the central processing unit is configured to perform the following operations: decoding the bitstream to obtain at least one image frame when information indicates that at least one image frame is referenced by a subsequent image frame; transmitting at least one image frame to off-chip memory; and reading at least one image frame from off-chip memory to a display module to display at least one image frame.

[0014] In one implementation of the second aspect, the central processing unit is configured to perform the following operation: when the information indicates that the at least one image frame is not referenced by the subsequent image frame, pre-synchronize the image frame and the audio before decoding the bitstream.

[0015] In one implementation of the second aspect, the apparatus further includes an on-chip memory, wherein the central processing unit is configured to perform the following operation: at least one image frame is stored in the on-chip memory without the need to store at least one image frame in off-chip memory.

[0016] In one implementation of the second aspect, image frames are stored in on-chip memory in the form of blocks or stripes.

[0017] In one implementation of the second aspect, the central processing unit is configured to perform the following operation: after storing the image frame to off-chip memory, synchronize the image frame and the audio.

[0018] In a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method of the first aspect of this disclosure.

[0019] It should be understood that the description in the Summary Section is not intended to limit the key or essential features of the implementation of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] The above and other features, advantages, and aspects of the various implementations of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 An illustrative use case is shown in which the methods according to embodiments of this disclosure may be applied; Figure 2 A block diagram of an electronic device according to an embodiment of the present disclosure is shown; Figure 3 A schematic flowchart of a method for processing video according to an embodiment of the present disclosure is shown; Figure 4 A data flow diagram according to an embodiment of the present disclosure is shown; and Figure 5A and Figure 5B Schematic diagrams of image frame segmentation according to embodiments of the present disclosure are shown respectively. Detailed Implementation

[0021] Implementations of this disclosure will now be described in more detail with reference to the accompanying drawings. While some implementations of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the implementations set forth herein. Rather, these implementations are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and implementations of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0022] In the description of implementations of this disclosure, the term "comprising" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an implementation" or "the implementation" should be understood as "at least one implementation". The terms "first", "second", etc., may refer to different or the same objects. The term "and / or" indicates at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0023] It should be understood that some of the technical solutions provided in this application may be repeated in the following description of specific implementations, but these specific implementations should be regarded as having mutual references and can be combined with each other.

[0024] Some illustrative implementations of this disclosure are described below with reference to the accompanying drawings.

[0025] Figure 1 An illustrative usage environment in which the methods according to embodiments of this disclosure can be applied is shown. As shown, the methods of embodiments of this disclosure can be used in a terminal device 100, such as a mobile phone. A user can play videos on the terminal device 100. Such videos can be videos stored locally on the terminal device 100 or videos played online using various types of networks. Embodiments of this disclosure do not impose any particular limitation on this. As mentioned above, with the gradual increase in video resolution, frame rate, and bitrate, video playback and processing require a significant amount of power from the terminal device 100, resulting in a shorter battery life for the terminal device 100. At least to solve the above problems, embodiments of this disclosure provide a video processing solution. This solution can effectively reduce the power consumption of the terminal device 100 for video processing and improve the user experience. It should be understood that, although Figure 1 The terminal device 100 is shown in the form of a mobile phone; however, this is merely illustrative and not restrictive. The terminal device 100 may also take other forms, such as a tablet computer, a laptop computer, a desktop computer, an in-vehicle smart device, etc., and its specific form is not limited to the embodiments of this disclosure.

[0026] In the context of this disclosure, a video can be composed of multiple images arranged in a certain time sequence and audio associated with these images. These images may sometimes be referred to as "frames" or "image frames." A video can contain a stream of bitstreams (also called bitstream segments), where each bitstream may correspond to an image frame. Taking a video with a frame rate of 60 frames per second as an example, its 1 second includes 60 images arranged in a specific order. It should be noted that the methods of the embodiments of this disclosure are applicable to processing videos of various frame rates and encoded based on different protocols, and there are no particular limitations on the specific frame rate and encoding protocol of the video to be processed.

[0027] The following is for reference. Figure 2 This is a block diagram illustrating an apparatus 200 according to embodiments of the present disclosure. The apparatus 200 may be integrated into... Figure 1 Terminal device 100 in the middle. For example... Figure 2 As shown, the device 200 may include a chip 210 and an off-chip memory 206 located outside the chip 210. As shown, the chip 210 includes a central processing unit (CPU) 201 for executing program code for methods according to embodiments of the present disclosure. This program code may be stored on a non-volatile memory 208 outside the chip 210. The CPU 201 may communicate with the non-volatile memory 208, thereby allowing the non-volatile memory 208 to read the program code to execute the method steps.

[0028] Continue to refer to Figure 2 The central processing unit 201 can be coupled to the video decoding module 202, display module 203, and on-chip memory 205 integrated on the chip 210 via bus 204. It should be noted that in some embodiments, the central processing unit 201, video decoding module 202, display module 203, and on-chip memory 205 can be integrated onto the same chip 210 and coupled to each other via bus 204. In other embodiments, the central processing unit 201, video decoding module 202, display module 203, and on-chip memory 205 can be located on different chips. That is, the chip 210 can be in the form of a system-on-a-chip (SoC) or other multi-chip combination forms. The embodiments of this disclosure do not particularly limit the specific form of the chip 210, as long as it enables mutual transmission and communication between different modules on the device 200.

[0029] The following is a brief introduction to the various modules on device 200. The central processing unit 201 can perform various appropriate actions and processes based on computer program instructions stored in read-only memory or loaded into random access memory. The video decoding module 202 can be configured to decode a standard compressed video stream. The display module 203 can be configured to overlay various image frames to be displayed on the screen of terminal device 100, thereby displaying a video containing these image frames on the screen. On-chip memory 205 can be a cache or static random access memory (SRAM). Off-chip memory 206 can be dynamic random access memory (DRAM). While on-chip memory 205 has a smaller storage space than off-chip memory 206, its read / write speed is much faster, and its power consumption is much lower. Figure 2 As shown, the on-chip memory 205 and the off-chip memory 206 can be coupled to the video decoding module 202 and the display module 203 via the bus 204.

[0030] The following reference Figure 3 This describes a method 300 for processing video provided according to embodiments of the present disclosure. For example... Figure 3As shown in box 301, one or more bitstreams included in the video are parsed to determine information indicating whether the image frame corresponding to the bitstream segment to be processed is referenced by subsequent image frames. It should be noted that for a bitstream containing many image frames, it is not required to determine this information for all image frames; information can be determined for the image frame corresponding to a segment of the bitstream. For a continuous video, the content reflected by consecutive image frames often has a strong correlation, especially when the scene changes little. Therefore, in the set of image frames constituting the video, some image frames can be used as references for subsequent image frames during decoding. Of course, some image frames will not be used as references for subsequent image frames. The video bitstream includes information reflecting whether the image frame corresponding to the bitstream segment to be processed in the video will be referenced by subsequent image frames. This information about the bitstream segments in the video can be obtained based on the corresponding software syntax parsing. It should be understood that in some embodiments, the image frame corresponding to the bitstream segment to be processed may be referenced by a subsequent image frame, while in other embodiments, it may be referenced by multiple subsequent image frames, which may be adjacent or separated by other image frames. That is to say, the image frame to be processed may be referenced during the decoding process of subsequent image frames. The specific reference form is not particularly limited.

[0031] In block 302, for the video bitstream, different processing methods are determined based on the information determined in block 301 indicating whether the image frame needs to be referenced by subsequent image frames. Thus, different operation methods can be applied to the bitstream according to different determination results. If it is determined in block 302 that the image corresponding to the bitstream segment being processed does not need to be referenced by subsequent image frames, then method 300 will proceed to block 303. In block 303, pre-synchronization processing of the video can be performed before decoding the bitstream. In some embodiments, the current frame sequence number and timestamp information can be reported to the audio / video synchronization module of device 200 for pre-synchronization of audio and image frames. When the audio / video synchronization time point is reached, method 300 enters block 304, triggering the video decoding module 202 to perform the decoding process. In block 304, various decoding methods can be used to decode the bitstream to obtain image frames. Subsequently, the decoded image frames are directly transmitted to the display module 203 for display via the on-chip memory 205 inside chip 210, as shown in block 309. Thus, the image frame is displayed on the device 200.

[0032] Figure 4 A data flow diagram 400 according to an embodiment of the present disclosure is shown. (In conjunction with...) Figure 4As can be seen from the embodiments of this disclosure, if it is determined that the image corresponding to the currently processed bitstream segment does not need to be referenced by subsequent image frames, then the off-chip memory 206 is not required. The on-chip memory 205 of chip 210 can be used alone to transmit the data decoded by the video decoding module 202 to the on-chip memory 205, and finally, the display module 203 reads the data from the on-chip memory 205 to display the image frame. This method can be understood as online transmission. In this way, the on-chip memory 205, with its faster read / write speed and lower power consumption, can be fully utilized, thereby avoiding excessive power consumption of the terminal device 100 during video processing.

[0033] In some embodiments, if it is determined at block 302 that the image frame corresponding to the currently processed bitstream segment will be referenced by subsequent image frames during decoding, method 300 proceeds to another branch, reaching block 306. At block 306, the bitstream can be decoded using various decoding methods to obtain image frames. Subsequently, at block 307, the obtained image frames are transmitted to off-chip memory 206 located outside chip 210. Then, through the off-chip memory 206, the image frames are transmitted to display module 203 for display. In some embodiments, at block 308, before transmitting the image frames to display module 203 for display, video and audio can be synchronized to improve the user's viewing experience.

[0034] According to embodiments of this disclosure, in conjunction with Figure 4 If the image frame corresponding to the currently processed bitstream segment will be referenced by subsequent image frames during parsing, then after the video decoding module 202 decodes the currently processed bitstream, the obtained image frame data is written to the external memory 206. Subsequently, the display module 303 reads the data from the external memory 306 for display. This method can be understood as offline transmission. In this case, utilizing the relatively large storage space of the external memory 306 ensures normal video display.

[0035] Therefore, the subsequent hardware decoding method can be determined based on the information of the image frame corresponding to the bitstream segment being processed. By reasonably differentiating the actual situation of the bitstream being processed, a balance can be achieved between low power consumption and stable video display.

[0036] In some embodiments, at block 304, when decoding the bitstream, image frames can be output in a certain manner. Figure 5A and Figure 5B Schematic diagrams illustrating the division of output image frames according to embodiments of the present disclosure are shown. In some embodiments, such as Figure 5AAs shown, image frame 500 can be segmented horizontally to form multiple stripes 502-1, 502-2, ..., 502-N. In other embodiments, such as Figure 5B As shown, image frame 410 can be segmented both horizontally and vertically, forming multiple stripes 512-1, 512-2, ..., 512-M. After decoding, the data of a stripe 502-1, 502-2, ..., 502-N or a stripe 512-1, 512-2, ..., 512-M is directly written to on-chip memory 205, instead of to off-chip memory 206, thus reducing the bandwidth of off-chip memory 206. Using this method, for image frames that will not be referenced by subsequent image frames, since they are written to the relatively small on-chip memory 205, a relatively coarse-grained division can be performed, reducing the space requirements of on-chip memory 205. It should be understood that although... Figure 5A The image shows four stripes; however, this is merely illustrative and not restrictive. Depending on the actual use case, image frame 500 can be divided into more or fewer stripes. Similarly, Figure 5B The number of blocks 512-1, 512-2, ... 512-M shown is merely illustrative; in other embodiments, other numbers of blocks may be formed. Furthermore, in some embodiments, the image frame 500 may be divided only vertically. It should also be understood that such division can be either equally spaced or non-equally spaced. That is, Figure 5A The strips 502-1, 502-2, ..., 502-N can have the same size or different sizes. Similarly, Figure 5B The size of the blocks 512-1, 512-2, ..., 512-M in the image can be the same or different. This application does not impose any restrictions on this, as long as it can segment the image frame and thus reduce the video processing time.

[0037] In some embodiments, since the data in the blocks or stripes decoded by the video decoding module 202 has already undergone audio and video pre-synchronization in frame 303, it can be directly transmitted to the display module 203 for display on the display of the terminal device 100. In some embodiments, when a predetermined number of blocks or stripes are transmitted to the on-chip memory 205, the central processing unit 201 can notify the display module 203 to transmit the image frames in the on-chip memory 205 to the display module 203 in a timely manner. (Return to Reference) Figure 2The timely communication between the video decoding module 202 and the display module 203 can be achieved through the communication module 207 located between them, thereby effectively reducing communication latency. In some embodiments, after the video decoding module 202 has written a predetermined number of blocks 512-1, 512-2, ..., 512-M or stripes 502-1, 502-2, ..., 502-N to the on-chip memory 205, it can notify the display module 203 via the communication module 207 that the predetermined number of blocks 512-1, 512-2, ..., 512-M or stripes 502-1, 502-2, ..., 502-N have been decoded, and inform the display module 203 of the storage address of this data. In this way, the display module 203 reads data from the address stored in the on-chip memory 205, including blocks 512-1, 512-2, ..., 512-M or stripes 502-1, 502-2, ..., 502-N. Then, it overlays the image frame with image frames from other layers and transmits it to the display of the terminal device 100 for display. After the above reading steps are completed, the video decoding module 202 can be notified via the communication module 207, so that the video decoding module 202 can reclaim the address to free up space on the on-chip memory 205 for subsequent decoding. Since the space of the on-chip memory 205 is usually very limited, it cannot store too much data. Using the method in the embodiments of this disclosure, through direct communication between the video decoding module 202 and the display module 203, the space of the on-chip memory 205 can be released in a timely manner to ensure efficient data processing. This further reduces the power consumption of the terminal device 100.

[0038] In some embodiments, the predetermined number of blocks or stripes can be one. This means that once the video decoding module 302 has finished writing the data of a block or stripe to the on-chip memory 205, it can notify the display module 203 via the communication module 207 that the data of that block or stripe has been decoded. Subsequently, the data in that block or stripe is read through the storage address for display, and once the reading of that block or stripe is finished, the space on the on-chip memory 205 is released for subsequent decoding. This makes data processing more efficient. It should be understood that, depending on the requirements for the battery life of the terminal device 100, this predetermined number can also be other numbers, such as two, three, or more.

[0039] In some embodiments, the communication module 207 may be a direct hardware connection or a hardware scheduling accelerator between the video decoding module 202 and the display module 203.

[0040] In some embodiments, to ensure that decoded image frames are accurately and efficiently transmitted to the display module 203, a synchronization signal can be used to enable the display module 203 to control the operating rhythm of the video decoding module 202, thus requiring the operating rhythm of the video decoding module 202 to be consistent with that of the display module 203. For example, if the refresh rate of the display screen of the device 200 is 60 frames per second, the display module 203 notifies the video decoding module 202 via the communication module 207 every 16.6 milliseconds (1000 / 60). At this time, if the video decoded by the video decoding module 202 is 30 frames per second, a decoding process is triggered every time two synchronization signals are received; if the video decoded by the video decoding module 202 is 60 frames per second, a decoding process is triggered every time one synchronization signal is received. Using this method, synchronized operation between the video decoding module 202 and the display module 203 can be ensured, thereby ensuring that the video can be correctly displayed on the device 200. It should be understood that the values ​​here are merely exemplary and not limiting.

[0041] The various processes and handling described herein, such as method 300, may be executed by central processing unit 201. For example, in some embodiments, method 300 may be implemented as a computer software program tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 300 via read-only memory and / or communication unit. When the computer program is loaded into random access memory and executed by central processing unit 301, one or more actions of method 300 described above may be performed.

[0042] This disclosure may be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium, such as the non-volatile memory 208 described above, which carries computer-readable program instructions for performing various aspects of this disclosure.

[0043] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0044] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0045] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0046] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0047] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0048] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0049] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0050] Compared to existing solutions, the implementation method of this disclosure transmits decoded image frames that do not need to be referenced online to the display module 203 without passing through the off-chip memory 206, thereby reducing the power consumption of the terminal device 100. For most videos, due to the need to save network transmission bandwidth or video storage space, a large number of unreferenced frames are usually used. Therefore, the embodiments of this disclosure have good practical effects. The more unreferenced frames there are, the greater the power consumption benefit of the embodiments of this disclosure.

[0051] It should be understood that the solutions according to the embodiments of this disclosure can also be applied to scenarios that require multi-address collaborative processing of video data, such as online data transmission solutions in camera recording scenarios, thereby reducing the power consumption of camera equipment in recording scenarios.

[0052] It should also be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0053] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for processing video, the method comprising: The video bitstream is parsed based on software syntax to determine information indicating whether at least one image frame is referenced by subsequent image frames. When the information indicates that at least one image frame is not referenced by the subsequent image frames. The bitstream is decoded to obtain the at least one image frame; Without needing to store the at least one image frame in off-chip memory, the at least one image frame is stored in on-chip memory, and the image frame is stored in the on-chip memory in the form of blocks or stripes; as well as Transferring the at least one image frame from the on-chip memory to the display module to display the at least one image frame includes: In response to a predetermined number of the blocks or stripes of the at least one image frame being stored in the on-chip memory, the display module is notified that the predetermined number of the blocks or stripes have been decoded, and the predetermined number of the blocks or stripes are transmitted to the display module, and the storage space on the on-chip memory corresponding to the predetermined number of the blocks or stripes is released.

2. The method according to claim 1, further comprising: When the information indicates that at least one image frame is referenced by the subsequent image frame. The bitstream is decoded to obtain the at least one image frame; Transmit the at least one image frame to off-chip memory; as well as The at least one image frame is read from the off-chip memory and written to the display module to display the at least one image frame.

3. The method according to claim 1 or 2, wherein when the information indicates that the at least one image frame is not referenced by the subsequent image frame, the method further comprises: Before decoding the bitstream, the image frames and audio are pre-synchronized.

4. The method according to claim 2, further comprising: After storing the image frame in the off-chip memory, the image frame and audio are synchronized.

5. An apparatus for processing video, comprising a video decoding module, a display module, and a central processing unit, wherein the central processing unit is configured to perform the following operations: The video bitstream is parsed based on software syntax to determine information indicating whether at least one image frame is referenced by subsequent image frames. When the information indicates that at least one image frame is not referenced by the subsequent image frames. The bitstream is decoded to obtain the at least one image frame; Without needing to store the at least one image frame in off-chip memory, the at least one image frame is stored in on-chip memory, and the image frame is stored in the on-chip memory in the form of blocks or stripes; as well as Transferring the at least one image frame from the on-chip memory to the display module to display the at least one image frame includes: In response to a predetermined number of the blocks or stripes of the at least one image frame being stored in the on-chip memory, the display module is notified that the predetermined number of the blocks or stripes have been decoded, and the predetermined number of the blocks or stripes are transmitted to the display module, and the storage space on the on-chip memory corresponding to the predetermined number of the blocks or stripes is released.

6. The apparatus of claim 5, further comprising off-chip memory, wherein the central processing unit is configured to perform the following operations: When the information indicates that at least one image frame is referenced by the subsequent image frame. The bitstream is decoded to obtain the at least one image frame; Transmit the at least one image frame to the off-chip memory; as well as The at least one image frame is read from the off-chip memory and written to the display module to display the at least one image frame.

7. The apparatus of claim 5 or 6, wherein the central processing unit is configured to perform the following operation: when the information indicates that the at least one image frame is not referenced by the subsequent image frame, pre-synchronizing the image frame and audio before decoding the bitstream.

8. The apparatus of claim 6, wherein the central processing unit is configured to perform the following operations: After storing the image frame in the off-chip memory, the image frame and audio are synchronized.

9. A computer-readable storage medium having a computer program stored thereon, the program, when executed by a processor, implementing the method according to any one of claims 1 to 4.

Images