SPD read-write and memory test synchronization method, system and program product

Abstract

The invention belongs to the technical field of memory testing, and particularly discloses an SPD read-write and memory testing synchronization method and system and a program product, channel change-over switches corresponding to memory banks synchronously mounted on a bus are sequentially and independently turned on through a substrate management controller, and SPD read-write testing is performed on the memory banks synchronously mounted on the bus one by one, so that the memory banks synchronously mounted on the bus are tested one by one. The method comprises the following steps of: performing SPD read-write test on each memory bank to obtain an SPD read-write test result of each memory bank, performing memory special test on each memory bank through a central processing unit to obtain a memory special test result of each memory bank, and finally summarizing the SPD read-write test result and the memory special test result of each memory bank and uploading the summarized results to a test control end. According to the invention, the parallel processing of the special test of the memory of the central processing unit and the SPD read-write test of the substrate management controller can be realized, and the SPD read-write test of the batch memory banks can be automatically completed one by one by the substrate management controller through an independent switching mode, so that the overall test time of the memory is greatly shortened, and the test efficiency of the memory banks is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory testing, and in particular relates to a method, system and program product for synchronizing SPD reading and writing and memory testing. Background Art

[0002] DRAM (Random Access Memory) is one of the most important core components of digital systems. From various terminal devices to core-layer data processing and storage devices, from various consumer electronic devices to special equipment in various industries, it is an indispensable turnover "warehouse" for processors of various levels to perform data processing operations and cache. A powerful core processing unit must be equipped with a high-speed, wide-path data access and storage unit.

[0003] With the continuous upgrading of memory sticks, high-performance memory has become the mainstream of memory development. However, with the increase of memory particle capacity, unit density, and more and more complex manufacturing process, the yield of produced memory sticks will also decrease. Therefore, it is necessary to conduct corresponding production tests on memory sticks. Through the test, the quality of memory stick products can be judged. The quality of memory sticks directly affects the stability and reliability of the memory system. Only a memory stick with excellent performance can make various high-speed systems such as servers and PCs work properly. It can be seen that memory testing is extremely important.

[0004] In memory testing, the read and write test of SPD (SPD is an erasable programmable read-only memory on the memory module, which is used to store memory-related parameter information) is a very time-consuming task, which will greatly reduce the overall memory test efficiency. With the development of memory technology, in the DDR5 era (DDR is Double Data Rate SDRAM, that is, double data rate synchronous dynamic random access memory, DDR5 memory has higher performance, lower power consumption, higher storage density, and greatly improved chip capacity), the content of SPD has increased to 1024 bytes, and the server platform supports up to 16 memories in single CPU mode. And in the DDR5 era, if you want to read and write test SPD, you need to process it on the hardware, let SPD enter offline mode, and unlock the block. After entering offline mode, the address of SPD is locked to a fixed value. If multiple memories are inserted at the same time for synchronous testing, address conflicts will occur. Therefore, the current memory testing method is usually a plug-in test one by one. After one test is completed and unplugged, other memories can be inserted and tested, and the test efficiency is low. Summary of the invention

[0005] The purpose of the present invention is to provide a method, system and program product for synchronizing SPD reading and writing and memory testing, so as to solve the above problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, a method for synchronizing SPD reading, writing and memory testing is provided, comprising:

[0008] Switch the SPD HUB chips of several memory modules mounted synchronously on the bus to offline mode through the baseboard management controller;

[0009] Receive test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information;

[0010] Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar;

[0011] When performing SPD read and write test on each memory bar synchronously mounted on the bus through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs memory special test on each memory bar to obtain the memory special test result of each memory bar;

[0012] The SPD read and write test results and memory special test results of each memory stick are summarized and uploaded to the test control terminal.

[0013] In a possible design, the switching of the SPD HUB chips of the plurality of memory bars synchronously mounted on the bus to the offline mode by the baseboard management controller includes:

[0014] The HSA pins of the SPD HUB chips of several memory modules synchronously mounted on the bus of the baseboard management controller are grounded.

[0015] In a possible design, when receiving the test plan information sent by the test control terminal, the method further includes:

[0016] Receive the SPD information sent by the test control terminal, and use the SPD information to complete the training of each memory stick through the central processing unit.

[0017] In a possible design, each channel switch corresponding to each memory stick synchronously mounted on the bus is provided with unique addressing information, and the SPD read / write test results and memory special test results of each memory stick are summarized and uploaded to the test control terminal, including:

[0018] According to the unique addressing information of the channel switching switch corresponding to each memory stick, the SPD read and write test results of each memory stick are summarized with the memory special test results to obtain the synchronous test results of each memory stick, and the synchronous test results of each memory stick are uploaded to the test control terminal.

[0019] In a second aspect, a SPD read / write and memory test synchronization system is provided, comprising a test control terminal and a test machine, wherein the test control terminal establishes data connection with the test machine, and the test machine is used to execute any one of the SPD read / write and memory test synchronization methods in the first aspect.

[0020] In a possible design, the test machine includes a baseboard management controller and a central processing unit. The central processing unit establishes a test connection with each memory stick respectively. The baseboard management controller establishes a test connection with the SPD HUB chip of each memory stick respectively through a bus, and a corresponding channel switching switch is provided between the SPD HUB chip of each memory stick and the bus, and each channel switching switch is provided with unique addressing information.

[0021] In a possible design, the number of memory bars is 16.

[0022] In one possible design, the bus is an I3C bus.

[0023] In a third aspect, a SPD read / write and memory test synchronization system is provided, comprising:

[0024] A memory for storing execution instructions;

[0025] An executor is used to read the execution instruction stored in the memory and execute any one of the methods described in the first aspect according to the execution instruction.

[0026] In a fourth aspect, a computer-readable storage medium is provided, wherein an execution instruction is stored on the computer, and when the execution instruction is executed on a computer, the computer executes any one of the methods described in the first aspect. In addition, a computer program product is provided, and when the computer program product is executed on a computer, the computer executes any one of the methods described in the first aspect.

[0027] Beneficial effects:

[0028] 1. The present invention can realize the parallel processing of the CPU memory special test and the baseboard management controller SPD read and write test, which greatly reduces the overall memory test time and increases the number of tests per unit time of the memory bar test.

[0029] 2. The present invention can implement batch SPD read and write tests of multiple memory sticks through a baseboard management controller. A separate I3C channel switching switch is set for each memory stick. The SPD read and write tests of all memory sticks can be automatically completed one by one through separate switching within one cycle, thereby greatly improving the efficiency of memory stick testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 This is a schematic diagram of the steps of the method in Example 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of the system in Example 2 of the present invention;

[0033] Figure 3 Schematic diagram of the system structure in Example 3 of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. The specific structures and functional details disclosed herein are only used to describe the exemplary embodiments of the present invention. However, the present invention can be embodied in many alternative forms, and it should not be understood that the present invention is limited to the embodiments set forth herein.

[0035] It should be understood that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments can be understood according to specific circumstances.

[0036] In the following description, certain details are provided to facilitate a complete understanding of the example embodiments. However, it will be appreciated by those of ordinary skill in the art that the example embodiments may be implemented without these certain details. For example, devices may be shown in block diagrams to avoid obscuring the examples with unnecessary details. In other embodiments, well-known processes, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the embodiments.

[0037] Embodiment 1:

[0038] This embodiment provides a method for synchronizing SPD reading and writing and memory testing, which can be applied to a corresponding test machine, wherein the test machine includes a baseboard management controller BMC and a central processing unit CPU, wherein the baseboard management controller BMC is used to complete the SPD reading and writing test of the memory, and the central processing unit CPU is used to complete other special tests of the memory, and the baseboard management controller BMC is a board-level management chip independent of the central processing unit CPU, such as Figure 1 As shown, the method comprises the following steps:

[0039] S1. Switch the SPD HUB chips of several memory modules synchronously mounted on the bus to offline mode through the baseboard management controller.

[0040] In specific implementation, 16 memory sticks can be plugged into the test machine (DDR technology has now developed to DDR5, and compared with DDR4 memory, DDR5 standard performance is stronger and power consumption is lower), establish a test connection between the central processor and each memory stick, establish a baseboard management controller BMC and the I3C bus connection of each memory stick, and a corresponding channel switching switch is provided between the SPD HUB (serial detection hub) chip of each memory stick and the I3C bus, and each channel switching switch is provided with unique addressing information. The test machine grounds the HSA pins of the SPD HUB chips of all memory sticks synchronously mounted on the I3C bus through the baseboard management controller BMC, so that the SPD HUB chips of each memory stick switch to offline mode. The DDR5 memory replaces the SPD chip of the DDR4 memory with the SPD HUB chip, and adds two temperature sensor TS chips. The TS integrated in the SPD HUB chip is used in combination with two discrete TS chips to provide three thermal telemetry points. Based on DDR5 technology, the communication bus between chips is upgraded to the I3C bus, which runs 10 times faster than the I2C bus used in DDR4. The DDR5 SPD HUB chip handles the communication from the module to the baseboard management controller BMC. By using the faster I3C protocol, the DDR5 SPD HUB chip can shorten the initialization time and support higher polling rates and real-time control, facilitating faster memory testing.

[0041] S2. Receive the test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information.

[0042] During specific implementation, the test machine receives the test plan information sent by the test control terminal, and the test plan information includes SPD test configuration information and memory special test configuration information. The SPD test configuration information is used for subsequent SPD read and write tests, and the memory special test configuration information is used for subsequent memory special tests. The memory special test includes other memory tests except SPD read and write tests. At the same time, the test machine also receives the SPD information sent by the test control terminal, and uses the SPD information to complete the training of each memory bar through the central processing unit CPU. The SPD information includes parameter indicators such as the operating frequency, operating voltage, speed, capacity, voltage, and row and column address bandwidth of the memory. The SPD information is used to complete the training of each memory bar, so as to realize the debugging of the timing parameters of the memory bar through the JEDEC specification (DDR5 memory adopts the JESD79-5 DDR5 SDRAM standard), so as to achieve the matching of the central processing unit CPU and the memory bar, so that the memory bar can run normally on the corresponding CPU platform.

[0043] S3A. Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar.

[0044] During specific implementation, the test machine executes the SPD test configuration information through the baseboard management controller BMC, and opens the channel switching switches corresponding to each memory stick synchronously mounted on the I3C bus in turn and separately (when the baseboard management controller BMC performs SPD read and write tests on each memory stick, a separate I3C channel switching switch is set for each memory stick, so that the SPD read and write tests of all memory sticks can be completed one by one within one POWER cycle by means of physical switch channel switching), so as to perform SPD read and write tests on each memory stick synchronously mounted on the bus one by one, and obtain the SPD read and write test results of each memory stick. The SPD read and write test results of each memory stick can be distinguished by associating them with the unique addressing information of the corresponding channel switching switch.

[0045] S3B. When performing the SPD read and write test process on each memory stick synchronously mounted on the bus one by one through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs a memory special test on each memory stick to obtain the memory special test result of each memory stick.

[0046] In specific implementation, when performing SPD read and write tests on each memory stick synchronously mounted on the I3C bus one by one through the baseboard management controller BMC, the test machine can execute memory-specific test configuration information through the central processing unit CPU in parallel, perform memory-specific tests on each memory stick, and obtain memory-specific test results for each memory stick. Exemplarily, the memory-specific test may include:

[0047] Encryption function test: including performance encryption and functional encryption, to ensure that the memory can work normally in the encrypted state.

[0048] Sequence test: such as DE OOBE_EOW sequence test, used to verify the serialization operation of memory.

[0049] Performance setting test: Test the performance of memory under different settings.

[0050] Debug function test: includes logo test to verify whether the debugging function of the memory is normal.

[0051] Driver Firmware Configuration Test: Verifies memory compatibility with system drivers and firmware.

[0052] DXGI HybridPresent test: Tests the hybrid presentation technology in memory graphics processing.

[0053] Hardware safety testability interface testing: Verify hardware safety and testability.

[0054] PowerManagement test: including power management tests in various scenarios such as AppIdle and MonitorOff.

[0055] INVDIMM error injection test: simulates memory errors to verify the memory's error handling capabilities.

[0056] Playback of protected content using a hardware decryptor: Tests the memory's performance when handling encrypted content.

[0057] Processor Power Management Test: Verifies that processor and memory power management work together.

[0058] Secure Boot Test: Includes logo test to ensure secure boot functionality of memory.

[0059] Signed Driver Check: Verifies the signature and compatibility of memory drivers.

[0060] These test items cover multiple aspects from basic functions to advanced performance to ensure the stability and reliability of the memory module in actual applications.

[0061] S4. Summarize the SPD read and write test results and memory special test results of each memory stick and upload them to the test control terminal.

[0062] During specific implementation, the test machine can summarize the SPD read and write test results of each memory stick with the memory special test results according to the unique addressing information of the channel switching switch corresponding to each memory stick, obtain the synchronous test results of each memory stick, upload the synchronous test results of each memory stick to the test control terminal, and complete the batch memory test of 16 memory sticks.

[0063] This embodiment can realize the parallel processing of the CPU memory special test and the baseboard management controller SPD read and write test, greatly reducing the overall memory test time and increasing the number of tests per unit time of the memory bar test. The baseboard management controller can be used to implement batch SPD read and write tests of multiple memory bars, and each memory bar is set with a separate I3C channel switch. In one cycle, the SPD read and write tests of all memory bars can be automatically completed one by one by switching separately, greatly improving the efficiency of the memory bar test.

[0064] Embodiment 2:

[0065] This embodiment provides a SPD read-write and memory test synchronization system, such as Figure 2 As shown, it includes a test control end and a test machine, the test control end establishes data connection with the test machine, and the test machine is used to execute the SPD read-write and memory test synchronization method described in Example 1:

[0066] S1. Switch the SPD HUB chips of several memory modules synchronously mounted on the bus to offline mode through the baseboard management controller.

[0067] S2. Receive the test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information.

[0068] S3A. Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar.

[0069] S3B. When performing the SPD read and write test process on each memory stick synchronously mounted on the bus one by one through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs a memory special test on each memory stick to obtain the memory special test result of each memory stick.

[0070] S4. Summarize the SPD read and write test results and memory special test results of each memory stick and upload them to the test control terminal.

[0071] The test machine includes a baseboard management controller and a central processing unit. The central processing unit establishes a test connection with each memory bar respectively. The baseboard management controller establishes a test connection with the SPD HUB chip of each memory bar respectively through a bus, and a corresponding channel switching switch is provided between the SPD HUB chip of each memory bar and the bus, and each channel switching switch is provided with unique addressing information. There are 16 memory bars. The bus is an I3C bus.

[0072] Embodiment 3:

[0073] This embodiment provides a SPD read-write and memory test synchronization system, such as Figure 3 As shown, at the hardware level, it includes:

[0074] Data interface, used to establish data connection between the actuator and the test control terminal;

[0075] A memory for storing execution instructions;

[0076] An executor is used to read the execution instruction stored in the memory, and execute the SPD read-write and memory test synchronization method in Example 1 according to the execution instruction:

[0077] S1. Switch the SPD HUB chips of several memory modules synchronously mounted on the bus to offline mode through the baseboard management controller.

[0078] S2. Receive the test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information.

[0079] S3A. Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar.

[0080] S3B. When performing the SPD read and write test process on each memory stick synchronously mounted on the bus one by one through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs a memory special test on each memory stick to obtain the memory special test result of each memory stick.

[0081] S4. Summarize the SPD read / write test results and memory special test results of each memory module and upload them to the test control terminal.

[0082] Optionally, the system further includes an internal bus, through which the processor, the memory and the data interface can be interconnected, and the internal bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0083] The memory may include, but is not limited to, random access memory (RAM), read only memory (ROM), flash memory, first input first output (FIFO) and / or first in last out (FILO) memory, etc. The processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0084] Embodiment 4:

[0085] This embodiment provides a computer-readable storage medium, on which execution instructions are stored. When the execution instructions are executed on a computer, the computer executes the SPD read-write and memory test synchronization method in Embodiment 1:

[0086] S1. Switch the SPD HUB chips of several memory modules synchronously mounted on the bus to offline mode through the baseboard management controller.

[0087] S2. Receive the test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information.

[0088] S3A. Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar.

[0089] S3B. When performing the SPD read and write test process on each memory stick synchronously mounted on the bus one by one through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs a memory special test on each memory stick to obtain the memory special test result of each memory stick.

[0090] S4. Summarize the SPD read and write test results and memory special test results of each memory stick and upload them to the test control terminal.

[0091] The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to a floppy disk, a CD, a hard disk, a flash memory, a USB flash drive and / or a memory stick, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device.

[0092] This embodiment further provides a computer program product. When the computer program product is run on a computer, the SPD read-write and memory test synchronization method in Embodiment 1 is executed:

[0093] S1. Switch the SPD HUB chips of several memory modules synchronously mounted on the bus to offline mode through the baseboard management controller.

[0094] S2. Receive the test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information.

[0095] S3A. Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar.

[0096] S3B. When performing the SPD read and write test process on each memory stick synchronously mounted on the bus one by one through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs a memory special test on each memory stick to obtain the memory special test result of each memory stick.

[0097] S4. Summarize the SPD read and write test results and memory special test results of each memory stick and upload them to the test control terminal.

[0098] The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices.

[0099] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for synchronizing SPD reading, writing and memory testing, characterized in that: include: Switch the SPD HUB chips of several memory modules mounted synchronously on the bus to offline mode through the baseboard management controller; Receive test plan information sent by the test control terminal, wherein the test plan information includes SPD test configuration information and memory special test configuration information; Based on the SPD test configuration information, the channel switching switches corresponding to the memory bars synchronously mounted on the bus are turned on separately in sequence through the baseboard management controller, and the SPD read and write tests are performed on the memory bars synchronously mounted on the bus one by one to obtain the SPD read and write test results of each memory bar; When performing SPD read and write test on each memory bar synchronously mounted on the bus through the baseboard management controller, based on the memory special test configuration information, the central processor synchronously performs memory special test on each memory bar to obtain the memory special test result of each memory bar; The SPD read and write test results and memory special test results of each memory stick are summarized and uploaded to the test control terminal.

2. A SPD read-write and memory test synchronization method according to claim 1, characterized in that: The method of switching the SPD HUB chips of the plurality of memory bars synchronously mounted on the bus to an offline mode by using the baseboard management controller includes: The HSA pins of the SPD HUB chips of several memory modules synchronously mounted on the bus of the baseboard management controller are grounded.

3. A SPD read-write and memory test synchronization method according to claim 1, characterized in that: When receiving the test plan information sent by the test control terminal, the method further includes: Receive the SPD information sent by the test control terminal, and use the SPD information to complete the training of each memory stick through the central processing unit.

4. The SPD read / write and memory test synchronization method according to claim 1, characterized in that: The channel switching switches corresponding to each memory stick synchronously mounted on the bus are all provided with unique addressing information, and the SPD read-write test results and memory special test results of each memory stick are summarized and uploaded to the test control terminal, including: According to the unique addressing information of the channel switching switch corresponding to each memory stick, the SPD read and write test results of each memory stick are summarized with the memory special test results to obtain the synchronous test results of each memory stick, and the synchronous test results of each memory stick are uploaded to the test control terminal.

5. A SPD read-write and memory test synchronization system, characterized in that: It comprises a test control terminal and a test machine, wherein the test control terminal establishes data connection with the test machine, and the test machine is used to execute the SPD reading and writing and memory test synchronization method according to any one of claims 1 to 4.

6. The SPD read-write and memory test synchronization system according to claim 5, characterized in that: The test machine includes a baseboard management controller and a central processing unit. The central processing unit establishes a test connection with each memory stick respectively. The baseboard management controller establishes a test connection with the SPD HUB chip of each memory stick respectively through a bus. A corresponding channel switching switch is provided between the SPD HUB chip of each memory stick and the bus, and each channel switching switch is provided with unique addressing information.

7. The SPD read-write and memory test synchronization system according to claim 6, characterized in that: There are 16 memory bars.

8. The SPD read-write and memory test synchronization system according to claim 6, characterized in that: The bus is an I3C bus.

9. An SPD read-write and memory test synchronization system, characterized in that: include: A memory for storing execution instructions; An executor is used to read the execution instruction stored in the memory, and execute the SPD read-write and memory test synchronization method described in any one of claims 1-4 according to the execution instruction.

10. A computer program product, characterized in that When the computer program product is run on a computer, the SPD reading, writing and memory testing synchronization method according to any one of claims 1 to 4 is executed.

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