A device and method for monitoring the etching depth of a trench MOS.

Abstract

This invention discloses a device and method for monitoring the etching depth of trench MOS. It employs a first component and a second component with identical structures but distinct features for comparative testing. The second component is distinguished by having several second trenches arranged in a matrix within the area surrounded by the first trench. Ion implantation is performed on both the first and second components, and the total resistance of the two components after ion implantation is compared to quickly obtain the deviation in the etching depth of the trench MOS. This method eliminates the need for destructive dissection testing of the chip and can monitor the etching depth of a specified location on each wafer, offering more comprehensive monitoring frequency and range compared to traditional methods.

Description

Technical Field

[0001] This invention relates to the field of semiconductor inspection technology, and in particular to a device and method for monitoring the etching depth of trench MOS. Background Technology

[0002] MOSFET chips are discrete semiconductor devices. Based on their physical structure, MOSFET chips can be classified into two main categories: planar MOSFETs and trench MOSFETs. The body and source regions of a trench MOSFET are diffusion regions formed through ion implantation followed by high-temperature annealing. The source region is typically located on the surface of the body region, and its diffusion depth is less than that of the body region. The doping type of the body region is opposite to that of the substrate and source region. Taking an N-channel MOSFET as an example, the substrate is N-type doped, the body region is P-type doped, and the source region is N-type doped.

[0003] The formation process of the polysilicon gate in a trench MOSFET includes polysilicon deposition and etching. The polysilicon etching process removes all the polysilicon outside the trench, leaving the polysilicon within the trench as the gate of the trench MOSFET. In practice, to ensure complete removal of the polysilicon outside the trench, over-etching is typically used. Therefore, the upper surface of the polysilicon remaining in the trench is usually lower than the silicon plane, creating a height difference, which is the etching depth. The polysilicon etching depth of the trench MOSFET affects the doping depth of the source region, and consequently, the threshold voltage of the trench MOSFET.

[0004] The current method for detecting the etching depth of trench MOS is to sample and dissect the chip. This method has obvious drawbacks, namely, it requires destructive dissection of the chip for testing. Therefore, it is impossible to monitor every wafer, which has great limitations. Summary of the Invention

[0005] The purpose of this invention is to address the technical problems existing in the background art by proposing a device and method for monitoring the etching depth of trench MOS.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention in the first aspect is as follows:

[0007] A device for monitoring the etching depth of a trench MOS includes a first component and a second component. The second component includes a body region, a source region, a plurality of contact holes, a first trench, and a plurality of second trenches. The source region is stacked on the body region. The plurality of contact holes are respectively inserted into the source region and the body region and are filled with metal electrodes. The first trenches are sequentially inserted into the source region and the body region to form a first diffusion resistor and a second diffusion resistor respectively in the source region and the body region. The plurality of second trenches are arranged in a matrix in the region surrounded by the first trenches. Both the first trenches and the second trenches are filled with a first material. The first component and the second component have the same structure but do not include the plurality of second trenches. The first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain a total resistance R1. The first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain a total resistance R2.

[0008] Preferably, the second groove is a square groove, and each second groove is equidistant from the others.

[0009] Preferably, the number of second grooves is N. 2 There are N rows and N columns arranged in a matrix within the area surrounded by the first trench, where N>1 and N is a positive integer.

[0010] Preferably, the first groove includes a main annular groove and four secondary annular grooves. The four secondary annular grooves are respectively connected to the four sides of the main annular groove. There are four contact holes, which are respectively connected to the areas surrounded by the four secondary annular grooves.

[0011] Preferably, the area surrounded by the main annular groove is square in shape.

[0012] Preferably, both the total resistance R1 and the total resistance R2 are van der Burg resistors.

[0013] Preferably, the first material is polycrystalline silicon.

[0014] Preferably, the first trench and the second trench are further filled with a second substance, which is silicon oxide. The silicon oxide covers the inner walls of the first trench and the second trench, and the remaining space in the first trench and the second trench is filled with polycrystalline silicon.

[0015] Preferably, the spacing between each second trench is less than twice the source region injection depth between the second trenches.

[0016] The technical solution adopted in the second aspect of the present invention is as follows:

[0017] A method for monitoring the etching depth of a trench MOS, characterized in that it is applied to a trench MOS etching depth monitoring device as described above, and the method for monitoring the etching depth of the trench MOS includes:

[0018] A pre-set ion implantation process was used to implant ions into the first component and the second component, respectively.

[0019] After the ion implantation process is completed, the total resistance R1 and the total resistance R2 are measured respectively to obtain the first total resistance value and the second total resistance value.

[0020] The difference between the first total resistance value and the second total resistance value is calculated to determine the deviation of the etching depth of the trench MOS.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects: it uses a first component and a second component with the same structure but different features for comparative testing. The distinguishing feature of the second component is that it has several second trenches arranged in a matrix in the area surrounded by the first trench. Ion implantation is performed on the first component and the second component, and the total resistance of the first component and the second component after ion implantation is compared to quickly obtain the deviation of the etching depth of the monitoring trench MOS. It does not require destructive dissection testing of the chip and can monitor the etching depth of a specified area on each wafer. Compared with the traditional method, the monitoring frequency and range are more complete. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the planar structure of the first component in the monitoring device when R=0 is selected in the first aspect embodiment of the present invention;

[0023] Figure 2 This is a cross-sectional view of the first component in the monitoring device when R=0 is taken in the first aspect embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the planar structure of the second component in the monitoring device when R=0 is selected in the first aspect embodiment of the present invention;

[0025] Figure 4 This is a cross-sectional view of the monitoring device of the second component in the monitoring device when R=0 is taken in the first aspect embodiment of the present invention;

[0026] Figure 5 This is a cross-sectional view of the monitoring device of the first component in the monitoring device when R>0 in the first aspect embodiment of the present invention;

[0027] Figure 6 This is a cross-sectional view of the monitoring device of the second component in the monitoring device when R>0 in the first aspect embodiment of the present invention;

[0028] Figure 7 This is a monitoring flowchart of a second aspect embodiment of the present invention.

[0029] Reference numerals: 100 Body region, 200 Source region, 300 Contact hole, 301 Metal electrode, 400 First trench, 401 Main annular trench, 402 Secondary annular trench, 500 Second trench, 600 First material, 700 Second material. Detailed Implementation

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0031] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more features. In the description of this invention, unless otherwise stated, "a number" means two or more.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or a specific connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0034] like Figure 1 as well as Figure 6 As shown, the present invention provides a monitoring device for the etching depth of a trench MOS in a first aspect, comprising a first component and a second component; the second component includes a body region 100, a source region 200, a plurality of contact holes 300, a first trench 400 and a plurality of second trenches 500; wherein the first component has the same structure as the second component and does not include the plurality of second trenches 500.

[0035] In this embodiment, the monitoring device is actually located in the dicing channel of the wafer. Specifically, the preparation of the monitoring device is also included in the chip fabrication process such as etching of the wafer, and is carried out synchronously with the wafer etching. For example, the first trench 400, the second trench 500, the body region 100, and the source region 300 in the first component and the second component are all formed synchronously with the trench, body region, and source region of the monitored trench MOS. Among them, the first material in the first trench 400 and the second trench 500 is formed synchronously with the control gate in the monitored trench MOS.

[0036] A source region 200 is stacked on a body region 100. Several contact holes 300 are inserted into the source region 200 and the body region 100 respectively. Metal electrodes 301 are filled in the contact holes 300. A first trench 400 is inserted into the source region 200 and the body region 100 in sequence to form a first diffusion resistor and a second diffusion resistor in the source region 200 and the body region 100 respectively. Several second trenches 500 are arranged in a matrix in the area surrounded by the first trenches 400. Both the first trenches 400 and the second trenches 500 are filled with a first material 600.

[0037] The first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain the total resistance R1, and the first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain the total resistance R2.

[0038] Specifically, the first groove 400 includes a main annular groove 401 and four secondary annular grooves 402. The four secondary annular grooves 402 are respectively connected to the four sides of the main annular groove 401. There are four contact holes 300, which are respectively connected to the areas surrounded by the four secondary annular grooves 402. The area surrounded by the main annular groove 401 is square in shape, as shown in the figure. W1 and W2 refer to the side length of the main annular groove 401 in the first component and the main annular groove 401 in the second component, respectively. In this embodiment, since the structures of the first component and the second component are basically the same, W1 = W2.

[0039] The boundaries of the source region 200 of the first component and the second component are located on the center line of the widths X1 and X2 of the first groove 400. It can be understood that the boundary of the first groove 400 is contracted inward, and the inward contraction distance is half of the widths X1 and X2 of the first groove 400, which finally results in the source region 200.

[0040] In this embodiment, the monitoring device is located in the dicing channel of the wafer. During the chip fabrication process, such as etching, the fabrication of the monitoring device is also included in the process and is formed synchronously with the chip. By applying a certain current to two adjacent metal electrodes 301 on the first and second components and detecting the voltage of the other two adjacent metal electrodes 301, the total resistance R1 and total resistance R2 corresponding to the first and second components are calculated. The difference between the total resistance R1 and total resistance R2 is judged to determine the deviation of the etching depth of the trench MOS. After confirming that the etching depth of the trench MOS is not problematic, the dicing process is used to slice the wafer in the dicing channel, destroying the monitoring device along with the wafer. This allows for the monitoring of the trench MOS using the monitoring device without the need for destructive dissection testing of the chip.

[0041] Furthermore, the second groove 500 is a square groove, and each second groove 500 is equidistant from the others.

[0042] The number of second grooves 500 is N. 2 There are N rows and N columns arranged in a matrix within the area surrounded by the first trench 400, where N>1 and N is a positive integer.

[0043] Specifically, in the attached diagram, S represents the distance between each second trench 500, and S is much smaller than W2. Specifically, the spacing S between each second trench 500 is less than twice the implantation depth of the source region 200 between the second trenches 500. Since ion implantation has a certain depth, in actual operation, assuming the ion implantation depth is 0.3 μm, and the spacing between two second trenches 500 is less than or equal to 0.6 μm, ion implantation occurs from the sidewall between these two second trenches 500. Therefore, at this depth, the implanted ions will meet and achieve a relatively uniform doping. If the spacing between the two second trenches 500 is too large, for example, greater than the aforementioned 0.6 μm, then the ions will not meet during implantation, only affecting the area within 0.3 μm of the second trench 500, resulting in the area beyond 0.3 μm not being affected. This affects the detection effect of the monitoring device. It should be noted that the second component is used as a comparison group with the first component, and the depth J2 of the spacing S between each second trench 500 in the second component is affected by the etching depth R of the first material in the second trench 500. Once the etching depth R of the first material is greater than 0, the ion implantation depth needs to be added to this etching depth R. Since the spacing S is fixed in advance, the ion implantation depth is also fixed, which increases the depth J2 of the spacing S to the depth J4, thereby reducing the resistance value of the first diffusion resistor in the source region 200. Therefore, by comparing the ratio between the total resistance of the second component and the total resistance of the first component with the original ratio, the deviation of the etching depth of the trench MOS can be determined. The specific etching depth can be determined by the difference in the ratio.

[0044] Furthermore, both the total resistance R1 and the total resistance R2 are van der Burg resistors.

[0045] The first material 600 is polycrystalline silicon. The first trench 400 and the second trench 500 are also filled with a second material 700, which is silicon oxide. The silicon oxide covers the inner walls of the first trench 400 and the second trench 500, and the remaining space in the first trench 400 and the second trench 500 is filled by polycrystalline silicon.

[0046] Specifically, silicon oxide is formed synchronously with the gate oxide layer of the monitored trench MOS, and polysilicon is formed synchronously with the control gate of the monitored trench MOS. The actual etch depth monitored is the etch depth of the polysilicon.

[0047] like Figure 7 As shown, in a second aspect, the present invention provides a method for monitoring the etching depth of a trench MOS, characterized in that it is applied to a trench MOS etching depth monitoring device as described above, and the method for monitoring the etching depth of the trench MOS includes:

[0048] S1. Using a pre-set ion implantation process, ion implantation is performed on the first component and the second component respectively;

[0049] S2. After the ion implantation process is completed, the total resistance R1 and the total resistance R2 are detected respectively to obtain the first total resistance value and the second total resistance value.

[0050] S3. Calculate the difference between the first total resistance value and the second total resistance value to determine the deviation of the etching depth of the trench MOS.

[0051] Specifically, the total resistance R1 formed by the second diffusion resistance R11 formed in the body region 100 and the first diffusion resistance R12 formed in the source region 200 in the first component is R1, which is formed by the parallel connection of the two components. According to the formula for calculating parallel resistance, R1 = R11 * R12 / (R11 + R12).

[0052] The total resistance R2 formed by the parallel connection of the second diffusion resistance R21 formed by the body region 100 and the first diffusion resistance R22 formed by the source region 200 in the second component is known to be R2 = R21 * R22 / (R21 + R22). According to the formula for calculating parallel resistance, R2 = R21 * R22 / (R21 + R22).

[0053] Since the first component and the second component are of equal size and the body region 100 therein are formed synchronously, the resistance values ​​of the second diffusion resistors in the first component and the second component are equal, that is, R11 = R21.

[0054] When the etching depth R of polysilicon is 0:

[0055] Since the source region 200 in the first and second components is formed synchronously, the depth J1 is equal to the depth J2, that is, J1 = J2, which corresponds to the resistance values ​​of the two first diffusion resistors being equal, R12 = R22.

[0056] In summary, since R11 = R21 and R12 = R22, therefore R1 = R2.

[0057] At this point, if the total resistance of the first and second components is the same, meaning there is no difference, then it can be determined that the etching depth of the trench MOS has not deviated.

[0058] When the etching depth R of polysilicon is greater than 0:

[0059] The ion implantation process penetrates the silicon surface to enter the doped region formed in the bulk region 100. Its depth is not affected by the polysilicon etching depth; therefore, its depth J3 (e.g.) Figure 5 As shown) and the depth J1 corresponding to the etching depth R = 0 of polysilicon. Figure 2 (As shown) are equal, that is, J3 = J1;

[0060] When the source region 200 is doped using an ion implantation process, in the polysilicon over-etched region of the second trench 500 in the second component, the doped material penetrates the silicon oxide and enters the body region 100 from the sidewall of the second trench 500. Therefore, the depth J4 of the source region 200 in the second component is... Figure 6 As shown, the depth J2 corresponds to the etching depth R = 0 of polysilicon. Figure 4 As shown in the figure, J4>J2, while J1=J2 and J3=J1, so J4>J3.

[0061] Since the diffusion resistance decreases with increasing depth, and J4>J3, therefore, R12>R22.

[0062] In summary, since R11 = R21 and R12 > R22, therefore R1 > R2.

[0063] It can be concluded that when the polysilicon etching depth is greater than 0, the ratio of R1 to R2 (R1 / R2) is greater than 1, and the greater the polysilicon etching depth, the greater the ratio.

[0064] Therefore, by comparing the ratio of the total resistance of the second component to the total resistance of the first component with the original ratio, we can determine the deviation of the etching depth of the trench MOS. The specific etching depth can be determined by the difference in the ratio.

[0065] The above describes a device and method for monitoring the etching depth of a trench MOS, or various embodiments thereof, in conjunction with specific details. It is not intended that the specific implementation of this invention be limited to these descriptions. Any methods or structures similar to or identical to those of this invention, or any technical deductions or substitutions made based on the concept of this invention, should be considered within the scope of protection of this invention.

Claims

1. A device for monitoring the etching depth of a trench MOS, characterized in that, include: First component and second component; The second component includes: Body area (100); The source region (200) is stacked on the body region (100); A plurality of contact holes (300) are respectively inserted into the source region (200) and the body region (100), and the contact holes (300) are filled with metal electrodes (301). A first trench (400) is inserted sequentially into the source region (200) and the body region (100) to form a first diffusion resistor and a second diffusion resistor in the source region (200) and the body region (100), respectively. Several second trenches (500) are arranged in a matrix within the area surrounded by the first trench (400), and both the first trench (400) and the second trenches (500) are filled with a first substance (600). Among them, there is a unique distinguishing feature between the first component and the second component. The distinguishing feature is that the first component does not include the second trench (500), the first diffusion resistor and the second diffusion resistor in the first component are connected in parallel to obtain a total resistance R1, and the first diffusion resistor and the second diffusion resistor in the second component are connected in parallel to obtain a total resistance R2. The first groove (400) includes a main annular groove (401) and four secondary annular grooves (402). The four secondary annular grooves (402) are respectively connected to the four sides of the main annular groove (401). The contact hole (300) is provided with four holes, which are respectively connected to the areas surrounded by the four secondary annular grooves (402).

2. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that, The second groove (500) is a square groove, and each second groove (500) is equidistant from the others.

3. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that, The number of the second grooves (500) is There are N rows and N columns arranged in a matrix within the area surrounded by the first trench (400), where N>1 and N is a positive integer.

4. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that, The area surrounded by the main annular groove (401) is square in shape.

5. The device for monitoring the etching depth of a trench MOS according to claim 4, characterized in that, Both the total resistance R1 and the total resistance R2 are van der Burg resistors.

6. The device for monitoring the etching depth of a trench MOS according to claim 1, characterized in that, The first substance (600) is polycrystalline silicon.

7. The device for monitoring the etching depth of a trench MOS according to claim 6, characterized in that, The first trench (400) and the second trench (500) are further filled with a second substance (700), which is silicon oxide. The silicon oxide covers the inner walls of the first trench (400) and the second trench (500), and the remaining space in the first trench (400) and the second trench (500) is filled by the polycrystalline silicon.

8. The device for monitoring the etching depth of a trench MOS according to claim 2, characterized in that, The spacing between each of the second trenches (500) is less than twice the injection depth of the source region (200) between the second trenches (500).

9. A method for monitoring the etching depth of a trench MOS, characterized in that, An apparatus for monitoring the etching depth of a trench MOS as described in any one of claims 1-8, wherein the method for monitoring the etching depth of the trench MOS comprises: A pre-set ion implantation process was used to implant ions into the first component and the second component, respectively. After the ion implantation process is completed, the total resistance R1 and the total resistance R2 are measured respectively to obtain the first total resistance value and the second total resistance value. The difference between the first total resistance value and the second total resistance value is calculated to determine the deviation of the etching depth of the trench MOS.

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