A transistor and its application

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a transistor and its application, wherein the transistor comprises a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode and a composite field plate, wherein the barrier layer is arranged on the channel layer, the source electrode is arranged on the barrier layer, the drain electrode is arranged on the barrier layer, the gate electrode is arranged on the barrier layer and is located between the source electrode and the drain electrode, the composite field plate is electrically connected to the source electrode, and the composite field plate comprises a bottom field plate and a top field plate, wherein the bottom field plate is located on the side of the gate electrode close to the drain electrode, the top field plate is located on the side of the bottom field plate electrode close to the drain electrode, the bottom surface of the bottom field plate is higher than the bottom surface of the gate electrode, the top surface of the bottom field plate is lower than the bottom surface of the top field plate, the bottom surface of the top field plate is lower than the top surface of the gate electrode, and the top surface of the top field plate is higher than the top surface of the gate electrode. With this arrangement, the transistor has the advantages of uniform electric field distribution and low parasitic capacitance, thereby improving the gain of the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a transistor, a radio frequency amplifier including the transistor, and a communication device including the radio frequency amplifier. Background Art

[0002] The third generation semiconductor material gallium nitride (GaN) has the advantages of wide bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate and higher radiation resistance, and has a very broad application prospect in high temperature, high frequency and microwave high power semiconductor devices. High electron mobility transistor (HEMT) has the advantages of high frequency, high voltage and high temperature, and is the future development direction of solid-state microwave power devices and power electronic devices.

[0003] Due to the presence of surface electron traps, unpassivated GaN HEMT devices often exhibit severe current collapse and a significant drop in output performance. At present, the electric field distribution between the source and drain is adjusted mainly by adding field plates on the gate-drain side, thereby effectively providing the device's compressive strength. However, since the field plate will introduce parasitic capacitance, the parasitic capacitance will affect the output performance of the device, resulting in high parasitic capacitance of the device and reduced gain. Therefore, how to maintain uniform electric field distribution and low parasitic capacitance of the device after introducing the field plate has become a technical difficulty that technicians in this field need to solve urgently.

[0004] It should be noted that the information disclosed in this background technology section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes prior art already known to a person skilled in the art. Summary of the invention

[0005] The present invention provides a transistor, which includes a channel layer, a barrier layer, a source, a drain, a gate and a composite field plate. The barrier layer is arranged on the channel layer. The source is arranged on the barrier layer. The drain is arranged on the barrier layer. The gate is arranged on the barrier layer and is located between the source and the drain. The composite field plate is electrically connected to the source, and the composite field plate includes a bottom field plate and a top field plate. The bottom field plate is located on a side of the gate close to the drain, and the top field plate is located on a side of the bottom field plate close to the drain. The lower surface of the bottom field plate is higher than the lower surface of the gate, and the upper surface of the bottom field plate is lower than the lower surface of the top field plate. The lower surface of the top field plate is lower than the upper surface of the gate, and the upper surface of the top field plate is higher than the upper surface of the gate.

[0006] The present invention also provides a radio frequency amplifier, which comprises the transistor mentioned above.

[0007] The present invention also provides a communication device, which includes the above-mentioned radio frequency amplifier.

[0008] A transistor, a radio frequency amplifier and a communication device provided by the present invention can effectively adjust the off-state electric field distribution of the transistor device, reduce the peak electric field, make the electric field distribution more uniform, reduce the parasitic capacitance of the transistor device, and improve the device gain by setting a bottom field plate close to the gate corner and a top field plate higher than the gate and the bottom field plate.

[0009] Other features and beneficial effects of the present invention will be described in the following description, and some of the technical features and beneficial effects can be obviously derived from the description or understood by implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 is a schematic structural diagram of a transistor provided by a first embodiment of the present invention;

[0012] Figure 2 yes Figure 1 A magnified schematic diagram of the middle A area;

[0013] Figure 3 is a schematic structural diagram of a transistor provided by a second embodiment of the present invention;

[0014] Figure 4 yes Figure 3 A magnified schematic diagram of the middle B area;

[0015] Figures 5 to 10 It is a schematic diagram of the structure of each stage in the process of preparing each passivation layer and field plate of the transistor provided by the second embodiment of the present invention.

[0016] Reference numerals:

[0017] 1-source; 2-drain; 3-gate; 10-channel layer; 20-barrier layer; 40-dielectric layer; 41-bottom passivation layer; 42-middle passivation layer; 43-top passivation layer; 51-bottom field plate; 52-middle field plate; 53-top field plate; H1-thickness of bottom field plate; H2-thickness of middle field plate; H3-thickness of top field plate; H4-thickness of dielectric layer; H5-thickness of bottom passivation layer; H6-thickness of middle passivation layer; H7-thickness of top passivation layer; h1-first height difference; h2-second height difference; h3-third height difference; L1-length of top field plate; L2-length of middle field plate; L3-length of bottom field plate; S1-first horizontal minimum spacing; S2-second horizontal minimum spacing; S3-third horizontal minimum spacing. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof all mean "at least including".

[0020] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the structure of a transistor provided by the first embodiment of the present invention, Figure 2 yes Figure 1In order to achieve at least one of the above advantages or other advantages, a first embodiment of the present invention provides a transistor. As shown in the figure, the transistor may include a channel layer 10, a barrier layer 20, a source 1, a drain 2, a gate 3 and a composite field plate.

[0021] The channel layer 10 is also called an electron transit layer. The channel layer 10 may be an unintentionally doped gallium nitride layer. The channel layer 10 may be an unintentionally doped aluminum gallium nitride (Al X Ga 1－X N(0≤X<1)). More specifically, for example, the channel layer 10 is non-intentionally doped gallium nitride (GaN), and the thickness of the channel layer 10 ranges from 200 to 640 nm, thereby greatly improving the voltage resistance characteristics of the transistor device, so that the transistor can be used in higher voltage scenarios to obtain greater output power and efficiency.

[0022] The barrier layer 20 is disposed on the channel layer 10. The barrier layer 20 is also called an electron supply layer. The band gap of the barrier layer 20 is larger than the band gap of the channel layer 10. The barrier layer 20 is, for example, non-intentionally doped aluminum gallium nitride (Al Y Ga 1－Y N(0<Y≤1, X<Y)). The thickness of the barrier layer 20 is, for example, 2 nm or more and 100 nm or less. A heterojunction interface is formed between the channel layer 10 and the barrier layer 20. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface.

[0023] The source electrode 1 is disposed on the barrier layer 20. The source electrode 1 is, for example, directly connected to the barrier layer 20, or may be electrically connected to the barrier layer 20 via a cap layer, or may be disposed in the channel layer 10. The source electrode 1 may be a metal electrode, such as a stacked structure of titanium (Ti) and aluminum (Al).

[0024] The drain electrode 2 is disposed on the barrier layer 20. The drain electrode 2 is, for example, directly connected to the barrier layer 20, or electrically connected to the barrier layer 20 via a cap layer, or disposed in the channel layer 10. The drain electrode 2 may be a metal electrode, such as a stacked structure of titanium (Ti) and aluminum (Al).

[0025] The gate 3 is disposed on the barrier layer 20 and between the source 1 and the drain 2. The gate 3 may be a metal electrode, for example, a metal such as titanium nitride (TiN).

[0026] The composite field plate is electrically connected to the source 1, and includes a bottom field plate 51 and a top field plate 53. The bottom field plate 51 is located on the side of the gate 3 close to the drain 2, and the top field plate 53 is located on the side of the bottom field plate 51 close to the drain 2. That is, the bottom field plate 51 is located between the gate 3 and the drain 2, and the top field plate 53 is provided between the bottom field plate 51 and the drain 2, and the top field plate 53 is closer to the drain 2 than the bottom field plate 51. In some embodiments, the positional relationship between the bottom field plate 51 and the top field plate 53 may be in a step-like shape.

[0027] The lower surface of the bottom field plate 51 is higher than the lower surface of the gate 3, and the upper surface of the bottom field plate 51 is lower than the lower surface of the top field plate 53. The lower surface of the top field plate 53 is lower than the upper surface of the gate 3, and the upper surface of the top field plate 53 is higher than the upper surface of the gate 3. In other words, from a horizontal angle comparison, the bottom field plate 51 is between the gate 3 and the top field plate 53, and the top field plate 53 is higher than the gate 3. In this way, the off-state electric field distribution of the transistor device can be adjusted. Since the bottom field plate 51 is closer to the corner position of the gate 3, the peak electric field can be reduced, and the stepped field plate makes the electric field distribution more uniform; since the top field plate 53 is higher than the gate 3, the parasitic capacitance Cgd can be reduced and the overall device gain can be improved. Optionally, the first height difference h1 between the lower surface of the bottom field plate 51 and the lower surface of the gate 3 ranges from 0.02 to 0.25 μm. The second height difference h2 between the upper surface of the top field plate 53 and the upper surface of the gate 3 is in the range of 0.12 μm<h2≤0.95 μm.

[0028] In some embodiments, the thickness H3 of the top field plate 53 is greater than the thickness H1 of the bottom field plate 51, the thickness H3 of the top field plate 53 is in the range of 0.4-0.7 μm, and the thickness H1 of the bottom field plate 51 is in the range of 0.05-0.2 μm. With this arrangement, the stepped field plate is optimized to achieve uniform electric field distribution, while reducing the projected area of ​​the gate 3 and avoiding an increase in the parasitic capacitance Cgs.

[0029] In some embodiments, to optimize the electric field distribution, the length L1 of the top field plate 53 may be greater than the length L3 of the bottom field plate 51. Optionally, the length L3 of the bottom field plate 51 ranges from 0.1 to 0.2 μm, and the length L1 of the top field plate 53 ranges from 0.2 to 0.5 μm.

[0030] In some embodiments, the first horizontal minimum spacing S1 from the bottom field plate 51 to the gate 3 is smaller than the second horizontal minimum spacing S2 from the top field plate 53 to the gate 3. By controlling the spacing between the bottom field plate 51 and the gate 3 and the spacing between the top field plate 53 and the gate 3, the field plate can be prevented from being placed on a non-planar passivation layer, and the projected area relative to the gate 3 can be increased, thereby reducing the parasitic capacitance Cgs of the transistor device. Optionally, the first horizontal minimum spacing S1 ranges from 0.05 to 0.2 μm, and the second horizontal minimum spacing S2 ranges from 0.4 to 1.1 μm. The first horizontal minimum spacing S1 is the shortest distance between the gate 3 and the bottom field plate 51 in the direction from the source 1 to the drain 2; the second horizontal minimum spacing S2 is the shortest distance between the gate 3 and the top field plate 53 in the direction from the source 1 to the drain 2.

[0031] In some embodiments, the transistor further includes a bottom passivation layer 41 and a top passivation layer 43. The bottom passivation layer 41 covers the gate 3, and the bottom field plate 51 is disposed on the bottom passivation layer 41. The top passivation layer 43 covers the bottom passivation layer 41 and the bottom field plate 51, and the top field plate 53 is disposed on the top passivation layer 43, and the upper surface of the top field plate 53 is higher than the upper surface of the top passivation layer 43 corresponding to the top of the gate 3. In this way, the parasitic capacitance of the device can be further reduced. Optionally, the thickness H5 of the bottom passivation layer 41 ranges from 0.02 to 0.1 μm, and the thickness H7 of the top passivation layer 43 ranges from 0.05 to 0.2 μm. Optionally, the third height difference h3 between the upper surface of the top field plate 53 and the upper surface of the top passivation layer 43 corresponding to the gate 3 ranges from: 0<h3≤0.45 μm.

[0032] The bottom field plate 51 does not cover the gate 3. Specifically, the projection of the bottom field plate 51 from the barrier layer 20 to the substrate below does not overlap with the projection of the gate 3 from the barrier layer 20 to the substrate. In other words, the vertical projection of the bottom field plate 51 on the barrier layer 20 does not overlap with the vertical projection of the gate 3 on the barrier layer 20. Compared with the traditional field plate covering the gate 3, the parasitic capacitance Cgs of the transistor can be reduced.

[0033] In some embodiments, the transistor further includes a dielectric layer 40. The dielectric layer 40 covers the source 1 and the drain 2, and is connected to the bottom of the gate 3. The bottom passivation layer 41 covers the dielectric layer 40. The thickness H4 of the dielectric layer 40 ranges from 0 to 0.15 μm. For example, when the gate 3 is not T-shaped, the thickness H4 of the dielectric layer 40 can be 0 μm. When the gate 3 is T-shaped, the thickness H4 of the dielectric layer 40 is 0<H4≤0.15 μm. The dielectric layer 40 is between the top of the T-shaped gate 3 and the barrier layer 20 (epitaxial layer), and surrounds the root of the gate 3.

[0034] See also Figure 3 and Figure 4 , Figure 3is a schematic diagram of the structure of a transistor provided by a second embodiment of the present invention, Figure 4 yes Figure 3 A magnified schematic diagram of area B in the middle. Figure 1 Compared with the transistor of the first embodiment, the difference of this embodiment is mainly that the composite field plate further includes at least one intermediate field plate 52, and the transistor further includes a bottom passivation layer 41, an intermediate passivation layer 42 and a top passivation layer 43. The number of intermediate field plates 52 in this embodiment is one. In some embodiments, more intermediate field plates 52 are arranged in a stepped position relationship, and the stepped position relationship from the bottom field plate 51 to the intermediate field plate 52 can be referred to. It should be noted that Figure 3 Omitted Figure 1 The channel layer 10 in the embodiment of the present invention.

[0035] The bottom passivation layer 41 covers the gate 3, and the bottom field plate 51 is arranged on the bottom passivation layer 41. The middle passivation layer 42 covers the bottom passivation layer 41 and the bottom field plate 51, and the middle field plate 52 is arranged on the middle passivation layer 42. The top passivation layer 43 covers the middle passivation layer 42 and the middle field plate 52, and the top field plate 53 is arranged on the top passivation layer 43. The upper surface of the top field plate 53 is higher than the upper surface of the top passivation layer 43 corresponding to the top of the gate 3. In other words, the top field plate 53 is arranged higher than the top passivation layer 43, so as to achieve the effect of the stepped field plate optimizing the electric field distribution and reducing the parasitic capacitance Cgd. Optionally, the thickness H6 of a single middle passivation layer 42 ranges from 0.05 to 0.2 μm. The thickness H2 of a single middle field plate 52 ranges from 0.05 to 0.2 μm, and the length L2 of a single middle field plate 52 ranges from 0.1 to 0.2 μm.

[0036] In some embodiments, the first horizontal minimum spacing S1 from the bottom field plate 51 to the gate 3 is smaller than the third horizontal minimum spacing S3 from the middle field plate 52 to the gate 3, and the third horizontal minimum spacing S3 is smaller than the second horizontal minimum spacing S2 from the top field plate 53 to the gate 3, which can avoid the field plate from being placed on the non-planar passivation layer and increase the projected area of ​​each field plate relative to the gate 3, thereby reducing the parasitic capacitance Cgs of the transistor device. The first horizontal minimum spacing S1 ranges from 0.05 to 0.2 μm, the second horizontal minimum spacing S2 ranges from 0.4 to 1.1 μm, and the third horizontal minimum spacing S3 ranges from 0.2 to 0.6 μm. In some embodiments, the horizontal spacing (S2-S1-L1) between the bottom field plate 51 and the middle field plate 52 is greater than the thickness H6 of the middle passivation layer 42; the horizontal spacing (S3-S2-L2) between the top field plate 53 and the middle field plate 52 is greater than the thickness H7 of the top passivation layer 43.

[0037] In some embodiments, the thickness H1 of the bottom field plate 51 is equal to the thickness H6 of the middle passivation layer 42 , and the thickness H2 of the middle field plate 52 is equal to the thickness H7 of the top passivation layer 43 .

[0038] In this embodiment, the thickness H4 of the dielectric layer 40 is 0.1 μm, the thickness H5 of the bottom passivation layer 41 is 0.02 μm, the thickness H6 of the middle passivation layer 42 is 0.1 μm, the thickness H7 of the top passivation layer 43 is 0.1 μm, the thickness H3 of the top field plate 53 is 0.6 μm, the length L3 of the bottom field plate 51 is 0.15 μm, the length L2 of the middle field plate 52 is 0.15 μm, and the length L1 of the top field plate 53 is 0.2 μm. The data effects corresponding to the transistor of this embodiment are shown in Table 1 below. Compared with the traditional transistor settings, the parasitic capacitances Cgs, Cgd, and Cds have all decreased. In terms of overall gain, compared with the traditional transistor settings, it has increased.

[0039] Table 1

[0040]

[0041] See also Figures 5 to 10 , Figures 5 to 10 1 is a schematic diagram of the structure of the transistor provided by the second embodiment of the present invention at each stage in the process of preparing each passivation layer and field plate. An embodiment of the present invention also provides a method for preparing a transistor, which includes the following steps:

[0042] First, if Figure 5 As shown, on the basis of the prepared transistor basic structure, a bottom passivation layer 41 is deposited on the surface of the gate 3 and the dielectric layer 40. The material of the bottom passivation layer 41 may include silicon nitride, silicon oxide, etc.

[0043] Secondly, if Figure 6 As shown, a bottom field plate 51 is disposed on the surface of the bottom passivation layer 41. Specifically, it can be formed by photolithography, metal deposition, and lift-off processes.

[0044] Then, if Figure 7 As shown, an intermediate passivation layer 42 is deposited on the surface of the bottom field plate 51 and the bottom passivation layer 41. The thickness H6 of the intermediate passivation layer 42 is the same as the thickness H1 of the bottom field plate 51, and the material of the intermediate passivation layer 42 may include silicon nitride, silicon oxide, etc.

[0045] Then, if Figure 8 As shown, an intermediate field plate 52 is disposed on the surface of the intermediate passivation layer 42. Specifically, it can be formed by photolithography, metal deposition, and stripping. The thickness H2 of the intermediate field plate 52 is the same as the thickness H6 of the intermediate passivation layer 42.

[0046] Then, if Fig. 9As shown, a top passivation layer 43 is deposited on the surface of the middle field plate 52 and the middle passivation layer 42. The thickness H7 of the top passivation layer 43 is the same as the thickness H2 of the middle field plate 52, and the material of the top passivation layer 43 may include silicon nitride, silicon oxide, etc.

[0047] Finally, if Fig.10 As shown, a top field plate 53 is disposed on the surface of the top passivation layer 43. Specifically, it can be formed by photolithography, metal deposition, and stripping. The thickness H7 of the top passivation layer 43 can be greater than or equal to the thickness H6 of the middle passivation layer 42.

[0048] The above preparation steps are used to illustrate a method for preparing a transistor, but the present invention is not limited thereto.

[0049] In some embodiments, the transistor may further include a protective passivation layer, which covers the composite field plate and the top passivation layer 43 to provide overall protection.

[0050] Accordingly, an embodiment of the present invention further provides a radio frequency amplifier, the radio frequency amplifier comprising the transistor of any of the above embodiments. An embodiment of the present invention further provides a communication device, the radio frequency amplifier can be applied to communication devices such as microwave systems, radars, wireless communication modules, network devices, etc.

[0051] In summary, the transistor, radio frequency amplifier and communication equipment provided by the present invention can effectively adjust the off-state electric field distribution of the transistor device, reduce the peak electric field, make the electric field distribution more uniform, reduce the parasitic capacitance of the transistor device, and improve the device gain by setting a bottom field plate 51 close to the gate corner and a top field plate 53 higher than the gate 3 and the bottom field plate 51.

[0052] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention can be improved in only one or several aspects, without having to solve all the technical problems listed in the prior art or background technology at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be used as a limitation on the claim.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transistor, characterized in that: The transistor comprises: Channel layer; A barrier layer, disposed on the channel layer; A source electrode, disposed on the barrier layer; A drain electrode, disposed on the barrier layer; A gate electrode, disposed on the barrier layer and located between the source electrode and the drain electrode; A composite field plate electrically connected to the source electrode; The composite field plate comprises a bottom field plate and a top field plate, wherein the bottom field plate is located on a side of the gate close to the drain, and the top field plate is located on a side of the bottom field plate close to the drain, wherein the lower surface of the bottom field plate is higher than the lower surface of the gate, the upper surface of the bottom field plate is lower than the lower surface of the top field plate, the lower surface of the top field plate is lower than the upper surface of the gate, and the upper surface of the top field plate is higher than the upper surface of the gate; The transistor further comprises a bottom passivation layer and a top passivation layer, the bottom passivation layer covers the gate, the bottom field plate is arranged on the bottom passivation layer, the top passivation layer covers the bottom passivation layer and the bottom field plate, the top field plate is arranged on the top passivation layer, and the upper surface of the top field plate is higher than the upper surface of the top passivation layer corresponding to above the gate; A projection of the bottom field plate on the gate does not overlap a projection of the top field plate on the gate.

2. The transistor according to claim 1, characterized in that: The thickness of the bottom passivation layer is in the range of 0.02-0.1 μm, and the thickness of the top passivation layer is in the range of 0.05-0.2 μm.

3. The transistor according to claim 1, characterized in that: The thickness of the top field plate is greater than that of the bottom field plate. The thickness of the top field plate is in a range of 0.4 to 0.7 μm, and the thickness of the bottom field plate is in a range of 0.05 to 0.2 μm.

4. The transistor according to claim 1, characterized in that: The length of the top field plate is greater than that of the bottom field plate. The length of the bottom field plate is in the range of 0.1 to 0.2 μm, and the length of the top field plate is in the range of 0.2 to 0.5 μm.

5. The transistor according to claim 1, characterized in that: A first horizontal minimum spacing from the bottom field plate to the gate is smaller than a second horizontal minimum spacing from the top field plate to the gate.

6. The transistor according to claim 5, characterized in that: The first horizontal minimum spacing ranges from 0.05 to 0.2 μm, and the second horizontal minimum spacing ranges from 0.4 to 1.1 μm.

7. The transistor according to claim 1, characterized in that: The bottom field plate does not cover the gate, the channel layer is an unintentionally doped gallium nitride layer, and the thickness of the channel layer ranges from 200 to 640 nm.

8. A transistor, characterized in that: The transistor comprises: Channel layer; A barrier layer, disposed on the channel layer; A source electrode, disposed on the barrier layer; A drain electrode, disposed on the barrier layer; A gate electrode, disposed on the barrier layer and located between the source electrode and the drain electrode; A composite field plate electrically connected to the source electrode; The composite field plate comprises a bottom field plate and a top field plate, wherein the bottom field plate is located on a side of the gate close to the drain, and the top field plate is located on a side of the bottom field plate close to the drain, wherein the lower surface of the bottom field plate is higher than the lower surface of the gate, the upper surface of the bottom field plate is lower than the lower surface of the top field plate, the lower surface of the top field plate is lower than the upper surface of the gate, and the upper surface of the top field plate is higher than the upper surface of the gate; The transistor further comprises a bottom passivation layer and a top passivation layer, the bottom passivation layer covers the gate, the bottom field plate is arranged on the bottom passivation layer, the top passivation layer covers the bottom passivation layer and the bottom field plate, the top field plate is arranged on the top passivation layer, and the upper surface of the top field plate is higher than the upper surface of the top passivation layer corresponding to above the gate; The composite field plate also includes at least one intermediate field plate, and the transistor also includes an intermediate passivation layer, the intermediate passivation layer covers the bottom passivation layer and the bottom field plate, the intermediate field plate is arranged on the intermediate passivation layer, the top passivation layer covers the intermediate passivation layer and the intermediate field plate, the vertical projection of the bottom field plate on the barrier layer does not overlap with the vertical projection of the intermediate field plate on the barrier layer, and the vertical projection of the top field plate on the barrier layer does not overlap with the vertical projection of the intermediate field plate on the barrier layer.

9. The transistor according to claim 8, characterized in that: The thickness of a single intermediate passivation layer is in the range of 0.05-0.2 μm.

10. The transistor according to claim 8, characterized in that: The thickness of a single intermediate field plate is in the range of 0.05 to 0.2 μm, and the length of a single intermediate field plate is in the range of 0.1 to 0.2 μm.

11. The transistor according to claim 8, characterized in that: The first minimum horizontal spacing from the bottom field plate to the gate is smaller than the third minimum horizontal spacing from the middle field plate to the gate, and the third minimum horizontal spacing is smaller than the second minimum horizontal spacing from the top field plate to the gate.

12. The transistor according to claim 11, characterized in that: The first horizontal minimum spacing ranges from 0.05 to 0.2 μm, the second horizontal minimum spacing ranges from 0.4 to 1.1 μm, and the third horizontal minimum spacing ranges from 0.2 to 0.6 μm.

13. A radio frequency amplifier, characterized in that: The radio frequency amplifier comprises the transistor according to any one of claims 1 to 12.

14. A communication device, characterized in that: The communication device comprises the radio frequency amplifier according to claim 13.

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