Communication module and switch
Patent Information
- Application Number
- CN202411513228.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2024-12-10
Smart Images
Figure CN119109891A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a communication module and a switch. Background Art
[0002] With the development of industrial automation and Internet of Vehicles, people have higher and higher requirements for communication networks. The current TSN technology is a new generation of Ethernet standard, but the current TSN communication module still has the following problems: First, it cannot fundamentally meet the transmission needs of dynamic real-time data, or cannot maintain stable low latency and low jitter under high load; Second, the transmission rate is not high, most of which is concentrated in Gigabit port communication, and the 10 Gigabit rate will cause packet loss through the module connector; Third, it cannot support multiple different types of interfaces at the same time, resulting in the inability to adapt to devices with different physical interfaces, making the application scenarios of the module relatively single and the versatility poor. Summary of the invention
[0003] In view of this, an embodiment of the present application provides a communication module and a switch, which can achieve real-time, accuracy and reliability of data transmission.
[0004] In a first aspect, an embodiment of the present application provides a communication module, comprising: a TSN switching chip module and a communication interface group, wherein the communication interface group is connected to the TSN switching chip module; wherein the printed circuit of the communication module comprises a top layer, a first power supply layer, a signal layer, a power supply layer, a second power supply layer and a bottom layer which are sequentially arranged; the TSN switching chip is arranged on the top layer; and the communication interface is arranged on the bottom layer;
[0005] The TSN switching chip module is used to adjust the clock frequency of the slave port in real time according to the time when the master port sends two adjacent synchronization messages and the time when the slave port receives the synchronization message, so that the resonance of the slave port is consistent with that of the master port;
[0006] The communication interface group is used to connect different external devices through different types of communication interfaces to achieve communication transmission between the TSN switching chip module and each of the external devices.
[0007] In some embodiments, the TSN switch chip module is specifically used for:
[0008] Determine the master-slave frequency offset ratio according to the ratio of the time difference between two adjacent times when the master port sends the synchronization message and the time difference between two adjacent times when the slave port receives the synchronization message;
[0009] Determining a target clock frequency of the slave port according to a ratio of the clock frequency of the master port to the master-slave frequency offset ratio;
[0010] The real-time frequency of the slave port is adjusted to the target clock frequency.
[0011] In some embodiments, the communication module further includes a power management module;
[0012] The power management module is connected to the TSN switch chip module and is used to supply power to the TSN switch chip module and realize timing control of the TSN switch chip module.
[0013] In some embodiments, the power management module includes a multi-channel DC-DC buck conversion circuit and a timing control circuit;
[0014] Each of the DC-DC step-down conversion circuits is used to provide different working voltages required in the communication module; each of the DC-DC step-down conversion circuits is connected to the timing control circuit, and the timing control circuit is used to control the enable and off states of each of the DC-DC step-down conversion circuits according to the output sequence of each working voltage.
[0015] In some embodiments, the timing control circuit includes a first triode and a second triode arranged in cascade; the base of the first triode is connected to a first voltage through a third resistor and a second resistor connected in series; the collector of the first triode is connected to a third voltage through a first resistor; the base of the second triode is connected to the second voltage through a fourth resistor; the collector of the second triode is connected to a series node of the second resistor and the third resistor; the first voltage is used to power the entire TSN switch chip module;
[0016] The second voltage and the third voltage are used to power corresponding circuits in the TSN switching chip module.
[0017] In some embodiments, the communication interface includes a first type of communication interface and a second type of communication interface;
[0018] The second type of communication interface is used to connect to an electrical interface device, and a connector of the second type of communication interface is connected to an input end of the power management module;
[0019] The first type of communication interface is used to connect to an optical interface device.
[0020] In some embodiments, the communication module further includes a high-speed connector; the first type of communication interface communicates with the external device through the high-speed connector;
[0021] The impedance of the high-speed connector is 100 ohms;
[0022] The insertion loss of the high-speed connector is as follows: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency is between 4 GHz < f < 8 GHz, the insertion loss is (-0.25*f + 0.5) dB; if the frequency is between 8 GHz ≤ f < 10 GHz, the insertion loss is (-0.75*f + 4.5) dB;
[0023] The crosstalk of the high-speed connector is as follows: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.
[0024] In some embodiments, the external device includes one or more combinations of a PLC, a sensor, a camera, and a bridge.
[0025] In some embodiments, the first triode and the second triode are NPN transistors.
[0026] In a second aspect, an embodiment of the present application provides a switch, and the switch includes the communication module as described above.
[0027] The embodiments of the present application have the following beneficial effects: By adjusting the clock frequency of the slave port according to the time when the master port sends the Sync message and the time when the slave port receives the Sync message in two adjacent times, the embodiments of the present application can make the resonance of the slave port consistent with that of the master port. By modifying and processing the timestamps of the incoming TSN data, the accuracy, real-time performance, and stability of data transmission can be achieved, thereby reducing the latency and jitter of data transmission, and further solving the technical problem that the existing standard Ethernet communication module cannot meet the transmission requirements of dynamic real-time data. Further, the communication interfaces of the present application include optical interfaces and electrical interfaces to achieve the versatility of the communication module. Furthermore, through the stacked design of the printed circuit, the embodiments of the present application ensure that there is no packet loss through the connector at a 10 Gigabit communication rate, meeting the design of the communication module for high-speed communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0029] Figure 1 Shows a first schematic structural diagram of the communication module according to an embodiment of the present application;
[0030] Figure 2 Shows a second schematic structural diagram of the communication module according to an embodiment of the present application;
[0031] Figure 3 A schematic diagram of a process for adjusting the clock frequency of a slave port according to an embodiment of the present application is shown;
[0032] Figure 4 A schematic diagram of master and slave port timestamps in an embodiment of the present application is shown;
[0033] Figure 5 A schematic diagram of a timing control circuit according to an embodiment of the present application is shown;
[0034] Figure 6 A schematic diagram of the stacking of the printed circuit of the communication module of an embodiment of the present application is shown. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0036] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0037] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0038] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0039] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0040] Since traditional Ethernet has limitations in high bandwidth and low latency, especially in a multi-node, high-real-time network environment, most Ethernet currently uses TSN technology to improve data transmission stability. However, existing communication modules still have deficiencies in integration, high bandwidth, and low latency, mainly reflected in:
[0041] High latency: Traditional Ethernet can only process static data and is not suitable for dynamic real-time data transmission.
[0042] The transmission rate is not high: Most modules can only reach a 1 Gigabit rate, and packet loss is prone to occur at a 10 Gigabit rate.
[0043] Single interface: Existing modules do not support multiple interfaces and their application scenarios are limited.
[0044] Based on this, the present application proposes a communication module and switch based on a time-sensitive network switching chip. The communication module can achieve high-bandwidth and low-latency data transmission, ensuring the real-time, accuracy and reliability of data transmission. The modular and highly integrated design reduces the need for external components, reduces the complexity and cost of the module design, and can adapt to the ever-changing network scale and different application scenarios.
[0045] The communication module is described below in conjunction with some specific embodiments.
[0046] Figure 1 A schematic diagram of the structure of a communication module of an embodiment of the present application is shown. Exemplarily, the communication module includes: a TSN switching chip module 100 and a communication interface group 200;
[0047] The TSN switching chip module 100 is used to process communication data with an external device 300, and adjust the clock frequency of the slave port in real time according to the time when the master port sends two adjacent synchronization messages (Sync messages) and the time when the slave port receives the synchronization message, so that the resonance of the slave port is consistent with that of the master port.
[0048] In some embodiments, Figure 2 As shown, the TSN switch chip module 100 is used to process communication data with an external device 300, including but not limited to scheduling and forwarding of data packets, etc. The TSN switch chip module 100 includes but is not limited to a TSN switch chip 110, a DDR circuit 120, a reset circuit 130, a storage circuit 140 and a crystal oscillator circuit 150, etc.
[0049] Among them, the TSN switching chip 110 is the core of the TSN switching chip module 100 and also the core of the communication module. It is used to process and transmit time-sensitive data, parse, identify and process the sent and received data. After receiving the TSN data, it will parse and identify the timestamp, priority, etc. in the TSN data; when forwarding the TSN data, it can give priority to forwarding high-priority data; in addition, before forwarding the data, the built-in processor of the TSN switching chip 110 will adjust the clock frequency of the slave port in real time to achieve consistency with the resonance of the master port, so as to improve the time accuracy of TSN stream data forwarding, so as to achieve the effect of reducing latency, thereby ensuring the real-time, accuracy and reliability of data transmission.
[0050] like Figure 3 As shown, in this embodiment, the steps of the TSN switching chip module 100 adjusting the clock frequency of the slave port in real time mainly include:
[0051] Step S100, determining a master-slave frequency offset ratio according to a ratio of a time difference between two consecutive synchronization messages sent by the master port and a time difference between two consecutive synchronization messages received by the slave port.
[0052] Step S200, determining a target clock frequency of the slave port according to a ratio of the clock frequency of the master port to a master-slave frequency offset ratio.
[0053] Step S300: adjusting the real-time frequency of the slave port to the target clock frequency.
[0054] It is understandable that Figure 4 As shown, the slave port determines the time of the last synchronization message sent by the master port based on the synchronization message received from the master port, which is recorded as t1_pred, and the time when it receives the synchronization message is recorded as t2_pred. These two values are continuously updated as the synchronization process progresses; then the slave port records the time when it receives the synchronization message sent by the master port this time as t1, and records the time when it receives the synchronization message this time as t2. Since the link delay is sufficiently stable, the difference between the timestamps t1_pred and t1 recorded by the master port from the last synchronization to this synchronization is the same as the actual time interval between the difference between the timestamps t1_pred and t1 recorded by the slave port, so the embodiment of the present application can calculate the master-slave frequency offset ratio based on t1_pred, t2_pred, t1 and t2.
[0055] The frequency offset is calculated as follows: rateRatio=(t1-t1_pred) / (t2-t2_pred); wherein rateRatio is the master-slave frequency offset ratio.
[0056] For the master port, its own clock frequency can be obtained from the master real-time clock, and then the target clock frequency of the slave port can be determined based on the obtained clock frequency of the master port and the master-slave frequency offset ratio; the calculation formula for the target clock frequency is: f_slave = f_master / rateRatio; where f_slave is the target clock frequency and f_master is the clock frequency of the master port.
[0057] After calculating the target clock frequency, the clock frequency of the slave port is adjusted to the target clock frequency. The embodiment of the present application continuously adjusts the frequency of the real-time clock from the slave port to maintain resonance with the master port, thereby reducing errors caused by abnormalities in the PTP protocol, improving the robustness of the PTP clock network timing, and achieving improved accuracy of master-slave synchronization.
[0058] Among them, DDR is a high-speed memory. In the TSN switching chip 110, DDR is mainly used as a high-speed cache memory for fast storage and retrieval of data and speeding up data processing. The connection between it and the TSN switching chip 110 is reflected in the fast exchange and processing of data. DDR can provide instant data access when the chip needs it, thereby improving the overall performance of the communication module.
[0059] Among them, the reset circuit 130 is a hardware or software logic circuit used to restore the communication module to an initial state when the communication module is started or in a specific error state; in the TSN switching chip module 100, the reset circuit 130 ensures that when the communication module is started or needs to be reinitialized, all registers and processor states are restored to a predefined initial state, which is crucial to ensure that the communication module operates stably under various conditions.
[0060] The storage circuit 140 is a Flash circuit. In the TSN switch chip module 100, the Flash circuit is used to store important data such as the system startup code, configuration information, firmware updates, etc. When the communication module is started, the Flash circuit provides a startup program to the communication module to ensure that data can be saved even after power failure. The connection between this and the TSN chip is to provide a basic environment for the startup and operation of the communication module.
[0061] Among them, the crystal oscillator circuit 150 (Crystal Oscillator Circuit) is a circuit that generates a precise clock signal, which is crucial for any communication module that requires a precise time reference, especially for communication protocols that require time sensitivity such as TSN. The TSN chip relies on a precise clock signal to accurately transmit data and timestamp processing. The connection between the crystal oscillator circuit 150 and the TSN chip is to provide a stable clock signal to ensure the real-time and accuracy of data transmission.
[0062] The DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150 interact with the TSN switch chip 110 through circuit connection, data signal transmission, etc., and together form an efficient and reliable communication module.
[0063] The TSN switching chip module 100 of the embodiment of the present application integrates 8 Gigabit copper phys and 4 Serdes high-speed serial deserializers, and can be directly connected to a 10 Gigabit optical module; among them, 8 ports (8 Gigabit copper phys) support 100 / 1000BASE-T, and four ports (4 Serdes high-speed serial deserializers) are Serdes interfaces, which can be configured as SGMII / 100BAS-FX / 1000BASE-X / 2500BASE-X / 5GBASE-R / 10GBASE-R1; the TSN switching chip 110 has a built-in ARM dual-core processor based on the Cortex A55 architecture with a frequency of 1.2GhZ, and uses a 256Mb SPI FLASH to complete the loading of the system startup program, and an external 2Gb DDR3 SDRAM is used for program operation and data storage. The TSN switching chip 110 can be a DX15XX chip.
[0064] The communication module of the embodiment of the present application further includes a communication interface group 200, which is connected to the TSN switch chip module 100 and is used to connect different external devices 300 through different types of communication interfaces, and to realize communication transmission between the TSN switch chip module 100 and the external device 300. The external device 300 includes but is not limited to terminal devices such as PLC, sensor, camera, bridge, etc.
[0065] The communication interface group 200 includes a first type communication interface 210 and a second type communication interface 220; the second type communication interface 220 is used to connect an electrical interface device, and a connector of the second type communication interface 220 is connected to an input end of the power management module 400; the first type communication interface 210 is used to connect an optical interface device.
[0066] It can be understood that the first type of communication interface 210 is connected to the 4 Serdes ports of the TSN switch chip module 100 to provide high-speed data transmission with the external device 300. This interface supports a data transmission rate of at least 10 Gbps for 4 channels and can be externally connected to an SFP+ optical interface device. This communication interface is connected to the external device 300 through a high-speed connector. In this application, in order to ensure the data transmission rate and signal integrity, for the high-speed connector, parameters such as characteristic impedance, insertion loss, and crosstalk need to be strictly controlled. In the embodiment of this application, the impedance of the high-speed connector is 100 ohms; the insertion loss needs to meet the following conditions: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency range is 4 GHz < f < 8 GHz, the insertion loss is (-0.25*f + 0.5) dB, that is, from 4 GHz to 8 GHz, the greater the frequency, the greater the insertion loss; if the frequency range is 8 GHz ≤ f < 10 GHz, the insertion loss is (-0.75*f + 4.5) dB, that is, from 8 GHz to 10 GHz, the greater the frequency, the greater the insertion loss; its crosstalk is: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.
[0067] The second type of communication interface 220 is connected to the 8 ports of the TSN switch chip module 100 that support 100 / 1000BASE-T to provide high-speed data transmission with the external device 300. This interface supports a data transmission rate of at least 1000 Mbps for 8 channels and can be externally connected to an RJ45 electrical interface device. This communication interface is connected to the external device 300 through a European-style connector. In addition, the second type of communication interface 220 also includes some control signals and power input signals, such as GPIO, I2C, RS232, etc. signals, which are responsible for the status monitoring and fault diagnosis of the communication module. In the embodiment of this application, it can interact with the user through a user interface, allowing the user to set parameters and monitor the status of the communication module. This control signal is configured as output or input by the built-in processor of the TSN switch chip module 100 and is connected to the external device 300 through a European-style connector.
[0068] In some embodiments, the communication module of the embodiment of this application further includes a power management module 400. The power management module is connected to the TSN switch chip module 100 and is used to supply power to the TSN switch chip module 100 and implement timing control of the TSN switch chip module; the power management module includes a multi-channel DC-DC buck conversion circuit and a timing control circuit; each DC-DC buck conversion circuit is used to provide different operating voltages required in the communication module.
[0069] Exemplarily, a DC-DC buck conversion circuit is provided between the TSN switching chip 110, the DDR circuit 120, the reset circuit 130, the storage circuit 140 and the crystal oscillator circuit 150 and the power management module; wherein the DC-DC buck conversion circuit is used to convert the output voltage of the power management module into an operating voltage corresponding to the TSN switching chip 110, the DDR, the reset circuit 130, the storage circuit 140 and the crystal oscillator circuit 150.
[0070] It can be understood that the power management module 400 is used to provide power management for the entire communication module, including but not limited to voltage conversion, timing control, etc. The input end of the power management module 400 is connected to the connector of the second type communication interface 220, and the output end is connected to the TSN switch chip module 100. The input voltage of the power management module 400 can be 3.3V, 5V or 12V. When supplying power to the TSN switch chip 110, DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150, it can be converted into a corresponding working voltage value through a DC-DC step-down conversion circuit according to the needs of the TSN switch chip 110, DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150, and provide voltage to power-consuming circuits such as the TSN switch chip 110, DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150. In addition, the embodiment of the present application controls the on and off of the enable pin of each DC-DC buck conversion circuit by connecting each DC-DC buck conversion circuit to implement a power timing control circuit, thereby achieving the order of controlling the output voltage of each DC-DC buck conversion circuit.
[0071] For example, Figure 5 As shown, the timing control circuit includes a first transistor Q1 and a second transistor Q2 arranged in cascade; the base of the first transistor Q1 is connected to a first voltage V1 through a third resistor R3 and a second resistor R2 connected in series; the collector of the first transistor Q1 is connected to a third voltage V3 through the first resistor R1; the base of the second transistor is connected to the second voltage V2 through a fourth resistor; the collector of the second transistor Q2 is connected to the series node of the second resistor R2 and the third resistor R3.
[0072] The first voltage V1 is used to power the entire TSN switching module; the second voltage V2 is used to power the corresponding circuit in the TSN switching module; the third voltage V3 is used to provide a power supply voltage to the DC-DC buck conversion circuit; the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are both grounded. The first transistor Q1 and the second transistor Q2 are both NPN transistors.
[0073] It can be understood that the first voltage V1 is used to power the entire TSN switching chip module 100, and the second voltage V2 is used to control the power-on of the third voltage V3, so as to achieve the control of the order of output voltages. Specifically, when the first voltage V1 is powered, it is connected to the base of the first transistor Q1 through the second resistor R2 and the third resistor R3, the emitter of the first transistor Q1 is connected to the digital ground, and the collector of the first transistor Q1 is connected to the enable pin of the DC-DC buck converter circuit of the third voltage to be controlled. At this time, the PN junction of the first transistor Q1 is forward biased, the first transistor Q1 is turned on, the enable pin is turned on with the digital ground, and the voltage of the enable pin is lower than the start threshold of the DC-DC buck converter circuit of the third voltage V3, so the third voltage V3 cannot be output; when the second voltage V2 is powered, the third voltage V3 cannot be output; when the second voltage V2 is powered, the third voltage V3 cannot be output; when the second voltage V2 is powered, the third voltage V3 cannot be output; when the second voltage V2 is powered, the third voltage V3 cannot be output; When the power is on, the base of the second transistor Q2 is connected through the fourth resistor R4, the emitter of the second transistor Q2 is connected to the digital ground, the collector of the second transistor Q2 is connected to the base of the first transistor Q1 through the third resistor R3, and is connected to the first voltage V1 through the second resistor R2. At this time, the PN junction of the second transistor Q2 is forward biased, the second transistor Q2 is turned on, resulting in a decrease in the base voltage of the first transistor Q1, the first transistor Q1 is turned off, and the enable pin voltage of the third voltage V3 is pulled high, which is higher than the start-up threshold of the DC-DC step-down conversion circuit, so the third voltage V3 is powered normally.
[0074] The embodiment of the present application ensures that all relevant power supply voltages are provided to different parts of the TSN switching chip module 100 at the appropriate time through power timing control, which avoids startup failure or erroneous behavior caused by improper power supply; further, power timing control also helps to enhance the stability of the entire communication module. When the power supply is interrupted or restored, correct timing control can prevent power interference from causing the communication module to crash, protect data security and normal operation of the module; that is, power timing control can ensure that the communication module operates stably according to the predetermined working state, thereby improving the reliability and performance of the equipment.
[0075] In some embodiments, Figure 6As shown, the printed circuit of the communication module includes a top layer, a first power ground layer, a signal layer, a power layer, a second power ground layer and a bottom layer arranged in sequence; wherein, the TSN switching chip is arranged at the top layer; the communication interface group is arranged at the bottom layer; the communication interface group wiring adopts differential 100 ohm impedance matching; the power management module 400 is arranged at the top layer or the bottom layer; in the embodiment of the present application, the printed circuit of the communication module is provided with two layers of power ground layers (the first power ground layer and the second power ground layer), the first power ground layer is arranged between the top layer and the signal layer, the second power ground layer is arranged between the power layer and the bottom layer, and the signal layer and the power layer are arranged adjacently, so that each routing layer has a reference ground plane, and then the impedance of each routing layer can be better controlled, and the two power ground layers can absorb magnetic lines of force well. Since each routing layer has an adjacent power ground layer, the power ground layer can provide a better return path for each signal layer (routing layer). Further, in order to shorten the routing distance from the impedance transformation point to different communication interfaces and ensure the signal quality, the four Serdes ports of the TSN switching chip module 100 can be arranged near the data transmission interface.
[0076] The communication module of the embodiment of the present application provides a deterministic time-sensitive network technology through the TSN switching chip module 100. By modifying and processing the timestamp of the incoming TSN data, the accuracy, real-time and stability of data transmission can be achieved, thereby reducing the delay and jitter of data transmission, and further solving the technical problem that the existing standard Ethernet communication module cannot meet the transmission requirements of dynamic real-time data. In addition, the embodiment of the present application ensures that the 10G communication rate does not lose packets through the connector through the stacked design of the printed circuit, meeting the communication module design for high-speed communication; further, the communication interface of the present application includes an optical interface and an electrical interface to achieve the versatility of the communication module.
[0077] In some embodiments, the present application also provides a switch, which includes the above-mentioned communication module.
[0078] It can be understood that the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.
[0079] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A communication module, characterized in that: include: A TSN switching chip module and a communication interface group, wherein the communication interface group is connected to the TSN switching chip module; The printed circuit of the communication module includes a top layer, a first power layer, a signal layer, a power layer, a second power layer and a bottom layer which are arranged in sequence; the TSN switching chip is arranged on the top layer; and the communication interface is arranged on the bottom layer; The TSN switching chip module is used to adjust the clock frequency of the slave port in real time according to the time when the master port sends two adjacent synchronization messages and the time when the slave port receives the synchronization message, so that the resonance of the slave port is consistent with that of the master port; The communication interface group is used to connect different external devices through different types of communication interfaces to achieve communication transmission between the TSN switching chip module and each of the external devices.
2. The communication module according to claim 1, characterized in that: The TSN switching chip module is specifically used for: Determine the master-slave frequency offset ratio according to the ratio of the time difference between two adjacent times when the master port sends the synchronization message and the time difference between two adjacent times when the slave port receives the synchronization message; Determining a target clock frequency of the slave port according to a ratio of the clock frequency of the master port to the master-slave frequency offset ratio; The real-time frequency of the slave port is adjusted to the target clock frequency.
3. The communication module according to claim 1, characterized in that: The communication module also includes a power management module; The power management module is connected to the TSN switch chip module and is used to supply power to the TSN switch chip module and realize timing control of the TSN switch chip module.
4. The communication module according to claim 3, characterized in that: The power management module includes a multi-channel DC-DC step-down conversion circuit and a timing control circuit; Each of the DC-DC step-down conversion circuits is used to provide different working voltages required in the communication module; each of the DC-DC step-down conversion circuits is connected to the timing control circuit, and the timing control circuit is used to control the enable and off states of each of the DC-DC step-down conversion circuits according to the output sequence of each working voltage.
5. The communication module according to claim 4, characterized in that: The timing control circuit comprises a first triode and a second triode arranged in cascade; the base of the first triode is connected to a first voltage through a third resistor and a second resistor connected in series; the collector of the first triode is connected to a third voltage through the first resistor; the base of the second triode is connected to the second voltage through a fourth resistor; the collector of the second triode is connected to a series node of the second resistor and the third resistor; The first voltage is used to power the entire TSN switch chip module; The second voltage and the third voltage are used to power corresponding circuits in the TSN switching chip module.
6. The communication module according to claim 3, characterized in that: The communication interface includes a first type of communication interface and a second type of communication interface; The second type of communication interface is used to connect to an electrical interface device, and a connector of the second type of communication interface is connected to an input end of the power management module; The first type of communication interface is used to connect to an optical interface device.
7. The communication module according to claim 6, characterized in that: The communication module further includes a high-speed connector; the first type of communication interface communicates with the external device via the high-speed connector; The impedance of the high-speed connector is 100 ohms; The insertion loss of the high-speed connector is as follows: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency is between 4 GHz < f < 8 GHz, the insertion loss is (-0.25*f + 0.5) dB; if the frequency is between 8 GHz ≤ f < 10 GHz, the insertion loss is (-0.75*f + 4.5) dB. The crosstalk of the high-speed connector is as follows: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.
8. The communication module according to claim 1, characterized in that: The external device includes one or more combinations of a PLC, a sensor, a camera, and a bridge.
9. The communication module according to claim 5, characterized in that: The first triode and the second triode are NPN transistors.
10. A switch, characterized in that: The switch includes the communication module according to any one of claims 1-9.
Citation Information
Cited By
Communication module and switch
WO2026091460A1