A compound Hall integrated chip and its preparation method

Abstract

A compound Hall integrated chip and a preparation method thereof. The preparation method is to form grooves on the wafer surface of a silicon-based signal conditioning chip after the device manufacturing process through yellow light and etching, deposit a dielectric film and an organic adhesive in the grooves respectively, then assemble a compound Hall element into the interior of the grooves, fill the grooves with a dielectric layer, and finally use CONTACT, VIA, and interconnect lines to achieve signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, thus finally obtaining the compound Hall integrated chip. By means of heterogeneous integration, the present invention combines a compound Hall element and a silicon-based signal conditioning chip together to form a single compound Hall integrated chip, which has performance advantages such as sensitivity and temperature drift characteristics compared with a single-chip silicon-based Hall.

Description

Technical Field

[0001] The present invention relates to the technical field of Hall chips, and particularly relates to a compound Hall integrated chip and a preparation method thereof. Background Art

[0002] A Hall chip can convert an externally input magnetic field into an output electrical signal, and detect the magnetic field change through the electrical signal. The Hall chip mainly consists of two parts: a signal conditioning circuit and a Hall element. Among them, the signal conditioning circuit is generally fabricated on a silicon-based substrate using standard integrated circuit processes, and mainly includes functional module elements such as amplification, filtering, oscillation, clock, and storage. The Hall element can be divided into silicon-based and compound-based (GaAs / InSb / InAs, etc.) according to the substrate. Due to the material property advantages of the compound substrate such as carrier concentration and carrier mobility, the compound-based Hall element has higher sensitivity and better temperature characteristics than the silicon-based Hall element.

[0003] Currently, Hall chips in the industry are divided into two types. The first type is a pure silicon-based Hall and silicon-based signal conditioning circuit integrated chip. This chip is limited by the silicon-based material itself and has problems such as low sensitivity and poor temperature drift. The second type is to integrate a compound Hall chip and a silicon-based signal conditioning circuit chip in the same package through die bonding, wire bonding, and encapsulation. Package-level integration generally means bonding the compound Hall chip and the silicon-based signal conditioning circuit chip separately during die bonding, then interconnecting them through wire bonding between the compound Hall chip and the silicon-based signal conditioning circuit chip, and finally encapsulating them together into the package to achieve integration. This chip benefits from the advantages of compound materials and is significantly superior to the first type of pure silicon-based Hall chip in terms of Hall electrical performance indicators. However, this co-packaging method has disadvantages such as large package volume, high difficulty in alignment accuracy, long signal transmission path, and poor package reliability. Currently, there is no method in the industry to obtain a single-chip integrated compound Hall and silicon-based signal conditioning circuit through heterogeneous integration.

[0004] The complete wafer manufacturing process can be divided into three parts from front to back: device manufacturing process → CONTACT manufacturing process → interconnect manufacturing process. Among them, the device manufacturing process mainly includes related processes such as active area definition, ion implantation, and oxidation isolation device function definition; the CONTACT manufacturing process is to connect functional devices and interconnects through a via structure; the interconnect manufacturing process mainly includes related processes such as VIA vias, metal interconnects, metal pads, dielectric layers, and passivation layers for signal lines.

[0005] Aiming at the deficiencies of the prior art, this solution provides a compound Hall integrated chip and a preparation method thereof to solve the problem of heterogeneous integration of existing compound Hall and silicon-based signal conditioning circuits. Summary of the Invention

[0006] The important significance of the present invention lies in solving the problem that the current compound Hall and silicon-based signal conditioning circuits cannot be hetero-integrated, and providing a preparation method for a compound Hall integrated chip. The preparation method of the compound Hall integrated chip first proposes to integrate a compound Hall element and a silicon-based signal conditioning chip together through hetero-integration to form a single compound Hall integrated chip; it overcomes the current implementation method of only realizing the dual-chip co-packaging of the compound Hall chip and the silicon-based signal conditioning chip at the packaging level. The prepared compound Hall integrated chip has the characteristics of higher integration, higher precision, better performance, and higher reliability.

[0007] The above object of the present invention is achieved by the following technical measures:

[0008] Provide a structure and a preparation method for a compound Hall integrated chip. After the device manufacturing process is completed, grooves are formed on the wafer surface of the silicon-based signal conditioning chip through yellow light and etching. A dielectric film is deposited and an organic adhesive is coated in the grooves. Then, the compound Hall element is assembled into the interior of the grooves. Next, the grooves are filled with a dielectric layer. Finally, signals are connected between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip by using CONTACT, VIA, and interconnections, and the compound Hall integrated chip is finally obtained.

[0009] The preparation method of the compound Hall integrated chip of the present invention is carried out by the following steps:

[0010] S1. Perform device manufacturing processes on the wafer to obtain a silicon-based signal conditioning chip;

[0011] S2. On the wafer surface of the silicon-based signal conditioning chip obtained in S1, form grooves through yellow light and etching, and deposit a dielectric film and coat an organic adhesive in the grooves;

[0012] S3. Assemble the compound Hall element into the interior of the grooves obtained in S2, and enter S4;

[0013] S4. Deposit a dielectric layer on the wafer surface to fill the gap between the grooves and the compound Hall element, thereby completing the chip surface planarization operation and entering S5;

[0014] S5. Perform the CONTACT manufacturing process, and then perform the interconnection manufacturing process. The interconnection manufacturing process includes the fabrication of VIA structure, METAL structure, output signal pad PAD, and passivation layer structure to realize signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.

[0015] Preferably, the above S2 is carried out by the following steps:

[0016] S2.1. Perform yellow light exposure and etching on the S1 silicon-based signal conditioning chip to obtain a first groove structure;

[0017] S2.2. Deposit a dielectric film on the inner surface of the first groove structure obtained in S2.1 to obtain a second groove structure;

[0018] S2.3. Coat an organic adhesive on the bottom of the second groove structure obtained in S2.2 to obtain the groove.

[0019] Preferably, the width of the above-mentioned first groove structure increases sequentially from the bottom to the opening direction, and the cross-sectional shape of the first groove structure is an inverted trapezoid.

[0020] Preferably, S2.3 is specifically to spin-coat a layer of organic adhesive on the inner surface of the wafer of the second groove structure obtained in S2.2, and then only retain the organic adhesive at the bottom of the second groove structure through exposure and development to obtain the groove.

[0021] Preferably, the bottom width of the above-mentioned first groove structure is greater than the maximum length of the compound Hall element.

[0022] Preferably, the bottom width of the above-mentioned first groove structure is 100 μm to 250 μm.

[0023] Preferably, the opening width of the above-mentioned first groove structure is 150 μm to 300 μm.

[0024] Preferably, the depth of the above-mentioned first groove structure is 1 μm to 10 μm.

[0025] Preferably, the thickness of the above-mentioned dielectric film is 1 nm to 5 nm.

[0026] Preferably, the thickness of the above-mentioned organic adhesive is 1 nm to 5 nm.

[0027] Preferably, the above-mentioned silicon-based signal conditioning chip is provided with a substrate and functional module elements constituting a silicon-based signal conditioning circuit.

[0028] Another object of the present invention is to provide a compound Hall integrated chip to avoid the deficiencies of the prior art. The compound Hall integrated chip can have the characteristics of higher integration, higher precision, and higher reliability.

[0029] The above object of the present invention is achieved by the following technical measures:

[0030] Provide a compound Hall integrated chip, which is prepared by using the preparation method of the above-mentioned compound Hall integrated chip.

[0031] A compound Hall integrated chip and its manufacturing method according to the present invention. The manufacturing method includes forming a groove on the wafer surface of a silicon-based signal conditioning chip after the device manufacturing process through yellow light and etching, depositing a dielectric film and coating an organic adhesive in the groove respectively, then assembling a compound Hall element into the inside of the groove, filling the groove with a dielectric layer, and finally using CONTACT, VIA, and interconnecting lines to achieve signal connection between the compound Hall element and the functional module elements of the silicon-based signal conditioning chip, thus finally obtaining the compound Hall integrated chip. The present invention integrates a compound Hall element and a silicon-based signal conditioning chip through heterogeneous integration to form a single compound Hall integrated chip, which has performance advantages such as sensitivity and temperature drift characteristics compared with a single-chip silicon-based Hall. Moreover, compared with the dual-chip co-packaging method of a compound Hall element and a silicon-based signal conditioning circuit in the prior art, the present invention has the advantages of higher integration, higher precision, and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip to provide a wafer integration space for the compound Hall, so as to achieve the purpose of wafer integration of the compound Hall and the silicon-based signal conditioning circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention is further described with reference to the accompanying drawings, but the content in the drawings does not constitute any limitation to the present invention.

[0033] Figure 1 It is a schematic diagram of the compound Hall integrated chip of the present invention.

[0034] Figure 2 is Figure 1 a cross-sectional schematic diagram in the direction of “A-A” in

[0035] Figure 3 It is a structural schematic diagram of the silicon-based signal conditioning chip.

[0036] Figure 4 It is a schematic diagram of the silicon-based signal conditioning chip after S2.1 processing.

[0037] Figure 5 It is a schematic diagram of the silicon-based signal conditioning chip after S2.2 processing.

[0038] Figure 6 is Figure 5 a top view of

[0039] Figure 7 It is a schematic diagram of the silicon-based signal conditioning chip after S2.3 processing.

[0040] Figure 8 is Figure 7 a partial enlarged schematic diagram of the groove in

[0041] Figure 9Schematic diagram after assembling the compound Hall element into the groove in S3.

[0042] Figure 10 Schematic diagram after depositing the dielectric layer in S4.

[0043] In Figures 1 to 10 it includes:

[0044] Silicon-based signal conditioning chip 100,

[0045] First groove structure 200, dielectric thin film 210, organic adhesive 220,

[0046] Dielectric layer 300, compound Hall element 400, CONTACT structure 500, VIA structure / METAL structure 600, output signal pad PAD700, substrate 800, functional module element 900. Detailed implementation manners

[0047] The technical solution of the present invention will be further described in conjunction with the following embodiments.

[0048] Embodiment 1

[0049] A preparation method of a compound Hall integrated chip. After the device manufacturing process is completed, a groove is formed on the wafer surface of the silicon-based signal conditioning chip 100 through yellow light and etching. A dielectric thin film 210 is deposited and an organic adhesive 220 is coated in the groove. Then, the compound Hall element 400 is assembled into the inside of the groove, and then filled with the dielectric layer 300. Finally, signals are connected between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100 by using CONTACT, VIA, and interconnecting lines, and finally a compound Hall integrated chip is obtained, as shown in Figure 1 and Figure 2 shown.

[0050] It should be noted that in the conventional wafer processing of silicon-based Hall chips, from front to back, there are three major parts: device manufacturing process → CONTACT manufacturing process → interconnecting line manufacturing process. The present invention innovatively introduces a structure and its process method between the device manufacturing process and the CONTACT manufacturing process to achieve chip-level integration of the compound Hall and the silicon-based signal conditioning circuit, and solve the problem of heterogeneous integration of the current compound Hall and the silicon-based conditioning circuit on the same wafer. Specifically, the present invention forms a groove on the wafer surface after the device manufacturing process is completed through yellow light and etching, coats an adhesive layer in the groove, assembles the compound Hall element 400 in the groove, fills and planarizes the dielectric layer 300. Thus, the new structure and process are completed. Subsequently, the CONTACT manufacturing process and the interconnecting line manufacturing process are carried out according to the standard process, and finally a compound Hall integrated chip is obtained.

[0051] It can be seen that the preparation method of the compound Hall integrated chip of the present invention overcomes the current implementation method that can only achieve the dual-chip co-packaging of the compound Hall chip and the silicon-based signal conditioning chip 100 at the packaging level. The prepared compound Hall integrated chip has the characteristics of higher integration, higher precision, better performance, and higher reliability.

[0052] Among them, the silicon-based signal conditioning chip 100 of the present invention is obtained by processing through device manufacturing processes and before the CONTACT manufacturing process in the prior art. The specific structure of the silicon-based signal conditioning chip 100 is not the key point of the present invention. The silicon-based signal conditioning chip 100 is provided with a substrate 800 and functional module elements 900 constituting the silicon-based signal conditioning circuit. The functional module elements 900 can be elements such as amplification, filtering, oscillation, clock, and storage, and these functional module elements 900 form the conditioning circuit of the silicon-based signal conditioning chip 100. Moreover, the device manufacturing process, the CONTACT manufacturing process, and the interconnection line manufacturing process all belong to the conventional technical means of integrated chips, and those skilled in the art should know the specific operation process.

[0053] The preparation method of the compound Hall integrated chip of the present invention is carried out by the following steps:

[0054] S1. Perform device manufacturing processes on the wafer to obtain the silicon-based signal conditioning chip 100, such as Figure 3 , and the silicon-based signal conditioning chip 100 has not been processed through the CONTACT process;

[0055] S2. Form a groove on the wafer surface of the silicon-based signal conditioning chip 100 obtained in S1 through yellow light and etching, and deposit a dielectric film 210 and coat an organic adhesive 220 in the groove. Among them, S2 is specifically carried out by the following steps:

[0056] S2.1. Perform yellow light and etching on the silicon-based signal conditioning chip 100 in S1 to obtain a first groove structure 200, such as Figure 4 ; among them, the width of the first groove structure 200 increases sequentially from the bottom to the opening direction, and the cross-sectional shape of the first groove structure 200 is an inverted trapezoid. The bottom width of the first groove structure 200 is greater than the maximum length of the compound Hall element 400. The bottom width of the first groove structure 200 is 100 μm to 250 μm, the opening width of the first groove structure 200 is 150 μm to 300 μm, and the depth of the first groove structure 200 is 1 μm to 10 μm;

[0057] S2.2. Deposit a dielectric film 210 on the inner surface of the first groove structure 200 obtained in S2.1 to obtain a second groove structure, such as Figure 5 and Figure 6 , where the thickness of the dielectric film 210 is 1 nm to 5 nm;

[0058] S2.3. Apply an organic adhesive 220 to the bottom of the second groove structure obtained in S2.2 to obtain a groove, as shown in Figure 7 and Figure 8 , where the thickness of the organic adhesive 220 is 1 nm to 5 nm;

[0059] S3. Assemble the compound Hall element 400 into the interior of the groove obtained in S2, and proceed to S4, as shown in Figure 9 ;

[0060] S4. Deposit a dielectric layer 300 on the wafer surface to fill the gap between the groove and the compound Hall element 400, thereby completing the planarization operation on the chip surface and proceeding to S5, as shown in Figure 10 , where the dielectric layer 300 is SiO 2 ;

[0061] S5. Perform the CONTACT manufacturing process, and then perform the interconnect manufacturing process. The interconnect manufacturing process includes the fabrication of the VIA structure 600, METAL structure 600, output signal pad PAD700, and passivation layer structure to achieve signal connection between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100, and finally obtain the compound Hall integrated chip.

[0062] It should be noted that the function of the organic adhesive 220 is to temporarily fix the compound Hall element 400. By depositing the dielectric layer 300 on the wafer surface in S4, the compound Hall element 400 can be completely fixed on the wafer and form an integral structure with the silicon-based signal conditioning chip 100. The width of the first groove structure 200 increases sequentially from the bottom to the opening direction, that is, the cross-sectional shape of the first groove structure 200 is an inverted trapezoid, and the overall shape of the first groove structure is an inverted trapezoid. The advantage of this structure is that it is convenient for the uniform deposition of the dielectric layer 300. The material of the compound substrate 800 of the compound Hall element 400 can be GaAs, InSb, InAs, etc.

[0063] The compound Hall element 400 of the present invention is prepared by pre-preparing a Hall chip wafer of the compound substrate 800 (including the Hall functional area and interconnects) and completing thinning and cutting to separate each compound Hall element 400, and then picking up a single compound Hall element 400 and assembling it into the groove.

[0064] In S4 of the present invention, by depositing the dielectric layer 300, the dielectric layer 300 is filled in the gap between the groove and the compound Hall element 400, and then continuous deposition is carried out to form a planarized structure surface on the surface of the first integrated chip.

[0065] Specifically, in S2.3, an organic adhesive 220 is spin-coated on the inner surface of the second groove structure obtained in S2.2, and then, through exposure and development, only the organic adhesive 220 at the bottom of the second groove structure is retained to obtain a groove.

[0066] It should be noted that the METAL structure 600 is a circuit trace structure in the X / Y direction, and the VIA structure 600 is a column connection point structure in the Z direction. The METAL structure 600 and the VIA structure 600 follow the IC circuit design specifications. The METAL structure 600 and the VIA structure 600 are the internal interconnections of the Hall element pads and the signal conditioning pads. The preparation methods of the METAL structure 600 and the VIA structure 600 are common knowledge in the art, and those skilled in the art should be aware of them, so they will not be elaborated here one by one. The output signal pad PAD700 is exposed outside the dielectric layer 300. The output signal pad PAD700 is used for subsequent packaging leads. Moreover, the preparation method of the output signal pad PAD700 is common knowledge in the art, and those skilled in the art should be aware of it, so they will not be elaborated here one by one.

[0067] The compound Hall integrated chip obtained by the present invention can be used for subsequent packaging processes after thinning and cutting. The thickness after thinning is generally 150 μm to 300 μm. Thinning the substrate 800 is also common knowledge in the art, and those skilled in the art should be aware of it, so they will not be elaborated here one by one.

[0068] The preparation method of the compound Hall integrated chip innovatively introduces a structure and its process method between the device manufacturing process and the CONTACT manufacturing process to achieve chip-level integration of the compound Hall and the silicon-based signal conditioning circuit, and solves the problem of heterogeneous integration of the current compound Hall and the silicon-based conditioning circuit on the same wafer. The preparation method of the compound Hall integrated chip integrates the compound Hall element 400 and the silicon-based signal conditioning chip 100 together through heterogeneous integration to form a single compound Hall integrated chip, which has performance advantages such as sensitivity and temperature drift characteristics compared with the single-chip silicon-based Hall. Moreover, compared with the dual-chip co-packaging method of the compound Hall element 400 and the silicon-based signal conditioning circuit in the prior art, the present invention has the advantages of higher integration, higher precision, and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip 100 to provide a wafer integration space for the compound Hall, so as to achieve the purpose of wafer integration of the compound Hall and the silicon-based signal conditioning circuit.

[0069] Example 2

[0070] A preparation method of a compound Hall integrated chip, other features are the same as those in Example 1, except that: both the dielectric thin film 210 and the dielectric layer 300 are SiO 2The thickness of the dielectric thin film 210 is 2 nm, and the thickness of the organic adhesive 220 is 2 nm. The bottom width of the first groove structure 200 is 150 μm, the opening width of the first groove structure 200 is 250 μm, and the depth of the first groove structure 200 is 6 μm.

[0071] The size of the first groove structure 200 in this embodiment can facilitate the compound Hall element 400 and at the same time reduce the gap between the groove and the compound Hall element 400.

[0072] Embodiment 3

[0073] A compound Hall integrated chip is prepared by using the preparation method of the compound Hall integrated chip in Embodiment 1 or 2.

[0074] The compound Hall integrated chip integrates the compound Hall element 400 and the silicon-based signal conditioning chip 100 to form a single compound Hall integrated chip, which has performance advantages such as sensitivity and temperature characteristics compared with the single-chip silicon-based Hall. Moreover, compared with the dual-chip co-packaging method of the compound Hall element 400 and the silicon-based signal conditioning circuit in the prior art, the present invention has the advantages of higher integration, higher precision, and higher reliability. The present invention forms a groove in the silicon-based signal conditioning chip 100 to provide a wafer integration space for the compound Hall, so as to achieve the purpose of wafer integration of the compound Hall and the silicon-based signal conditioning circuit.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a compound Hall integrated chip, characterized in that: After the device manufacturing process is completed, a groove is formed on the wafer surface of the silicon-based signal conditioning chip by yellow light and etching, a dielectric film is deposited and an organic adhesive is applied in the groove, and then a compound Hall element is assembled into the inside of the groove, and then the groove is filled with a dielectric layer, and finally a signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip is realized by using CONTACT, VIA, and interconnection lines, and finally the compound Hall integrated chip is obtained; The following steps are performed: S1, performing device manufacturing process on the wafer to obtain a silicon-based signal conditioning chip; S2, forming grooves on the surface of the wafer of the silicon-based signal conditioning chip obtained in S1 by yellow light and etching, and depositing a dielectric layer and coating an organic adhesive in the grooves; S3, assembling the compound Hall element into the inside of the groove obtained in S2, and proceeding to S4; S4, depositing a dielectric layer on the surface of the wafer so that the dielectric layer fills the gap between the groove and the compound Hall element, thereby completing the chip surface flattening operation and entering S5; S5. Perform a CONTACT manufacturing process, and then perform an interconnect manufacturing process. The interconnect manufacturing process includes the production of a VIA structure, a METAL structure, an output signal pad PAD, and a passivation layer structure to achieve signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.

2. The method for preparing the compound Hall integrated chip according to claim 1, characterized in that: The S2 is performed by the following steps: S2.1, performing yellow light treatment and etching on the S1 silicon-based signal conditioning chip to obtain a first groove structure; S2.2, depositing a dielectric film on the inner surface of the first groove structure obtained in S2.1 to obtain a second groove structure; S2.

3. Apply an organic adhesive to the bottom of the second groove structure obtained in S2.2 to obtain the groove.

3. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The width of the first groove structure increases gradually from the bottom to the opening direction, and the cross-sectional shape of the first groove structure is an inverted trapezoid.

4. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The S2.3 is specifically to spin-coat a layer of organic adhesive on the inner surface wafer of the second groove structure obtained in S2.2, and then to retain only the organic adhesive at the bottom of the second groove structure through exposure and development to obtain the groove.

5. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The bottom width of the first groove structure is greater than the maximum length of the compound Hall element.

6. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The bottom width of the first groove structure is 100 μm to 250 μm; The opening width of the first groove structure is 150 μm to 300 μm; The depth of the first groove structure is 1 μm to 10 μm.

7. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The thickness of the dielectric film is 1 nm to 5 nm.

8. The method for preparing the compound Hall integrated chip according to claim 2, characterized in that: The thickness of the organic adhesive is 1nm to 5nm; The silicon-based signal conditioning chip is provided with a substrate and functional module elements constituting a silicon-based signal conditioning circuit.

9. A compound Hall integrated chip, characterized in that: The compound Hall integrated chip is prepared by the preparation method of any one of claims 1 to 8.

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