Method of inspecting touch panel

Abstract

A method of inspecting a touch panel includes: determining a first test correction capacitance based on a mutual capacitance of a first test boundary line channel testing the touch panel and a candidate correction coefficient; determining a second test correction capacitance based on a mutual capacitance of a second test boundary line channel of the test touch panel and the candidate correction coefficient; determining a test channel gap of the first test boundary line channel based on the first test correction capacitance and the second test correction capacitance; determining a reference channel gap based on mutual capacitance of a test non-boundary line channel of the test touch panel; determining the candidate correction coefficient as a correction coefficient based on the reference channel gap and the test channel gap; determining a first correction capacitance of a first boundary line channel of the touch panel; determining a second correction capacitance of a second boundary line channel of the touch panel; determining a channel gap of the first boundary line channel based on the first correction capacitance and the second correction capacitance; and inspecting the first boundary line channel based on the channel gap.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0075174, filed on June 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method of inspecting a touch panel and a display device for inspecting a touch panel. Background Art

[0004] Electronic devices equipped with a touch panel that allows a position to be indicated by touch are widely used. In particular, with the proliferation of mobile devices like smartphones and tablet computers, touch panels have become increasingly popular.

[0005] The touch panel may include touch electrodes for detecting touch input. If the touch electrodes are short-circuited or open-circuited, the touch electrodes may not accurately detect the touch input. Therefore, in order to ensure accurate touch input detection, it may be necessary to detect the short circuit or open circuit of the touch electrodes. Summary of the invention

[0006] Embodiments of the present disclosure provide a method of inspecting a touch panel for detecting an open circuit of a boundary line channel.

[0007] Another embodiment of the present disclosure provides a display device for inspecting a touch panel.

[0008] According to an embodiment of the present disclosure, a method for inspecting a touch panel is provided, the method comprising: determining a first test correction capacitor based on a mutual capacitance of a first test boundary line channel of the test touch panel and a candidate correction coefficient; determining a second test correction capacitor based on a mutual capacitance of a second test boundary line channel of the test touch panel and a candidate correction coefficient, wherein the second test boundary line channel is adjacent to the first test boundary line channel; determining a test channel gap of the first test boundary line channel based on the first test correction capacitor and the second test correction capacitor; determining a reference channel gap based on a mutual capacitance of at least one of a plurality of test non-boundary line channels of the test touch panel; determining a candidate correction coefficient as a correction coefficient based on the reference channel gap and the test channel gap; determining a first correction capacitor of the first boundary line channel based on a mutual capacitance of the first boundary line channel of the touch panel and a correction coefficient, wherein the first boundary line channel corresponds to the first test boundary line channel; determining a second correction capacitor of the second boundary line channel based on a mutual capacitance of the second boundary line channel of the touch panel and a correction coefficient, wherein the second boundary line channel corresponds to the second test boundary line channel; determining a channel gap of the first boundary line channel based on the first correction capacitor and the second correction capacitor; and inspecting the first boundary line channel based on the channel gap.

[0009] According to an embodiment of the present disclosure, a display device is provided, including: a touch panel including a touch channel; a touch panel driver configured to drive the touch panel; a plurality of lines connected to a first portion of the touch channel in a first direction, connected to a second portion of the touch channel different from the first portion in a direction opposite to the first direction, and connecting the touch channel to the touch panel driver; and a touch panel inspector configured to inspect the touch panel, wherein the touch panel inspector determines a first correction capacitance of the first boundary line channel based on a mutual capacitance of the first boundary line channel included in the first portion and a correction coefficient, determines a second correction capacitance of the second boundary line channel based on a mutual capacitance of the second boundary line channel included in the second portion and adjacent to the first boundary line channel and the correction coefficient, and determines a channel gap of the first boundary line channel based on the first correction capacitance and the second correction capacitance.

[0010] The method of inspecting a touch panel according to an embodiment of the present disclosure may minimize caustic defects of a boundary line channel by determining a channel gap of the boundary line channel based on a correction capacitance of the boundary line channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by further describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0012] Figure 1 is a diagram showing a display device according to an embodiment of the present disclosure;

[0013] Figure 2 It is shown Figure 1 A cross-sectional view of an example of a display device;

[0014] Figure 3 It is shown Figure 1 A block diagram of an example of a display panel and a display panel driver;

[0015] Figure 4 It is shown Figure 3 A circuit diagram of an example of a sub-pixel;

[0016] Figure 5 It is shown Figure 2 An enlarged cross-sectional view of an example of an element layer;

[0017] Figure 6 It is shown Figure 1 A block diagram of an example of a touch panel;

[0018] Figure 7 It is shown Figure 1 FIG. 1 is a diagram of an example of a touch panel;

[0019] Figure 8 It is shown Figure 7 A cross-sectional view of an example of a first touch electrode and a second touch electrode;

[0020] Fig. 9 It is shown Figure 7 A cross-sectional view of an example of a first touch electrode and a second touch electrode;

[0021] Fig. 10A yes Figure 7 A magnified view of the first zone;

[0022] Fig. 10B It is along Fig. 10A A cross-sectional view taken along line II';

[0023] Fig.11A yes Figure 7 A magnified view of the second area;

[0024] Fig. 11B It is along Fig.11A A cross-sectional view taken along line II-II';

[0025] Fig.12 It is shown Figure 1 Figure 1: A diagram of a touch panel driver;

[0026] Fig.13 is a flowchart illustrating a method of inspecting a touch panel according to an embodiment of the present disclosure;

[0027] Fig.14 is a diagram showing touch channels and nodes;

[0028] Fig.15 is a diagram showing a method of checking touch channels and nodes;

[0029] Fig.16 It shows that according to Fig.13 A table of examples of testing mutual capacitance of a first test boundary line channel and a second test boundary line channel of a touch panel of a method of inspecting a touch panel;

[0030] Fig.17 It shows that according to Fig.13 A table of examples of a first test correction capacitance and a second test correction capacitance of a method of inspecting a touch panel;

[0031] Fig.18 It shows that according to Fig.13 A table of examples of a first test correction capacitance and a second test correction capacitance of a method of inspecting a touch panel;

[0032] Fig.19is a table showing an example of a first test correction capacitance and a second test correction capacitance of a method of inspecting a touch panel according to an embodiment of the present disclosure;

[0033] Fig. 20 It shows that according to Fig.13 A table of examples of methods of inspecting a touch panel to determine a correction coefficient;

[0034] Fig.21 is a table showing an example of determining a correction coefficient by means of a method of inspecting a touch panel according to an embodiment of the present disclosure; and

[0035] Fig. 22 It shows that according to Fig.13 A table of examples of a method of inspecting a touch panel to determine a channel gap of a first boundary line channel. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be understood that the present disclosure can be embodied in other forms and is not limited to the embodiments described herein.

[0037] Throughout the specification, when a part is "connected" to another part, the situation includes not only the situation that the part is "directly connected" to the other part, but also the situation that the part is "indirectly connected" to the other part (wherein another element is between the part and the other part). The terms used in this article are used to describe specific embodiments and are not intended to limit the present disclosure. Throughout the specification, the situation that a certain part "includes" a component means that the part may further include another component without excluding another component, unless otherwise stated. "At least any one of X, Y and Z" and "at least any one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (for example, XYZ, XY, YZ and XZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0038] Throughout the specification, terms such as first and second may be used to describe various components, but these components are not limited by these terms. These terms are used to distinguish one component from another component. Therefore, a first component may refer to a second component.

[0039] Spatially relative terms such as "under" and "on" can be used for descriptive purposes to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms are intended to include other orientations of the device in use, in operation and / or in manufacture. For example, when the device shown in the drawings is turned over, the element depicted as being positioned "under" other elements or features is then positioned "on" the other elements or features. Therefore, in an embodiment, the term "under" can include both "on" and "under" orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or other orientations), and therefore, the spatially relative terms used in this article are interpreted accordingly.

[0040] Various embodiments are described with reference to the accompanying drawings that schematically illustrate ideal embodiments. Accordingly, it is expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein are not to be construed as limited to the specific shapes shown in the accompanying drawings, and should be construed to include changes in shape that occur, for example, due to manufacturing. As described above, the shapes shown in the accompanying drawings may not illustrate the actual shape of the area of ​​the device, and the present disclosure is not limited thereto.

[0041] Figure 1 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0042] refer to Figure 1 , the display device 100 may include a touch panel 110 , a display panel 120 , a touch panel driver 130 , a display panel driver 140 , and a touch panel inspector 150 .

[0043] exist Figure 1 In the embodiment, the touch panel 110 and the display panel 120 are separated from each other. In an embodiment, the touch panel 110 may be formed in a process separate from the process of forming the display panel 120, and then, the touch panel 110 and the display panel 120 may be coupled to each other (e.g., the touch panel 110 may be attached and coupled to one surface of the display panel 120). In other words, the touch panel 110 may be formed as an add-on type. Alternatively, the touch panel 110 and the display panel 120 may be formed in one process (e.g., a process of manufacturing the display panel 120). In other words, the touch panel 110 may be formed as an in-cell type.

[0044] The touch panel 110 may be provided on one surface of the display panel 120. For example, the touch panel 110 may be provided on one surface (e.g., the upper surface) of the display panel 120 from which an image is displayed. In another embodiment, the touch panel 110 may be directly formed on one surface of the display panel 120, or may be formed inside the display panel 120. For example, the touch panel 110 may be directly formed on the outer surface of the upper substrate or the lower substrate of the display panel 120 (i.e., the upper surface of the upper substrate or the lower surface of the lower substrate). Alternatively, the touch panel 110 may be directly formed on the inner surface of the upper substrate (i.e., the lower surface of the upper substrate) or the inner surface of the lower substrate (i.e., the upper surface of the lower substrate).

[0045] The touch panel 110 may include a touch area TA capable of detecting a touch and a non-touch area NTA disposed outside the touch area TA (e.g., a peripheral area or edge area of ​​the touch area TA). As an example, the non-touch area NTA may surround the touch area TA. In an embodiment, the touch area TA may be disposed to correspond to the display area DA of the display panel 120. In other words, the touch area TA may overlap the display area DA of the display panel 120.

[0046] In an embodiment, the touch panel 110 may be arranged so that at least one area of ​​the touch panel 110 overlaps with the display panel 120. For example, the touch area TA of the touch panel 110 may be arranged on the display area DA of the display panel 120. In an embodiment, at least one electrode for detecting a touch may be arranged in the touch area TA. The at least one electrode for detecting a touch may include a first touch electrode TX and a second touch electrode RX. The first touch electrode TX and the second touch electrode RX may be provided on the display area DA of the display panel 120.

[0047] A line for electrically connecting the above-mentioned at least one electrode provided in the touch area TA to the touch panel driver 130 may be provided in the non-touch area NTA. For example, a line for electrically connecting the first touch electrode TX and the second touch electrode RX to the touch panel driver 130 may be provided in the non-touch area NTA. The non-touch area NTA may be provided to correspond to the non-display area NDA of the display panel 120. In other words, the non-touch area NTA may overlap with the non-display area NDA of the display panel 120.

[0048] The touch panel 110 may include at least one first touch electrode TX and at least one second touch electrode RX provided in the touch area TA. For example, the touch panel 110 may include a first touch electrode TX and a second touch electrode RX intersecting the first touch electrode TX. According to an embodiment, the first touch electrode TX may extend along a first direction, and the second touch electrode RX may extend along a second direction intersecting the first direction while being insulated from the first touch electrode TX by an insulating layer. A capacitor CSE (or capacitance) is formed between the first touch electrode TX and the second touch electrode RX. When a touch occurs at or around a corresponding point, the capacitance between the first touch electrode TX and the second touch electrode RX is changed. Accordingly, the touch panel driver 130 may detect a touch by detecting a change in the capacitance (in other words, mutual capacitance) between the first touch electrode TX and the second touch electrode RX.

[0049] However, the present disclosure does not limit the shape, size, and / or arrangement direction, etc. of the first touch electrodes TX and the second touch electrodes RX.

[0050] The display panel 120 includes a display area DA and a non-display area NDA located outside the display area DA (eg, an edge area or a peripheral area of ​​the display area DA).

[0051] In the display area DA, gate lines GL and data lines DL are provided, and sub-pixels SP electrically connected to the gate lines GL and data lines DL are provided. In the non-display area NDA, lines for supplying various driving signals and / or power for driving the sub-pixels SP may be provided.

[0052] However, the present disclosure is not limited to a specific type of display panel 120. For example, the display panel 120 may be a self-emissive display panel. For example, the display panel 120 may include a plurality of light-emitting elements. For example, the light-emitting element may be an organic light-emitting diode (LED). For example, the light-emitting element may be an inorganic LED, a micro-LED, or a quantum dot LED. For example, the light-emitting element may be an element configured by a combination of an organic material and an inorganic material. For example, the display panel 120 may be a non-emissive display panel such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electrowetting display panel (EWD panel). When the display panel 120 is a non-emissive display panel, the display device 100 may further include a backlight unit for supplying light to the display panel 120.

[0053] The touch panel driver 130 may be connected to the touch panel 110 to supply a signal to be input to the touch panel 110 or to receive a signal output from the touch panel 110. The touch panel driver 130 may detect a touch by supplying a touch drive signal to the touch panel 110 and then receiving a touch sensing signal corresponding to the touch drive signal from the touch panel 110. To this end, the touch panel driver 130 may include a touch drive signal output unit and a touch sensing signal receiver. In an embodiment, the touch drive signal output unit and the touch sensing signal receiver may be integrated into one integrated circuit (IC), but the present disclosure is not limited thereto. In an embodiment, the touch panel driver 130 (e.g., the touch drive signal output unit) may supply a touch drive signal to a plurality of first touch electrodes TX simultaneously (or sequentially). The touch panel driver 130 (e.g., the touch sensing signal receiver) may receive a touch sensing signal from a second touch electrode RX. The touch panel driver 130 may receive a touch sensing signal from the touch panel 110, and may perform signal processing to detect whether a touch is input and / or a touch coordinate corresponding to the position of a touch point on the touch panel 110.

[0054] The display panel driver 140 may be connected to the display panel 120 to supply a signal to be input to the display panel 120 or receive a signal output from the display panel 120. The display panel driver 140 may supply a gate signal to the gate line GL and may supply a data voltage to the data line DL.

[0055] The touch panel inspector 150 may receive data on mutual capacitance from the touch panel driver 130, and may detect whether the touch electrodes TX and RX are open based on the data. In other words, the touch panel inspector 150 may obtain data on mutual capacitance from the touch panel driver 130, and may determine whether the touch electrodes TX and RX are open based on the data.

[0056] Figure 2 It is shown Figure 1 1 is a cross-sectional view of an example of a display device 100 .

[0057] refer to Figure 2 , the display device 100 may include a display panel 120 and a touch panel 110 disposed on the display panel 120. A cover window CW may be disposed on the touch panel 110.

[0058] Figure 2 It is shown that the display panel 120 is a self-emissive display panel including a light emitting element. However, the present disclosure does not limit the type of the display panel 120.

[0059] The display panel 120 may include a first base substrate BSL, a device layer DSL, an encapsulation layer TFE, and the like.

[0060] The first base substrate BSL may support the element layer DSL. The first base substrate BSL may include an insulating material. As an example of the insulating material, at least one of a glass material, a quartz material, a ceramic material, and a plastic material may be included. The first base substrate BSL may be a rigid substrate, and according to an embodiment, the first base substrate BSL may be a flexible substrate.

[0061] The element layer DSL may be located on the first base substrate BSL (eg, in the third direction D3). The element layer DSL may be in direct contact with the first base substrate BSL. The element layer DSL may include Figure 1 The sub-pixel SP and the signal line located on the first base substrate BSL. The sub-pixel SP may include a thin film transistor (TFT) and a capacitor. In an embodiment, the sub-pixel SP may further include a light emitting element electrically connected to the TFT and / or the capacitor. The signal line may include Figure 1 The gate line GL configured to transmit a gate signal to each sub-pixel SP and Figure 1 The data line DL is configured to transmit a data voltage. The sub-pixel SP included in the element layer DSL may be located in the display area DA. A common electrode (eg, a cathode electrode of a light emitting element or a common electrode of a display device, etc.) may be formed in the element layer DSL.

[0062] The encapsulation layer TFE may be disposed on the element layer DSL. The encapsulation layer TFE may also be in direct contact with the first base substrate BSL. The encapsulation layer TFE may protect the element layer DSL from external moisture and / or oxygen. The encapsulation layer TFE may include two or more thin film layers (or insulating layers) formed on the element layer DSL. For example, the encapsulation layer TFE may include an inorganic thin film layer formed on the element layer DSL, an organic thin film layer formed on the inorganic thin film layer, and an inorganic thin film layer formed on the organic thin film layer. In an embodiment, the encapsulation layer TFE may be formed of a glass substrate and may cover the element layer DSL. The encapsulation layer TFE may cover the element layer DSL in the display area DA and the non-display area NDA.

[0063] The touch panel 110 may be disposed on the encapsulation layer TFE. In an embodiment, the touch panel 110 may be directly formed on the encapsulation layer TFE. In an embodiment, the touch panel 110 may be formed by a process separate from a process of forming the display panel 120, and may be disposed (e.g., attached) on the encapsulation layer TFE. The touch panel 110 may have a plurality of touch panels in at least a portion of an area overlapping with the display area DA. Figure 1 The touch panel 110 may have a touch area TA in at least a portion of an area overlapping with the non-display area NDA. Figure 1 Non-touch area NTA.

[0064] A cover window CW may be provided on the touch panel 110. The cover window CW may protect the display panel 120 and the touch panel 110 from external impact. The cover window CW may be implemented with a film of a light-transmitting (eg, transparent) material (eg, a glass material and / or a plastic material).

[0065] In an embodiment, the display device 100 may further include one or more optical layers (eg, an anti-glare layer, a polarizing plate, a color filter, a liquid crystal layer, etc.).

[0066] Figure 3 It is shown Figure 1 1 is a block diagram of an example of a display panel 120 and a display panel driver 140.

[0067] refer to Figure 3 , the display device may include a display panel 120 and a display panel driver 140. The display panel driver 140 may include a driving controller 141, a gate driver 142, and a data driver 143. In an embodiment, the driving controller 141 and the data driver 143 may be integrated into one chip.

[0068] The display panel 120 may include a display area DA for displaying an image and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 142 may be installed in the non-display area NDA.

[0069] The display panel 120 may include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels SP electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0070] The drive controller 141 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU), etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may further include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0071] The driving controller 141 may generate a first control signal CONT1 , a second control signal CONT2 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0072] The driving controller 141 may generate a first control signal CONT1 for controlling the operation of the gate driver 142 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 142. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0073] The driving controller 141 may generate a second control signal CONT2 for controlling the operation of the data driver 143 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 143. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0074] The driving controller 141 may generate a data signal DATA by receiving input image data IMG and an input control signal CONT. The driving controller 141 may output the data signal DATA to the data driver 143 .

[0075] The gate driver 142 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 141. The gate driver 142 may output the gate signal to the gate line GL. For example, the gate driver 142 may sequentially output the gate signal to the gate line GL.

[0076] The data driver 143 may receive the second control signal CONT2 and the data signal DATA from the driving controller 141. The data driver 143 may generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 143 may output the data voltage to the data line DL.

[0077] Figure 4 It is shown Figure 3 2 is a circuit diagram of an example of a sub-pixel SP.

[0078] refer to Figure 3 and Figure 4 The sub-pixel SP may include a pixel driving circuit PC and a light emitting element EL. The pixel driving circuit PC may drive the light emitting element EL.

[0079] The pixel driving circuit PC may include: a first transistor T1, including a control electrode (for example, a gate electrode) connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3; a second transistor T2, including a control electrode for receiving a write gate signal GW, a first electrode connected to a data line DL, and a second electrode connected to the second node N2; a third transistor T3, including a control electrode for receiving a write gate signal GW, a first electrode connected to the third node N3, and a second electrode connected to the first node N1; a fourth transistor T4, including a control electrode for receiving an initialization gate signal GI, a first electrode for receiving an initialization voltage VINT, and a second electrode connected to the first node N 1; a fifth transistor T5 including a control electrode for receiving an emission signal EM, a first electrode for receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second electrode connected to the second node N2; a sixth transistor T6 including a control electrode for receiving an emission signal EM, a first electrode connected to a third node N3, and a second electrode connected to a fourth node N4; a seventh transistor T7 including a control electrode for receiving a bias gate signal GB, a first electrode for receiving an initialization voltage VINT, and a second electrode connected to the fourth node N4; and a storage capacitor CST including a first electrode for receiving the first power supply voltage ELVDD and a second electrode connected to the first node N1. An anode electrode of the light emitting element EL may be connected to the fourth node N4, and a cathode electrode of the light emitting element EL may receive a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0080] In an embodiment, the emission signal EM may be generated by the gate driver 142. In another embodiment, the emission signal EM may be generated by an emission driver separate from the gate driver 142.

[0081] Figure 5 It is shown Figure 2 FIG. 4 is an enlarged cross-sectional view of an example of the element layer DSL.

[0082] Figure 5 In the embodiment, for convenience of description, transistors other than the second transistor T2 and the sixth transistor T6 are omitted.

[0083] refer to Figure 5 The element layer DSL may include a buffer layer BFL, a gate insulating layer GIL, an interlayer insulating layer ILD, second and sixth transistors T2 and T6 , a protective layer PSV, a light emitting element EL, and a pixel defining layer PDL.

[0084] The buffer layer BFL may be disposed on the first base substrate BSL and may prevent impurities from diffusing into the second transistor T2 and the sixth transistor T6. The buffer layer BFL may be provided as a single layer, but may also be provided as a plurality of layers of at least two layers or more. Depending on the material and process conditions of the first base substrate BSL, the buffer layer BFL may be omitted.

[0085] Each of the second transistor T2 and the sixth transistor T6 may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0086] The semiconductor layer SCL of each of the second transistor T2 and the sixth transistor T6 may be provided on the buffer layer BFL. The semiconductor layer SCL may include a source region and a drain region contacting the source electrode SE and the drain electrode DE, respectively. A region between the source region and the drain region may be a channel region.

[0087] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, or an oxide semiconductor. The channel region may be an intrinsic semiconductor pattern not doped with impurities. Here, impurities such as n-type impurities, p-type impurities, and other metals may be used as the above-mentioned impurities. The source region and the drain region may be semiconductor patterns doped with impurities.

[0088] The gate electrode GE of each of the second transistor T2 and the sixth transistor T6 may be provided on the corresponding semiconductor layer SCL with the gate insulating layer GIL interposed therebetween.

[0089] The source electrode SE of each of the second transistor T2 and the sixth transistor T6 may contact the source region of the corresponding semiconductor layer SCL through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GIL. For example, the source electrode SE of the second transistor T2 may contact the source region of the corresponding semiconductor layer SCL through a first contact hole CCH1 passing through the interlayer insulating layer ILD and the gate insulating layer GIL, and the source electrode SE of the sixth transistor T6 may contact the source region of the corresponding semiconductor layer SCL through a third contact hole CCH3 passing through the interlayer insulating layer ILD and the gate insulating layer GIL.

[0090] The drain electrode DE of each of the second transistor T2 and the sixth transistor T6 may contact the drain region of the corresponding semiconductor layer SCL through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GIL. For example, the drain electrode DE of the second transistor T2 may contact the drain region of the corresponding semiconductor layer SCL through a second contact hole CCH2 passing through the interlayer insulating layer ILD and the gate insulating layer GIL, and the drain electrode DE of the sixth transistor T6 may contact the drain region of the corresponding semiconductor layer SCL through a fourth contact hole CCH4 passing through the interlayer insulating layer ILD and the gate insulating layer GIL.

[0091] In an embodiment, each of the interlayer insulating layer ILD and the gate insulating layer GIL may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0092] A protection layer PSV may be provided on the second transistor T2 and the sixth transistor T6 and may cover the second transistor T2 and the sixth transistor T6. The protection layer PSV may include a fifth contact hole CH5 exposing a portion of the drain electrode DE of the sixth transistor T6 to the outside.

[0093] The element layer DSL may include a light emitting element EL provided on the protective layer PSV and emitting light.

[0094] The light emitting element EL may include a first electrode AE ​​and a second electrode CE and a light emitting layer EML provided between the first electrode AE ​​and the second electrode CE. Here, any one of the first electrode AE ​​and the second electrode CE may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode AE ​​may be an anode electrode, and the second electrode CE may be a cathode electrode. When the light emitting element EL is a front surface emission type organic light emitting element, the first electrode AE ​​may be a reflective electrode, and the second electrode CE may be a transmissive electrode. In the embodiment of the present disclosure, the case where the light emitting element EL is a front surface emission type organic light emitting element and the first electrode AE ​​is an anode electrode is described as an example.

[0095] The first electrode AE ​​may be electrically connected to the drain electrode DE of the sixth transistor T6 through the fifth contact hole CH5 passing through the protective layer PSV. The first electrode AE ​​may include a reflective layer capable of reflecting light and a transparent conductive layer disposed on or under the reflective layer. At least one of the transparent conductive layer and the reflective layer may be electrically connected to the drain electrode DE of the sixth transistor T6.

[0096] The element layer DSL may further include a pixel defining layer PDL having an opening OP exposing a portion of the first electrode AE ​​(eg, an upper surface of the first electrode AE).

[0097] refer to Figure 3 and Figure 5 , each sub-pixel SP provided in the display panel 120 may be disposed in a pixel area included in the display area DA. In an embodiment, the pixel area may include an emission area EMA and a non-emission area NEM adjacent to the emission area EMA. The non-emission area NEM may surround the emission area EMA. In an embodiment, the emission area EMA may correspond to a partial area of ​​the first electrode AE ​​exposed by the opening OP.

[0098] The light emitting element EL may further include a hole control layer HCL and an electron control layer ECL.

[0099] The hole control layer HCL may be commonly disposed in the emission area EMA and the non-emission area NEM. A common layer such as the hole control layer HCL may be commonly formed in the plurality of sub-pixels SP.

[0100] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening OP. In other words, the light emitting layer EML may be separately provided in each of a plurality of sub-pixels SP. The light emitting layer EML may include an organic material and / or an inorganic material. In an embodiment of the present disclosure, a patterned light emitting layer EML is shown as an example, but according to an embodiment, the light emitting layer EML may be provided in common in each sub-pixel SP. The color of light generated from the light emitting layer EML may be one of red, green, blue, and white, but is not limited thereto. For example, the color of light generated from the light emitting layer EML may be one of magenta, cyan, and yellow.

[0101] The electron control layer ECL may be provided on the light emitting layer EML. In this configuration, the light emitting layer EML is disposed between the hole control layer HCL and the electron control layer ECL. The electron control layer ECL may be commonly formed in each sub-pixel SP and may be used to inject and / or transfer electrons to the light emitting layer EML.

[0102] The second electrode CE may be provided on the electron control layer ECL. The second electrode CE may be provided in common in each sub-pixel SP.

[0103] An encapsulation layer TFE covering the second electrode CE may be provided on the second electrode CE.

[0104] The encapsulation layer TFE may be formed as a single layer, but may also be formed as a plurality of layers. The encapsulation layer TFE may include a plurality of insulating layers covering the light emitting element EL. For example, the encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked. According to an embodiment, the encapsulation layer TFE may be an encapsulation substrate disposed on the light emitting element EL and bonded to the first base substrate BSL by a sealant.

[0105] Figure 6 It is shown Figure 1 1 is a block diagram of an example of a touch panel 110 .

[0106] refer to Figure 6 , the touch panel 110 may include a second base substrate 111 , first touch electrodes TX1 to TX9 , second touch electrodes RX1 to RX20 , a pad unit 112 , and a line 113 .

[0107] The second base substrate 111 may be a substrate that becomes a base of the touch panel 110, and may be a rigid substrate or a flexible substrate. For example, the second base substrate 111 may be a rigid substrate including a glass material (e.g., a tempered glass material) or a flexible substrate including a thin film of a flexible plastic material. The first touch electrodes TX1 to TX9, the second touch electrodes RX1 to RX20, the pad unit 112, and the line 113, etc. may be disposed on the second base substrate 111. In an embodiment, the second base substrate 111 may be omitted (or, the second base substrate 111 may be replaced with another configuration). For example, when the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 are directly formed on Figure 1 When the display panel 120 is formed on the second base substrate 111, the second base substrate 111 may be formed on the display panel 120. Figure 2 The first base substrate BSL or Figure 2 The encapsulation layer is replaced by TFE.

[0108] The first touch electrodes TX1 to TX9 may extend along the second direction D2. For example, each of the first touch electrodes TX1 to TX9 may extend along a column direction and may be disposed in the touch panel 110. The first touch electrodes TX1 to TX9 may be spaced apart from each other in the first direction D1.

[0109] The second touch electrodes RX1 to RX20 may extend along the first direction D1. For example, each of the second touch electrodes RX1 to RX20 may extend along a row direction and may be disposed in the touch panel 110. The second touch electrodes RX1 to RX20 may be spaced apart from each other in the second direction D2.

[0110] The touch panel 110 may be driven in a mutual capacitance method. In the mutual capacitance method, any one of the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 may be used as a touch drive electrode, and the other may be used as a touch sensing electrode. A touch drive signal TDS is input to the touch drive electrode, and a touch sensing signal TSS is output from the touch sensing electrode. In an embodiment, the first touch electrodes TX1 to TX9 may receive a touch drive signal TDS for touch drive, and the second touch electrodes RX1 to RX20 may output a touch sensing signal TSS corresponding to the touch drive signal TDS. In an embodiment, the second touch electrodes RX1 to RX20 may receive a touch drive signal TDS, and the first touch electrodes TX1 to TX9 may output a touch sensing signal TSS corresponding to the touch drive signal TDS. Hereinafter, for ease of description, the case where the touch drive signal TDS is input to the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 output the touch sensing signal TSS is described as an example, but the present disclosure is not limited thereto.

[0111] The capacitor CSE may be formed between the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20. For example, the capacitor CSE may be formed at the area where the first touch electrodes TX1 to TX9 overlap with the second touch electrodes RX1 to RX20. The first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 may overlap each other in the overlapping area OLA in a vertical direction (e.g., a third direction D3 intersecting the first direction D1 and the second direction D2). In the overlapping area OLA, the first touch electrodes TX1 to TX9 may be used as one side electrode of the capacitor CSE, and the second touch electrodes RX1 to RX20 may be used as the other side electrode of the capacitor CSE. The capacitor CSE may be formed between the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 in the overlapping area OLA. When an object (e.g., a human finger, etc.) approaches the touch panel 110, the capacitance between the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 may change. The touch panel driver 130 may detect whether a touch is input and / or the touch coordinates based on such a change in capacitance.

[0112] The pad unit 112 may include one or more pads PAD. The pad PAD may connect the first touch electrodes TX1 to TX9 and the second touch electrodes RX1 to RX20 to the touch panel driver 130. For example, the touch drive signal TDS may be input to the first touch electrodes TX1 to TX9 through the first pad unit 112a. For example, the touch sensing signal TSS may be output from the second touch electrodes RX1 to RX20 through the second pad unit 112b.

[0113] The wire 113 may electrically connect the pad PAD and the first touch electrodes TX1 to TX9 , or may electrically connect the pad PAD and the second touch electrodes RX1 to RX20 .

[0114] The pad unit 112 and the wiring 113 may be disposed in the non-touch area NTA.

[0115] In the current embodiment, the number of the first touch electrodes TX1 to TX9 is 9 and the number of the second touch electrodes RX1 to RX20 is 20, but the present disclosure is not limited to 9 first touch electrodes TX1 to TX9 and 20 second touch electrodes RX1 to RX20.

[0116] One touch electrode may be one touch channel. In an embodiment, one touch channel may correspond to one of the second touch electrodes RX1 to RX20. In an embodiment, one touch channel may correspond to one of the first touch electrodes TX1 to TX9. However, for ease of description, Figures 14 to 22It is shown that one touch channel corresponds to one of the second touch electrodes RX1 to RX20. In addition, for the convenience of description, Figures 14 to 22 It is shown that a portion of one touch channel crossing one of the first touch electrodes TX1 to TX9 corresponds to one node.

[0117] A first portion (e.g., RX11 to RX20) of the touch channels of the touch panel 110 may be connected to the line 113 in a first direction D1, and a second portion (e.g., RX1 to RX10) of the touch channels different from the first portion may be connected to the line 113 in a direction opposite to the first direction D1.

[0118] Figure 7 It is shown Figure 1 FIG. 1 is a diagram of an example of a touch panel 110 .

[0119] The first touch electrode TX of the touch panel 110 may include a first sensing unit 211 and a first connection electrode 212 . The second touch electrode RX of the touch panel 110 may include a second sensing unit 221 and a second connection electrode 222 .

[0120] The first touch electrode TX may extend along a column direction (e.g., a second direction D2). The first touch electrode TX disposed in each column may include a plurality of first sensing units 211 and a first connection electrode 212 configured to connect the plurality of first sensing units 211 to each other. In an embodiment, the first connection electrode 212 may be configured integrally with the first sensing unit 211. In an embodiment, the first connection electrode 212 may be configured in a bridge-shaped connection pattern.

[0121] The second touch electrodes RX may extend along a row direction (e.g., a first direction D1). The second touch electrodes RX arranged in each row may include a plurality of second sensing units 221 and a second connection electrode 222 configured to connect the plurality of second sensing units 221 to each other. In an embodiment, the second connection electrode 222 may be configured integrally with the second sensing unit 221. In an embodiment, the second connection electrode 222 may be configured in a bridge-shaped connection pattern.

[0122] The first connection electrode 212 and the second connection electrode 222 may overlap each other in a vertical direction (eg, the third direction D3). The first connection electrode 212 and the second connection electrode 222 may be insulated from each other by an insulating layer.

[0123] The capacitor CSE may be formed between the first touch electrode TX and the second touch electrode RX. For example, the first touch electrode TX is used as one side electrode of the capacitor CSE, and the second touch electrode RX adjacent to the first touch electrode TX may be used as the other side electrode of the capacitor CSE. The capacitor CSE may be formed in an adjacent area between the first touch electrode TX and the second touch electrode RX. The air (e.g., atmosphere) between the first touch electrode TX and the second touch electrode RX may be used as an insulating material of the capacitor CSE. Accordingly, whether a touch is input and / or the touch coordinates may be detected in a mutual capacitance method.

[0124] Figure 8 It is shown Figure 7 A cross-sectional view of an example of a first touch electrode TX and a second touch electrode RX.

[0125] refer to Figure 7 and Figure 8 , the touch panel 110 may include first touch electrodes TX, second touch electrodes RX, and a bridge pattern BRP.

[0126] The first touch electrodes TX (e.g., the first sensing units 211) may be arranged in the second direction D2, and may be electrically connected to adjacent first touch electrodes TX through bridge patterns BRP (e.g., the first connection electrodes 212) to configure at least one sensor column. The second touch electrodes RX (e.g., the second sensing units 221) may be arranged in the first direction D1 crossing the second direction D2, and may be electrically connected to adjacent second touch electrodes RX through bridge patterns (e.g., the second connection electrodes 222) to configure at least one sensor row.

[0127] The first insulating layer INS1 may be provided on the second base substrate 111. The first insulating layer INS1 may include the same material as that of the second base substrate 111, but is not limited thereto. In an embodiment, the first insulating layer INS1 may include an organic insulating layer including an organic material or an inorganic insulating layer including an inorganic material. The first insulating layer INS1 may be provided between the bridge pattern BRP and the second touch electrode RX.

[0128] The first touch electrodes TX may be electrically and / or physically connected to each other by the bridge pattern BRP through the contact holes CNT passing through the first insulating layer INS1.

[0129] The second insulating layer INS2 may be provided on the first insulating layer INS1. The second insulating layer INS2 may prevent the first touch electrode TX and the second touch electrode RX from being exposed to the outside, thereby preventing corrosion of the first touch electrode TX and the second touch electrode RX. The second insulating layer INS2 may be formed of an organic insulating layer including an organic material. The organic material may include one of an acrylic resin, a polyimide (PI) resin, a polyamide (PA) resin, and a benzocyclobutene (BCB). The second insulating layer INS2 formed of the organic insulating layer may be transparent and have fluidity, and therefore, the second insulating layer INS2 may flatten the lower structure by slowing down the curvature of the lower structure. According to an embodiment, the second insulating layer INS2 may be formed of an inorganic insulating layer including an inorganic material.

[0130] Fig. 9 It is shown Figure 7 A cross-sectional view of an example of a first touch electrode TX and a second touch electrode RX.

[0131] refer to Figure 7 and Fig. 9 , the first touch electrodes TX and the second touch electrodes RX may be disposed in different layers.

[0132] The first insulating layer INS1 may be provided on the second base substrate 111. The first touch electrode TX may be provided on the second base substrate 111. The first insulating layer INS1 may prevent the first touch electrode TX from being exposed to the outside, thereby preventing corrosion of the first touch electrode TX. In an embodiment, the first insulating layer INS1 may include an organic insulating layer including an organic material or an inorganic insulating layer including an inorganic material.

[0133] The second insulating layer INS2 may be provided on the first insulating layer INS1. The second touch electrode RX may be provided on the first insulating layer INS1. The second insulating layer INS2 may prevent the second touch electrode RX from being exposed to the outside, thereby preventing corrosion of the second touch electrode RX.

[0134] In the current embodiment, the first touch electrode TX is provided on the second base substrate 111 and the second touch electrode RX is provided on the first insulating layer INS1, but the present disclosure is not limited thereto. For example, the second touch electrode RX may be provided on the second base substrate 111 and the first touch electrode TX may be provided on the first insulating layer INS1.

[0135] Fig. 10A yes Figure 7 An enlarged view of the first area AR1.

[0136] Each of the sub-pixels SP may include an emission area EMA and a non-emission area NEM. The sub-pixels SP may include a first sub-pixel SP_R, a second sub-pixel SP_G, and a third sub-pixel SP_B.

[0137] The emission area EMA is an area from which light may be emitted. For example, in an embodiment in which the sub-pixel SP includes a light emitting element, the emission area EMA may correspond to an area in which the light emitting element is located.

[0138] The non-emission area NEM may be located around the emission area EMA (for example, the non-emission area NEM may be located at an edge area of ​​the emission area EMA). The sub-pixels SP may be distinguished from each other by the non-emission area NEM. In an embodiment, a pixel driving circuit for driving a light-emitting element may be located in at least a portion of an area overlapping the non-emission area NEM. In an embodiment, the non-emission area NEM may correspond to an area where a pixel defining layer and a black matrix, etc. are located. The emission area EMA and the non-emission area NEM may be configured Figure 1 Display area DA.

[0139] The first subpixel SP_R may emit light of a first wavelength band (e.g., a red wavelength band). The second subpixel SP_G may emit light of a second wavelength band (e.g., a green wavelength band). The third subpixel SP_B may emit light of a third wavelength band (e.g., a blue wavelength band). The red wavelength band may be a wavelength band of about 600 nm to about 750 nm, the green wavelength band may be a wavelength band of about 480 nm to about 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to about 460 nm.

[0140] For ease of description, assume that the first subpixel SP_R is a red subpixel R emitting light of a red band, the second subpixel SP_G is a green subpixel G emitting light of a green band, and the third subpixel SP_B is a blue subpixel B emitting light of a blue band, but the present disclosure is not limited thereto.

[0141] The sub-pixels SP may be arranged in various ways. Fig. 10A As shown in , the first subpixel SP_R and the third subpixel SP_B may be alternately arranged along a row direction (e.g., the first direction D1), and the second subpixel SP_G may be arranged along a row adjacent to the first subpixel SP_R and the third subpixel SP_B. The second subpixel SP_G may be alternately disposed with the first subpixel SP_R and the third subpixel SP_B in a direction crossing the row direction (e.g., the first direction D1) and the column direction (e.g., the second direction D2).

[0142] The area of ​​the emission area EMA of any one of the first sub-pixel SP_R, the second sub-pixel SP_G, and the third sub-pixel SP_B may be different from the areas of the emission areas EMA of the other two sub-pixels. For example, the area of ​​the emission area EMA_B of the third sub-pixel SP_B may be greater than the area of ​​the emission area EMA_R of the first sub-pixel SP_R. For example, the area of ​​the emission area EMA_R of the first sub-pixel SP_R may be greater than the area of ​​the emission area EMA_G of the second sub-pixel SP_G. However, the present disclosure is not limited thereto. For example, all areas of the emission areas EMA of the first sub-pixel SP_R, the second sub-pixel SP_G, and the third sub-pixel SP_B may be the same.

[0143] The shape of the emission area EMA can be designed differently. For example, Fig. 10A , the shape of the emission area EMA may be octagonal, but the emission area EMA may have a shape such as a circular shape, other polygonal shapes, or a polygonal shape in which corners are rounded.

[0144] The first touch electrode TX (eg, the first sensing unit 211 of the first touch electrode TX) may include a mesh MH and a body portion BP.

[0145] The mesh MH may overlap the emission area EMA in a vertical direction (eg, the third direction D3). The emission area EMA may be located in a region corresponding to the mesh MH. The area of ​​the mesh MH may be greater than the area of ​​the emission area EMA.

[0146] The body portion BP may overlap the non-emission region NEM in a vertical direction (eg, the third direction D3 ). A width of the body portion BP may be smaller than a width of the non-emission region NEM.

[0147] Through the above structure, light output from the emission area EMA of the sub-pixel SP may effectively pass through the first touch electrode TX.

[0148] Fig. 10B It is along Fig. 10A A cross-sectional view taken along line II'.

[0149] refer to Fig. 10B , the pixel defining layer PDL, the light emitting element EL, the encapsulation layer TFE, the first sensing unit 211 and the first insulating layer IL1 may be located on the first base substrate BSL. The pixel defining layer PDL and the light emitting element EL may be included in the above Figure 2 The first sensing unit 211 and the first insulating layer IL1 may be included in the above Figure 2 In the touch panel 110.

[0150] The light emitting element EL may include a first electrode AE, a second electrode CE, and a light emitting layer EML. The light emitting layer EML is located between the first electrode AE ​​and the second electrode CE. The light emitting element EL may be provided in each sub-pixel SP.

[0151] The first electrode AE ​​may be disposed in each sub-pixel SP. A pixel defining layer PDL exposing the first electrode AE ​​may be disposed on the first electrode AE. The first electrode AE ​​may correspond to an anode electrode of the light emitting element EL. The first electrode AE ​​may include a metal layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or an alloy thereof, and a transparent conductive layer including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO).

[0152] The pixel defining layer PDL may overlap with the non-emitting area NEM. The pixel defining layer PDL may include an organic insulating layer containing an organic material. As the organic material, one or more of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin may be selected. The pixel defining layer PDL may include a light absorbing material. The pixel defining layer PDL may be coated with a light absorber and may absorb light introduced from the outside. For example, the pixel defining layer PDL may include a carbon-based black pigment. However, the present disclosure is not limited thereto, and the pixel defining layer PDL may include an opaque metal material such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co) or nickel (Ni).

[0153] The light emitting layer EML may overlap with a region where at least a portion of the pixel defining layer PDL is removed to expose the first electrode AE. The light emitting layer EML may include an organic light emitting layer. Depending on the organic material included in the light emitting layer EML, the light emitting layer EML may emit light of a first wavelength band (e.g., a red wavelength band), may emit light of a second wavelength band (e.g., a green wavelength band), or may emit light of a third wavelength band (e.g., a blue wavelength band).

[0154] The second electrode CE may be arranged on the light emitting layer EML (for example, in the third direction D3). The second electrode CE may be completely formed in the emission area EMA and the non-emission area NEM. The second electrode CE may correspond to the cathode electrode of the light emitting element EL. The second electrode CE may include a metal layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or an alloy thereof and a transparent conductive layer including ITO, IZO, ZnO or ITZO. For example, the second electrode CE may be formed as a plurality of layers including two or more layers of a thin metal layer. For example, the second electrode CE may include three layers of ITO / Ag / ITO.

[0155] In an embodiment, the light emitting element EL may further include a hole control layer disposed between the first electrode AE ​​and the light emitting layer EML, and an electron control layer disposed between the second electrode CE and the light emitting layer EML.

[0156] The encapsulation layer TFE may be located on the second electrode CE (eg, in the third direction D3). The encapsulation layer TFE may have a stack structure in which an inorganic layer including an inorganic material, an organic layer including an organic material, and an inorganic layer including an inorganic material are sequentially formed. Fig. 10B The encapsulation layer TFE may be formed by sequentially forming a first inorganic encapsulation layer IOL1 including an inorganic material, an organic encapsulation layer OL including an organic material, and a second inorganic encapsulation layer IOL2 including an inorganic material. The encapsulation layer TFE may protect the light emitting element EL (eg, light emitting layer EML) below from external moisture and / or oxygen.

[0157] The body portion BP of the first sensing unit 211 may be disposed on the encapsulation layer TFE. The first insulating layer IL1 is located on the body portion BP.

[0158] refer to Figure 6 and Fig. 10B The first insulating layer IL1 may insulate the touch electrodes from each other. The first touch electrodes TX1 to TX9 may be insulated from each other by the first insulating layer IL1. The second touch electrodes RX1 to RX20 may be insulated from each other by the first insulating layer IL1.

[0159] refer to Figure 7 and Fig. 10B The first connection electrode 212 and the second connection electrode 222 may be insulated from each other by the first insulating layer IL1. For example, the first connection electrode 212 and the second connection electrode 222 may overlap each other in a vertical direction (eg, a third direction D3) with the first insulating layer IL1 interposed therebetween.

[0160] The mesh MH of the first sensing unit 211 may overlap the emission area EMA.

[0161] Fig.11A yes Figure 7 An enlarged view of the second area AR2.

[0162] refer to Fig. 10A and Fig.11A , the description of the first sensing unit 211 can be generally applied to the description of the second sensing unit 221. The second sensing unit 221 may include a body portion BP and a mesh MH. The description of the remaining configuration is the same as that of the above reference Fig. 10A The configuration described is the same.

[0163] Fig. 11B It is along Fig.11A A cross-sectional view taken along line II-II'.

[0164] refer to Fig. 10B and Fig. 11B , the description of the first sensing cell 211 may generally be applied to the description of the second sensing cell 221. The body portion BP of the second sensing cell 221 may be covered with the first insulating layer IL1. In an embodiment, the body portion BP of the second sensing cell 221 may be disposed on the first insulating layer IL1.

[0165] Fig.12 It is shown Figure 1 FIG. 1 is a diagram of a touch panel driver 130 .

[0166] refer to Figure 1 and Fig.12 The touch panel driver 130 may include a touch driving circuit 131 and a touch sensing circuit 132 .

[0167] The touch driving circuit 131 may generate a touch driving signal TDS. The touch driving signal TDS may be implemented as a square wave, but according to an embodiment, the touch driving signal TDS may be implemented as a sine wave. The touch driving signal TDS may be input to the first touch electrode TX.

[0168] The capacitor CSE (or capacitance) may be formed by the first touch electrode TX and the second touch electrode RX. A touch sensing signal TSS corresponding to the touch drive signal TDS may be output to the second touch electrode RX in response to the touch drive signal TDS supplied to the first touch electrode TX. The touch sensing signal TSS may be input to the touch sensing circuit 132. The touch sensing circuit 132 may amplify and convert the touch sensing signal TSS input from the second touch electrode RX, and may perform signal processing on the touch sensing signal TSS input from the second touch electrode RX. The touch sensing circuit 132 may detect whether a touch is input and / or the touch coordinates based on the result of the signal processing.

[0169] The touch sensing circuit 132 may include a signal receiver 310 , an analog-to-digital converter 320 (ADC), a signal processor 330 , and the like.

[0170] The signal receiver 310 may receive a touch sensing signal TSS from the second touch electrode RX. The signal receiver 310 may amplify and output the touch sensing signal TSS. As an example, the signal receiver 310 may be implemented as an analog front end (AFE) including an operational amplifier (OP-Amp). According to an embodiment, a first input terminal IN1 (e.g., an inverting input terminal of an operational amplifier) ​​of the signal receiver 310 may be electrically connected to the second touch electrode RX. A second input terminal IN2 (e.g., a non-inverting input terminal of the OP-Amp) of the signal receiver 310 may be electrically connected to a ground terminal. A ground voltage may be input to the second input terminal IN2 of the signal receiver 310.

[0171] The ADC 320 may convert an analog signal input from the signal receiver 310 into a digital signal. According to an embodiment, the ADC 320 may be provided as many as the number of the second touch electrodes RX to correspond 1:1 to the touch channels corresponding to the second touch electrodes RX. According to an embodiment, the ADC 320 may be configured so that a plurality of second touch electrodes RX share one ADC 320. In this case, a switching circuit (e.g., a 1:N multiplexer) may be provided between the signal receiver 310 and the ADC 320.

[0172] The signal processor 330 may perform signal processing on the signal (e.g., digital signal) converted by the ADC 320, and may detect whether a touch is input and / or the touch coordinates according to the result of the signal processing. As an example, the signal processor 330 may detect whether a touch input is generated and the position of the touch input by comprehensively analyzing the signal (e.g., amplified and converted touch sensing signal TSS) input from the plurality of second touch electrodes RX via the signal receiver 310 and the ADC 320. According to an embodiment, the signal processor 330 may be implemented as a microprocessor unit (MPU). In this case, a memory for storing a driver program for driving the signal processor 330 may be additionally provided inside the touch sensing circuit 132. However, the configuration of the signal processor 330 is not limited thereto. As another example, the signal processor 330 may be implemented as a microcontroller unit (MCU) or the like.

[0173] Fig.13 is a flowchart illustrating a method of inspecting a touch panel according to an embodiment of the present disclosure.

[0174] refer to Fig.13 , Fig.13 The method for inspecting a touch panel may determine a first test correction capacitor based on a mutual capacitance of a first test boundary line channel of the test touch panel and a candidate correction coefficient (step S100), may determine a second test correction capacitor based on a mutual capacitance of a second test boundary line channel adjacent to the first test boundary line channel of the test touch panel and a candidate correction coefficient (step S200), may determine a test channel gap of the first test boundary line channel based on the first test correction capacitor and the second test correction capacitor (step S300), may determine a reference channel gap based on a mutual capacitance of at least one of the test non-boundary line channels of the test touch panel (step S400), may determine a reference channel gap based on a reference channel gap and the test channel gap to determine the candidate correction coefficient as the correction coefficient (step S500), the first correction capacitance of the first boundary line channel can be determined based on the mutual capacitance of the first boundary line channel of the touch panel corresponding to the first test boundary line channel and the correction coefficient (step S600), the second correction capacitance of the second boundary line channel can be determined based on the mutual capacitance of the second boundary line channel of the touch panel corresponding to the second test boundary line channel and the correction coefficient (step S700), the channel gap of the first boundary line channel can be determined based on the first correction capacitance and the second correction capacitance (step S800), and the first boundary line channel can be checked based on the channel gap (step S900).

[0175] Fig.13 Steps S600, S700, S800 and S900 of the method for inspecting a touch panel may be performed by Figure 1 For example, Figure 1 The touch panel inspector 150 may perform steps S600, S700, S800, and S900. However, the present disclosure is not limited thereto. For example, steps S600, S700, S800, and S900 may be performed in conjunction with Figure 1 The display device 100 is executed in a separate computer device.

[0176] Fig.13 Steps S100, S200, S300, S400 and S500 of the method for inspecting a touch panel may be performed using a touch panel having Figure 1 The configuration of the touch panel 110 is substantially the same as that of the test touch panel. For example, the test touch panel can be a standard sample for determining the correction coefficient. In an embodiment, the operation for determining the correction coefficient can be performed by a separate computer device. However, the present disclosure does not limit the device for performing such an operation.

[0177] In the following, reference Figures 14 to 22 The present disclosure is described specifically.

[0178] Fig.14 is a diagram showing touch channels CH1 to CH20 and nodes N1 to N9, and Fig.15 is a diagram illustrating a method of checking touch channels CH1 to CH20 and nodes N1 to N9 .

[0179] refer to Figure 6 and Fig.14 As described above, one of the touch channels CH1 to CH20 corresponds to one of the second touch electrodes RX1 to RX20. For example, the first touch channel CH1 corresponds to the first touch electrode RX1, the second touch channel CH2 corresponds to the second touch electrode RX2, and so on. In addition, a portion of one of the touch channels CH1 to CH20 that intersects with the first touch electrodes TX1 to TX9 corresponds to nodes N1 to N9, respectively. For example, a portion of the first touch channel CH1 that intersects with the first touch electrode TX1 corresponds to the first node N1, a portion of the second touch channel CH2 that intersects with the second touch electrode TX2 corresponds to the second node N2, and so on.

[0180] A first portion (e.g., CH11 to CH20) of the touch channels of the touch panel 110 may be connected to the wiring 113 in a first direction D1, and a second portion (e.g., CH1 to CH10) of the touch channels different from the first portion may be connected to the wiring 113 in a direction opposite to the first direction D1.

[0181] The touch channels CH10 and CH11 of the portion where the first portion and the second portion contact each other may be the first boundary line channel BC1 and the second boundary line channel BC2. For example, the first boundary line channel BC1 may be included in the first portion. For example, the second boundary line channel BC2 may be included in the second portion and may be adjacent to the first boundary line channel BC1.

[0182] refer to Figure 1 , Figure 6 and Fig.15 , a channel gap and / or a node gap may be determined at each of the nodes of the touch panel 110 .

[0183] The channel gap may be determined based on a ratio of mutual capacitances between adjacent touch channels among the touch channels CH1 to CH20. For example, the channel gap may increase as a difference in mutual capacitances between adjacent touch channels among the touch channels CH1 to CH20 increases.

[0184] For example, the channel gap of the ninth node N9 of the second touch channel CH2 may be calculated using [Equation 1].

[0185] [Equation 1]

[0186] CHG(CH2,N9)=|(Cm(CH1,N9) / Cm(CH2,N9))×100-100|

[0187] Here, CHG(CH2, N9) is a channel gap of a ninth node N9 of the second touch channel CH2, Cm(CH1, N9) is a mutual capacitance of a ninth node N9 of the first touch channel CH1, and Cm(CH2, N9) is a mutual capacitance of a ninth node N9 of the second touch channel CH2.

[0188] The node gap may be determined based on a ratio of mutual capacitances between adjacent nodes among the nodes N1 to N9. For example, the node gap may increase as a difference in mutual capacitances between adjacent nodes among the nodes N1 to N9 increases.

[0189] For example, the node gap of the ninth node N9 of the second touch channel CH2 may be calculated using [Equation 2].

[0190] [Equation 2]

[0191] NG(CH2,N9)=|(Cm(CH2,N8) / Cm(CH2,N9))×100-100|

[0192] Here, NG(CH2, N9) is a node gap of a ninth node N9 of the second touch channel CH2, Cm(CH2, N8) is a mutual capacitance of an eighth node N8 of the second touch channel CH2, and Cm(CH2, N9) is a mutual capacitance of a ninth node N9 of the second touch channel CH2.

[0193] According to [Equation 1] and [Equation 2], the channel gap of the node of the second area A2 of the touch panel 110 may not be determined, the node gap of the node of the third area A3 of the touch panel 110 may not be determined, and the channel gap and the node gap of the node of the fourth area A4 of the touch panel 110 may not be determined. For example, the channel gap and the node gap may be determined at each of the nodes of the first area A1 of the touch panel 110. For example, the node gap may be determined at each of the nodes of the second area A2 of the touch panel 110. For example, the channel gap may be determined at each of the nodes of the third area A3 of the touch panel 110. For example, the channel gap and the node gap may not be determined at the node of the fourth area A4 of the touch panel 110.

[0194] When a portion connected to a channel or a node is open, the channel gap or the node gap may have an abnormal value. Accordingly, whether a channel or a node is open can be checked by the channel gap or the node gap.

[0195] In the current embodiment, the channel gap is calculated by channels adjacent in a direction opposite to the second direction D2 , and the node gap is calculated by nodes adjacent in a direction opposite to the first direction D1 , but the present disclosure is not limited thereto.

[0196] In an embodiment, the inspection of the touch channels CH1 to CH20 may be performed by the touch panel inspector 150. However, the present disclosure is not limited thereto. For example, the inspection of the touch channels CH1 to CH20 may be performed in a separate computer device.

[0197] The resistance at one of the resistances at the nodes N1 to N9 may decrease as the one node approaches the line 113 connecting the corresponding touch channel of the touch channels CH1 to CH20 and the pad unit 112 of the touch panel 110. In other words, the capacitance at one of the mutual capacitances may increase as the one node approaches the line 113 connecting the corresponding touch channel of the touch channels CH1 to CH20 and the pad unit 112 of the touch panel 110.

[0198] According to [Equation 1], the channel gap of the first boundary line channel BC1 can be determined by the second boundary line channel BC2. However, in the first boundary line channel BC1, the line 113 may be connected in the first direction D1 (for example, the line 113 may be connected on the left side of the touch panel 110), and in the second boundary line channel BC2, the line 113 may be connected in the direction opposite to the first direction D1 (for example, the line 113 may be connected on the right side of the touch panel 110). Therefore, the channel gap of the first boundary line channel BC1 calculated based on the mutual capacitance of the first boundary line channel BC1 and the mutual capacitance of the second boundary line channel BC2 may cause a caustic defect. Accordingly, Fig.13 The method of inspecting a touch panel may use a first correction capacitor of the first boundary line channel BC1 and a second correction capacitor of the second boundary line channel BC2 in determining a channel gap of the first boundary line channel BC1. A detailed description thereof will be given later.

[0199] Fig.16 It shows that according to Fig.13 A table of examples of mutual capacitances Cm of first test boundary line channels TBC1 and second test boundary line channels TBC2 of a test touch panel TTP of a method of inspecting a touch panel. Fig.17 It shows that according to Fig.13 Table of examples of the first test correction capacitor TCCm1 and the second test correction capacitor TCCm2 of the method of inspecting a touch panel.

[0200] Fig.16 The value of the mutual capacitance Cm and Fig.17 The values ​​of the test correction capacitors TCCm1 and TCCm2 represent digital values.

[0201] refer to Figure 6 as well as Fig.13 , Fig.14 , Fig.16 and Fig.17 , Fig.13 The method for detecting a touch panel can determine a first test correction capacitor TCCm1 based on the mutual capacitance Cm of the first test boundary line channel TBC1 of the test touch panel TTP and the candidate correction coefficient CCF (step S100), and can determine a second test correction capacitor TCCm2 based on the mutual capacitance Cm of the second test boundary line channel TBC2 of the test touch panel TTP adjacent to the first test boundary line channel TBC1 and the candidate correction coefficient CCF (step S200). Fig.17 , the candidate correction coefficient CCF is 0.1, but the present disclosure is not limited thereto.

[0202] The test touch panel TTP may have a configuration substantially the same as that of the touch panel 110. For example, the test touch panel TTP may be a standard sample for determining a correction coefficient. For clarity, the lines connecting the touch electrodes with the pads for the test touch panel TTP may use the same reference numerals as those of the lines 113 of the touch panel 110.

[0203] The first test boundary line channel TBC1 may correspond to the first boundary line channel BC1 of the touch panel 110. For example, when the eleventh touch channel CH11 of the touch panel 110 is the first boundary line channel BC1, the eleventh touch channel of the test touch panel TTP may be the first test boundary line channel TBC1.

[0204] The second test boundary line channel TBC2 may correspond to the second boundary line channel BC2 of the touch panel 110. For example, when the tenth touch channel CH10 of the touch panel 110 is the second boundary line channel BC2, the tenth touch channel of the test touch panel TTP may be the second test boundary line channel TBC2.

[0205] Fig.13 The method of inspecting a touch panel may calculate an average deviation of the mutual capacitance Cm of the first test boundary line channel TBC1. The average deviation of the mutual capacitance Cm of the first test boundary line channel TBC1 may increase as the difference between the maximum value and the minimum value of the mutual capacitance Cm of the first test boundary line channel TBC1 increases.

[0206] For example, the average deviation can be calculated using [Equation 3].

[0207] [Equation 3]

[0208] AD=(MAXCm-MINCm) / (NODE-1)

[0209] Here, AD is the average deviation, MAXCm is the maximum mutual capacitance of each touch channel, MINCm is the minimum mutual capacitance of each touch channel, and NODE is the number of nodes of each touch channel.

[0210] For example, Fig.16 As shown in , in the first test boundary line channel TBC1, the maximum mutual capacitance is 1660 at the ninth node N9, the minimum mutual capacitance is 1500 at the first node N1, and the number of nodes N1 to N9 is 9. Therefore, the average deviation of the first test boundary line channel TBC1 is 20. For example, the average deviation may correspond to the difference in mutual capacitance between adjacent nodes (e.g., 1520 at the second node N2 minus 1500 at the first node N1 or 1540 at the third node N3 minus 1520 at the second node N2).

[0211] In an embodiment, in [Equation 3], the mutual capacitance of the node closest to the line 113 (e.g., the ninth node N9 of the first test boundary line channel TBC1) may be used instead of the maximum mutual capacitance. In an embodiment, in [Equation 3], the mutual capacitance of the node farthest from the line 113 (e.g., the first node N1 of the first test boundary line channel TBC1) may be used instead of the minimum mutual capacitance.

[0212] Fig.13 The method for detecting a touch panel can determine a test correction deviation TCD by multiplying the average deviation by a candidate correction coefficient CCF, and can determine a first test correction capacitor TCCm1 based on an average value AV of the mutual capacitance Cm of the first test boundary line channel TBC1 and the test correction deviation TCD. The first test correction capacitor at one node among the first test correction capacitors TCCm1 can increase as the one node approaches the line 113 connecting the first test boundary line channel TBC1 and the pad unit of the test touch panel TTP.

[0213] The candidate correction factor CCF may have a value between 0 and 1. Fig.13 The method of inspecting a touch panel may determine any one of the candidate correction coefficients CCF as the correction coefficient. To this end, the first test correction capacitance TCCm1 and the second test correction capacitance TCCm2 may be calculated using one of the candidate correction coefficients CCF.

[0214] For ease of description, Fig.17 It is shown that a candidate correction factor CCF of 0.1 is used.

[0215] For example, Fig.16 and Fig.17 As shown in , the average deviation of the first test boundary line channel TBC1 can be 20, and the test correction deviation TCD can be 2 (20×0.1=2). The first test correction capacitor TCCm1 of the middle node (e.g., the fifth node N5) can be 1580, which is the average value AV of the mutual capacitance Cm of the first test boundary line channel TBC1. The first test correction capacitor TCCm1 of the node closest to the line 113 (e.g., the ninth node N9) can be 1588 (1580+2×4=1588) obtained by adding 8 (which is four times the test correction deviation TCD of 2) to the average value AV (i.e., 1580) of the mutual capacitance Cm of the first test boundary line channel TBC1. The first test correction capacitor TCCm1 of the node farthest from the line 113 (e.g., the first node N1) can be 1572 (1580-2×4=1572) obtained by subtracting 8 (which is four times the test correction deviation TCD of 2) from the average value AV (i.e., 1580) of the mutual capacitance Cm of the first test boundary line channel TBC1.

[0216] Since the second test correction capacitance TCCm2 is calculated in substantially the same method as the method of calculating the first test correction capacitance TCCm1 , repeated description is omitted.

[0217] However, the present disclosure does not limit the coefficient by which the test correction deviation TCD is multiplied.

[0218] Fig.18 It shows that according to Fig.13 A table showing an example of a first test correction capacitor TCCm1 and a second test correction capacitor TCCm2 of a method for inspecting a touch panel. Fig.17 different, Fig.18 It is shown that the number of nodes N1 to N8 is an even number, and the average deviation of the first test boundary line channel TBC1 is 40.

[0219] refer to Fig.18 , the average deviation of the first test boundary line channel TBC1 may be 40, and the test correction deviation TCD may be 4 (40×0.1=4). The first test correction capacitor TCCm1 of the fifth node N5 among the intermediate nodes may be 1582 (1580+4×0.5=1582) obtained by adding 2 (which is 0.5 times the test correction deviation TCD of 4) to the average value AV (i.e., 1580) of the mutual capacitance Cm of the first test boundary line channel TBC1. The first test correction capacitor TCCm1 of the fourth node N4 among the intermediate nodes may be 1578 (1580-4×0.5=1578) obtained by subtracting 2 (which is 0.5 times the test correction deviation TCD of 4) from the average value AV (i.e., 1580) of the mutual capacitance Cm of the first test boundary line channel TBC1.

[0220] Fig.19 : is a table showing an example of a first test correction capacitance TCCm1 and a second test correction capacitance TCCm2 of the method of inspecting a touch panel according to an embodiment of the present disclosure.

[0221] Since the method of inspecting a touch panel according to the present embodiment is different from the method of inspecting a touch panel according to the present embodiment except that the mutual capacitance Cm of the middle node is used instead of the average value AV. Fig.13 The method of inspecting a touch panel is substantially the same, and thus the same reference numerals and reference symbols are used for the same or similar components, and thus, repeated descriptions are omitted.

[0222] refer to Fig.16 and Fig.19 , Fig.19The method for detecting a touch panel can calculate an average deviation of the mutual capacitance Cm of the first test boundary line channel TBC1, can determine a test correction deviation TCD by multiplying the average deviation by a candidate correction coefficient CCF, and can determine a first test correction capacitance TCCm1 based on the mutual capacitance Cm of an intermediate node (for example, the fifth node N5) among the mutual capacitance Cm of the first test boundary line channel TBC1 and the test correction deviation TCD.

[0223] For example, Fig.16 and Fig.19 As shown in , the average deviation of the first test boundary line channel TBC1 can be 20, and the test correction deviation TCD can be 2 (20×0.1=2). The first test correction capacitor TCCm1 of the node closest to the line 113 (e.g., the ninth node N9) can be 1588 (1580+2×4=1588) obtained by adding 8 (which is four times the test correction deviation TCD of 2) to the mutual capacitance Cm of the middle node (e.g., the fifth node N5). The first test correction capacitor TCCm1 of the node farthest from the line 113 (e.g., the first node N1) can be 1572 (1580-2×4=1572) obtained by subtracting 8 (which is four times the test correction deviation TCD of 2) from the mutual capacitance Cm of the middle node (e.g., the fifth node N5).

[0224] In an embodiment, when the number of nodes is an even number, the first test correction capacitance TCCm1 may be determined based on the mutual capacitance Cm of any one of the intermediate nodes.

[0225] Fig. 20 It shows that according to Fig.13 A table of examples of a method of inspecting a touch panel to determine a correction coefficient CF.

[0226] refer to Fig.13 , Fig.14 , Fig.16 , Fig.17 and Fig. 20 , Fig.13 The method of inspecting a touch panel may determine a test channel gap TCG of a first test boundary line channel TBC1 based on a first test correction capacitor TCCm1 and a second test correction capacitor TCCm2 (step S300 ).

[0227] The test channel gap TCG may be determined based on a ratio of the first test correction capacitor TCCm1 and the second test correction capacitor TCCm2 at each of the nodes N1 to N9. For example, the test channel gap TCG may increase as the difference between the first test correction capacitor TCCm1 and the second test correction capacitor TCCm2 at each of the nodes N1 to N9 increases.

[0228] The test channel gap TCG may be calculated in substantially the same method as the method of calculating the channel gap described with reference to [Equation 1] except that the first test correction capacitor TCCm1 and the second test correction capacitor TCCm2 are used.

[0229] For example, the test channel gap TCG of the ninth node N9 of the first test boundary line channel TBC1 may be calculated using [Equation 4].

[0230] [Equation 4]

[0231] TCG(N9)=|(TCCm2(N9) / TCCm1(N9))×100-100|

[0232] Here, TCG(N9) is a test channel gap of a ninth node N9 of the first test boundary line channel TBC1, TCCm2(N9) is a second test correction capacitor TCCm2 of the ninth node N9, and TCCm1(N9) is a first test correction capacitor TCCm1 of the ninth node N9.

[0233] Fig.13 The method of inspecting a touch panel may determine a reference channel gap RCG based on a mutual capacitance Cm of at least one of the test non-border line channels TNBC of the test touch panel TTP (step S400 ).

[0234] In an embodiment, the test non-border line channel TNBC may be a test touch channel other than the first test border line channel TBC1 and the second test border line channel TBC2 among the test touch channels of the test touch panel TTP. Fig.14 , the test non-border line channel TNBC may correspond to any one of the touch channels CH1 to CH9 and CH12 to CH20. In an embodiment, the test non-border line channel TNBC may be a test touch channel other than the first test border line channel TBC1 among the test touch channels of the test touch panel TTP. In this case, reference Fig.14 , the test non-border line channel TNBC may correspond to any one of the touch channels CH1 to CH10 and CH12 to CH20 . The test touch channel of the test touch panel TTP may correspond to the touch channels CH1 to CH20 of the touch panel 110 .

[0235] The reference channel gap RCG may be determined based on a ratio of mutual capacitances Cm between adjacent test non-boundary line channels TNBC at each of the nodes N1 to N9. The reference channel gap RCG may increase as a difference in mutual capacitances Cm between adjacent test non-boundary line channels TNBC at each of the nodes N1 to N9 increases.

[0236] In an embodiment, the average value of the channel gap of the test non-boundary line channel TNBC at each of the nodes N1 to N9 may be calculated. In addition, the average value of the channel gap at each of the nodes N1 to N9 may be determined as the reference channel gap RCG at each of the nodes N1 to N9. The channel gap of the test non-boundary line channel TNBC may be calculated in a method substantially the same as the method of calculating the channel gap described with reference to [Equation 1].

[0237] In an embodiment, any one of the test non-border line channels TNBC may be selected. In addition, the channel gap of the selected test touch channel may be determined as the reference channel gap RCG. The channel gap of the selected test touch channel may be calculated in a method substantially the same as the method of calculating the channel gap described with reference to [Equation 1].

[0238] Fig.13 The method of inspecting a touch panel may determine a candidate correction coefficient CCF as a correction coefficient CF based on a reference channel gap RCG and a test channel gap TCG (step S500). When the average value of the test channel gap TCG is less than the average value of the reference channel gap RCG, the candidate correction coefficient CCF may be determined as the correction coefficient CF.

[0239] For example, Fig. 20 As shown in , when the candidate correction coefficient CCF is 0.1 to 0.3, the average value of the test channel gap TCG may be smaller than the average value of the reference channel gap RCG. Accordingly, any one of 0.1, 0.2, and 0.3 may be determined as the correction coefficient CF.

[0240] Fig.21 : is a table showing an example of determining a correction coefficient CF by means of a method of inspecting a touch panel according to an embodiment of the present disclosure.

[0241] Since the configuration of the method for inspecting a touch panel according to the current embodiment is different from that of the method for inspecting a touch panel according to the present embodiment in addition to comparing the maximum value of the test channel gap TCG and the maximum value of the reference channel gap RCG. Fig.13 The configuration of the method of inspecting a touch panel is substantially the same, and thus the same reference numerals and reference symbols are used for the same or similar components, and thus, repeated description is omitted.

[0242] refer to Fig.21 , when the maximum value of the test channel gap TCG is less than the maximum value of the reference channel gap RCG, the candidate correction coefficient CCF may be determined as the correction coefficient CF.

[0243] For example, Fig.21As shown in , when the candidate correction coefficient CCF is 0.1, the maximum value of the test channel gap TCG may be smaller than the maximum value of the reference channel gap RCG. Accordingly, 0.1 may be determined as the correction coefficient CF.

[0244] Fig. 22 It shows that according to Fig.13 FIG. 1 is a table of an example of a method of inspecting a touch panel to determine a channel gap CHG of a first boundary line channel BC1.

[0245] refer to Figure 6 , Fig.13 , Fig.14 and Fig. 22 , Fig.13 The method for inspecting the touch panel can determine the first correction capacitor CCm1 of the first boundary line channel BC1 based on the mutual capacitance Cm of the first boundary line channel BC1 of the touch panel 110 and the correction coefficient CF (step S600), and can determine the second correction capacitor CCm2 of the second boundary line channel BC2 based on the mutual capacitance Cm of the second boundary line channel BC2 of the touch panel 110 and the correction coefficient CF (step S700).

[0246] Fig.13 The method of inspecting a touch panel may calculate an individual deviation ND of the mutual capacitance Cm of the first boundary line channel BC1 at each of the nodes N1 to N9. The individual deviation ND may increase as the nodes N1 to N9 approach the line 113 connecting the first boundary line channel BC1 and the pad unit 112 of the touch panel 110.

[0247] For example, the individual deviation ND may be a difference between the mutual capacitance Cm at each of the nodes N1 to N9 of the touch channels CH1 to CH20 and the average value Cm_Avg of the mutual capacitance Cm of the corresponding touch channel among the touch channels CH1 to CH20. For example, the difference between 1660, which is the mutual capacitance Cm of the ninth node N9 of the first boundary line channel BC1, and 1580, which is the average value Cm_Avg of the mutual capacitance Cm of the first boundary line channel BC1, may be 80. Accordingly, the individual deviation ND of the ninth node N9 of the first boundary line channel BC1 may be 80.

[0248] Since the individual deviations ND of the second border line channel BC2 can be calculated in substantially the same method as the method of calculating the individual deviations ND of the first border line channel BC1 , repeated descriptions are omitted.

[0249] Fig.13The method of inspecting a touch panel can determine the correction deviation CD by multiplying the individual deviation ND by the correction coefficient CF. For example, the correction deviation CD of the ninth node N9 of the first boundary line channel BC1 can be 8, which is the product of 80, which is the individual deviation ND, and 0.1, which is the correction coefficient CF.

[0250] Since the correction deviation CD of the second border line channel BC2 can be calculated in substantially the same method as the method of calculating the correction deviation CD of the first border line channel BC1 , repeated description is omitted.

[0251] Fig.13 The method of inspecting a touch panel can determine the first correction capacitor CCm1 based on the average value Cm_Avg of the mutual capacitance Cm of the first boundary line channel BC1 and the correction deviation CD. The first correction capacitor CCm1 at each of the nodes N1 to N9 can be calculated by adding the correction deviation CD of each of the nodes N1 to N9 and the average value Cm_Avg of the mutual capacitance Cm of the first boundary line channel BC1. For example, the first correction capacitor CCm1 at the ninth node N9 can be determined by adding the correction deviation CD of 8 to the average value Cm_Avg of 1580 to obtain 1588. Similarly, the first correction capacitor CCm1 at the first node N1 can be determined by adding the correction deviation CD of -8 to the average value Cm_Avg of 1580 to obtain 1572.

[0252] Since the second correction capacitance CCm2 can be calculated in substantially the same method as the method of calculating the first correction capacitance CCm1 , repeated description is omitted.

[0253] Fig.13 The method of inspecting a touch panel may determine a channel gap CHG of a first boundary line channel BC1 based on a first correction capacitor CCm1 and a second correction capacitor CCm2 (step S800 ).

[0254] The channel gap CHG of the first boundary line channel BC1 may be determined based on the ratio of the first correction capacitor CCm1 and the second correction capacitor CCm2 at each of the nodes N1 to N9. The channel gap CHG of the first boundary line channel BC1 may increase as the difference between the first correction capacitor CCm1 and the second correction capacitor CCm2 at each of the nodes N1 to N9 increases.

[0255] The channel gap CHG of the first boundary line channel BC1 may be calculated in substantially the same method as the method of calculating the channel gap described with reference to [Equation 1] except that the first correction capacitor CCm1 and the second correction capacitor CCm2 are used.

[0256] The first boundary line channel BC1 can be checked based on the channel gap CHG of the first boundary line channel BC1. As described above, the channel gap of the first boundary line channel BC1 calculated based on the mutual capacitance Cm of the first boundary line channel BC1 and the mutual capacitance Cm of the second boundary line channel BC2 may cause caustic defects. Therefore, in order to prevent caustic defects, Fig.13 The method of inspecting a touch panel may inspect the first boundary line channel BC1 using the channel gap CHG of the first boundary line channel BC1 calculated based on the first correction capacitor CCm1 and the second correction capacitor CCm2 .

[0257] When a portion of the first boundary line channel BC1 is open, the channel gap CHG of the first boundary line channel BC1 may have an abnormal value. Accordingly, whether the first boundary line channel BC1 is open may be checked by the channel gap CHG of the first boundary line channel BC1.

[0258] The present disclosure may be applied to a display device and an electronic device including a display device. For example, the present disclosure may be applied to a digital TV, a three-dimensional (3D) TV, a mobile phone, a smart phone, a virtual reality (VR) device, a personal computer (PC) (e.g., a tablet computer or a notebook computer), a home electronic device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, and a navigation system, etc.

[0259] Although the present disclosure has been described with reference to the above-mentioned embodiments, it will be understood that those skilled in the art may make various modifications and changes to the embodiments without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A method for inspecting a touch panel, the method include: determining a first test correction capacitance based on a mutual capacitance of a first test boundary line channel of the test touch panel and a candidate correction coefficient; determining a second test correction capacitance based on a mutual capacitance of a second test boundary line channel of the test touch panel and the candidate correction coefficient, wherein the second test boundary line channel is adjacent to the first test boundary line channel; determining a test channel gap of the first test boundary line channel based on the first test correction capacitor and the second test correction capacitor; determining a reference channel gap based on a mutual capacitance of at least one of a plurality of test non-boundary line channels of the test touch panel; determining the candidate correction coefficient as a correction coefficient based on the reference channel gap and the test channel gap; determining a first correction capacitance of a first boundary line channel of the touch panel based on a mutual capacitance of the first boundary line channel and the correction coefficient, wherein the first boundary line channel corresponds to the first test boundary line channel; determining a second correction capacitance of a second boundary line channel of the touch panel based on a mutual capacitance of the second boundary line channel and the correction coefficient, wherein the second boundary line channel corresponds to the second test boundary line channel; determining a channel gap of the first boundary line channel based on the first correction capacitance and the second correction capacitance; and The first borderline channel is checked based on the channel gap.

2. The method according to claim 1, in, A first portion of the touch channel of the touch panel is connected to a first line in a first direction, A second portion of the touch channel different from the first portion is connected to a second line in a direction opposite to the first direction, The first boundary line channel is included in the first portion, and The second boundary line channel is included in the second portion and is adjacent to the first boundary line channel.

3. The method according to claim 1, in, Determining the first test correction capacitance includes: Calculating an average deviation of the mutual capacitance of the first test boundary line channel; determining a test correction deviation by multiplying the mean deviation by the candidate correction factor; and The first test correction capacitance is determined based on an average value of the mutual capacitance of the first test boundary line channel and the test correction deviation.

4. The method according to claim 3, in, The average deviation of the mutual capacitance of the first test boundary line channel increases as the difference between the maximum value and the minimum value of the mutual capacitance of the first test boundary line channel increases.

5. The method according to claim 3, in, The first test correction capacitance at one node among the first test correction capacitances increases as the one node approaches a line connecting the first test boundary line channel to a pad unit of the test touch panel.

6. The method according to claim 1, in, Determining the first test correction capacitance includes: Calculating an average deviation of the mutual capacitance of the first test boundary line channel; determining a test correction deviation by multiplying the mean deviation by the candidate correction factor; and The first test correction capacitance is determined based on a mutual capacitance of an intermediate node among the mutual capacitances of the first test boundary line channel and the test correction deviation.

7. The method according to claim 1, in, The test channel gap is determined based on a ratio of the first test correction capacitance to the second test correction capacitance at each node.

8. The method according to claim 1, in, The test channel gap increases as the difference between the first test correction capacitance and the second test correction capacitance at each node increases.

9. The method according to claim 1, in, The reference channel gap is determined based on a ratio of the mutual capacitances between adjacent test non-boundary line channels among the plurality of test non-boundary line channels at each node.

10. The method according to claim 1, in, The reference channel gap increases as a difference in the mutual capacitance between adjacent test non-boundary line channels among the plurality of test non-boundary line channels at each node increases.

11. The method according to claim 1, in, When the average value of the test channel gap is less than the average value of the reference channel gap, the candidate correction coefficient is determined as the correction coefficient.

12. The method according to claim 1, in, When the maximum value of the test channel gap is smaller than the maximum value of the reference channel gap, the candidate correction coefficient is determined as the correction coefficient.

13. The method according to claim 1, in, Determining the first correction capacitance includes: Calculating individual deviations of the mutual capacitance of the first boundary line channel at each node; determining a corrected deviation by multiplying the individual deviation by the correction factor; and The first correction capacitance is determined based on an average value of the mutual capacitance of the first boundary line channel and the correction deviation.

14. The method according to claim 13, in, The individual deviation increases as a node of the first boundary line channel including each of the nodes approaches a line connecting the first boundary line channel to a pad unit of the touch panel.

15. The method according to claim 1, in, Determining the first correction capacitance includes: Calculating individual deviations of the mutual capacitance of the first boundary line channel at each node; determining a corrected deviation by multiplying the individual deviation by the correction factor; and The first correction capacitance is determined based on a mutual capacitance of an intermediate node among the mutual capacitances of the first boundary line channel and the correction deviation.

16. The method according to claim 1, in, The channel gap is determined based on a ratio of the first correction capacitance to the second correction capacitance at each node.

17. The method according to claim 1, in, The channel gap increases as the difference between the first correction capacitance and the second correction capacitance at each node increases.

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