A server chassis system and computer device

Abstract

The application relates to a server chassis system and computer equipment. The system comprises a server mainboard, a backboard and a signal relay device, the server mainboard is provided with a controller; the first ends of a plurality of backboards are connected with the controller through a connecting device; the first ends of a plurality of signal relay devices are connected with the second ends of the plurality of backboards through the connecting device; the connecting device comprises a first cable and a second cable, the first end of the first cable is connected with the second end of the controller, the second end of the first cable is connected with the first ends of the plurality of backboards, the first end of the second cable is connected with the second ends of the plurality of backboards, and the second end of the second cable is connected with the first ends of the plurality of signal relay devices; wherein the first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable. The system can reduce the number of cables and occupy less server chassis space while meeting the interaction of the controller, the backboard and the signal relay device.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a server chassis system and computer equipment. Background Technology

[0002] With the rapid development of technology, big data has permeated every industry and business function. The dramatic increase in information volume and the growing amount of data requiring processing have placed a greater demand on servers. As a type of computer, servers provide computing, storage, and data exchange services to internet users, making them a crucial component of the internet age. Servers not only boast high processing speeds, long operating times, and large data throughput, but their designs have also become increasingly complex to meet diverse customer needs. However, this increased complexity in server design, including overly complex interfaces, cables, and other components, can lead to decreased signal transmission and heat dissipation performance. Summary of the Invention

[0003] Therefore, it is necessary to provide a server chassis system and computer equipment that can occupy less server space to address the above-mentioned technical problems.

[0004] To address the aforementioned technical problems, in a first aspect, a server chassis system is provided, comprising:

[0005] The server motherboard contains the controller.

[0006] Backplate, there are multiple backplates, and the first end of the multiple backplates is connected to the controller through a connecting device;

[0007] Signal relay equipment, there are multiple signal relay equipment, and the first end of the multiple signal relay equipment is connected to the second end of multiple backplanes through a connecting device;

[0008] The connection device includes a first cable and a second cable. The first end of the first cable is connected to the second end of the controller, the second end of the first cable is connected to the first end of a plurality of backplanes, the first end of the second cable is connected to the second end of a plurality of backplanes, and the second end of the second cable is connected to the first end of a plurality of signal relay devices.

[0009] The first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable.

[0010] In one embodiment, the system further includes a hard disk device mounted on a backplane, which is connected to a signal relay device and the backplane via pre-set high-speed and low-speed cables, respectively.

[0011] In one embodiment, the preset high-speed and low-speed cables include multiple sub-high-speed cables and multiple sub-low-speed cables. The hard disk device is connected to the signal relay device and the backplane respectively through the preset high-speed and low-speed cables, including:

[0012] The first end of the hard drive device is connected to the second end of the backplane via multiple low-speed cables. The second end of the hard drive device is connected to the first end of the signal relay device via multiple high-speed cables. The second end of the backplane is connected to the first end of the signal relay device via multiple low-speed cables.

[0013] In one embodiment, the controller includes at least a first interface and a second interface. The first interface is connected to a target device disposed on a server motherboard, and the second interface is connected to a target device disposed on a backplane and a signal relay device.

[0014] In one embodiment, the target device includes a first target device, a second target device, and a third target device. The first target device is disposed on a server motherboard, the second target device is disposed on a backplane, and the third target device is disposed on a signal relay device. The second interface is connected to the target devices disposed on the backplane and the signal relay device, including:

[0015] The second interface is connected to the first end of the second target device, and the second end of the second target device is connected to the first end of the third target device.

[0016] In one embodiment, a third interface is provided at the first end of the backplane, and a fourth interface is provided at the first end of the signal relay device.

[0017] The second interface connects to the third interface via the target cable;

[0018] The third interface is connected to the first end of the second target device via the target cable, and the second end of the second target device is connected to the fourth interface via the target cable.

[0019] The fourth interface is connected to the first end of the third target device via the target cable;

[0020] The backplane also includes a first control module, and the signal relay device includes a second control module.

[0021] The first end of the first control module is connected to the third interface, and the second end of the first control module is connected to the first end of the second target device.

[0022] The first end of the second control module is connected to the fourth interface, and the second end of the second control module is connected to the first end of the third target device.

[0023] In one embodiment, the first control module includes a first signal control module and a first switch control module, and the second control module includes a second signal control module and a second switch control module;

[0024] The first signal control module and the second signal control module are used to control the on / off state of the digital signals of the second target device and the third target device, respectively.

[0025] The first switch control module and the second switch control module are used to control the on / off state of the clock signals of the second target device and the third target device, respectively.

[0026] In one embodiment, a first end of the backplane is provided with a first crystal oscillator, a first pin, and a first trigger, and a second end of the backplane is provided with a second crystal oscillator, a second pin, and a second trigger.

[0027] The output terminal of the first crystal oscillator is connected to the input terminal of the first flip-flop, and the output terminal of the first flip-flop is connected to the first pin.

[0028] The output of the second crystal oscillator is connected to the input of the second flip-flop, and the output of the second flip-flop is connected to the second pin.

[0029] In one embodiment, a first crystal oscillator is used to generate a first base frequency signal, the first crystal oscillator transmits the first base frequency signal to a first flip-flop, the first flip-flop is used to generate a first frequency division signal according to the first base frequency signal, the first flip-flop transmits the first frequency division signal to a first pin, and the first pin is connected to a first cable.

[0030] The first frequency division signal is transmitted to the controller via the first cable. The controller is used to determine the connection status of the first cable between the controller and the backplane based on the first frequency division signal.

[0031] The second crystal oscillator is used to generate the second base frequency signal. The second crystal oscillator transmits the second base frequency signal to the second flip-flop. The second flip-flop is used to generate a second frequency division signal according to the second base frequency signal. The second flip-flop transmits the second frequency division signal to the second pin. The second pin is connected to the second cable.

[0032] The second frequency division signal is transmitted to the control chip on the signal relay device via the second cable. The control chip is used to determine the connection status of the second cable between the signal relay device and the backplane based on the second frequency division signal.

[0033] In order to solve the above-mentioned technical problems, a second aspect provides a server chassis device, which includes the server chassis system of any of the above-mentioned claims.

[0034] Unlike existing technologies, this application sets up a server chassis system comprising: a server motherboard, a backplane, and signal relay devices. A controller is mounted on the server motherboard. Multiple backplanes are connected to the controller via a connection device at their first ends. Multiple signal relay devices are connected to the backplanes via the same connection device at their first ends. The connection device includes a first cable and a second cable. The first end of the first cable is connected to the controller at its second end, and the second end of the first cable is connected to the first ends of the multiple backplanes. The first end of the second cable is connected to the second ends of the multiple backplanes, and the second end of the second cable is connected to the first ends of the multiple signal relay devices. The first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable. This system can reduce the number of interfaces and occupy less server space while satisfying the interaction requirements of the controller, backplane, and signal relay devices. Attached Figure Description

[0035] Figure 1 This is a structural block diagram of a server chassis system in the prior art;

[0036] Figure 2 This is a schematic diagram of the structure of a backplane and signal relay device in the prior art;

[0037] Figure 3 This is a schematic diagram of the server chassis system in one embodiment;

[0038] Figure 4 This is a structural diagram of the server chassis system in yet another embodiment;

[0039] Figure 5 This is a structural diagram of the server chassis system in yet another embodiment;

[0040] Figure 6 This is a schematic diagram of the backplane and signal relay device in another embodiment;

[0041] Figure 7 This is a structural diagram of the server chassis system in yet another embodiment;

[0042] Figure 8 This is an internal structural diagram of a server chassis device in one embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] Please see Figure 1In existing technologies, for designs with multiple boards (backplane and retimer card shown in the diagram) in a single chassis, the Baseboard Management Controller (BMC) needs to manage each board uniformly via I2C (bidirectional serial bus). For separate boards, a low-speed cable (I2C) is typically used to connect the BMC and the other boards (backplane and retimer card), assigning a dedicated low-speed cable to each board for monitoring, reading, and writing operations. This requires the BMC to dedicate one I2C port for each board it manages, resulting in a waste of BMC ports when there are many boards. Furthermore, since the BMC connects the boards via cables, a large number of cables leads to numerous cables, occupying server chassis space, creating clutter, hindering airflow, making cable management difficult, and increasing the risk of cable damage and overall system quality issues.

[0045] Please see Figure 2 In existing technologies, for high-speed signal topology design, taking PCIe signals as an example, when the cable is too long, a Retimer card (signal repeater) is used. The Retimer card (signal repeater) is then connected to the backplane via a cable, and a PCIe drive is then inserted on the backplane. In this solution, the high-speed signal from the Retimer card travels through multiple interfaces, from the interface to the high-speed cable, then through the cable to the backplane interface, and finally from the backplane to the PCIe drive interface. This multiple interface routing, combined with the backplane wiring, results in significant signal loss and is very unfriendly to high-speed signals.

[0046] To address the aforementioned technical problems, this application provides a server chassis system, comprising: a server motherboard, a backplane, and signal relay devices. The server motherboard has a controller; multiple backplanes are included, with their first ends connected to the controller via a connection device; multiple signal relay devices are also included, with their first ends connected to the second ends of the multiple backplanes via the connection device. This system can reduce the number of interfaces and occupy less server space while satisfying the interaction requirements of the controller, backplane, and signal relay devices.

[0047] Example 1

[0048] In the embodiments disclosed in this application, there are such Figure 3 The server chassis system shown includes a server motherboard (management board), backplane, signal relay equipment, and connection devices.

[0049] The server motherboard is used to house various devices installed on the server motherboard, including controllers, which may specifically be baseboard management controllers (BMC), processors, heat sinks, and other devices.

[0050] Multiple backplanes provide interfaces corresponding to expansion slots on the server motherboard, allowing the installation of various expansion cards to enhance the server's functionality and performance. The diagram shows multiple backplanes including backplane 1, backplane 2, and backplane n.

[0051] Multiple signal relay devices are included. Optionally, these relay devices can be Retimer cards, which are signal conditioning chips used for signal equalization and enhancement. Similar to a PHY chip, when a signal passes through a Retimer card, the signal is reconstructed using the card's internal clock, increasing the signal transmission power before continued transmission, thus improving the reliability of the server chassis system. The diagram shows multiple relay devices including Retimer card 1, Retimer card 2, and Retimer card n.

[0052] In order to achieve coupling of the components in the embodiment, this application also provides a connection device. In this embodiment, the connection device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller. The second end of the first cable 11 is connected to the first end of a plurality of backplanes. The first end of the second cable 12 is connected to the second end of a plurality of backplanes. The second end of the second cable 12 is connected to the first end of a plurality of signal relay devices.

[0053] In this embodiment, the connection device includes a first cable 11 and a second cable 12. In this implementation, the second cable is a high-speed cable, and the first cable is a low-speed cable. As shown in the figure, the second cable 12 includes multiple high-speed cables, and the first cable 11 includes multiple low-speed cables. The second cable 12 can be an existing high-speed cable connecting the backplane and the signal relay equipment, and the first cable 11 can be an I2C serial communication bus.

[0054] In this embodiment, the connection between the backplane and the signal relay device on the server motherboard is achieved by using the existing high-speed cable connecting the backplane and the signal relay device. The connection between the controller on the server motherboard and multiple backplanes is achieved by using low-speed cables. There is no need to set up additional connection cables for the connection between the backplane and the signal relay device. Furthermore, using low-speed cables to connect the controller on the server motherboard and multiple backplanes can also reduce costs.

[0055] Furthermore, in this embodiment, a backplane and a signal relay device are connected in series through one interface, which reduces the number of interfaces in the server and further frees up available server space.

[0056] In this embodiment, both the first cable 11 and the second cable 12 can be high-speed cables, and both the first cable 11 and the second cable 12 can be existing high-speed cables connecting the backplane and the signal relay equipment. In this embodiment, by using the existing high-speed cables connecting the backplane and the signal relay equipment, the connection between the controller set on the server motherboard and the backplane and the signal relay equipment can be realized, which can reduce the space occupied by the cables in the server and thus improve the performance of the server.

[0057] And compare Figure 1 The traditional approach involves arranging multiple interfaces on the controller mounted on the server motherboard to connect to multiple backplanes and signal relay devices, i.e., one interface corresponds to one backplane or one interface corresponds to one signal relay device. In this application, a backplane and a signal relay device are connected in series through one interface, which reduces the number of interfaces arranged in the server and further frees up the available space in the server.

[0058] Example 2

[0059] In the embodiments disclosed in this application, there are such Figure 4 The server chassis system shown includes a server motherboard (management board), backplane, signal relay equipment, connection devices, hard disk devices, and pre-installed high-speed and low-speed cables.

[0060] The server motherboard is used to house various devices installed on the server motherboard, including controllers, which may specifically be baseboard management controllers (BMC), processors, heat sinks, and other devices.

[0061] Multiple backplanes provide interfaces corresponding to the expansion slots on the server motherboard, allowing the installation of various expansion cards to increase the server's functionality and performance.

[0062] Multiple signal relay devices are available. Optionally, the signal relay device can be a Retimer card, which is a signal conditioning chip used for signal equalization and enhancement.

[0063] In this embodiment, the connection device includes a first cable 11 and a second cable 12. The first end of the first cable 11 is connected to the second end of the controller, that is, the output end of the controller. The second end of the first cable 11 is connected to the first end of a plurality of backplanes. The first end of the second cable 12 is connected to the second end of a plurality of backplanes. The second end of the second cable 12 is connected to the first end of a plurality of signal relay devices.

[0064] The hard drive device 30 is mounted on the backplane, possibly on the side of the backplane closer to the signal relay device. The gray filled block shown in the figure represents the hard drive device 30. The hard drive device can be an SSD, PCIe, or other type of hard drive. The hard drive device 30 is connected to the signal relay device and the backplane via pre-set high-speed and low-speed cables 13, respectively.

[0065] Specifically, the preset high-speed and low-speed cables include multiple sub-high-speed cables and multiple sub-low-speed cables. The first end of the hard disk device 30 is connected to the second end of the backplane through multiple sub-low-speed cables 133. The second end of the hard disk device 30 is connected to the first end of the signal relay device through multiple sub-high-speed cables 131. The second end of the backplane is connected to the first end of the signal relay device through multiple sub-low-speed cables 132.

[0066] In this application, a preset high-speed and low-speed cable is used to connect the signal relay device, backplane, and hard disk device. The sub-high-speed cable of the preset high-speed and low-speed cable does not pass through the backplane and directly connects to the signal relay device and hard disk device. The low-speed signals of the signal relay device and hard disk device are respectively connected to the backplane through the sub-low-speed cables of the preset high-speed and low-speed cable. In this way, the connectors on the high-speed signal link and the high-speed signal loss on the PCB (printed circuit board) are saved, and more cables can be introduced, which objectively increases the stability of the high-speed link.

[0067] It is understood that this application only describes the connection relationship between the backplane 1, the hard disk device, and the signal relay device (Retimer card 1) by taking the hard disk device as an example. In actual applications, there can be multiple hard disk devices arranged on multiple backplanes.

[0068] It is understood that the preset high-speed and low-speed cables and hard disk devices in this embodiment can also be applied to the server chassis system in Embodiment 1 of this application.

[0069] Example 3

[0070] In the embodiments disclosed in this application, there are such Figure 5 The server chassis system shown includes a server motherboard, backplane, signal relay equipment, connection devices, and target devices.

[0071] The server motherboard is used to house various devices installed on the server motherboard, including controllers, which may specifically be baseboard management controllers (BMC), processors, heat sinks, and other devices.

[0072] In this embodiment, the controller on the server motherboard is provided with an interface, including at least a first interface 141 and a second interface 142. The first interface 141 is connected to the target device on the server motherboard; the second interface 142 is connected to the target device on the backplane and the signal relay device.

[0073] Multiple backplanes provide interfaces corresponding to the expansion slots on the server motherboard, allowing the installation of various expansion cards to increase the server's functionality and performance.

[0074] Multiple signal relay devices are available. Optionally, the signal relay device can be a Retimer card, which is a signal conditioning chip used for signal equalization and enhancement.

[0075] The connection device includes a first cable 11 and a second cable 12. A first end of the first cable 11 is connected to a second end of the controller, i.e., the controller's output end. The second end of the first cable 11 is connected to the first ends of multiple backplanes. The first end of the second cable 12 is connected to the second ends of multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices. In this embodiment, both the first cable 11 and the second cable 12 are high-speed cables.

[0076] The target devices include a first target device 15, a second target device 16, and a third target device 17. The first target device 15 is mounted on the server motherboard, the second target device 16 is mounted on the backplane, and the third target device 17 is mounted on the signal relay device. The second interface 142 is connected to the first end of the second target device 16, and the second end of the second target device 16 is connected to the first end of the third target device 17.

[0077] Here, the first target device 15 can be an I2C master device, and the second target device 16 and the third target device 17 can be I2C slave devices. By setting up I2C master and slave devices on the server motherboard, backplane, and signal relay devices respectively, the I2C master device can send stop conditions to the slave device to stop signal and data transmission. By setting up I2C master and slave devices, high-speed data transmission capabilities can be achieved through simple system connections, providing convenience and efficiency for the design of server chassis systems.

[0078] Please see Figure 5 as well as Figure 6In one embodiment, a third interface 18 is provided at the first end of the backplane, and a fourth interface 19 is provided at the first end of the signal relay device; the second interface 142 is connected to the third interface 18 via a target cable 40; the third interface 18 is connected to the first end of the second target device 16 via the target cable 40, and the second end of the second target device 16 is connected to the fourth interface 19 via the target cable 40; the fourth interface 19 is connected to the first end of the third target device 17 via the target cable 40.

[0079] The backplane also includes a first control module 20, and the signal relay device includes a second control module 21; the first end of the first control module 20 is connected to the third interface 18, and the second end of the first control module 20 is connected to the first end of the second target device 16; the first end of the second control module 21 is connected to the fourth interface 19, and the second end of the second control module 21 is connected to the first end of the third target device 17.

[0080] In this embodiment, a third interface 18, a first control module 20, a fourth interface 19, and a second control module 21 are configured between the I2C master device and the I2C slave device. The first end of the third interface 18 is connected to the control terminal of the I2C master device, and the second end of the third interface 18 is connected to the first control module, which in turn connects to the I2C slave device. This configuration allows for monitoring of the I2C link status, identification of any stalled I2C slave device based on the link status, and isolation of the stalled I2C slave device. Due to the series connection between the control module and the target device, any failure of an I2C slave device at the back end of the link is promptly detected and isolated without affecting I2C slave devices in other links. Therefore, this structural design significantly improves the accuracy of I2C link control, thereby enhancing the management efficiency of the I2C link.

[0081] In one embodiment, the first control module 20 includes a first signal control module (not shown) and a first switch control module, and the second control module 21 includes a second signal control module and a second switch control module; the first signal control module and the second signal control module are respectively used to control the on / off state of the digital signals of the second target device 16 and the third target device 17; the first switch control module and the second switch control module are respectively used to control the on / off state of the clock signals of the second target device 16 and the third target device 17.

[0082] The first switch control module and / or the second switch control module are used to control the on / off state of digital signals of I2C slave devices connected to the first switch control module and / or the second switch control module in the I2C link according to the acquired signals. The input terminals of the first switch control module and / or the second switch control module are connected to the data output terminals of the upstream and downstream devices, respectively. The output terminals of the first switch control module and / or the second switch control module are connected to the I2C slave devices via the I2C_SDA Slave signal. The I2C_SDA Slave signal is the data signal of the I2C slave device.

[0083] The first signal control module and / or the second signal control module are used to control the on / off state of the clock signal of the I2C slave device connected to the first signal control module and / or the second signal control module in the I2C link according to the acquired signal. The input terminal of the first signal control module and / or the second signal control module is connected to the clock output terminal of the upper-level device and the clock input terminal of the lower-level device. The output terminal of the first signal control module and / or the second signal control module is connected to the I2C slave device through the I2C_SCLSlave signal, wherein the I2C_SCL Slave signal is the clock signal of the I2C slave device.

[0084] Thus, by controlling the digital signal switching of the second target device 16 and the third target device 17 by the first signal control module and the second signal control module respectively, and by controlling the clock signal switching of the second target device 16 and the third target device 17 respectively, data transmission and signal transmission accuracy can be achieved.

[0085] Example 4

[0086] In the embodiments disclosed in this application, there are such Figure 7 The server chassis system shown includes a server motherboard, a backplane, a signal relay device, a connection device, a first crystal oscillator, a first pin, a first trigger, a second crystal oscillator, a second pin, and a second trigger.

[0087] The server motherboard is used to house various devices installed on the server motherboard, including controllers, which may specifically be baseboard management controllers (BMC), processors, heat sinks, and other devices.

[0088] Multiple backplanes provide interfaces corresponding to the expansion slots on the server motherboard, allowing the installation of various expansion cards to increase the server's functionality and performance.

[0089] Multiple signal relay devices are available. Optionally, the signal relay device can be a Retimer card, which is a signal conditioning chip used for signal equalization and enhancement.

[0090] The connection device includes a first cable 11 and a second cable 12. A first end of the first cable 11 is connected to a second end of the controller, i.e., the controller's output end. The second end of the first cable 11 is connected to the first ends of multiple backplanes. The first end of the second cable 12 is connected to the second ends of multiple backplanes, and the second end of the second cable 12 is connected to the first ends of multiple signal relay devices. In this embodiment, both the first cable 11 and the second cable 12 are high-speed cables.

[0091] In this embodiment, a first crystal oscillator 23, a first pin 27, and a first trigger 25 are provided at the first end of the backplane, and a second crystal oscillator 24, a second pin 28, and a second trigger 26 are provided at the second end of the backplane.

[0092] Specifically, the output of the first crystal oscillator 23 is connected to the input of the first flip-flop 25, and the output of the first flip-flop 25 is connected to the first pin 27; the output of the second crystal oscillator 24 is connected to the input of the second flip-flop 26, and the output of the second flip-flop 26 is connected to the second pin 28.

[0093] The first crystal oscillator 23 is used to generate a first base frequency signal. The first crystal oscillator 23 transmits the first base frequency signal to the first trigger 25. The first trigger 25 is used to generate a first frequency division signal according to the first base frequency signal. The first trigger 25 transmits the first frequency division signal to the first pin 27. The first pin 27 is connected to the first cable 11. The first frequency division signal is transmitted to the controller (BMC) through the first cable 11. The controller is used to determine the connection status of the first cable 11 between the controller and the backplane according to the first frequency division signal.

[0094] The second crystal oscillator 24 is used to generate a second base frequency signal. The second crystal oscillator 24 transmits the second base frequency signal to the second flip-flop 26. The second flip-flop 26 is used to generate a second frequency division signal based on the second base frequency signal. The second flip-flop 26 transmits the second frequency division signal to the second pin 28. The second frequency division signal is transmitted to the control chip on the signal relay device through the second cable 12. The control chip determines the connection status of the second cable 12 between the signal relay device and the backplane based on the second frequency division signal.

[0095] In this application, by providing a first crystal oscillator 23, a first pin 27, and a first trigger 25 at the first end of the backplane, and a second crystal oscillator 24, a second pin 28, and a second trigger 26 at the second end of the backplane, the first baseband signal generated by the first crystal oscillator 23 can be transmitted to the first trigger 25 to obtain a first divided frequency signal. This first divided frequency signal is then transmitted to the first pin 27, which is connected to the first cable 11. This allows the first divided frequency signal to be transmitted to the controller on the server motherboard. The controller on the server motherboard determines whether the first cable is connected correctly based on the first divided frequency signal. Similarly, [the following can be achieved]. The second base frequency signal generated by the second crystal oscillator 24 is transmitted to the second trigger 26 to obtain the first frequency division signal. The first frequency division signal is then transmitted to the second pin 28, which is connected to the second cable 12. This enables the transmission of the second frequency division signal to the control chip on the signal relay device. The control chip on the signal relay device determines whether the second cable is connected correctly based on the second frequency division signal. This enables the detection of multiple cables in a multi-connection device. Furthermore, the triggers and crystal oscillators used are very small in size, which can further save internal space in the server chassis while ensuring the connection reliability of the connection device.

[0096] This application utilizes existing high-speed cables connecting the backplane and signal relay equipment to connect the controller on the server motherboard to the backplane and signal relay equipment. This reduces the space occupied by cables, saves cable management, facilitates cable plugging and unplugging by operators, minimizes the space occupied by cables within the chassis, reduces the impact of cables on heat dissipation, and frees up server system space for other designs. Furthermore, it saves the I2C interface of the BMC, allowing the BMC to be used in more complex systems.

[0097] By setting up a pre-defined high-speed and low-speed cable to connect the signal relay device, backplane, and hard drive, where the sub-high-speed cables of the pre-defined high-speed and low-speed cables directly connect to the signal relay device and hard drive without passing through the backplane, and the low-speed signals of the signal relay device and hard drive are respectively connected to the backplane through the sub-low-speed cables of the pre-defined high-speed and low-speed cables, this saves on connectors and high-speed signal loss on the high-speed signal link and PCB (printed circuit board), allowing for the introduction of more cables and objectively increasing the stability of the high-speed link. Through the above implementation method, this application solves the problem of insufficient BMC I2C interfaces, reduces cables in the chassis, and addresses issues such as complex cabling within the chassis, easy cable damage, and excessive cables affecting heat dissipation. It also solves the problem of excessive high-speed link loss and the inability to run long traces.

[0098] In one embodiment, a temperature detection chip can be installed on the upstream side of the server motherboard to monitor the temperature of various components within the server system in real time. The controller on the server can obtain the temperature information of various components within the server system in real time via a connector and I2C, thereby achieving real-time temperature monitoring of various components within the server system and adjusting the heat dissipation strategy based on the temperature data to reduce power consumption, thus achieving the goal of energy saving and environmental protection.

[0099] The Baseboard Management Controller (BMC) on the server motherboard obtains temperature information of various components within the server system through GPIO or I2C reads, thereby enabling real-time temperature monitoring of these components. For example, the I2C driver chip connected to the motherboard can obtain the response signal for each I / O interface on each signal relay device; parsing each response signal yields an array corresponding to each I / O interface on each signal relay device.

[0100] In one embodiment, the temperature detection chip can be located at the very front of the server motherboard, which can be the air intake of the motherboard. The copper plating and traces on the motherboard where the temperature detection chip is placed can be removed to prevent heat from other components from being conducted to the temperature detection chip and affecting the measurement accuracy. The temperature detection chip is installed at this location. The temperature detection chip is connected to the BMC (Baseboard Management Controller) via an I2C channel and transmits raw data to the BMC chip. The BMC chip corrects the data, thereby improving the accuracy of temperature detection.

[0101] Specifically, the temperature detection chip can obtain the real-time operating temperature of various components in the server chassis system, such as the processor and network switch on the motherboard, during operation. The I2C bus can determine whether the current operating temperature is within the normal operating temperature range of the server chassis system based on this operating temperature. If the real-time operating temperature of a certain component is not within the normal operating temperature range of the server chassis system, the location information of the component is obtained, an alarm message is issued, and it is displayed on the configuration interface.

[0102] In one embodiment, a server chassis device is provided, including the server chassis system described above. Its internal structure diagram can be as follows: Figure 8 As shown. Those skilled in the art will understand that... Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the server chassis equipment on which the solution of this application is applied. The specific server chassis equipment may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A server chassis system, characterized in that, include: Server motherboard, wherein a controller is mounted on the server motherboard; A backplate, wherein there are multiple backplates, and the first end of the multiple backplates is connected to the controller via a connecting device; A signal relay device, wherein there are multiple signal relay devices, and the first end of the multiple signal relay devices is connected to the second end of the multiple backplanes through a connecting device; The connection device includes a first cable and a second cable. A first end of the first cable is connected to a second end of the controller. A second end of the first cable is connected to a first end of the plurality of backplanes. A first end of the second cable is connected to a second end of the plurality of backplanes. A second end of the second cable is connected to a first end of the plurality of signal relay devices. The hard disk device is mounted on a backplane and is connected to a signal relay device and the backplane via pre-set high-speed and low-speed cables, respectively. Wherein, the first cable is a low-speed / high-speed cable, and the second cable is a high-speed cable; the preset high-speed and low-speed cables include multiple sub-high-speed cables and multiple sub-low-speed cables, the first end of the hard disk device is connected to the second end of the backplane through the multiple sub-low-speed cables, the second end of the hard disk device is connected to the first end of the signal relay device through the multiple sub-high-speed cables, and the second end of the backplane is connected to the first end of the signal relay device through the multiple sub-low-speed cables; Among them, the sub-high-speed cables in the preset high-speed and low-speed cables do not pass through the backplane and are directly connected to the signal relay equipment and hard disk equipment.

2. The system according to claim 1, characterized in that, The controller includes at least a first interface and a second interface. The first interface is connected to a target device mounted on the server motherboard, and the second interface is connected to a target device mounted on the backplane and a signal relay device.

3. The system according to claim 2, characterized in that, The target devices include a first target device, a second target device, and a third target device. The first target device is mounted on the server motherboard, the second target device is mounted on the backplane, and the third target device is mounted on a signal relay device. The second interface connects to the target devices mounted on the backplane and the signal relay device, including: The second interface is connected to the first end of the second target device, and the second end of the second target device is connected to the first end of the third target device.

4. The system according to claim 3, characterized in that, The first end of the backplane is provided with a third interface, and the first end of the signal relay device is provided with a fourth interface; The second interface is connected to the third interface via the target cable; The third interface is connected to the first end of the second target device via a target cable, and the second end of the second target device is connected to the fourth interface via a target cable. The fourth interface is connected to the first end of the third target device via a target cable; The backplane further includes a first control module, and the signal relay device includes a second control module. The first end of the first control module is connected to the third interface, and the second end of the first control module is connected to the first end of the second target device. The first end of the second control module is connected to the fourth interface, and the second end of the second control module is connected to the first end of the third target device.

5. The system according to claim 4, characterized in that, The first control module includes a first signal control module and a first switch control module, and the second control module includes a second signal control module and a second switch control module; The first signal control module and the second signal control module are respectively used to control the on / off state of the digital signals of the second target device and the third target device; The first switch control module and the second switch control module are used to control the on / off state of the clock signals of the second target device and the third target device, respectively.

6. The system according to claim 1, characterized in that, The first end of the backplane is provided with a first crystal oscillator, a first pin, and a first trigger, and the second end of the backplane is provided with a second crystal oscillator, a second pin, and a second trigger. The output terminal of the first crystal oscillator is connected to the input terminal of the first flip-flop, and the output terminal of the first flip-flop is connected to the first pin. The output terminal of the second crystal oscillator is connected to the input terminal of the second flip-flop, and the output terminal of the second flip-flop is connected to the second pin.

7. The system according to claim 6, characterized in that, The first crystal oscillator is used to generate a first base frequency signal. The first crystal oscillator transmits the first base frequency signal to a first flip-flop. The first flip-flop is used to generate a first frequency division signal according to the first base frequency signal. The first flip-flop transmits the first frequency division signal to a first pin. The first pin is connected to the first cable. The first frequency division signal is transmitted to the controller through the first cable, and the controller is used to determine the connection status of the first cable between the controller and the backplane based on the first frequency division signal. The second crystal oscillator is used to generate a second base frequency signal. The second crystal oscillator transmits the second base frequency signal to a second flip-flop. The second flip-flop is used to generate a second frequency division signal according to the second base frequency signal. The second flip-flop transmits the second frequency division signal to a second pin. The second pin is connected to the second cable. The second frequency division signal is transmitted to the control chip on the signal relay device via the second cable. The control chip is used to determine the connection status of the second cable between the signal relay device and the backplane based on the second frequency division signal.

8. A server chassis device, characterized in that, The server chassis device includes the server chassis system as described in any one of claims 1-7.

Images