Method for judging PCIe fault position, server and electronic device

Abstract

Embodiments of the present application provide a method for judging a PCIe fault position, a server and an electronic device. In the embodiments of the present application, PCIe tree structure information obtained is first sent to a BMC by a BIOS for subsequent fault positioning; then, when a PCIe device fault signal is detected, the BIOS reports it to the BMC, so that the BMC determines a target PCIe link in which a target PCIe device is located based on BDF information of the target PCIe device indicated by the PCIe device fault signal and the PCIe tree structure information. In this way, by positioning a faulty PCIe device based on AER register information of all PCIe devices on the target PCIe link, the situation that a faulty PCIe device is difficult to locate due to fault analysis based only on AER register information of a faulty PCIe device can be avoided, and the accuracy of PCIe fault position positioning is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method for determining the location of a PCIe fault, a server, and electronic equipment. Background Technology

[0002] With the continuous development of technology, the number of high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) devices configured in current servers is gradually increasing, and the management and maintenance of these PCIe devices are becoming increasingly important.

[0003] In practical applications, the Baseboard Management Controller (BMC) only collects the Advanced Error Reporting (AER) register information of PCIe devices that report faults. However, the PCIe device that reports a fault may not actually be the PCIe device that is actually malfunctioning, but may be another PCIe device. In this case, since the BMC only records the AER register information of the PCIe device that reports a fault, it is difficult to locate the actual faulty PCIe device. Summary of the Invention

[0004] In view of this, this application provides a method, server, and electronic device for determining the location of PCIe faults, so as to improve the accuracy of PCIe fault location.

[0005] This application provides a method for determining the location of a PCIe fault. This method is applied to a server and includes:

[0006] A high-speed serial computer extended bus standard (PCIe) tree structure is constructed through the Basic Input Output System (BIOS) in the server, and the PCIe tree structure information is sent to the BMC in the server. The PCIe tree structure consists of N nodes connected in a hierarchical manner, where N is the number of PCIe devices deployed on the server, and N is greater than 1. Each node in the PCIe tree structure is represented by the BusNumber, Device Number, Function Number (BDF) information of one of the PCIe devices deployed on the server. The BDF information of any PCIe device is used to uniquely identify the PCIe device. The hierarchical connection means that for any PCIe device, the PCIe device at the upper level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the lower level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device.

[0007] When the BIOS detects a PCIe device fault signal, it sends the AER register information of the target PCIe device indicated by the PCIe device fault signal to the BMC. The AER register information of any PCIe device refers to the information recorded in the AER register of that PCIe device, and the AER register information includes at least the BDF information of that PCIe device.

[0008] The BMC determines the target PCIe link from the PCIe tree structure based on the BDF information of the target PCIe device. The target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the nodes represented by the BDF information of the target PCIe device.

[0009] The AER register information of all PCIe devices on the target PCIe link is obtained through the BMC, so as to locate the faulty PCIe device based on the obtained AER register information.

[0010] This application embodiment also provides a server, which is equipped with a BMC, a BIOS, and N PCIe devices, where N is greater than 1;

[0011] The BIOS is used to construct the PCIe tree structure and send the PCIe tree structure information to the BMC in the server. The PCIe tree structure includes N nodes connected according to a hierarchical connection relationship. Each node in the PCIe tree structure is represented by the BDF information of one of the PCIe devices deployed on the server. The BDF information of any PCIe device is used to uniquely identify the PCIe device. The hierarchical connection relationship means that for any PCIe device, the PCIe device at the upper level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the lower level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device.

[0012] The BIOS is also used to send the AER register information of the target PCIe device indicated by the PCIe device fault signal to the BMC when a PCIe device fault signal is detected; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information includes at least the BDF information of the PCIe device.

[0013] BMC is used to determine the target PCIe link from the PCIe tree structure based on the BDF information of the target PCIe device; the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the nodes represented by the BDF information of the target PCIe device.

[0014] BMC is also used to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

[0015] This application also provides an electronic device, which includes:

[0016] Processor; and

[0017] A computer-readable storage medium storing computer program instructions that, when executed by a processor, cause the processor to perform the steps of the method described above.

[0018] This application also provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the above method.

[0019] As can be seen from the above technical solutions, in this embodiment, the PCIe tree structure is first constructed by the BIOS and the PCIe tree structure information is sent to the BMC for subsequent PCIe fault location. Then, when the BIOS detects a PCIe device fault signal, it reports the PCIe device fault signal to the BMC so that the BMC can determine the target PCIe link in the PCIe tree structure based on the BDF information of the target PCIe device indicated by the PCIe device fault signal and the PCIe tree structure information. In this way, by locating the faulty PCIe device based on the AER register information of all PCIe devices on the target PCIe link, the situation where it is difficult to locate the actual faulty PCIe device due to fault analysis based solely on the AER register information of the reported faulty PCIe device can be avoided, thereby improving the accuracy of PCIe fault location. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this application, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] Figure 1 This is a flowchart illustrating the method provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the PCIe tree structure provided in an embodiment of this application.

[0023] Figure 3 Another method flowchart provided for an embodiment of this application.

[0024] Figure 4 This is a schematic diagram of the server structure provided in an embodiment of this application.

[0025] Figure 5 This is a schematic diagram of the electronic device structure provided in an embodiment of this application. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions provided in the embodiments of this application, and to make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the technical solutions in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0027] See Figure 1 , Figure 1 This is a flowchart illustrating a method provided in an embodiment of this application. The method is applied to a server, which has at least a BIOS, a BMC, and N PCIe devices deployed thereon, where N is greater than 1.

[0028] like Figure 1 As shown, the process may include the following steps:

[0029] Step 101: Construct a PCIe tree structure through the BIOS in the server, and send the PCIe tree structure information to the BMC in the server.

[0030] In this embodiment, the PCIe tree structure refers to the topology of a PCIe system consisting of N PCIe devices in a server. The PCIe tree structure comprises N nodes connected in a hierarchical manner, as described above, where N is the number of PCIe devices deployed on the server. Each node in the PCIe tree structure is characterized by the BDF information of one of the PCIe devices deployed on the server; the BDF information of any PCIe device is used to uniquely identify that PCIe device.

[0031] In this embodiment, the above-mentioned hierarchical connection relationship means that, for any PCIe device, the PCIe device at the next higher level refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the next lower level refers to the PCIe device connected to the downstream port of the PCIe device.

[0032] As an example, there are many ways to implement the construction of the PCIe tree structure through the BIOS in the server in step 101. For example, it can be as follows: First, the configuration space of all PCIe devices on the server is traversed through the BIOS in the server to obtain the BDF information of each PCIe device and the physical connection relationship between each PCIe device and other connected PCIe devices. Then, the PCIe tree structure is constructed based on the obtained BDF information of each PCIe device and the physical connection relationship between each PCIe device and other connected PCIe devices. Here, the physical connection relationship between any PCIe device and other connected PCIe devices refers to which port (such as upstream port or downstream port) of the PCIe device is used to connect the PCIe device to the other connected PCIe devices.

[0033] As one example, the above-described method of sending the PCIe tree structure information to the BMC in the server can be implemented in a different way. For example, the constructed PCIe tree structure can be encapsulated into a file with a specified format (i.e., PCIe tree structure information) and sent to the BM in the server. This specified file format could be, for example, JSON format, etc., and this embodiment is not specifically limited to this. In this embodiment, the PCIe tree structure information is sent to the BMC in the server for subsequent use in locating faulty PCIe devices.

[0034] Step 102: When the BIOS detects a PCIe device fault signal, it sends the AER register information of the target PCIe device indicated by the PCIe device fault signal to the BMC.

[0035] In this embodiment, the AER register information of any PCIe device refers to the information recorded in the AER register of that PCIe device. The AER register information includes at least the BDF information of the PCIe device. AER is a feature of the PCIe specification used to improve the diagnostic and troubleshooting capabilities of PCIe devices when errors occur. AER allows PCIe devices to generate error reports when errors occur, including error type, location information, and other relevant error details. Error reports can be recorded and tracked through the operating system's logging system to assist management and maintenance personnel in diagnosing and troubleshooting PCIe device errors.

[0036] As an example, the aforementioned PCIe device fault signal is generated and sent to the BIOS by one of the PCIe devices deployed on the server when it detects a data processing error event. Therefore, the PCIe device fault signal at least includes the BDF information of the PCIe device that generated the fault signal; thus, the target PCIe device is the PCIe device that generated the fault signal. This embodiment does not specifically limit how the data processing error event is detected; for example, it can be determined that a data processing error event has been detected when the PCIe device detects a data transmission anomaly.

[0037] In this embodiment, as an example, when a PCIe device detects an error, the corresponding error information is recorded in the PCIe device's AER register. The PCIe device then generates a hardware interrupt signal (i.e., a PCIe device fault signal) to notify the BIOS. The BIOS can obtain the PCIe device's BDF information based on the configured mapping between the interrupt vector indicated by the hardware interrupt signal and the BDF information. In other words, this PCIe device can be considered the target PCIe device indicated by the PCIe device fault signal. Subsequently, the BIOS can obtain the PCIe device's AER register information from the PCIe device's BDF information configuration space based on the PCIe device's BDF information and send it to the BMC. The specific method of obtaining the PCIe device's AER register information from the PCIe device's BDF information configuration space will be described with examples below and will not be elaborated here.

[0038] Step 103: Determine the target PCIe link based on the BDF information and PCIe tree structure information of the target PCIe device through the BMC.

[0039] In this embodiment, based on the above description, the PCIe tree structure information indicates the BDF information of each PCIe device and the hierarchical connection relationship between each PCIe device. Based on this, the BMC can determine the target PCIe link by using the BDF information of the target PCIe device and the PCIe tree structure information. Here, the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the nodes represented by the BDF information of the target PCIe device. The root node in the PCIe tree structure refers to the PCIe device among the N PCIe devices deployed on the server that is directly connected to the server's Central Processing Unit (CPU).

[0040] As one embodiment, the above-described method of determining the target PCIe link based on the BDF information and PCIe tree structure information of the target PCIe device using the BMC can be implemented as follows: First, obtain at least one shortest path from the root node to the terminal node in the PCIe tree structure. Then, use the shortest path from the root node to the terminal node that passes through the node represented by the BDF information of the target PCIe device as the target PCIe link. This embodiment can quickly determine the link where the target PCIe device is located by constructing a PCIe tree structure, thereby effectively reducing the time required to search for the PCIe devices to be collected and improving the efficiency of locating faulty PCIe devices.

[0041] For example, see Figure 2 The PCIe tree structure shown has two PCIe devices directly connected to the CPU, namely PCIe devices corresponding to node 1 and node 2. Figure 2 In the diagram, the root nodes are nodes 1 and 2, and the terminal nodes are nodes 7, 8, 10, and 11. Based on this, the shortest paths from the root nodes to the terminal nodes include: shortest path 1 consisting of nodes 1-3-7, shortest path 2 consisting of nodes 1-4-8, shortest path 3 consisting of nodes 1-4-9-11, shortest path 4 consisting of nodes 2-5, and shortest path 5 consisting of nodes 2-6-10, for a total of 5 shortest paths.

[0042] like Figure 2As shown, assuming node 4 is the node represented by the BDF information of the target PCIe device, then the shortest paths passing through node 4 among the five shortest paths in the PCIe tree structure include shortest path 2 and shortest path 3. In other words, shortest path 2 and shortest path 3 are both target PCIe links. Based on this, all PCIe devices on the target PCIe link can be considered to refer to the PCIe devices corresponding to nodes 1, 4, 8, 9, and 11, respectively.

[0043] Step 104: Obtain the AER register information of all PCIe devices on the target PCIe link through BMC, so as to locate the faulty PCIe device based on the obtained AER register information.

[0044] In this embodiment, when the BIOS detects a PCIe device fault signal, the target PCIe device indicated by the PCIe device fault signal (i.e., the PCIe device that generated the PCIe device fault signal) may not necessarily be the PCIe device that actually failed. Instead, it may be another PCIe device on the PCIe link (i.e., the target PCIe link) where the target PCIe device is located that has failed. Therefore, in order to ensure that the faulty PCIe device can be accurately located, it is not necessary to obtain the AER register information of all PCIe devices in the server. It is only necessary to obtain the AER register information of all PCIe devices on the PCIe link where the target PCIe device is located for the location analysis of the faulty PCIe device.

[0045] As for how to obtain the AER register information of all PCIe devices on the target PCIe link through BMC in step 104, and how to locate the faulty PCIe device based on the obtained AER register information, examples will be given below, and will not be elaborated here.

[0046] This concludes the process. Figure 1 The process is shown below.

[0047] pass Figure 1As can be seen from the process shown, in this embodiment of the application, the PCIe tree structure is first constructed by the BIOS and the PCIe tree structure information is sent to the BMC for subsequent PCIe fault location. Then, when the BIOS detects a PCIe device fault signal, it reports the PCIe device fault signal to the BMC so that the BMC can determine the target PCIe link in the PCIe tree structure based on the BDF information of the target PCIe device indicated by the PCIe device fault signal and the PCIe tree structure information. In this way, by locating the faulty PCIe device based on the AER register information of all PCIe devices on the target PCIe link, the situation where it is difficult to locate the actual faulty PCIe device due to fault analysis based solely on the AER register information of the reported faulty PCIe device can be avoided, thereby improving the accuracy of PCIe fault location.

[0048] The PCIe tree structure in step 101 above is described below:

[0049] As an example, the number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured for the server's CPU; where channel width refers to the number of channels used for data transmission.

[0050] In this embodiment, the number of root nodes in the above PCIe tree structure depends on the channel width of the PCIe interface configured for the server's CPU. There are many specific implementation methods for this. For example, as an embodiment, the channel width of the PCIe interface configured for the server's CPU is first obtained as x. That is, the PCIe interface configured for the CPU includes x data transmission channels. Among them, a PCIe device is configured to use y data transmission channels for data transmission. Based on this, the number of PCIe devices that can be connected to the PCIe interface configured for the CPU can be obtained as x / y. In other words, the number of root nodes in the above PCIe tree structure is x / y (that is, the ratio of x to y).

[0051] For example, assuming the server's CPU is configured with a PCIe interface channel width of 16, and a PCIe device is configured to use 2 data transmission channels for data transmission, then the number of root nodes in the PCIe tree structure is 16 / 2 = 8.

[0052] The following describes how to obtain the AER register information of all PCIe devices on the target PCIe link through the BMC in step 104 above:

[0053] As one example, in step 104, the AER register information of all PCIe devices on the target PCIe link is obtained through the BMC. There are many ways to implement this in practice; for example, see [link to relevant documentation]. Figure 3 As shown, its specific implementation may include the following steps:

[0054] Step 301: Obtain the BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information.

[0055] Step 302: For each BDF information obtained, the AER register information is obtained from the configuration space of the PCIe device corresponding to the BDF information through the PCI configuration access interface used for direct access to the configuration space of the PCIe device.

[0056] In this embodiment, the PCI configuration access interface may refer to the PCI Cfg interface, but this embodiment does not make any specific limitation.

[0057] In this embodiment, the AER register address corresponding to any BDF information is obtained from the configured AER register address-BDF information mapping relationship; wherein, the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

[0058] The following describes how to locate the faulty PCIe device based on the obtained AER register information in step 104 above:

[0059] In this embodiment, after obtaining the AER register information of all PCIe devices on the target PCIe link, the faulty PCIe device can be located based on the obtained AER register information. As an example, the AER register information also includes correctable error records and / or uncorrectable error records; therefore, the above-mentioned location of the faulty PCIe device based on all obtained AER register information can, in specific implementation, be as follows: based on the correctable error records and / or uncorrectable error records in the obtained AER register information, the faulty PCIe device is located from all PCIe devices on the target PCIe link. This embodiment does not specifically limit how the faulty PCIe device is located based on the correctable error records and / or uncorrectable error records in the obtained AER register information.

[0060] As an example, for any PCIe device, before obtaining the AER register information of that PCIe device, it can be checked whether the PCIe device supports AER. For example, it can be checked in the configuration space of the PCIe device to see if there is an AER extension capability record and whether the AER extension capability record contains information indicating support for AER. If so, it is determined that the PCIe device supports AER; otherwise, it is determined that the PCIe device does not support AER. Afterwards, if the PCIe device supports AER, the AER register information of the PCIe device can continue to be obtained from the configuration space of the PCIe device; if the PCIe device does not support AER, the PCIe device is skipped, that is, the AER register information is not obtained from the configuration space of the PCIe device.

[0061] This concludes the description of the method provided in the embodiments of this application. The server provided in the embodiments of this application will now be described:

[0062] See Figure 4 , Figure 4 This is a schematic diagram of the server structure provided in an embodiment of this application. Figure 4 As shown, the server 400 includes: BIOS 401, BMC 402, and N PCIe devices 403, where N is greater than 1;

[0063] BIOS 401 is used to construct a PCIe tree structure and send the PCIe tree structure information to BMC 402 in server 400. The PCIe tree structure includes N nodes connected according to a hierarchical connection relationship. Each node in the PCIe tree structure is represented by the BDF information of one of the PCIe devices 403 deployed in server 400. The BDF information of any PCIe device is used to uniquely identify the PCIe device. The hierarchical connection relationship means that for any PCIe device, the PCIe device at the upper level of the PCIe device refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the lower level of the PCIe device refers to the PCIe device connected to the downstream port of the PCIe device.

[0064] BIOS 401 is also used to send the AER register information of the target PCIe device indicated by the PCIe device fault signal to BMC 402 when a PCIe device fault signal is detected; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information includes at least the BDF information of the PCIe device.

[0065] BMC 402 is used to determine the target PCIe link based on the BDF information and PCIe tree structure information of the target PCIe device; the target PCIe link refers to the shortest path from the root node to the terminal node in the PCIe tree structure that passes through the nodes represented by the BDF information of the target PCIe device.

[0066] BMC 402 is also used to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

[0067] As an example, the number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured for the server's central processing unit (CPU); channel width refers to the number of channels used for data transmission.

[0068] As an example, a PCIe device fault signal is generated and sent to the BIOS by one of the PCIe devices deployed on the server when it detects a data processing error event.

[0069] As an example, the PCIe device fault signal includes at least the BDF information of the PCIe device that generated the PCIe device fault signal; the target PCIe device is the PCIe device that generated the PCIe device fault signal.

[0070] As an example, obtaining the AER register information of all PCIe devices on the target PCIe link through the BMC includes:

[0071] Obtain the BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information;

[0072] For each BDF information obtained, the AER register information is obtained from the configuration space of the PCIe device corresponding to the BDF information through the PCI configuration access interface used for direct access to the configuration space of the PCIe device. The AER register address corresponding to the BDF information is obtained from the configured AER register address-BDF information mapping relationship. The AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

[0073] As one example, the AER register information also includes correctable error records and / or uncorrectable error records;

[0074] Locating faulty PCIe devices based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on correctable and / or uncorrectable error records in the obtained AER register information.

[0075] This concludes the process. Figure 4 The server structure is shown in the diagram.

[0076] The implementation process of the functions and roles of each module in the above server is detailed in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0077] For the server embodiments, since they basically correspond to the method embodiments, relevant details can be found in the descriptions of the method embodiments. The server embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0078] Please see Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of this application. The electronic device may include a processor 501, a communication interface 502, a computer-readable storage medium 503, and a communication bus 504. The processor 501, communication interface 502, and computer-readable storage medium 503 communicate with each other via the communication bus 504. The computer-readable storage medium 503 stores computer program instructions; the processor 501 can execute the steps of the method described in the above embodiments by executing the computer program instructions stored on the computer-readable storage medium 503. Depending on the actual function of the electronic device, other hardware may also be included, which will not be elaborated further.

[0079] Correspondingly, embodiments of this application also provide a computer-readable storage medium storing a plurality of computer program instructions, which, when executed by a processor, can implement the methods disclosed in the above examples of this application.

[0080] For example, the aforementioned computer-readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, etc. For instance, computer-readable storage media can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof. The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0081] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for determining the location of a PCIe fault, characterized in that, This method is applied to a server, and the method includes: A high-speed serial computer extended bus standard PCIe tree structure is constructed through the Basic Input / Output System (BIOS) in the server, and the PCIe tree structure information is sent to the Baseboard Management Controller (BMC) in the server. The PCIe tree structure includes N nodes connected in a hierarchical manner, where N is the number of PCIe devices deployed on the server, and N is greater than 1. Each node in the PCIe tree structure is characterized by the Bus Number-Device Number-Function Number (BDF) information of one of the PCIe devices deployed on the server. The BDF information of any PCIe device is used to uniquely identify that PCIe device. The hierarchical connection relationship means that for any PCIe device, the PCIe device at the upper level refers to the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the lower level refers to the PCIe device connected to the downstream port of the PCIe device. When the BIOS detects a PCIe device fault signal, it obtains the BDF information of the target PCIe device indicated by the PCIe device fault signal from the configured mapping relationship between interrupt vectors and BDF information, based on the interrupt vector indicated by the PCIe device fault signal. Then, based on the BDF information of the target PCIe device, it obtains the Advanced Error Reporting (AER) register information of the target PCIe device from the configuration space of the target PCIe device and sends it to the BMC. The AER register information of any PCIe device refers to the information recorded in the AER register of that PCIe device, and the AER register information includes at least the BDF information of that PCIe device. The PCIe device fault signal is generated and sent to the BIOS by one of the PCIe devices deployed on the server when it detects a data processing error event. The BMC determines the target PCIe link based on the BDF information of the target PCIe device and the PCIe tree structure information; the target PCIe link refers to the shortest path in the PCIe tree structure from the root node to the terminal node that passes through the nodes represented by the BDF information of the target PCIe device. The BMC obtains the AER register information of all PCIe devices on the target PCIe link, and locates the faulty PCIe device based on the obtained AER register information.

2. The method according to claim 1, characterized in that, The number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured for the server's central processing unit (CPU); the channel width refers to the number of channels used for data transmission.

3. The method according to claim 1, characterized in that, The target PCIe device is the PCIe device that generates the PCIe device fault signal.

4. The method according to claim 1, characterized in that, Obtaining the AER register information of all PCIe devices on the target PCIe link through the BMC includes: Obtain the BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information; For each BDF information obtained, the AER register information is obtained from the configuration space of the PCIe device corresponding to the BDF information through the PCI configuration access interface used for direct access to the configuration space of the PCIe device. The AER register address corresponding to the BDF information is obtained from the configured AER register address-BDF information mapping relationship. The AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information.

5. The method according to claim 1, characterized in that, The AER register information also includes correctable error records and / or uncorrectable error records; Locating faulty PCIe devices based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on correctable error records and / or uncorrectable error records in the obtained AER register information.

6. A server, characterized in that, The server is equipped with a Baseboard Management Controller (BMC), a Basic Input / Output System (BIOS), and N high-speed serial computer expansion bus standard PCIe devices, where N is greater than 1; The BIOS is used to construct a PCIe tree structure and send the PCIe tree structure information to the BMC in the server. The PCIe tree structure includes N nodes connected according to a hierarchical relationship. Each node in the PCIe tree structure is represented by the Bus Number-Device Number-Function Number (BDF) information of one of the PCIe devices deployed on the server. The BDF information of any PCIe device is used to uniquely identify that PCIe device. The hierarchical connection relationship means that for any PCIe device, the PCIe device at the next higher level is the PCIe device connected to the upstream port of the PCIe device, and the PCIe device at the next lower level is the PCIe device connected to the downstream port of the PCIe device. The BIOS is further configured to, upon detecting a PCIe device fault signal, obtain the BDF information of the target PCIe device indicated by the PCIe device fault signal from the configured mapping relationship between interrupt vectors and BDF information based on the interrupt vector indicated by the PCIe device fault signal, and based on the BDF information of the target PCIe device, obtain the Advanced Error Reporting (AER) register information of the target PCIe device from the configuration space of the target PCIe device and send it to the BMC; the AER register information of any PCIe device refers to the information recorded in the AER register of the PCIe device, and the AER register information includes at least the BDF information of the PCIe device; the PCIe device fault signal is generated and sent to the BIOS by one of the PCIe devices deployed on the server when a data processing error event is detected; The BMC is used to determine the target PCIe link based on the BDF information of the target PCIe device and the PCIe tree structure information; the target PCIe link refers to the shortest path in the PCIe tree structure from the root node to the terminal node that passes through the nodes represented by the BDF information of the target PCIe device. The BMC is also used to obtain AER register information of all PCIe devices on the target PCIe link, so as to locate the faulty PCIe device based on the obtained AER register information.

7. The server according to claim 6, characterized in that, The number of root nodes in the PCIe tree structure depends on the channel width of the PCIe interface configured for the server's central processing unit (CPU); the channel width refers to the number of channels used for data transmission. And / or, The target PCIe device is the PCIe device that generated the PCIe device fault signal; And / or, Obtaining AER register information of all PCIe devices on the target PCIe link through the BMC includes: obtaining BDF information of all PCIe devices on the target PCIe link from the PCIe tree structure information; for each obtained BDF information, obtaining AER register information from the configuration space of the corresponding PCIe device based on the AER register address of the BDF information through the PCI configuration access interface for direct access to the configuration space of the PCIe device; the AER register address corresponding to the BDF information is obtained from the configured AER register address-BDF information mapping relationship, wherein the AER register address refers to the address of the AER register in the configuration space of the PCIe device corresponding to the BDF information; and / or, The AER register information also includes correctable error records and / or uncorrectable error records; locating the faulty PCIe device based on the obtained AER register information includes: locating the faulty PCIe device from all PCIe devices on the target PCIe link based on the correctable error records and / or uncorrectable error records in the obtained AER register information.

8. An electronic device, characterized in that, include: processor; as well as A computer-readable storage medium storing computer program instructions that, when executed by the processor, cause the processor to perform the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, cause the processor to perform the steps of the method as described in any one of claims 1 to 5.

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