Decision feedback equalizer for double data rate memory

Abstract

A decision feedback equalizer for double data rate memory includes a sampling circuit for sampling target even bits and odd bits, outputting even bit data on an even bit path and odd bit data on an odd bit path; and an adder and parallel-to-serial conversion circuit coupled to the sampling circuit for receiving the even bit data and the odd bit data and combining full rate data.

Description

Technical Field

[0001] This case concerns an equalizer for the input / output terminals of a chip, specifically for use in dual data rate memory (DDR). Background Technology

[0002] As server / personal computer central processing units (CPUs) began to support high-speed dual data rate memory (such as fifth-generation dual data rate memory DDR5, or fifth-generation power-saving dual data rate memory LPDDR5, etc., hereinafter referred to as DDR), DDR began to be widely implemented in mobile devices. DDR is not only fast but also has large bandwidth, which can significantly improve system power, but it also brings challenges to the input / output (I / O) design of DDR.

[0003] DDR input / output (IO) terminals are typically equipped with equalizers. Compared to traditional equalization techniques such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) does not amplify signal noise and can effectively solve signal integrity problems caused by intersymbol interference (ISI).

[0004] However, traditional analog DFEs include heavily loaded adders, limiting the maximum transmission rate of DDR receivers. As for traditional digital DFEs, the adder circuitry has tight timing constraints, with critical path timing of only one unit interval (1UI), which is difficult to meet with 16nm process technology.

[0005] Improving DFE speed is an important issue in the DDR field. Summary of the Invention

[0006] The digital decision feedback equalizer (DFE) used in this case is applied to dual data rate memory (DDR) and features second-order half-rate speculation. This speculation function is also known as open-loop unrolled technology.

[0007] The DFE includes an initialization circuit (including adjustment of the read-to-read turn-around function), a selection circuit (used for DFE order selection, and even DDR mode selection), a sampling circuit, and an adder and a parallel-to-serial conversion circuit. In particular, the sampling circuit is placed before the adder, effectively gaining more time for critical timing paths (e.g., from 1UI to 2UI). DDR mode selection allows the system to support multiple DDR modes (e.g., DDR5 or LPDDR5). Additionally, this invention introduces a special control called read-to-read turn-around control, which supports various read-to-read turn-around combinations. This invention also enables high transmission rates to be achieved using common processes. For example, a 16nm process can achieve a transmission rate of 6400Mbps.

[0008] In one embodiment, the present invention implements a decision feedback equalizer (DFE) for a dual data rate memory (DDR), comprising: a sampling circuit that samples the target data into even-numbered bits and odd-numbered bits, outputs even-numbered bit data on the even-numbered bit path and outputs odd-numbered bit data on the odd-numbered bit path; and an adder and a parallel-to-serial conversion circuit coupled to the aforementioned sampling circuit to receive the aforementioned even-numbered bit data and the aforementioned odd-numbered bit data, and combine them to generate full-rate data.

[0009] The present disclosure is described in detail below with reference to specific embodiments and accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a decision feedback equalizer (DFE) 100 implemented according to one embodiment of the present invention;

[0011] Figure 2 This is a block diagram illustrating the functional blocks of the initialization circuit 102 according to one embodiment of this invention;

[0012] Figure 3 The implementation details of the initialization circuit 102 are illustrated according to one embodiment of this case;

[0013] Figure 4 The diagram illustrates the functional blocks of the selection circuit 104 according to one embodiment of this invention.

[0014] Figure 5 The details of the selection circuit 104 are illustrated according to one embodiment of this case;

[0015] Figure 6 This is a block diagram illustrating the functional blocks of the sampling circuit 106 according to one embodiment of this invention;

[0016] Figure 7 The details of the sampling circuit 106 are illustrated according to one embodiment of this case;

[0017] Figure 8 The implementation details of the adder and the parallel-to-serial conversion circuit 108 are illustrated according to one embodiment of this case; and

[0018] Figure 9 The diagram is a block diagram illustrating a dual data rate memory (DDR) 900 implemented according to one embodiment of this invention.

[0019] [Symbol Explanation]

[0020] 100: Decision Feedback Equalizer

[0021] 102: Initialization Circuit

[0022] 104: Selection Circuit

[0023] 106: Sampling Circuit

[0024] 108: Adders and Parallel-to-Serial Conversion Circuits

[0025] 202: Enable Initialization Circuit

[0026] 204: Read and Read Switching Initialization Circuit

[0027] 206, 606: Logic circuit combination

[0028] 208: Multitasking

[0029] 210, 212: Inverters

[0030] 214, 302, 304: D flip-flops

[0031] 216: With the door

[0032] 306: Asynchronous Counter

[0033] 402, 404: First and second selector circuits

[0034] 602: Even-numbered bit path sampling circuit

[0035] 604: Odd-bit Path Sampling Circuit

[0036] 802, 804, 808: Multitasking

[0037] 806: Delay Circuit

[0038] 810, 812, 814: Buffers

[0039] 900: Dual Data Rate Memory

[0040] 902: Receiver Circuit

[0041] DDRMODE: Mode selection signal

[0042] DFE0…DFE3: Sampling target

[0043] DFE_EN: DFE enable signal

[0044] CKON, CKOP, DFECLKN, DFECLKP: Sampling clock

[0045] DFE_TAP1 / DFE_TAP2, TAP1 / TAP2: First-order / second-order enable signals

[0046] Even0…Even3: Even-numbered data

[0047] EVENOUT: Even-numbered half-rate data

[0048] Init0T, InitB, InitNT: Relay signals

[0049] Initevent1, Initevent2, Initoddt2: First bit selection signal

[0050] Muxeven, Muxodd: Even-bit and odd-bit multitasking outputs

[0051] Muxeven_d, Muxeven_dd, Muxeven_ddN, Muxodd_d, Muxodd_dd, Muxodd_dN, Muxodd_ddN, Sel_dfemux, Sel_eyemux: signals

[0052] Odd0…Odd3: Odd-digit data

[0053] ODDOUT: Odd-bit half-rate data

[0054] R2RTRUNAROUND: Read and read switching signal

[0055] Sel_even1, Sel_even2: Selection signals for even-numbered paths

[0056] Sel_odd1, Sel_odd2: Selection signals for odd-numbered paths

[0057] ZI: Full Rate Data Detailed Implementation

[0058] The following description illustrates various embodiments of the present invention and introduces the basic concepts of the invention, but is not intended to limit the scope of the invention. The actual scope of the invention should be defined according to the scope of the patent application. The various functional blocks mentioned below can be implemented by a combination of hardware, software, and firmware, and may also include special circuits. The various functional blocks are not limited to being implemented separately, but can also be combined to share certain functions.

[0059] Figure 1 A decision feedback equalizer (DFE) 100, implemented according to one embodiment of this invention, can be used in a DDR receiver. It includes an initialization circuit 102, a selection circuit 104 (used for DFE order "TAP" selection, or even DDR mode selection), a sampling circuit 106, and an adder and parallel-to-serial conversion circuit 108. All circuits operate in the digital voltage power domain (DVDD power domain), with operating voltages lower than the activation voltage power domain (VPP power domain) of the signal received by the DDR.

[0060] The initialization circuit 102 includes four input signals DFE_EN, DFECLKP, DFECLKN, and R2RTURNAROUND, and three output signals Initevent1, Initevent2, and Initoddt2.

[0061] The signal R2RTURNAROUND is the adjustment signal for the read-to-read turn-around function, originating from a logic circuit (not shown in the diagram). When the sampling clocks DFECLKP / DFECLKN are continuous clocks, the signal R2RTURNAROUND is set to 1'b0. If the read-to-read turn-around function is enabled, the signal R2RTURNAROUND is set to 1'b1. The signal DFE_EN is the DFE enable signal, active high. The sampling clock DFECLKP is used for rising-edge sampling. The sampling clock DFECLKN is used for falling-edge sampling. The signals Initevent1, Initevent2, and Initoddt2 generated by the initialization circuit 102 are all fed into the selection circuit 104, where they are logically operated with the signals Muxeven and Muxodd to generate selection signals for even paths (Sel_even1, Sel_even2) and odd paths (Sel_odd1, Sel_odd2) to control the adder and the multiplexer in the parallel-to-serial conversion circuit 108.

[0062] As shown in the figure, the selection circuit 104 also receives six signals: DDRMODE, DFE_EN, DFE_TAP1, DFE_TAP2, DFECLKP, and DFECLKN. The DDRMODE signal is the mode selection signal: 1'b1 supports the DDR5 protocol; 1'b0 supports the LPDDR5 protocol. The DFE_TAP1 signal is a first-order enable signal, active high, used to consider the previous bit's condition when identifying the current bit. When the first-order DFE is insufficient to salvage the eye pattern, the second-order enable signal DFE_TAP2 becomes active high, considering the conditions of the previous two bits when identifying the current bit, effectively resolving misjudgments of 1 values ​​caused by a long 0 or a long 1. For example, a long 0 requires a more lenient 1 value judgment, using a lower reference value to accurately identify the 1 value. Similarly, a long 1 requires a more lenient 0 value judgment, using a higher reference value to accurately identify the 0 value.

[0063] The sampling circuit 106 includes nine input signals (DFE0, DFE1, DFE2, DFE3, DFE_EN, DFE_TAP1, DFE_TAP2, DFECLKP, DFECLKN) and generates eight output signals (Even0…Even3, and Odd0…Odd3). Signals DFE0…DFE3 are digital signals received and converted from the DDR, representing the content identified by different reference values ​​Vref, and are the sampling targets of the sampling circuit 106. Signals DFE0 and DFE1 are used to implement first-order DFE, while signals DFE2 and DFE3 further implement second-order DFE. Signals DFE0 and DFE2 are sampled by the sampling clock DFECLKP, outputting even-numbered bits of data Even0…Even3 (corresponding to data 0, 2, 4, 6…). Signals DFE1 and DFE3 are sampled by the sampling clock DFECLKN, outputting odd-numbered bits of data Odd0…Odd3 (corresponding to data 1, 3, 5, 7…).

[0064] First, let's discuss the first-order DFE. When signals DFE_EN = 1'b1, DFE_TAP2 = 1'b0, and DFE_TAP1 = 1'b1, the DFE is only in its first order. The sampling circuit 106 samples and obtains even-numbered data Even0 and Even1, and odd-numbered data Odd0 and Odd1. This odd-and-even-numbered data splitting achieves half-rate serial-to-parallel conversion. The even-numbered data Even0 and Even1 and the odd-numbered data Odd0 and Odd1 are separated into even-numbered paths and odd-numbered paths, respectively.

[0065] When switching to a second-order DFE, DFE_EN = 1'b1, DFE_TAP2 = 1'b1, and DFE_TAP1 = 1'bx. The sampling circuit 106 samples to obtain even-numbered data Even0…Even3 and odd-numbered data Odd0…Odd3. Through half-rate serial-to-parallel conversion, the even-numbered data Even0…Even3 and the odd-numbered data Odd0…Odd3 are separated into even-numbered paths and odd-numbered paths.

[0066] Even-numbered and odd-numbered data are sent to the adder and the parallel-to-serial conversion circuit 108 for further processing.

[0067] The adder and parallel-to-serial conversion circuit 108 receives sampling clocks DFECLKP and DFECLKN, as well as even-bit data Even0…Even3, odd-bit data Odd0…Odd3, even-bit path selection signals Sel_even1 and Sel_even2, and odd-bit path selection signals Sel_odd1 and Sel_odd2. Besides selecting data, the adder and parallel-to-serial conversion circuit 108 also performs parallel-to-serial conversion (2-to-1) of the output data, and buffers the sampling clocks DFECLKP / DFECLKN before outputting. The final output signal includes even-bit half-rate data EVENOUT, odd-bit half-rate data ODDOUT, full-rate data ZI, and sampling clocks CKOP / CKON. Sampling clock CKOP corresponds to even-bit half-rate data EVENOUT. Sampling clock CKON corresponds to odd-bit half-rate data ODDOUT.

[0068] The initialization circuit 102 generates selection signals Initevent1, Initevent2, and Initoddt2 for the first digit of the even-numbered path and the odd-numbered path under different circuit states (such as power-on, enable switching, or read-to-read switching) based on its four input signals DFE_EN, DFECLKP, DFECLKN, and R2RTURNAROUND.

[0069] Selection circuit 104 performs logical operations on each input signal to obtain selection signals for even-numbered paths (Sel_even1, Sel_even2) and selection signals for odd-numbered paths (Sel_odd1, Sel_odd2). Selection signals Sel_even1 and Sel_odd1 correspond to first-order DFEs. Selection signals Sel_even1 and Sel_odd1, in conjunction with Sel_even2 and Sel_odd2, select corresponding second-order DFEs.

[0070] The sampling circuit 106 samples the even-numbered bit paths according to the sampling clock DFECLKP and the odd-numbered bit paths according to the sampling clock DFECLKN. The sampling circuit 106 further determines the output signal of each sampled data channel based on the input signals DFE_TAP1 and DFE_TAP2. The sampling circuit 106 then splits the even-numbered and odd-numbered data into the even-numbered and odd-numbered bit paths, respectively.

[0071] The adder and parallel-to-serial conversion circuit 108 divides the data collected by the sampling circuit 106 into half-rate data (EVENOUT and ODDOUT) and full-rate data ZI based on the output of the selection circuit 104 and the sampling clocks DFECLKP and DFECLKN.

[0072] Since the sampling circuit 106 collects even-numbered data and odd-numbered data separately through even-numbered and odd-numbered paths and transmits them separately to the adder and the parallel-to-serial conversion circuit 108 for logic operations, half-rate data acquisition can be achieved, increasing the circuit's path timing from 1 unit time (1UI) to 2UI.

[0073] In sampling circuit 106, the sampling clock for even-numbered paths uses DFECLKP, and the sampling clock for odd-numbered paths uses DFECLKN. Inputs DFE_TAP1 and DFE_TAP2 are the first-order and second-order enable signals for DFE, respectively, which determine which channels the sampled data is output on.

[0074] Figure 2 The diagram illustrates the functional blocks of the initialization circuit 102 according to one embodiment of the present invention, including an enable initialization circuit 202, a read and read switching initialization circuit 204, and a logic circuit combination 206.

[0075] Taking DDR5 as an example, the initialization circuit 102 has two working states.

[0076] In the first operating state, the circuit is powered on or the signal DFE_EN switches from 1'b0 to 1'b1. During a read operation, the input R2RTRUNAROUND = 1'b0 enables the initialization circuit 202 to output a pulse signal Init0T with a period width of (1T)0. This pulse is then passed through multiplexer 208 and inverted by inverters 210 and 212, becoming signals Initevent2 and Initevent1, which are used as selection signals for the first data data0 of the even-numbered path (1st / 2nd order multiplexing). D flip-flop 214 further samples the signal Init0T according to the sampling clock DFECLKN, delays it by 1UI, and inverts it at the output. It becomes signal Initoddt2, serving as the selection signal for the first data (data1) of the odd-numbered path (applicable only to second order).

[0077] The second working state is that after power-on, the signal DFE_EN = 1'b1. At this time, the enabling initialization circuit 202 is enabled to make the signal Inti0T always output 1. If there is a read-to-read transition, the logic controller will make the signal R2RTRUNAROUND generate a pulse with a length of N time periods (NT, 6 < N < 12). Correspondingly, the relay signal InitNT generated by the read-to-read transition initialization circuit 204 outputs a zero-valued pulse with a width of 1 time period in the first cycle according to the sampling clock DFECLKP. The relay signals InitNT and Init0T are subjected to an "AND" operation by the "AND" logic 216 to obtain the relay signal InitB, which is then sent to the inverters 210 and 212 through the multiplexer 208 to be inverted and become Initevent2 and Initevent1, which are used as the selection signals (1st order / 2nd order multiplexing) for the first data bit data0 of the even-numbered path. The D flip-flop 214 further samples the signal IntiB according to the sampling clock DFECLKN, takes the inverse after a delay of 1UI, and outputs at the output end becomes the signal Initoddt2, which is used as the selection signal for the first data bit (data1) of the odd-numbered path (only applicable to the second order).

[0078] Figure 3 According to an embodiment of this case, the implementation details of the initialization circuit 102 are illustrated, in which the aforementioned enabling switching initialization circuit 202 is composed of two D flip-flops 302 and 304, and the aforementioned read-to-read switching initialization circuit 204 is composed of an asynchronous counter 306. The logic circuit combination 206 then implements the selection function, corresponding to power-on, enabling switching, and read-to-read switching, to generate the selection signals Initevent1, Initevent2, and Initoddt2 for the first digits of the even-numbered path and the odd-numbered path.

[0079] As shown in the figure, the D flip-flop 302 receives the sampling clock DFECLKN in the state where the D input pin receives the signal 1'b0. The D flip-flop 304 receives the sampling clock DFECLKP in the state where the D input pin receives the Q output of the D flip-flop 302, and outputs at a Q inverse output end the relay signal Init0T. The asynchronous counter 306 generates the relay signal InitNT according to the read-to-read transition signal R2RTRUNAROUND, the sampling clocks DFECLKP and DFECLKN. The logic circuit combination generates the selection signals (Initevent1, Initevent2, Initoddt2) for the first digits of the digital path and the odd-numbered path according to the aforementioned relay signal Init0T, the relay signal InitNT, and the sampling clock DFECLKN.

[0080] As shown in the figure, the logic circuit combination 206 further includes: an AND logic circuit that receives the aforementioned relay signals Init0T and InitNT to generate a three-relay signal InitB; a multiplexer; and a D flip-flop. The multiplexer receives the aforementioned relay signals Init0T and InitB, and under the control of the inverted signal of the read / read switching signal R2RTRUNAROUND, generates an output to the D input of the D flip-flop, causing the Q output of the D flip-flop to be inverted. The output signal is Initoddt2; and two inverters, each inverting the output of the aforementioned multiplexer, generate signals Initevent1 and Initevent2.

[0081] Figure 4 The diagram illustrates the function of the selection circuit 104 according to one embodiment of this invention, including a first selection sub-circuit 402 and a second selection sub-circuit 404. The first selection sub-circuit 402 is used in a first-order DFE and includes a DDR mode selection function. The second selection sub-circuit 404 is used in a second-order DFE and also includes a DDR mode selection function.

[0082] DDR mode can be either DDR5 or LPDDR5. The receiver (RX) of DDR typically has an on-chip termination (ODT) design. In DDR5, the ODT is power-coupled, so the bit preceding the valid bit is usually a high-order bit. In LPDDR5, the ODT is grounded, so the bit preceding the valid bit is usually a low-order bit.

[0083] The DDRmode signal indicates the DDR mode. DDRMODE = 1'b1 indicates DDR5 is being used. DDRMODE = 1'b0 indicates LPDDR5 is being used. In DDR5 mode, the on-chip pull-up signal level is set to high by default by the initialization circuit 102, typically lasting for one cycle. In LPDDR5 mode, the on-chip pull-down signal level is set to low by default by the initialization circuit 102, typically lasting for one cycle. Different DFE orders are set by the signals DFE_TAP1 and DFE_TAP2; the DFE operation order is usually set based on the data rate and the quality of the propagation channel, including the calibration procedure. Generally, first-order DFE operation is used first. After calibration, if the eye diagram meets the requirements, second-order DFE operation is not required to save power. Conversely, when the second-order DFE operation is initiated, the selection circuit 102 generates selection signals Sel_even1, Sel_even2, Sel_odd1, and Sel_odd2 to control the adder and the parallel-to-serial conversion circuit 108 to select appropriate signals from signals Even0…Even3 and Odd0…Odd3 and output them to the even-numbered bit path and the odd-numbered bit path.

[0084] Figure 5 The details of the selection circuit 104 are illustrated according to one embodiment of this invention. The following explanation uses a second-order DFE in DDR5 mode as an example to illustrate how the selection circuit 104 generates the selection signal.

[0085] Referring to the first selection sub-circuit 402, signals Muxeven and Muxodd are the outputs of the adder and parallel-to-serial conversion circuit 108. Signal Muxodd_d is obtained based on the sampling signal Muxodd sampled by the sampling clock DFECLKP. After adding signal Muxodd_d to signal initevent1, it is multiplied by signals DFE_TAP1 and DDRMODE to obtain the selection signal Sel_even1 for even-numbered paths. Signal Muxeven_d is obtained based on the sampling signal Muxeven sampled by the sampling clock DFECLKN. After delaying, signal Muxeven_d is multiplied by signals DFE_TAP1 and DDRMODE to obtain the selection signal Sel_odd1 for odd-numbered paths.

[0086] Referring to the second selection sub-circuit 404, signals Muxeven_d and Muxodd_d are input from the first selection sub-circuit 402. After sampling by the sampling clock DFECLKP, signal Muxeven_dd is obtained, which is added to signal initevent2, and then multiplied by signals DFE_TAP2 and DDRMODE to obtain the even-numbered path selection signal Sel_even2. After sampling by the sampling clock DFECLKN, signal Muxodd_dd is obtained, which is added to signal initoddt2, and then multiplied by signals DFE_TAP2 and DDRMODE to obtain the odd-numbered path selection signal Sel_odd2.

[0087] In summary, the selection circuit 104 includes generating selection signals Sel_even1 and Sel_even2 (Sel_even1 for first-order DFE, [Sel_even2, Sel_even1] for second-order DFE) based on the previous odd-numbered data (refer to the signal Muxodd provided by the adder and parallel-to-serial conversion circuit 108), and controlling the aforementioned adder and parallel-to-serial conversion circuit 108; and the selection circuit 104 also generates selection signals Sel_odd1 and Sel_odd2 (Sel_odd1 for first-order DFE, [Sel_odd2, Sel_odd1] for second-order DFE) based on the previous even-numbered data (refer to the signal Muxeven provided by the adder and parallel-to-serial conversion circuit 108), and controls the aforementioned adder and parallel-to-serial conversion circuit 108.

[0088] Regarding the even-numbered path selection signals [Sel_even2, Sel_even1] and the odd-numbered path selection signals [Sel_odd2, Sel_odd1], different combinations can cause the adder and the parallel-to-serial conversion circuit 108 to perform the following operations:

[0089] When 2'b00 is taken, Muxeven = Even0 (Muxodd = Odd0);

[0090] When 2'b01 is taken, Muxeven = Even1 (Muxodd = Odd1);

[0091] When 2'b10 is taken, Muxeven = Even2 (Muxodd = Odd2);

[0092] When 2'b11 is taken, Muxeven = Even3 (Muxodd = Odd3).

[0093] Figure 6 The block diagram illustrates the functional blocks of the sampling circuit 106 according to one embodiment of this invention. It includes an even-numbered-bit sampling circuit 602, an odd-numbered-bit sampling circuit 604, and a logic circuit combination 606 to realize the serial-to-parallel half-rate conversion of data.

[0094] Even-numbered path sampling circuit 602 samples even-numbered data (i.e., data0, data2, data4, etc.) according to sampling clock DFECLKP. Odd-numbered path sampling circuit 604 samples odd-numbered data (i.e., data1, data3, data5, etc.) according to sampling clock DFECLKN. Logic circuit combination 606 is used to control the sampling output. When signal TAP1 is valid, sampling circuit 106 only outputs even-numbered data Even0 and Even1, and odd-numbered data Odd0 and Odd1. When signal TAP2 is valid, sampling circuit 106 outputs even-numbered data Even0…Even3, and odd-numbered data Odd0…Odd3.

[0095] Figure 7 The sampling circuit 106, illustrated according to one embodiment of the present invention, includes eight D flip-flops and a logic circuit combination 606 for generating signals TAP1 and TAP2.

[0096] As shown in the figure, the even-bit path sampling circuit 602 includes four D flip-flops, which receive sampling targets DFE0…DFE3 respectively to generate even-bit data Even0…Even3. The reset signals of two of the D flip-flops are connected to the enable signal TAP1 of the first-order decision feedback equalization operation, and the reset signals of the other two D flip-flops are connected to the enable signal TAP2 of the second-order decision feedback equalization operation. Similarly, the odd-bit path sampling circuit 604 includes four D flip-flops, which receive sampling targets DFE0…DFE3 respectively to generate odd-bit data Odd0…Odd3. The reset signals of two of the D flip-flops are connected to the enable signal TAP1 of the first-order decision feedback equalization operation, and the reset signals of the other two D flip-flops are connected to the enable signal TAP2 of the second-order decision feedback equalization operation.

[0097] Figure 8 The implementation details of the adder and the parallel-to-serial conversion circuit 108 are illustrated according to one embodiment of this case.

[0098] When the first-order DFE is enabled, signals Sel_even2 and Sel_odd2 are 0. If the previous bit is 0, multiplexers 802 and 804 output signals Even0 and Odd0, respectively. If the previous bit is 1, multiplexers 802 and 804 output signals Even1 and Odd1, respectively.

[0099] When the second-order DFE is enabled, the control of multiplexers 802 and 804 is based on the values ​​of the first two bits. Even-numbered paths operate based on the selection signals [Sel_even2, Sel_even1]. Odd-numbered paths operate based on the selection signals [Sel_odd2, Sel_odd1]. When the value is 2'b00, multiplexers 802 and 804 output signals Even0 and Odd0, respectively. When the value is 2'b01, multiplexers 802 and 804 output signals Even1 and Odd1, respectively. When the value is 2'b10, multiplexers 802 and 804 output signals Even2 and Odd2, respectively. When the value is 2'b11, multiplexers 802 and 804 output signals Even3 and Odd3, respectively.

[0100] The sampling clock DFECLKN is delayed by at least 1UI by the delay circuit 806 to form the signal Sel_dfemux, which controls the multiplexer 808 to output the signal Muxeven (also known as the even-bit multiplexer output) or Muxodd (also known as the odd-bit multiplexer output), realizing the parallel-to-serial conversion (2-to-1). This data is then processed by the buffer 810 to become full-rate data ZI. The Muxeven signal can also be processed by the buffer 812 to become the half-rate output EVENOUT. The Muxodd signal is processed by the buffer 814 to become the half-rate output ODDOUT. Furthermore, the sampling clocks DFECLKP / DFECLKN are further processed by the buffer to become the sampling clocks CKOP / CKON.

[0101] Figure 9 This is a block diagram illustrating a dual data rate memory (DDR) 900 implemented according to one embodiment of this invention, wherein a receiver circuit 902 receives signals and generates signals DFE0 to DFE3, which are then processed by the aforementioned decision feedback equalizer 100. Any electronic device in which the DDR includes a decision feedback equalizer 100 with second-order half-rate functionality is within the scope of this invention.

[0102] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A decision feedback equalizer, applied to a dual data rate memory, comprising: A sampling circuit samples the target in even-numbered and odd-numbered positions, outputting even-numbered data on the even-numbered position path and odd-numbered data on the odd-numbered position path. An adder and a parallel-to-serial converter are coupled to the aforementioned sampling circuit to receive the aforementioned even-numbered bits of data and the aforementioned odd-numbered bits of data, and combine them to generate full-rate data; and A selection circuit generates a selection signal to control the multiplexer in the aforementioned adder and parallel-to-serial conversion circuit to sort the aforementioned even-numbered bit data and odd-numbered bit data into even-numbered half-rate data and odd-numbered half-rate data, and then combine them to form the aforementioned full-rate data. The selection circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit is used in the first-order decision feedback equalization operation and includes a DDR mode selection function. The second selection sub-circuit is used in the second-order decision feedback equalization operation and also includes a DDR mode selection function.

2. The decision feedback equalizer as described in claim 1, wherein: The aforementioned sampling circuit performs rising edge sampling according to a first sampling clock and falling edge sampling according to a second sampling clock to obtain the aforementioned even-numbered bits of data and the aforementioned odd-numbered bits of data.

3. The decision feedback equalizer as described in claim 2, wherein: The aforementioned adder and parallel-to-serial conversion circuit further organize the aforementioned first sampling clock into a third sampling clock corresponding to the aforementioned even-number half-rate data; and The aforementioned adder and parallel-to-serial conversion circuit further organizes the aforementioned second sampling clock into a fourth sampling clock corresponding to the aforementioned odd-bit half-rate data.

4. The decision feedback equalizer as described in claim 1, wherein: The aforementioned sampling circuit receives multiple sampling targets, which are the contents received by the aforementioned dual data rate memory and identified corresponding to different reference values; and For multiple sampling targets, the aforementioned sampling circuit samples multiple even-numbered data points and multiple odd-numbered data points.

5. The decision feedback equalizer as described in claim 4, wherein: The aforementioned selection circuit includes generating a selection signal for the even-numbered bit path based on the previously generated odd-numbered bit data, controlling the aforementioned adder and parallel-to-serial conversion circuit; and The aforementioned selection circuit includes generating a selection signal for the odd-numbered path based on the previous even-numbered bit data, and controlling the aforementioned adder and parallel-to-serial conversion circuit.

6. The decision feedback equalizer as described in claim 5, wherein: Based on the selection signal of the even-numbered path, the adder and the parallel-to-serial conversion circuit obtain an even-numbered multiplexer output of the even-numbered path from the multiple even-numbered data. Based on the aforementioned selection signal of the odd-numbered path, the aforementioned adder and parallel-to-serial conversion circuit obtain an odd-numbered multiplexer output of the odd-numbered path from the aforementioned multiple odd-numbered data. The aforementioned adder and parallel-to-serial conversion circuit take the outputs of the aforementioned even-bit multiplexer and the aforementioned odd-bit multiplexer, organize the aforementioned even-bit half-rate data and odd-bit half-rate data, and combine them to form the aforementioned full-rate data.

7. The decision feedback equalizer as described in claim 6, wherein: The aforementioned adder and parallel-to-serial conversion circuit further supply the output of the aforementioned odd-bit multiplexer to the aforementioned selection circuit as the previous odd-bit data; and The aforementioned adder and parallel-to-serial conversion circuit further supply the output of the aforementioned even-numbered bit multiplexer to the aforementioned selection circuit as the previous even-numbered bit data.

8. The decision feedback equalizer as described in claim 7, by default operates the aforementioned decision feedback equalizer to perform first-order decision feedback equalization operation, considers the previous position when identifying the current position, and switches the aforementioned decision feedback equalizer to perform second-order decision feedback equalization operation when the first-order decision feedback equalization operation cannot meet the eye diagram requirements, considers the previous two positions when identifying the current position.

9. The decision feedback equalizer as described in claim 8, wherein: The aforementioned sampling circuit receives four sampling targets, and samples four even-numbered data bits and four odd-numbered data bits.

10. The decision feedback equalizer as described in claim 9, wherein, The aforementioned sampling circuit includes: The four D flip-flops in the even-numbered paths receive the aforementioned four sampling targets to generate the aforementioned four even-numbered bits of data. The reset signals of two of the D flip-flops are connected to the enable signals of the first-order decision feedback equalization operation, and the reset signals of the other two D flip-flops are connected to the enable signals of the second-order decision feedback equalization operation. The four D flip-flops in the odd-numbered paths receive the aforementioned four sampling targets to generate the aforementioned four odd-numbered bit data. The reset signals of two of the D flip-flops are connected to the enable signals of the first-order decision feedback equalization operation, and the reset signals of the other two D flip-flops are connected to the enable signals of the second-order decision feedback equalization operation.

11. The decision feedback equalizer as described in claim 9, wherein: In the corresponding first-order decision feedback equalization operation, the aforementioned selection circuit provides a first even-numbered-bit path selection signal, which allows the aforementioned adder and parallel-to-serial conversion circuit to select the output of the aforementioned even-numbered-bit multiplexer from a zero even-numbered-bit data and a first even-numbered-bit data. In the corresponding first-order decision feedback equalization operation, the aforementioned selection circuit further provides a first odd-bit path selection signal, which allows the aforementioned adder and parallel-to-serial conversion circuit to select the output of the aforementioned odd-bit multiplexer from a zero odd-bit data and a first odd-bit data. In the corresponding second-order decision feedback equalization operation, the aforementioned selection circuit provides the aforementioned first even-numbered bit path selection signal and a second even-numbered bit path selection signal, for the aforementioned adder and parallel-to-serial conversion circuit to select the output of the aforementioned even-numbered bit multiplexer from the aforementioned zeroth even-numbered bit data, the aforementioned first even-numbered bit data, a second even-numbered bit data, and a third even-numbered bit data; and In the corresponding second-order decision feedback equalization operation, the aforementioned selection circuit provides the aforementioned first odd-bit path selection signal and a second odd-bit path selection signal, which are used by the aforementioned adder and parallel-to-serial conversion circuit to select the output of the aforementioned odd-bit multiplexer from the aforementioned zero odd-bit data, the aforementioned first odd-bit data, a second odd-bit data, and a third odd-bit data.

12. The decision feedback equalizer as described in claim 11, wherein, The aforementioned adder and parallel-to-serial conversion circuit includes: A first multiplexer, under the control of the aforementioned first even-numbered bit path selection signal and the second even-numbered bit path selection signal, outputs the aforementioned zero even-numbered bit data, the first even-numbered bit data, the second even-numbered bit data, or the third even-numbered bit data to form the aforementioned even-numbered bit multiplexer output; A second multiplexer, under the control of the aforementioned first odd-bit path selection signal and the second odd-bit path selection signal, outputs the aforementioned zero odd-bit data, first odd-bit data, second odd-bit data, or third odd-bit data to form the aforementioned odd-bit multiplexer output; A third multiplexer receives the outputs of the aforementioned even-numbered multiplexers and the outputs of the odd-numbered multiplexers to combine the aforementioned full-rate data.

13. The decision feedback equalizer as described in claim 7, wherein: The aforementioned selection circuit operates based on a mode selection signal; When the aforementioned mode selection signal is a first value, the aforementioned selection circuit is an on-chip terminal corresponding to the power supply of a first-type dual data rate memory, generating selection signals for even-numbered paths and selection signals for odd-numbered paths; and When the aforementioned mode selection signal is a second value, the aforementioned selection circuit is an on-chip terminal corresponding to a second type dual data rate memory grounded, generating selection signals for even-numbered paths and selection signals for odd-numbered paths.

14. The decision feedback equalizer as described in claim 11, wherein, The first selection sub-circuit operates according to the aforementioned odd-bit multiplexer output, the aforementioned even-bit multiplexer output, the enable signal of the first-order decision feedback equalization operation, and a mode selection signal, generating a first even-bit path selection signal and a first odd-bit path selection signal for the aforementioned adder and parallel-to-serial conversion circuit to operate.

15. The decision feedback equalizer as described in claim 14, wherein, The second selection sub-circuit operates according to the aforementioned odd-bit multiplexer output, the aforementioned even-bit multiplexer output, the enable signal of the second-order decision feedback equalization operation, and the aforementioned mode selection signal, generating a second even-bit path selection signal and a second odd-bit path selection signal for the aforementioned adder and parallel-to-serial conversion circuit to operate.

16. The decision feedback equalizer as described in claim 2, further comprising: An initialization circuit, corresponding to power-on, enable switching, and read-to-read switching, provides the first bit selection signal for even-numbered and odd-numbered paths, which is passed to the aforementioned selection circuit to generate selection signals for even-numbered and odd-numbered paths.

17. The decision feedback equalizer as described in claim 16, further comprising: A first D flip-flop receives the aforementioned second sampling clock when the D input pin receives signal 1'b0; A second D flip-flop, in the state that the Q output of the aforementioned first D flip-flop is received at the D input pin, receives the aforementioned first sampling clock, and outputs a first relay signal at a Q inverting output terminal; An asynchronous counter generates a second relay signal based on a read-to-read switching signal, the aforementioned first sampling clock, and the aforementioned second sampling clock; as well as A logic circuit combination generates a first bit selection signal for the digital path and the odd-numbered path based on the aforementioned first relay signal, second relay signal, and second sampling clock, and passes it to the aforementioned selection circuit to generate a selection signal for the even-numbered path and a selection signal for the odd-numbered path.

18. The decision feedback equalizer as described in claim 17, wherein, The aforementioned logic circuit combination also includes: A logic is used to receive the aforementioned first relay signal and second relay signal, and generate a third relay signal; A multiplexer and a third D flip-flop, wherein the multiplexer receives the first relay signal and the third relay signal, and under the control of the inverted signal of the read and read switching signal, generates an output to the D input terminal of the third D flip-flop, causing the inverted Q output terminal of the third D flip-flop to output the first digit selection signal; and Two inverters each invert the output of the aforementioned multiplexer to form the aforementioned first digit selection signal.

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