Voltage control method, device and storage medium

Abstract

Embodiments of the present application provide a voltage control method and device and storage medium, which are applied to the technical field of terminals. The method is applied to an electronic device with a pixel circuit, the pixel circuit comprising a driving module, a control end of the driving module being connected with a first node, and a source end of the driving module being connected with a second node. The method comprises: when driving a first region to display a first frame of image, controlling the voltage of the first node to be a first voltage and the voltage of the second node to be a second voltage; when driving a second region to display the first frame of image, controlling the voltage of the first node to be a third voltage and the voltage of the second node to be a fourth voltage; wherein the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first region is a first refresh rate, and the refresh rate of the second region is a second refresh rate, the first refresh rate being lower than the second refresh rate. In this way, the occurrence probability of flicker of the display panel of the electronic device can be reduced.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to voltage control methods, devices and storage media. Background Technology

[0002] With the development of terminal technology, electronic devices now offer the ability to display dynamic images in one area of ​​the display panel and static images in other areas. To reduce power consumption, the refresh rate of the static image display area is lower than that of the dynamic image display area.

[0003] However, when the static image display area switches to display a dynamic image, or vice versa, the display panel of the electronic device may flicker. Summary of the Invention

[0004] This application provides a voltage control method, device, and storage medium, applied in the field of terminal technology. Since dynamic images may be refreshed at a high refresh rate during display, and static images may be refreshed at a low refresh rate during display, by controlling the gate voltage of the driving thin-film transistors in the pixel circuit, the difference between the gate voltage of the driving thin-film transistors during the light-emitting phase when displaying images at a low refresh rate and the gate voltage of the driving thin-film transistors during the light-emitting phase when displaying images at a high refresh rate can be reduced. This can reduce the brightness difference between the static image display area and the dynamic image display area within the display panel, thereby reducing the probability of display panel flickering when the display area refresh rate switches.

[0005] In a first aspect, embodiments of this application propose a voltage control method applied to an electronic device having a pixel circuit. The pixel circuit includes a driving module, the control terminal of which is connected to a first node, and the source terminal of which is connected to a second node. The method includes:

[0006] When driving the display of the first region of the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage;

[0007] When driving the display of the second region of the first frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage;

[0008] Among them, the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first region is the first refresh rate, the refresh rate of the second region is the second refresh rate, and the first refresh rate is lower than the second refresh rate.

[0009] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region.

[0010] In one possible implementation, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0011] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region.

[0012] In one possible implementation, the pixel circuit further includes a data writing unit connected to the second node; the data writing unit is enabled when displaying the first and second regions of the first frame image; the method further includes:

[0013] When driving the display of the first area of ​​the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; when displaying the first area of ​​the second frame image, the data writing unit is disabled;

[0014] When driving the display of the second region of the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second region of the second frame image, the data writing unit is enabled.

[0015] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region.

[0016] In one possible implementation, the method also includes:

[0017] When driving the display of the first area of ​​the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; when displaying the first area of ​​the third frame image, the data writing unit is disabled.

[0018] When driving the display of the second area of ​​the third frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the third frame image, the data writing unit is enabled.

[0019] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region.

[0020] In one possible implementation, the method also includes:

[0021] When driving the display of the first area of ​​the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the first area of ​​the fourth frame image, the data writing unit is disabled.

[0022] When driving the display of the second area of ​​the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second area of ​​the fourth frame image, the data writing unit is enabled.

[0023] This reduces the power consumption of electronic devices when they are driving the display of images.

[0024] In one possible implementation, the pixel circuit further includes a data writing unit connected to the second node; the data writing unit is enabled when displaying the first and second regions of the first frame image; the method further includes:

[0025] When driving the display of the first area of ​​the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the first area of ​​the second frame image, the data writing unit is disabled;

[0026] When driving the display of the second region of the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second region of the second frame image, the data writing unit is enabled.

[0027] This reduces the power consumption of electronic devices when they are driving the display of images.

[0028] In one possible implementation, the method also includes:

[0029] Based on the identifier of the pixel circuit corresponding to the first region, the start and end positions of the first region are determined.

[0030] Based on the identifier of the pixel circuit corresponding to the second region, the start and end positions of the second region are determined.

[0031] This improves the accuracy and completeness of image display when electronic devices drive the display of images.

[0032] In one possible implementation, the method also includes:

[0033] When driving the display of the third region of the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third region is the third refresh rate, which is lower than the second refresh rate.

[0034] This allows for multi-area display of images, enhancing the user experience of electronic devices.

[0035] In one possible implementation, the driving module includes a driving thin-film transistor (DTFT), the drain of which is connected to a third node, and the DTFT is used to output current to the third node under the control of the first node.

[0036] The pixel circuit also includes:

[0037] A first reset unit, connected to a first node, is used to apply a first initialization voltage to the first node in response to a first reset signal;

[0038] The storage capacitor has one end connected to the first node and the other end connected to the positive terminal of the power supply.

[0039] The first light-emitting control unit is connected to the positive terminal of the power supply and the second node, and is used to apply the first power supply voltage from the positive terminal of the power supply to the second node in response to the light-emitting control signal.

[0040] A threshold compensation unit, connecting the first node and the third node, is used to enable the third node to conduct with the first node in response to the first scan signal.

[0041] The second light-emitting control unit is connected to the third node and the fourth node, and is used to make the third node and the fourth node conduct in response to the light-emitting control signal.

[0042] The light-emitting element is connected to the fourth node at one end and to the negative terminal of the power supply at the other end to apply the second power supply voltage to the negative terminal of the power supply.

[0043] The second reset unit, connected to the fourth node, is used to apply a second initialization voltage to the fourth node in response to a second reset signal;

[0044] The data writing unit is connected to the second node and is used to load data voltage to the second node in response to the second scan signal.

[0045] The third reset unit, connected to the second node, is used to apply a third initialization voltage to the second node in response to the second reset signal.

[0046] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region, thereby reducing the probability of flickering on the display panel of the electronic device.

[0047] In one possible implementation, the first reset unit includes a first reset transistor, the first light-emitting control unit includes a first light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light-emitting control unit includes a second light-emitting control transistor, the light-emitting element includes an organic light-emitting diode (OLED), the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

[0048] In this way, when the electronic device drives the display image, the voltage difference between the first node and the second node of the driving module corresponding to the first region can be reduced, as well as the difference between the voltage difference between the first node and the second node of the driving module corresponding to the second region, thereby reducing the probability of flickering on the display panel of the electronic device.

[0049] In a second aspect, embodiments of this application provide an electronic device, including: a processor, a display driver chip DDIC, a pixel circuit, and a memory;

[0050] The memory stores the instructions that the computer executes;

[0051] The processor indicates that the display driver chip drives the pixel circuit;

[0052] The display driver chip executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in the first aspect and drive the pixel circuit.

[0053] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program. When the computer program is executed by the display driver chip DDIC, it implements the method as described in the first aspect.

[0054] Fourthly, embodiments of this application provide a computer program product, which includes a computer program that, when run, causes a computer to perform the method as described in the first aspect.

[0055] Fifthly, embodiments of this application provide a chip, the chip including a processor, the processor being configured to invoke a computer program in memory to execute the method as described in the first aspect.

[0056] It should be understood that the second to fifth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0058] Figure 2Pixel circuit diagram provided for embodiments of this application Figure 1 ;

[0059] Figure 3 Level timing diagram of each signal provided in the embodiments of this application Figure 1 ;

[0060] Figure 4 A comparison diagram of the number of times transistor T4 is enabled in the high-frequency display area and the low-frequency display area when the electronic device refreshes an image according to an embodiment of this application;

[0061] Figure 5 The timing diagrams of the low-frequency display area corresponding to each signal and the schematic diagrams of each initialization voltage provided in the embodiments of this application are as follows: Figure 1 ;

[0062] Figure 6 The following diagrams illustrate the level timing of each signal and the initialization voltage of each signal in the high-frequency display area provided in this embodiment of the application.

[0063] Figure 7 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 1 ;

[0064] Figure 8 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 2 ;

[0065] Figure 9 The timing diagrams of the low-frequency display area corresponding to each signal and the schematic diagrams of each initialization voltage provided in the embodiments of this application are as follows: Figure 2 ;

[0066] Figure 10 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 3 ;

[0067] Figure 11 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 4 ;

[0068] Figure 12 The timing diagrams of the low-frequency display area corresponding to each signal and the schematic diagrams of each initialization voltage provided in the embodiments of this application are as follows: Figure 3 ;

[0069] Figure 13 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 5 ;

[0070] Figure 14 Timing of bias voltage when refreshing image in electronic devices provided in embodiments of this application Figure 6 ;

[0071] Figure 15 Pixel circuit diagram provided for embodiments of this application Figure 2 ;

[0072] Figure 16 This is a schematic diagram of the structure of the electronic device 100 provided in the embodiments of this application;

[0073] Figure 17 A software structure block diagram of the electronic device 100 provided in the embodiments of this application. Detailed Implementation

[0074] To facilitate a clear description of the technical solutions in the embodiments of this application, some terms and technologies involved in the embodiments of this application will be briefly introduced below:

[0075] 1. Some terms

[0076] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with substantially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order of execution. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0077] It should be noted that, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0078] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, and c can be single or multiple.

[0079] It should be noted that the phrase "at...time" in the embodiments of this application can refer to the instant at which a certain situation occurs, or to a period of time after the occurrence of a certain situation; the embodiments of this application do not specifically limit this. Furthermore, the display interface provided in the embodiments of this application is merely an example, and the display interface may include more or less content.

[0080] 2. Electronic equipment

[0081] The electronic devices in this application embodiment may include handheld devices with image processing functions, vehicle-mounted devices, etc. For example, some electronic devices include: mobile phones, tablets, PDAs, laptops, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, or future evolution of public land mobile communication networks. Terminal devices in a network (PLMN), etc., are not limited to this in the embodiments of this application.

[0082] By way of example and not limitation, in this embodiment, the electronic device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as hearing aids, glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0083] Furthermore, in this embodiment of the application, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0084] The electronic devices in the embodiments of this application may also be referred to as: user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device, etc.

[0085] In this embodiment, the electronic device or various network devices include a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as Linux, Unix, Android, iOS, or Windows. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0086] In one possible implementation, the electronic device includes a display panel. Figure 1 A schematic diagram of the display panel structure is shown. (See diagram below.) Figure 1As shown, the display panel includes a light emission control signal generation unit, a first reset signal generation unit, a second scan signal generation unit, a display area for displaying images, a second scan signal generation unit, a first scan signal generation unit, a second reset signal generation unit, and a display driver integrated circuit (DDIC). The display area includes an array of multiple pixel circuits. The light emission control signal generation unit, the first reset signal generation unit, the second scan signal generation unit, the display area for displaying images, the second scan signal generation unit, the first scan signal generation unit, the second reset signal generation unit, and the display driver chip can all transmit their corresponding signals to their respective pixel circuits via leads. The display driver chip can control the transmission of the corresponding signals from the light emission control signal generation unit, the first reset signal generation unit, the second scan signal generation unit, the display area for displaying images, the second scan signal generation unit, the first scan signal generation unit, and the second reset signal generation unit. The pixel circuit includes a driving thin-film transistor and a light-emitting element. The driving thin-film transistor drives the light-emitting element to emit light. The light-emitting element can serve as a sub-pixel of the display panel. By driving and controlling the corresponding pixel circuits in the display area, the electronic device achieves the function of displaying dynamic and static images on the display panel.

[0087] The display area can include a high-frequency display area and a low-frequency display area. The high-frequency display area refreshes the image at a high refresh rate. The low-frequency display area refreshes the image at a low refresh rate. When displaying dynamic images, the image may be refreshed at a high refresh rate. When displaying static images, the image may be refreshed at a low refresh rate. In possible implementations, under the same data voltage, the brightness of the display area at a low refresh rate differs from that at a high refresh rate. When the refresh rate of the display area switches from low to high, or vice versa, the display area experiencing the refresh rate switch will flicker, and the display panel of the electronic device will also flicker.

[0088] In view of this, embodiments of this application provide a voltage control method that reduces the difference between the gate voltage of the driving thin-film transistor during low-frequency display and the gate voltage of the driving thin-film transistor during high-frequency display by controlling the gate voltage of the driving thin-film transistor. This can reduce the brightness difference between the high and low frequency display areas in the display panel and thus reduce the probability of display panel flickering when the display area refresh rate is switched.

[0089] The voltage control method provided in this application will be described below with reference to some embodiments.

[0090] Figure 2 Pixel circuit diagram provided for embodiments of this application Figure 1 .like Figure 2 As shown, the pixel circuit includes multiple thin-film transistors (TFTs), a capacitor C1, and a light-emitting element. The light-emitting element may include an organic light-emitting diode (OLED).

[0091] In the embodiments of this application, thin-film transistors may be simply referred to as transistors or TFT transistors.

[0092] Multiple thin-film transistors, for example Figure 2 Transistors T1, T2, T3, T4, T5, T6, T7, and T8 are shown.

[0093] In this design, transistor T3 is a driving thin-film transistor (DTFT) that drives the light-emitting element to emit light. Transistor T2 is a compensation transistor that controls the charging of capacitor C1 and the conduction of transistor T3. Transistors T1 and T2 may include oxide transistors. Other transistors may include transistors using low-temperature poly-silicon (LTPS) technology.

[0094] like Figure 2 As shown, transistor T1, connected to the first node N1, is used to apply a first initialization voltage to the first node N1 in response to a first reset signal. The first reset signal can be referred to as ResetN. The first initialization voltage can be referred to as Vinit1.

[0095] Capacitor C1 is connected at one end to the first node N1 and at the other end to the positive terminal VDD of the power supply. The first node N1 can be referred to as node N1 or point N1.

[0096] Transistor T5, connected to the positive terminal VDD and the second node N2, is used to apply a first power supply voltage from the positive terminal VDD to the second node N2 in response to an illumination control signal. The illumination control signal can be referred to as EM. The second node N2 can be referred to as node N2 or point N2.

[0097] Transistor T3 is connected to the first node N1, the second node N2, and the third node N3, and is used to output current to the third node N3 under the control of the first node N1. The third node N3 can be called node N3 or point N3.

[0098] Transistor T2, connected to the first node N1 and the third node N3, is used to turn on the third node N3 and the first node N1 in response to the first scan signal. The first scan signal can be called Gate N.

[0099] Transistor T6 connects the third node N3 and the fourth node N4, and is used to turn on the third node N3 and the fourth node N4 in response to the light emission control signal.

[0100] The light-emitting element is connected at one end to the fourth node N4 and at the other end to the negative terminal VSS of the power supply to apply the second power supply voltage to the negative terminal VSS.

[0101] Transistor T7, connected to the fourth node N4, is used to apply a second initialization voltage to the fourth node N4 in response to a second reset signal. The second reset signal can be referred to as ResetP. The second initialization voltage can be referred to as Vinit2.

[0102] Transistor T4, connected to the second node N2, is used to apply a data voltage to the second node N2 in response to the second scan signal. The second scan signal can be referred to as GateP. The data voltage can be referred to as Vdata.

[0103] Transistor T8, connected to the second node N2, is used to apply a third initialization voltage to the second node N2 in response to the second reset signal. This third initialization voltage can be referred to as Vinit3.

[0104] In this embodiment, the "on" state of a transistor refers to the state where the source and drain of the transistor are electrically connected. The "off" state of a transistor refers to the state where the source and drain of the transistor are electrically disconnected. It can be understood that leakage current can still exist when the transistor is off. The conduction condition for transistors T1 and T2 is: Vgs > Vth. The conduction condition for the remaining transistors is: Vgs < Vth. The high level in this embodiment can satisfy the conduction condition for transistors T1 and T2, and the low level in this embodiment can satisfy the conduction condition for the remaining transistors. Transistor T4 is turned on and loads a data voltage to the second node N2, which can be called transistor T4 being enabled. Transistor T4 is not turned on or is in the off state and does not load a data voltage to the second node N2, which can be called transistor T4 being disabled. Transistor T2 is turned on, which can be called transistor T2 being enabled. Transistor T2 is not turned on or is in the off state, which can be called transistor T2 being disabled. When transistor T1 is turned on, it can be said that transistor T1 is enabled. When transistor T1 is not turned on or is in the off state, it can be said that transistor T1 is disabled.

[0105] When an electronic device refreshes a frame of image for display on a display panel, it can drive and control the pixel circuit in either a row-driven or column-driven manner; the principles are similar. The following explanation uses the row-driven method for driving and controlling the pixel circuit as an example.

[0106] Each time an electronic device refreshes a frame of an image, the operation of the pixel circuit can include a reset phase, a write phase, a light-emitting wait phase, and a light-emitting phase.

[0107] Figure 3 Level timing diagram of each signal provided in the embodiments of this application Figure 1 The following is combined with Figure 2 and Figure 3 This paper explains the various stages of pixel circuit operation when an electronic device refreshes a frame of an image.

[0108] When an electronic device refreshes a frame of an image, if transistors T1, T4 and T2 are enabled, the various stages of operation of the pixel circuit corresponding to the display area of ​​this frame of the image are as follows (1.1)-(1.4).

[0109] (1.1) Reset phase:

[0110] The light emission control signal (EM) is high. Transistors T5 and T6 are in the off state.

[0111] The first reset signal (ResetN) changes from low to high. The high level of the first reset signal turns on transistor T1.

[0112] The second reset signal (ResetP) changes from high to low and then back to high. The low-level start time of the second reset signal (ResetP) is earlier than the high-level start time of the first reset signal (ResetN). The low level of the second reset signal turns on transistors T8 and T7.

[0113] The first scan signal (GateN) changes from high to low and then back to high. The start and end times of the low level both fall within the high-level period of the first reset signal. The high level of the first scan signal turns on transistor T2, thereby turning on nodes N1 and N3.

[0114] The second scan signal (GateP) is high. Transistor T4 is in the off state.

[0115] The conducting transistor T1 applies the first initialization voltage Vinit1 to point N1, resetting point N1 and clearing the potential written in the previous frame. This also applies the first initialization voltage Vinit1 to capacitor C1. The conducting transistor T2 also applies the first initialization voltage Vinit1 to point N3, resetting point N3 and clearing any residual signals that may exist from the previous stage.

[0116] The conducting transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the initial state voltage Vinit3 to point N2. At this time, the gate-source voltage difference Vgs of transistor T3 is the voltage difference between points N1 and N2, that is, Vgs is the voltage difference between Vinit1 and Vinit3. At this time, Vgs is greater than the threshold voltage Vth of transistor T3, causing transistor T3 to not conduct.

[0117] The conducting transistor T7 applies the second initialization voltage Vinit2 to point N4, writing the initial state voltage Vinit2 to point N4.

[0118] (1.2) Writing phase:

[0119] The light emission control signal (EM) remains high. Transistors T5 and T6 are in the off state.

[0120] The first reset signal (ResetN) changes from high level to low level, causing transistor T1 to be in the off state.

[0121] The second reset signal (ResetP) remains high. Transistors T8 and T7 are both in the off state.

[0122] The first scan signal (GateN) remains high. The high level of the first scan signal (GateN) turns on transistor T2, which in turn turns on N1 and N3.

[0123] The second scan signal (GateP) changes from high to low, and then from low to high. The low level of the second scan signal (GateP) turns on transistor T4. The turned-on transistor T4 applies the data voltage Vdata to node N2. Since capacitor C1 can discharge to transistor T3, transistor T3 is turned on. Therefore, the turned-on transistor T4 can feed the data voltage Vdata back to N1 through transistors T3 and T2, and charge capacitor C1. The voltage at point N1 is Vdata + Vth, where Vth is the threshold voltage of transistor T3. When transistor T4 is on, the voltage at point N2 is Vdata.

[0124] (1.3) Luminescence waiting stage:

[0125] The light emission control signal (EM) remains high. Transistors T5 and T6 are in the off state.

[0126] The first reset signal (ResetN) remains low, and transistor T1 is in the off state.

[0127] The second reset signal (ResetP) changes from high to low, and then from low to high. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns off both transistors T8 and T7.

[0128] The first scan signal (GateN) is low, causing transistor T2 to be in the off state.

[0129] The second scan signal (GateP) remains high. Transistor T4 is in the off state.

[0130] The conducting transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the initial state voltage Vinit3 to point N2.

[0131] The conducting transistor T7 applies the second initialization voltage Vinit2 to point N4, writing the initial state voltage Vinit2 to point N4. This allows the light-emitting element to be reset before it emits light, thereby reducing the impact of any residual signals from the previous stage on the light-emitting element's emission.

[0132] Capacitor C1 can discharge transistor T3. When the gate-source voltage difference of transistor T3 is greater than the threshold voltage Vth of transistor T3, transistor T3 will not conduct.

[0133] (1.4) Luminescence stage:

[0134] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0135] The light emission control signal (EM) changes from high to low. The low level of the light emission control signal turns on transistors T5 and T6. The first power supply voltage (VDD) is written to node N2, and Vgs of transistor T3 is less than Vth, so transistor T3 turns on.

[0136] The first reset signal (ResetN) remains low. Transistor T1 is in the off state.

[0137] The second reset signal (ResetP) remains high. Transistors T7 and T8 are in the off state.

[0138] The first scan signal (GateN) remains low. Transistor T2 is in the off state.

[0139] The second scan signal (GateP) remains high. Transistor T4 is in the off state.

[0140] Transistor T5, which is conducting, applies the first power supply voltage (positive terminal) to point N2. Transistor T3 then conducts. Transistor T6, which is also conducting, conducts at points N3 and N4. A second power supply voltage (negative terminal) is applied to one end of the light-emitting element. The light-emitting element then begins to emit light.

[0141] When the light-emitting element emits light, transistor T3 divides the voltage, thus controlling the brightness of the light-emitting element. The voltage division of transistor T3 is affected by the gate voltage of transistor T3, i.e., the N1 voltage. For example, the greater the gate-source voltage difference of transistor T3, the smaller the current flowing through transistor T3. Since the light-emitting element is connected in series with transistor T3, the current flowing through the light-emitting element is also smaller, resulting in lower brightness of the light-emitting element.

[0142] When an electronic device refreshes a frame of an image, if transistors T1, T4, and T2 are not enabled, the operation stages of the pixel circuit corresponding to the display area of ​​this frame of the image are as follows (2.1)-(2.4).

[0143] (2.1) Reset phase:

[0144] The light emission control signal (EM) is high. Transistors T5 and T6 are in the off state.

[0145] The first reset signal (ResetN) remains low. Transistor T1 remains off.

[0146] The second reset signal (ResetP) changes from high to low, and then from low to high. Similar to the reset phase shown in (1.1), the low level of the second reset signal turns on transistors T8 and T7. The turned-on transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the third initialization voltage Vinit3 to point N2. The turned-on transistor T7 applies the second initialization voltage Vinit2 to point N4, writing the initial state voltage Vinit2 to point N4.

[0147] The first scan signal (GateN) remains low. Transistor T2 is in the off state.

[0148] The second scan signal (GateP) is high. Transistor T4 remains off.

[0149] Capacitor C1 can discharge to transistor T3, putting transistor T3 in the off state. The gate voltage of transistor T3 is the voltage at point N1.

[0150] (2.2) Writing phase:

[0151] The light emission control signal (EM) remains high. Transistors T5 and T6 are in the off state.

[0152] The first reset signal (ResetN) remains low. Transistor T1 is in the off state.

[0153] The second reset signal (ResetP) remains high. Transistors T7 and T8 are in the off state.

[0154] The first scan signal (GateN) remains low. Transistor T2 is in the off state.

[0155] The second scan signal (GateP) remains high. Transistor T4 is in the off state.

[0156] Capacitor C1 can discharge to transistor T3, putting transistor T3 in the off state. The gate voltage of transistor T3 is the voltage at point N1.

[0157] (2.3) Luminescence waiting stage:

[0158] The light emission control signal (EM) remains high. Transistors T5 and T6 are in the off state.

[0159] The first reset signal (ResetN) remains low, and transistor T1 is in the off state.

[0160] The second reset signal (ResetP) changes from high to low, and then from low to high. The low level of the second reset signal turns on transistors T8 and T7. The high level of the second reset signal turns off both transistors T8 and T7.

[0161] The first scan signal (GateN) remains low. Transistor T2 is in the off state.

[0162] The second scan signal (GateP) remains high. Transistor T4 is in the off state.

[0163] The conducting transistor T8 applies the third initialization voltage Vinit3 to point N2, writing the initial state voltage Vinit3 to point N2.

[0164] The conducting transistor T7 applies the second initialization voltage Vinit2 to point N4, writing the initial state voltage Vinit2 to point N4. This allows the light-emitting element to be reset before it emits light, thereby reducing the impact of any residual signals from the previous stage on the light-emitting element's emission.

[0165] Capacitor C1 discharges transistor T3, putting transistor T3 in the off state. The gate voltage of transistor T3 is the voltage at point N1.

[0166] (2.4) Luminescence stage:

[0167] Capacitor C1 can maintain the N1 voltage of transistor T3.

[0168] The light emission control signal (EM) changes from high to low. The low level of the light emission control signal turns on transistors T5 and T6. The first power supply voltage (VDD) is written to node N2, and Vgs of transistor T3 is less than Vth, so transistor T3 turns on.

[0169] The first reset signal (ResetN) remains low. Transistor T1 remains off.

[0170] The second reset signal (ResetP) remains high. Transistors T7 and T8 are in the off state.

[0171] The first scan signal (GateN) remains low. Transistor T2 is in the off state.

[0172] The second scan signal (GateP) remains high. Transistor T4 is in the off state.

[0173] Transistor T5, which is conducting, applies the first power supply voltage (positive terminal) to point N2. Transistor T3 then conducts. Transistor T6, which is also conducting, conducts at points N3 and N4. A second power supply voltage (negative terminal) is applied to one end of the light-emitting element. The light-emitting element then begins to emit light.

[0174] When the light-emitting element emits light, transistor T3 divides the voltage, thus controlling the brightness of the light-emitting element. The voltage division of transistor T3 is influenced by the voltage at point N1 maintained by capacitor C1. The voltage at point N1 is affected by the potential of capacitor C1. The potential of capacitor C1 is the remaining potential after capacitor C1 has discharged at the end of the previous stage. For example, the smaller the voltage at point N1, the smaller the gate-source voltage difference of transistor T3, the larger the current flowing through transistor T3. Since the light-emitting element is connected in series with transistor T3, the current flowing through the light-emitting element is also larger, resulting in higher brightness of the light-emitting element.

[0175] As can be seen from the above, when an electronic device refreshes a frame of image, if transistors T1, T4, and T2 corresponding to the display area are enabled, then capacitor C1 corresponding to that display area will be charged during the reset phase.

[0176] When an electronic device refreshes a frame of image, if transistors T1, T4, and T2 corresponding to the display area are disabled, the potential of capacitor C1 corresponding to that display area will continuously maintain the gate voltage of transistor T3 during the reset, write, and light-emitting phases. Alternatively, the potential of capacitor C1 corresponding to that display area will continuously be in a discharging state during the reset, write, and light-emitting phases, without being charged. The initial voltage of capacitor C1 corresponding to that display area is the voltage remaining after the previous frame's discharge.

[0177] Typically, when electronic devices refresh images, the refresh rate of high-frequency display areas is higher than that of low-frequency display areas.

[0178] For ease of understanding, this application embodiment uses a refresh rate of 10Hz for the low-frequency display area and 120Hz for the high-frequency display area as an example for illustration.

[0179] The refresh rate can be defined as the number of times transistors T1, T4, and T2 are enabled per unit time when an electronic device refreshes an image. A higher refresh rate means that transistors T1, T4, and T2 are enabled more frequently. Therefore, within the same time period, transistors T1, T4, and T2 are enabled more times in high-frequency display areas than in low-frequency display areas.

[0180] Figure 4 This diagram shows a comparison of the number of times transistors T4 and T2 are enabled in the high-frequency display area and the low-frequency display area when an electronic device refreshes an image within 1 second. The low-frequency display area is shown below. Figure 4 The first area is shown. The high-frequency display area is as follows: Figure 4 The second area is shown. The refresh rate of the low-frequency display area or the first area is 120Hz. The refresh rate of the high-frequency display area or the second area is 10Hz.

[0181] from Figure 2 and Figure 3 It can be seen that when an electronic device refreshes one frame of an image, transistors T1, T4, and T2 are enabled once or zero times. For example... Figure 4 As shown, when the electronic device refreshes 120 frames of images per second, the refresh rate of the high-frequency display area is 120Hz, and the refresh rate of the low-frequency display area is 10Hz. Transistors T1, T4, and T2 are enabled 120 times for the high-frequency display area. Transistors T1, T4, and T2 are enabled 10 times for the low-frequency display area, with an interval of 11 frames between each enable. The image sequence numbers of the 120 frames refreshed by the electronic device per second are as follows: Figure 4 F1, F2, ..., F120 in the series.

[0182] from Figure 2 and Figure 3 It can be seen that when an electronic device refreshes a frame of an image, if transistors T1, T2, and T4 corresponding to the display area of ​​that frame are enabled, then capacitor C1 corresponding to that display area is charged during the writing phase. For example... Figure 2 and Figure 3As shown in the embodiment, when the electronic device refreshes 120 frames of images per second and the refresh rate of the high-frequency display area is 120Hz, the capacitor C1 corresponding to the high-frequency display area is charged 120 times per second, or the frequency at which Vdata of the high-frequency display area is written to point N1 is 120Hz. When the electronic device refreshes 120 frames of images per second and the refresh rate of the low-frequency display area is 10Hz, the capacitor C1 corresponding to the low-frequency display area is charged 10 times per second, or the frequency at which Vdata of the low-frequency display area is written to point N1 is 10Hz.

[0183] In possible implementations, the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage in the high-frequency display area are the same as the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage in the low-frequency display area, combined with... Figure 2 , Figure 3 and Figure 4 It can be seen that the brightness of the high-frequency display area differs from that of the low-frequency display area in the following ways:

[0184] During the process of refreshing 120 frames of images per second in an electronic device, the low-frequency display area has a low refresh rate, and the capacitor C1 corresponding to the low-frequency display area is charged less frequently. The charge of capacitor C1 when transistors T1, T4, and T2 are enabled is needed to provide the gate voltage for transistor T3 when transistors T1, T4, and T2 are enabled, and for the subsequent 11 consecutive frames when transistors T1, T4, and T2 are disabled. While capacitor C1 is providing the gate voltage for transistor T3 during the 11 consecutive frames when transistors T1, T4, and T2 are disabled, capacitor C1 is constantly discharging and not being charged. The potential at point N1 decreases as capacitor C1 discharges. When the light-emitting element emits light, the gate voltage of transistor T3 decreases, the gate-source voltage difference of transistor T3 decreases, and the current flowing through transistor T3 increases. Since the light-emitting element is connected in series with transistor T3, the current flowing through the light-emitting element also increases, resulting in higher brightness of the light-emitting element, and consequently, higher brightness in the low-frequency display area.

[0185] Correspondingly, during the process of refreshing 120 frames of images per second in an electronic device, the high-frequency display area has a high refresh rate, and the capacitor C1 corresponding to the high-frequency display area is charged more times. Furthermore, the charge obtained by capacitor C1 when transistors T1, T4, and T2 are enabled only needs to provide the gate voltage for transistor T3 during the display of that single frame of image when transistors T1, T4, and T2 are enabled. When the light-emitting element emits light, the current flowing through transistor T3 is small. Since the light-emitting element is connected in series with transistor T3, the small current flowing through the light-emitting element results in low brightness, which in turn leads to low and constant brightness in the high-frequency display area.

[0186] It is known that when the voltage values ​​of the first initialization voltage, the second initialization voltage, and the third initialization voltage of the high-frequency display area are the same as those of the first initialization voltage, the second initialization voltage, and the third initialization voltage of the low-frequency display area are the same, the greater the difference between the gate voltage of the transistor T3 corresponding to the low-frequency display area and the gate voltage of the transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light or during the light-emitting phase, the greater the difference between the brightness of the low-frequency display area and the brightness of the high-frequency display area. When the refresh rate of the display area is switched, the display panel of the electronic device will flicker.

[0187] Therefore, by increasing the charge of capacitor C1 corresponding to the low-frequency display area when transistors T1, T4, and T2 are enabled during image refresh in electronic devices, the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light can be reduced. Alternatively, by reducing the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area during the light-emitting phase, the difference in brightness between the low-frequency display area and the high-frequency display area can be reduced, thereby reducing the probability of flickering on the display panel of electronic devices.

[0188] In response, Figure 5 The following diagram illustrates the level timing of each signal provided in the embodiments of this application. Figure 2 , Figure 6 The following diagram illustrates the level timing of each signal provided in the embodiments of this application. Figure 3 .

[0189] Figure 5 This diagram shows the level timing of each signal in the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 1 .like Figure 5 As shown, when the electronic device refreshes the image, if transistors T1, T4 and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V1 and the third initialization voltage Vinit3 to V2.

[0190] Figure 6 The diagram shows the timing sequence of the signal levels and the schematic diagram of the initialization voltages for each signal in the high-frequency display area when an electronic device refreshes an image. For example... Figure 6 As shown, when the electronic device refreshes the image, if transistors T1, T4 and T2 are enabled, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V3 and the third initialization voltage Vinit3 to V4.

[0191] Among them, V1 > V3 and V2 < V4.

[0192] Optionally, V1 can be equal to V3.

[0193] Optionally, V2 can be equal to V4.

[0194] If V1 > V3 and V2 ≤ V4, and transistors T1, T4, and T2 in the low-frequency display area are enabled, when the electronic device refreshes a frame of image, during the reset phase, voltage V1 is written to capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V1, the voltage at point N2 is V2, and the gate-source voltage difference of transistor T3 is the voltage difference between V1 and V2.

[0195] During the write phase, when transistor T4 is turned on, Vdata is loaded to point N2, and capacitor C1 is charged. The duration for which the second scan signal remains low during the write phase is fixed, and the duration for which transistor T4 remains on is also fixed. The amount of charge added to capacitor C1 during the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 during the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-l of transistor T3 during the reset phase, i.e., the voltage difference between V1 and V2. For example, Vth of transistor T3 is affected by the gate-source voltage difference of transistor T3; the more positive the gate-source voltage difference, the more positive Vth of transistor T3; conversely, the more negative the gate-source voltage difference, the more negative Vth of transistor T3.

[0196] If V1 > V3 and V2 ≤ V4, and transistors T1, T4, and T2 in the high-frequency display area are enabled, when the electronic device refreshes a frame of image, during the reset phase, voltage V3 is written to capacitor C1, so that the potential of C1 is reset and initialized, the voltage at point N1 is V3, the voltage at point N2 is V4, and the gate-source voltage difference of transistor T3 is the voltage difference between V3 and V4.

[0197] During the write phase, when transistor T4 is turned on, Vdata is loaded to point N2, and capacitor C1 is charged. Similarly, if the duration for which transistor T4 remains on is fixed, the amount of charge added to capacitor C1 during the write phase is related to the transient characteristics of transistor T3, or the value of Vdata written to capacitor C1 during the write phase is related to the transient characteristics of transistor T3. The transient characteristics of transistor T3 are determined by the gate-source voltage difference Vgs-h of transistor T3 during the reset phase, i.e., the voltage difference between V3 and V4.

[0198] During the write phase, when capacitor C1 is charged, a larger gate-source voltage difference in transistor T3 results in a positive shift of Vth in transistor T3, a larger current flowing through transistor T3, and thus more charge is injected into capacitor C1 or more Vdata is written to C1. Conversely, a smaller gate-source voltage difference in transistor T3 results in a negative shift of Vth in transistor T3, a smaller current flowing through transistor T3, and thus less charge is injected into capacitor C1 or less Vdata is written to C1.

[0199] Since Vgs-l > Vgs-h, the amount of charge that transistors T1, T4, and T2 in the low-frequency display area give to capacitor C1 when they are enabled is greater than the amount of charge that transistors T1, T4, and T2 in the high-frequency display area give to capacitor C1 when they are enabled. Alternatively, the amount of Vdata written to capacitor C1 when transistors T1, T4, and T2 in the low-frequency display area are enabled is more substantial than the amount of Vdata written to capacitor C1 when transistors T1, T4, and T2 in the high-frequency display area are enabled.

[0200] In this way, when the electronic device refreshes the image, the amount of charge of capacitor C1 corresponding to the low-frequency display area is increased each time, which can reduce the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light.

[0201] Furthermore, for low-frequency display areas, because the transient characteristics of transistor T3 are affected by the gate-source voltage difference of transistor T3, electronic devices refresh 120 frames of images per second (such as...). Figure 4 During the process shown (F1-F120), the changes in display brightness of the corresponding image when transistors T1, T4, and T2 are enabled, compared to when transistors T1, T4, and T2 are disabled, are as follows:

[0202] When F1 is displayed, the corresponding transistors T1, T4, and T2 are enabled; when F2-F12 are displayed, the corresponding transistors T1, T4, and T2 are disabled. The display brightness of F1-F12 will increase gradually.

[0203] Compared to F12, when F13 is displayed, transistors T1, T4, and T2 corresponding to F13 are enabled. The display brightness of F13 is comparable to that of F1, both lower than that of F12. When F14-F24 are displayed, transistors T1, T4, and T2 corresponding to F14 are disabled, and the display brightness of F13-F24 will increase progressively.

[0204] Similarly, the display brightness will increase from F25 to F36; ...; the display brightness will increase from F109 to F120.

[0205] Due to the gate-source voltage difference of transistor T3 and the changes in its transient characteristics, flickering may occur in adjacent frames during the display process of F1-F120 due to excessive brightness differences. For example, flickering may occur if the brightness difference between F1 and F2, or between F3 and F4, or between F12 and F13.

[0206] When displaying images in the low-frequency display area, flickering may occur in the low-frequency display area due to the significant difference in brightness between adjacent frames.

[0207] Therefore, when an electronic device refreshes an image, increasing the amount of charge on capacitor C1 corresponding to the low-frequency display area each time can also reduce the brightness difference between two adjacent frames of the image displayed in the low-frequency display area.

[0208] Similarly, if V1≥V3 and V2<V4, transistors T1, T4 and T2 are enabled. When the electronic device refreshes a frame of image, since V2<V4, the amount of charge on capacitor C1 corresponding to the low-frequency display area during the reset phase is greater than the amount of charge on capacitor C1 corresponding to the high-frequency display area during the reset phase. Alternatively, the Vdata written to capacitor C1 when transistors T1, T4 and T2 in the low-frequency display area are enabled is more sufficient than the Vdata written to capacitor C1 when transistors T1, T4 and T2 in the high-frequency display area are enabled.

[0209] In this way, when the electronic device refreshes the image, the amount of charge on capacitor C1 corresponding to the low-frequency display area is also increased with each refresh. This reduces the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light. Furthermore, increasing the amount of charge on capacitor C1 corresponding to the low-frequency display area with each refresh can also reduce the brightness difference between adjacent frames displayed in the low-frequency display area.

[0210] Reducing the brightness difference between high-frequency and low-frequency display areas, as well as the brightness difference between two adjacent frames displayed in the low-frequency display area, can make the in-plane display of electronic device panels more uniform, thereby improving the user experience of using electronic devices.

[0211] Optionally, such as Figure 5 and Figure 6 As shown, when an electronic device refreshes a frame of image, if transistors T1, T4, and T2 are disabled and capacitor C1 is not charged, the DDIC of the electronic device can control the first initialization voltage Vinit1 to V3 and the third initialization voltage Vinit3 to V4. This reduces the power consumption of the electronic device.

[0212] When an electronic device refreshes each frame of an image, the voltage difference between points N1 and N2 during the reset phase is also called the bias voltage of transistor T3. As can be seen above, the bias voltage affects the amount of charge applied to capacitor C1 during the write phase.

[0213] Figure 7 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 1 . Figure 8 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 2 .like Figure 7 As shown and Figure 8 As shown, the first area can be a low-frequency display area with a refresh rate of, for example, 10Hz, and the second area can be a high-frequency display area with a refresh rate of, for example, 120Hz.

[0214] The time for an electronic device to refresh one frame of an image line by line ranges from 0 to t3. For example... Figure 7 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t2, the electronic device drives the display of the second region of this frame of image. During the time period t2-t3, the electronic device drives the display of the first region of this frame of image. Figure 8 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t3, the electronic device drives the display of the second region of this frame of image.

[0215] like Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage for driving the display of the first region of F1 higher than the bias voltage for driving the display of the second region of F1.

[0216] The DDIC controls the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to ensure that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1. This is similar to... Figure 5 and Figure 6 The implementation principle of the embodiments shown is similar and will not be described again.

[0217] When the electronic device refreshes the second frame image, such as F2, transistors T1, T4, and T2 corresponding to the first region of F2 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F2 equal to the bias voltage when driving the display of the second region of F2.

[0218] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are disabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first area of ​​F3 equal to the bias voltage when driving the display of the second area of ​​F3.

[0219] Similarly, when the electronic device refreshes the thirteenth frame image, such as F13, the transistors T1, T4, and T2 corresponding to the first and second regions of F13 are all enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F13 higher than the bias voltage when driving the display of the second region of F13.

[0220] Similarly, when the electronic device refreshes the fourteenth frame image, such as F14, transistors T1, T4, and T2 corresponding to the first region of F14 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F14 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F14 equal to the bias voltage when driving the display of the second region of F14.

[0221] This reduces the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area when the light-emitting element emits light, thereby reducing the difference in brightness between the first and second areas. This reduces the probability of flickering in the first area during refresh rate switching, and / or reduces the probability of flickering in the second area during refresh rate switching, thus reducing the overall probability of flickering on the electronic device's display panel. Furthermore, it improves the brightness uniformity of the first area, reducing the probability of flickering in the first area due to brightness differences between adjacent frames, further reducing the overall probability of flickering on the electronic device's display panel.

[0222] The refresh rate of the first zone is switched, for example, the refresh rate of the first zone is switched to the refresh rate of the second zone.

[0223] The refresh rate of the second zone is switched, for example, the refresh rate of the second zone is switched to the refresh rate of the first zone.

[0224] In one possible implementation, Figure 9 This diagram shows the level timing of each signal in the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 2 . Figure 10 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 3 . Figure 11 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 4 .like Figure 10 As shown and Figure 11 As shown, the first area can be a low-frequency display area. The refresh rate of the first area is, for example, 10Hz. The second area can be a high-frequency display area. The refresh rate of the second area is, for example, 120Hz. The timing diagram of the signal levels and the schematic diagram of the initialization voltages corresponding to each signal in the high-frequency display area (or the second area) when the electronic device refreshes the image are shown below. Figure 6 As shown.

[0225] The time for an electronic device to refresh one frame of an image line by line ranges from 0 to t3. For example... Figure 10 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t2, the electronic device drives the display of the second region of this frame of image. During the time period t2-t3, the electronic device drives the display of the first region of this frame of image. Figure 11 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t3, the electronic device drives the display of the second region of this frame of image.

[0226] like Figure 6 , Figure 9 , Figure 10 and Figure 11 As shown, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage for driving the display of the first region of F1 higher than the bias voltage for driving the display of the second region of F1.

[0227] The DDIC controls the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to ensure that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1. This is similar to... Figure 5 and Figure 6 The implementation principle of the embodiments shown is similar and will not be described again.

[0228] When the electronic device refreshes the second frame image, such as F2, transistors T1, T4, and T2 corresponding to the first region of F2 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F2 higher than the bias voltage when driving the display of the second region of F2.

[0229] Similarly, when the electronic device refreshes the third frame image such as F3, the transistors T1, T4 and T2 corresponding to the first area of ​​F3 are disabled, and the transistors T1, T4 and T2 corresponding to the second area of ​​F3 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first area of ​​F3 equal to the bias voltage when driving the display of the second area of ​​F3.

[0230] Similarly, when the electronic device refreshes the fourth frame image such as F4, the transistors T1, T4 and T2 corresponding to the first area of ​​F4 are disabled, while the transistors T1, T4 and T2 corresponding to the second area of ​​F4 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first area of ​​F4 equal to the bias voltage when driving the display of the second area of ​​F4.

[0231] Similar to when an electronic device refreshes the first frame of an image, such as F1, when the electronic device refreshes the thirteenth frame of an image, such as F13, transistors T1, T4, and T2 corresponding to the first and second regions of F13 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage driving the display of the first region of F13 higher than the bias voltage driving the display of the second region of F13.

[0232] Similar to when an electronic device refreshes the second frame image, such as F2, when the electronic device refreshes the fourteenth frame image, such as F14, transistors T1, T4, and T2 corresponding to the first region of F14 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F14 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F14 higher than the bias voltage when driving the display of the second region of F14.

[0233] Similar to when an electronic device refreshes the third frame image, such as F3, when the electronic device refreshes the fifteenth frame image, such as F15, transistors T1, T4, and T2 corresponding to the first region of F15 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F15 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F15 equal to the bias voltage when driving the display of the second region of F15.

[0234] In this way, the difference between the gate voltage of transistor T3 corresponding to the low-frequency display area and the gate voltage of transistor T3 corresponding to the high-frequency display area can be reduced when the light-emitting element emits light, thereby reducing the difference in brightness between the first area and the second area, and also improving the brightness uniformity of the first area. Experimental verification shows that the voltage control method provided in this embodiment can reduce the probability of flickering on the display panel of electronic devices.

[0235] In one possible implementation, Figure 12 This diagram shows the level timing of each signal in the low-frequency display area and the schematic diagram of each initialization voltage when the electronic device refreshes the image. Figure 3 . Figure 13 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 5 . Figure 14 The timing diagram shows the bias voltage when the electronic device refreshes the image. Figure 6 .like Figure 13 As shown and Figure 14 As shown, the first area can be a low-frequency display area. The refresh rate of the first area is, for example, 10Hz. The second area can be a high-frequency display area. The refresh rate of the second area is, for example, 120Hz. The timing diagram of the signal levels and the schematic diagram of the initialization voltages corresponding to each signal in the high-frequency display area (or the second area) when the electronic device refreshes the image are shown below. Figure 6 As shown.

[0236] The time for an electronic device to refresh one frame of an image line by line ranges from 0 to t3. For example... Figure 13 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t2, the electronic device drives the display of the second region of this frame of image. During the time period t2-t3, the electronic device drives the display of the first region of this frame of image. Figure 14 As shown, during the time period 0-t1, the electronic device drives the display of the first region of this frame of image. During the time period t1-t3, the electronic device drives the display of the second region of this frame of image.

[0237] like Figure 6 , Figure 12 , Figure 13 and Figure 14 As shown, when the electronic device refreshes the first frame image, such as F1, transistors T1, T4, and T2 corresponding to the first and second regions of F1 are all enabled. DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage for driving the display of the first region of F1 higher than the bias voltage for driving the display of the second region of F1.

[0238] The DDIC controls the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to ensure that the bias voltage when driving the first area of ​​display F1 is higher than the bias voltage when driving the second area of ​​display F1. This is similar to... Figure 5 and Figure 6 The implementation principle of the embodiments shown is similar and will not be described again.

[0239] When the electronic device refreshes the second frame image, such as F2, transistors T1, T4, and T2 corresponding to the first region of F2 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F2 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F2 higher than the bias voltage when driving the display of the second region of F2.

[0240] When the electronic device refreshes the third frame image, such as F3, transistors T1, T4, and T2 corresponding to the first region of F3 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F3 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F3 higher than the bias voltage when driving the display of the second region of F3.

[0241] When the electronic device refreshes the fourth frame image, such as F4, transistors T1, T4, and T2 corresponding to the first region of F4 are disabled, while transistors T1, T4, and T2 corresponding to the second region of F4 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first region of F4 equal to the bias voltage when driving the display of the second region of F4.

[0242] When the electronic device refreshes the fifth frame image, such as F5, transistors T1, T4, and T2 corresponding to the first area of ​​F5 are disabled, while transistors T1, T4, and T2 corresponding to the second area of ​​F5 are enabled. The DDIC can control the first initialization voltage Vinit1 and the third initialization voltage Vinit3 to make the bias voltage when driving the display of the first area of ​​F5 equal to the bias voltage when driving the display of the second area of ​​F5.

[0243] The bias voltage in the first region when the electronic device refreshes the thirteenth frame (e.g., F13) is similar in control method and effect to the bias voltage in the first region when the electronic device refreshes the first frame (e.g., F1). The bias voltage in the first region when the electronic device refreshes the fourteenth frame (e.g., F14) is similar in control method and effect to the bias voltage in the first region when the electronic device refreshes the second frame (e.g., F2). The bias voltage in the first region when the electronic device refreshes the fifteenth frame (e.g., F15) is similar in control method and effect to the bias voltage in the first region when the electronic device refreshes the third frame (e.g., F3). The bias voltage in the first region when the electronic device refreshes the sixteenth frame (e.g., F16) is similar in control method and effect to the bias voltage in the first region when the electronic device refreshes the fourth frame (e.g., F4). These will not be elaborated further.

[0244] In this way, the difference between the gate voltage of transistor T3 corresponding to the static image display area and the gate voltage of transistor T3 corresponding to the dynamic image display area can be reduced when the light-emitting element emits light, thereby reducing the difference in brightness between the first area and the second area, and also improving the brightness uniformity of the first area. Experimental verification shows that the voltage control method provided in this embodiment can reduce the probability of flickering on the display panel of electronic devices.

[0245] Next, let's combine... Figure 15 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 The voltage control method provided in the embodiments of this application will be described.

[0246] Figure 15 Pixel circuit diagram provided for embodiments of this application Figure 2 .like Figure 15 As shown, the pixel circuit includes:

[0247] Driving module 13. The control terminal of driving module 13 is connected to a first node N1, and the source terminal of driving module 13 is connected to a second node N2. Driving module 13 may include a driving thin-film transistor (DTFT). The drain terminal of the DTFT is connected to a third node N3, and the DTFT is used to output current to the third node N3 under the control of the first node N1. The DTFT may include... Figure 2 The transistor T3 is shown.

[0248] A first reset unit 10, connected to a first node N1, is used to apply a first initialization voltage to the first node N1 in response to a first reset signal. The first reset unit 10 may include a first reset transistor. The first reset transistor is as follows: Figure 2 The transistor T1 is shown.

[0249] Storage capacitor 11 has one end connected to the first node N1 and the other end connected to the positive power supply (VDD). Storage capacitor 11 may include... Figure 2 The capacitor C1 shown.

[0250] A first light-emitting control unit 12 is connected to the positive terminal of a power supply and a second node N2, and is used to apply a first power supply voltage from the positive terminal to the second node N2 in response to a light-emitting control signal. The first light-emitting control unit 12 may include a first light-emitting control transistor. The first light-emitting control transistor is as follows: Figure 2 The transistor T5 is shown.

[0251] A threshold compensation unit 14, connected to the first node N1 and the third node N3, is used to turn on the third node N3 and the first node N1 in response to a first scan signal. The threshold compensation unit 14 may include a threshold compensation transistor. The threshold compensation transistor is as follows: Figure 2 The transistor T2 is shown.

[0252] The second light-emitting control unit 15 is connected to the third node N3 and the fourth node N4, and is used to turn on the third node N3 and the fourth node N4 in response to a light-emitting control signal. The second light-emitting control unit 15 may include a second light-emitting control transistor. The second light-emitting control transistor is as follows: Figure 2 The transistor T6 is shown.

[0253] The light-emitting element 16 has one end connected to the fourth node and the other end connected to the negative terminal of the power supply to apply a second power supply voltage to the negative terminal. The light-emitting element 16 may include an organic light-emitting diode (OLED).

[0254] The second reset unit 17, connected to the fourth node N4, is used to apply a second initialization voltage to the fourth node N4 in response to a second reset signal. The second reset unit 17 may include a second reset transistor. The second reset transistor is as follows: Figure 2 The transistor T7 is shown.

[0255] The data writing unit 18, connected to the second node N2, is used to apply a data voltage to the second node N2 in response to a second scan signal. The data writing unit 18 may include a data writing transistor. The data writing transistor is as follows: Figure 2 The transistor T4 is shown.

[0256] The first reset unit 10 is turned on, which can be referred to as the first reset unit 10 being enabled. The first reset unit 10 is not turned on, which can be referred to as the first reset unit 10 being disabled. The data writing unit 18 responds to the second scan signal by applying a data voltage to the second node N2, which can be referred to as the data writing unit 18 being enabled. The data writing unit 18 does not apply a data voltage to the second node N2, which can be referred to as the data writing unit 18 being disabled. The threshold compensation unit 14 responds to the first scan signal by making the third node N3 and the first node N1 conduct, which can be referred to as the threshold compensation unit 14 being enabled. The threshold compensation unit 14 makes the third node N3 and the first node N1 not conduct, which can be referred to as the threshold compensation unit 14 being disabled.

[0257] The third reset unit 19, connected to the second node N2, is used to apply a third initialization voltage to the second node N2 in response to the second reset signal. The third reset unit 19 may include a third reset transistor. The third reset transistor is as follows... Figure 2 The transistor T8 is shown.

[0258] like Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the electronic device drives the display of a first frame image in a first area, it controls the voltage of the first node to a first voltage and controls the voltage of the second node to a second voltage. The first voltage may include V1. The second voltage may include V2.

[0259] When the electronic device drives the second region of the first frame image for display, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. The third voltage may include V3. The fourth voltage may include V4.

[0260] The voltage difference between the first and second voltages is greater than the voltage difference between the third and fourth voltages. The refresh rate of the first region is the first refresh rate, and the refresh rate of the second region is the second refresh rate. The first refresh rate is lower than the second refresh rate. For example, the first refresh rate is 10Hz. For example, the second refresh rate is 120Hz.

[0261] Optionally, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage.

[0262] Furthermore, such as Figure 15 As shown, the pixel circuit also includes a data writing unit 18, which is connected to the second node N2. Figure 3 and Figure 4 As shown, when the electronic device displays the first and second regions of the first frame image, the data writing unit 18 is enabled in both cases. The voltage control method provided in this embodiment also includes:

[0263] like Figure 5 As shown, when the electronic device drives the display of the first area of ​​the second frame image, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is disabled.

[0264] like Figure 6 As shown, when the electronic device drives the display of the second region of the second frame image, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. When the electronic device displays the second region of the second frame image, the data writing unit 18 is enabled.

[0265] Optionally, such as Figure 15 As shown, the pixel circuit also includes a data writing unit 18 and a threshold compensation unit 14. For example... Figure 3 and Figure 4 As shown, when the electronic device displays the first and second regions of the first frame image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment also includes:

[0266] like Figure 5 As shown, when the electronic device drives the display of the first area of ​​the second frame image, it controls the voltage of the first node to be a third voltage and controls the voltage of the second node to be a fourth voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0267] like Figure 6 As shown, when the electronic device drives the display of the second region of the second frame image, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. When the electronic device displays the second region of the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0268] Optionally, the display area on the display panel of the electronic device may further include a third area. When driving the display of the third area of ​​the first frame image, the electronic device controls the voltage of the first node to a first voltage and controls the voltage of the second node to a second voltage. The refresh rate of the third area is a third refresh rate. The third refresh rate is lower than the second refresh rate.

[0269] Optionally, the third refresh rate can be the same as the first refresh rate, or it can be different from the first refresh rate. When the third refresh rate is the same as the first refresh rate, the third region is, for example... Figure 7 , Figure 10 and Figure 13 The first region corresponding to the time period t2-t3 is shown.

[0270] It is understood that the first refresh rate and the third refresh rate in the embodiments of this application may be, but are not limited to, 10Hz. The second refresh rate in the embodiments of this application may be, but is not limited to, 120Hz. For example, the third refresh rate may also be 30Hz or 60Hz, etc.

[0271] Optionally, when refreshing a frame of image, the electronic device can determine the start and end positions of the first region based on the identifier of the pixel circuit corresponding to the first region. Similarly, it can determine the start and end positions of the second region based on the identifier of the pixel circuit corresponding to the second region.

[0272] For example, the DDIC can determine the start and end positions of the second region by using the position information of the second region indicated by the application processor (AP) of the electronic device, and thus determine the start and end positions of the first region. The position information of the second region indicated by the AP can be the relative position information of the second region indicated by the AP, or it can be the actual position information of the second region indicated by the AP. The actual position information of the second region indicated by the AP can include the identifier of the pixel circuit corresponding to the start position of the second region and the identifier of the pixel circuit corresponding to the end position of the second region.

[0273] The location information of the second area indicated by the AP is determined by the AP based on the application type or application scenario to which the image data generated by the AP belongs. The image data generated by the AP refers to the data corresponding to Vdata when transistors T4 and T2 are enabled. If the image data generated by the AP belongs to the dynamic image data of application A, then the location information of the second area indicated by the AP can be determined based on the location information of the area displaying the dynamic image in the display interface of application A.

[0274] The specific implementation principle and technical effects of this embodiment are related to... Figure 2 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The specific implementation principles and technical effects of the embodiments shown are similar, and will not be described again.

[0275] like Figure 15 , Figure 4 , Figure 6 , Figure 9 , Figure 10 and Figure 11 As shown, when the electronic device displays the first and second regions of the first frame image, the data writing unit 18 is enabled in both cases. The voltage control method provided in this embodiment also includes:

[0276] When the electronic device drives the display of the first area of ​​the second frame image, it controls the voltage of the first node to a first voltage and controls the voltage of the second node to a second voltage. When the electronic device displays the first area of ​​the second frame image, the data writing unit 18 is disabled.

[0277] When the electronic device drives the display of the second region of the second frame image, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. When the electronic device displays the second region of the second frame image, the data writing unit 18 is enabled.

[0278] The specific implementation principle and technical effects of this embodiment are related to... Figure 6 , Figure 9 , Figure 10 and Figure 11 The specific implementation principles and technical effects of the embodiments shown are similar, and will not be described again.

[0279] For example, such as Figure 15 , Figure 4 , Figure 6 , Figure 9 , Figure 10 and Figure 11 As shown, when the electronic device displays the first and second regions of the first frame image, the first reset unit 10 is enabled, the data writing unit 18 is enabled, and the threshold compensation unit 14 is enabled. The voltage control method provided in this embodiment also includes:

[0280] When the electronic device drives the display of the first area of ​​the second frame image, it controls the voltage of the first node to a first voltage and controls the voltage of the second node to a second voltage. When the electronic device displays the first area of ​​the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0281] When the electronic device drives the display of the second region of the second frame image, it controls the voltage of the first node to a third voltage and controls the voltage of the second node to a fourth voltage. When the electronic device displays the first region of the second frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0282] The specific implementation principle and technical effects of this embodiment are related to... Figure 6 , Figure 9 , Figure 10 and Figure 11 The specific implementation principles and technical effects of the embodiments shown are similar, and will not be described again.

[0283] like Figure 15 , Figure 4 , Figure 6 , Figure 12 , Figure 13 and Figure 14As shown, the voltage control method provided in this embodiment further includes:

[0284] When the electronic device drives the display of the first area of ​​the third frame image, it controls the voltage of the first node to a first voltage and controls the voltage of the second node to a second voltage. When the electronic device displays the first area of ​​the third frame image, the data writing unit 18 is disabled.

[0285] When the electronic device drives the second area of ​​the third frame image for display, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the data writing unit 18 is enabled.

[0286] When the electronic device drives the display of the first area of ​​the fourth frame image, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the data writing unit 18 is disabled.

[0287] When the electronic device drives the second area of ​​the fourth frame image for display, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the data writing unit 18 is enabled.

[0288] The specific implementation principle and technical effects of this embodiment are related to... Figure 6 , Figure 12 , Figure 13 and Figure 14 The specific implementation principles and technical effects of the embodiments shown are similar, and will not be described again.

[0289] For example, such as Figure 15 , Figure 4 , Figure 6 , Figure 12 , Figure 13 and Figure 14 As shown, the voltage control method provided in this embodiment further includes:

[0290] When the electronic device drives the display of the first area of ​​the third frame image, it controls the voltage of the first node to be a first voltage and controls the voltage of the second node to be a second voltage. When the electronic device displays the first area of ​​the third frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0291] When the electronic device drives the display of the second area of ​​the third frame image, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the second area of ​​the third frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0292] When the electronic device drives the display of the first area of ​​the fourth frame image, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the first area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are disabled.

[0293] When the electronic device drives the second area of ​​the fourth frame image for display, it controls the voltage of the first node to the third voltage and controls the voltage of the second node to the fourth voltage. When the electronic device displays the second area of ​​the fourth frame image, the first reset unit 10, the data writing unit 18, and the threshold compensation unit 14 are enabled.

[0294] The specific implementation principle and technical effects of this embodiment are related to... Figure 6 , Figure 12 , Figure 13 and Figure 14 The specific implementation principles and technical effects of the embodiments shown are similar, and will not be described again.

[0295] To better understand the embodiments of this application, the following is combined with... Figure 16 and Figure 17 The structure of the electronic device according to the embodiments of this application will be described.

[0296] Figure 16 A schematic diagram of the structure of the electronic device 100 is shown.

[0297] Electronic device 100 may include processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) interface 130, charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, button 190, motor 191, indicator 192, camera 193, display screen 194, and subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0298] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0299] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0300] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0301] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0302] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0303] It is understood that the interface connection relationships between the modules illustrated in the embodiments of the present invention are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0304] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.

[0305] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0306] The wireless communication function of electronic device 100 can be achieved through Figure 16 The antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor shown are implemented.

[0307] Figure 16 Antennas 1 and 2 shown are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0308] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0309] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through an audio device (not limited to speaker 170A, receiver 170B, etc.) or displays images or videos through the display screen 194. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0310] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0311] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other devices via wireless communication technology. Wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-CDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. GNSS can include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0312] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0313] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0314] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0315] The ISP (Image Signal Processor) is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization of image noise, brightness, and skin tone. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

[0316] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0317] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when electronic device 100 selects a frequency, the DSP can perform Fourier transforms on the frequency energy.

[0318] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. Thus, electronic device 100 can play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0319] An NPU (Neural Processing Unit) is a computational processor for neural networks (NNs). By borrowing the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it can rapidly process input information and continuously learn on its own. NPUs can enable intelligent cognitive applications in electronic devices, such as image recognition, facial recognition, speech recognition, and text understanding.

[0320] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0321] Internal memory 121 can be used to store executable program code, including instructions. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of electronic device 100 (such as audio data, phonebook, etc.). Furthermore, internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. Processor 110 executes various functional applications and data processing of electronic device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory located within the processor.

[0322] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0323] The audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 may be located in the processor 110, or some functional modules of the audio module 170 may be located in the processor 110.

[0324] The speaker 170A, also known as a "loudspeaker," is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or make hands-free calls through the speaker 170A.

[0325] The receiver 170B, also known as the "earpiece," is used to convert audio electrical signals into sound signals. When the electronic device 100 answers a telephone call or voice message, the receiver 170B can be brought close to the ear to listen to the voice.

[0326] Microphone 170C, also known as a "microphone" or "voice transducer," is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can speak by bringing their mouth close to microphone 170C, inputting the sound signal into microphone 170C. Electronic device 100 may have at least one microphone 170C. In some embodiments, electronic device 100 may have two microphones 170C, which, in addition to collecting sound signals, can also perform noise reduction. In other embodiments, electronic device 100 may also have three, four, or more microphones 170C, which can collect sound signals, reduce noise, identify the sound source, and perform directional recording, etc.

[0327] The 170D headphone jack is used to connect wired headphones. The 170D headphone jack can be a USB 130 interface or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, a CTIA (Cellular Telecommunications Industry Association of the USA) standard interface.

[0328] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Electronic device 100 can receive button input and generate key signal inputs related to user settings and function control of electronic device 100.

[0329] Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. For example, different vibration feedback effects can correspond to touch operations performed on different applications (such as taking photos, playing audio, etc.). Motor 191 can also correspond to different vibration feedback effects for touch operations performed on different areas of the display screen 194. Different application scenarios (such as time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also be customized.

[0330] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0331] The SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to make contact with and separate from the electronic device 100. The electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. Multiple cards can be inserted into the same SIM card interface 195 simultaneously. The multiple cards can be of the same or different types. The SIM card interface 195 is also compatible with different types of SIM cards. The SIM card interface 195 is also compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to realize functions such as calls and data communication. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0332] The software system of electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This embodiment of the invention uses the layered architecture Android system as an example to exemplify the software structure of electronic device 100.

[0333] Figure 17 This is a software structure block diagram of the electronic device 100 according to an embodiment of the present invention.

[0334] A layered architecture divides software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0335] The application layer can include a series of application packages.

[0336] like Figure 17 As shown, the application package may include applications such as camera, gallery, games, calling, maps, navigation, WLAN, Bluetooth, music, video, and SMS.

[0337] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0338] like Figure 17 As shown, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc.

[0339] The window manager is used to manage windowed applications. It can retrieve screen size, determine the presence of a status bar, lock the screen, and capture screenshots, among other things.

[0340] Content providers store and retrieve data, making that data accessible to applications. This data can include videos, images, audio, phone calls made and received, browsing history and bookmarks, phone books, and more.

[0341] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display panel including a text message notification icon can include views for displaying text and views for displaying images.

[0342] The phone manager is used to provide communication functions for electronic device 100. For example, it manages call status (including connection and disconnection).

[0343] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0344] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.

[0345] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0346] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0347] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0348] System libraries can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing libraries (e.g., OpenGL ES), 2D graphics engines (e.g., SGL), etc.

[0349] The Surface Manager is used to manage the display subsystem and provides the blending of 2D and 3D layers for multiple applications.

[0350] The media library supports playback and recording of various common audio and video formats, as well as still image files. It supports multiple audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG.

[0351] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0352] A 2D graphics engine is a graphics engine for 2D drawing.

[0353] The kernel layer is the layer between hardware and software. The kernel layer contains at least the display driver, camera driver, audio driver, and sensor driver.

[0354] The following example, using a scene of capturing a photograph, illustrates the workflow of the software and hardware of the electronic device 100.

[0355] When touch sensor 180K receives a touch operation, a corresponding hardware interrupt is sent to the kernel layer. The kernel layer processes the touch operation into a raw input event (including touch coordinates, timestamp of the touch operation, etc.). The raw input event is stored in the kernel layer. The application framework layer retrieves the raw input event from the kernel layer and identifies the control corresponding to the input event. Taking a touch click as an example, where the corresponding control is the camera application icon, the camera application calls the application framework layer's interface to launch the camera application, and then calls the kernel layer to launch the camera driver, capturing still images or videos through camera 193.

[0356] The voltage control method provided in this application can be applied to electronic devices with communication functions. The electronic devices include terminal devices, and the specific device form of the terminal devices can be referred to the above-described related descriptions, which will not be repeated here.

[0357] This application provides an electronic device comprising: a processor, a display driver chip (DDIC), pixel circuitry, and a memory. The memory stores computer-executable instructions. The processor instructs the display driver chip to drive the pixel circuitry. The display driver chip executes the computer-executable instructions stored in the memory, causing the electronic device to perform the aforementioned method and drive the pixel circuitry.

[0358] This application provides a chip. The chip includes a processor, which is used to call a computer program in memory to execute the technical solutions in the above embodiments. Its implementation principle and technical effects are similar to those in the related embodiments described above, and will not be repeated here.

[0359] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a display driver chip (DDIC), it implements the above-described method. The methods described in the above embodiments can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted over the computer-readable medium. The computer-readable medium can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0360] In one possible implementation, a computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or any other medium targeted to carry or to store the required program code in the form of instructions or data structures, and accessible by a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs, laser discs, optical discs, Digital Versatile Discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0361] This application provides a computer program product, which includes a computer program that, when run, causes a computer to perform the above-described method.

[0362] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable device to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0363] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A voltage control method, characterized in that, An electronic device having a pixel circuit, the pixel circuit including a driving module, the control terminal of the driving module being connected to a first node, and the source terminal of the driving module being connected to a second node; the method includes: When driving the display of the first area of ​​the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage. When driving the display of the second region of the first frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage. Wherein, the first voltage is greater than the third voltage, and / or the second voltage is less than the fourth voltage; the voltage difference between the first voltage and the second voltage is greater than the voltage difference between the third voltage and the fourth voltage; the refresh rate of the first region is a first refresh rate, the refresh rate of the second region is a second refresh rate, and the first refresh rate is lower than the second refresh rate.

2. The method according to claim 1, characterized in that, The pixel circuit further includes a data writing unit, which is connected to the second node; When displaying the first region and the second region of the first frame image, the data writing unit is enabled in both cases; The method further includes: When driving the display of the first area of ​​the second frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; when displaying the first area of ​​the second frame image, the data writing unit is disabled; When driving the display of the second region of the second frame image, the voltage of the first node is controlled to the third voltage, and the voltage of the second node is controlled to the fourth voltage; when displaying the second region of the second frame image, the data writing unit is enabled.

3. The method according to claim 2, characterized in that, The method further includes: When driving the display of the first area of ​​the third frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; when displaying the first area of ​​the third frame image, the data writing unit is disabled; When driving the display of the second region of the third frame image, the voltage of the first node is controlled to the third voltage, and the voltage of the second node is controlled to the fourth voltage; when displaying the second region of the third frame image, the data writing unit is enabled.

4. The method according to claim 3, characterized in that, The method further includes: When driving the first area of ​​the fourth frame image to be displayed, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when the first area of ​​the fourth frame image is displayed, the data writing unit is disabled; When driving the display of the second region of the fourth frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the second region of the fourth frame image, the data writing unit is enabled.

5. The method according to claim 1, characterized in that, The pixel circuit further includes a data writing unit, which is connected to the second node; When displaying the first region and the second region of the first frame image, the data writing unit is enabled in both cases; The method further includes: When driving the display of the first area of ​​the second frame image, the voltage of the first node is controlled to be the third voltage, and the voltage of the second node is controlled to be the fourth voltage; when displaying the first area of ​​the second frame image, the data writing unit is disabled; When driving the display of the second region of the second frame image, the voltage of the first node is controlled to the third voltage, and the voltage of the second node is controlled to the fourth voltage; when displaying the second region of the second frame image, the data writing unit is enabled.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: Based on the identifier of the pixel circuit corresponding to the first region, the start position and end position of the first region are determined; Based on the identifier of the pixel circuit corresponding to the second region, the start and end positions of the second region are determined.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: When driving the display of the third region of the first frame image, the voltage of the first node is controlled to be the first voltage, and the voltage of the second node is controlled to be the second voltage; the refresh rate of the third region is the third refresh rate, which is lower than the second refresh rate.

8. The method according to any one of claims 1-7, characterized in that, The driving module includes a driving thin-film transistor (DTFT), the drain of which is connected to a third node, and the DTFT is used to output current to the third node under the control of the first node. The pixel circuit also includes: A first reset unit, connected to a first node, is used to apply a first initialization voltage to the first node in response to a first reset signal; The storage capacitor has one end connected to the first node and the other end connected to the positive terminal of the power supply. The first light-emitting control unit is connected to the positive terminal of the power supply and the second node, and is used to apply the first power supply voltage of the positive terminal of the power supply to the second node in response to the light-emitting control signal. A threshold compensation unit, connected to the first node and the third node, is used to enable the third node to conduct with the first node in response to a first scan signal; The second light-emitting control unit is connected to the third node and the fourth node, and is used to make the third node and the fourth node conduct in response to the light-emitting control signal; The light-emitting element is connected at one end to the fourth node and at the other end to the negative terminal of the power supply to apply the second power supply voltage to the negative terminal of the power supply. The second reset unit is connected to the fourth node and is used to apply a second initialization voltage to the fourth node in response to a second reset signal. A data writing unit, connected to the second node, is used to load a data voltage to the second node in response to a second scan signal; The third reset unit, connected to the second node, is used to apply a third initialization voltage to the second node in response to the second reset signal.

9. The method according to claim 8, characterized in that, The first reset unit includes a first reset transistor, the first light-emitting control unit includes a first light-emitting control transistor, the threshold compensation unit includes a threshold compensation transistor, the second light-emitting control unit includes a second light-emitting control transistor, the light-emitting element includes an organic light-emitting diode (OLED), the second reset unit includes a second reset transistor, the data writing unit includes a data writing transistor, and the third reset unit includes a third reset transistor.

10. An electronic device, characterized in that, include: Processor, display driver chip DDIC, pixel circuit and memory; The memory stores computer-executed instructions; The processor instructs the display driver chip to drive the pixel circuit; The display driver chip executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1-9 and drive the pixel circuit.

11. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the display driver chip DDIC, it implements the method as described in any one of claims 1-9.

12. A computer program product, characterized in that, Includes a computer program that, when run, causes a computer to perform the method as described in any one of claims 1-9.

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