A MOSFET device based on NiO gate modulation and its manufacturing method

Abstract

The present invention relates to a MOSFET device based on NiO gate modulation and a preparation method thereof. The device includes: a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer, which are sequentially arranged from bottom to top; a gate step extending from both ends of the upper surface of the third N-type GaN layer to the inside of the second N-type GaN layer; a gate structure extending from the upper surface of the third N-type GaN layer to the bottom of the gate step; a source groove; a source electrode; a drain electrode; and a NiO modulation layer extending from the bottom of the gate step to the upper surface of the first N-type GaN layer. The present invention depletes the interface states of the second N-type GaN layer and the electrons on the surface of the second N-type GaN layer through the NiO modulation layer, generates a depletion region, broadens the electric field distribution range of the device, reduces the peak electric field intensity of the device, and improves the breakdown voltage level of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a MOSFET device based on NiO gate modulation and a preparation method thereof. Background Art

[0002] Compared with Si-based materials, GaN has excellent electrical properties such as a large bandgap, a high critical breakdown electric field, a large saturation velocity, and good thermal conductivity. The prepared devices have a higher breakdown voltage. And under the same breakdown voltage requirement, GaN-based devices have a lower on-resistance. Therefore, GaN also has great potential in the field of high-voltage and high-power power electronics. For GaN planar devices applied in high-voltage environments, to increase the breakdown voltage of the device, the source-drain distance and the gate-drain distance must be increased to provide a larger breakdown voltage space when the device is blocking. However, this method increases the size of the device, resulting in a decrease in the wafer utilization rate and an increase in the cost of a single device.

[0003] The GaN trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) uses a vertical drift layer for blocking breakdown voltage. Therefore, when increasing the breakdown voltage of the device, it is not necessary to increase the size of the device. Only by increasing the thickness of the drift region of the device can the cost of a single device be effectively reduced and the utilization rate of the overall wafer be improved.

[0004] However, there is electric field concentration at the bottom corners of the trenches of the GaN trench-gate MOSFET, which affects the breakdown voltage performance of the device. Summary of the Invention

[0005] To solve the above problems existing in the prior art, the present invention provides a MOSFET device based on NiO gate modulation and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a MOSFET device based on NiO gate modulation and a preparation method thereof, including:

[0007] A substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer arranged in sequence from bottom to top;

[0008] A gate step extending from both ends of the upper surface of the third N-type GaN layer into the second N-type GaN layer;

[0009] A gate structure extending from the upper surface of the third N-type GaN layer to the bottom of the gate step;

[0010] Source groove, extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0011] Source electrode, located within the source groove;

[0012] Drain electrode, located on the upper surface of the first N-type GaN layer on both sides of the second N-type GaN layer, and there is a gap between the drain electrode and the second N-type GaN layer;

[0013] NiO modulation layer, extending from the bottom of the gate step to the upper surface of the first N-type GaN layer.

[0014] In an achievable manner, the source electrode extends from within the source groove to the upper surface of the third N-type GaN layer, and there is a gap between the source electrode and the gate structure.

[0015] In an achievable manner, the gate structure includes: a gate dielectric layer and a gate electrode, where,

[0016] The gate dielectric layer extends from the upper surface of the third N-type GaN layer to the bottom of the gate step;

[0017] The gate electrode is located on the surface of the gate dielectric layer.

[0018] In an achievable manner, the material of the substrate layer includes one or more of Si, SiC, and sapphire;

[0019] The material of the gate dielectric layer includes Al 2 O 3 ;

[0020] The material of the gate electrode includes Ni / Au;

[0021] The material of the source electrode includes Ti / Al / Ni / Au;

[0022] The material of the drain electrode includes Ti / Al / Ni / Au.

[0023] In an achievable manner, the length of the gate structure at the bottom of the gate step is 0.1 - 6 μm.

[0024] In an achievable manner, the length of the NiO modulation layer at the bottom of the gate step is 2 - 8 μm;

[0025] The length of the NiO modulation layer on the upper surface of the first N-type GaN layer is 5 - 8 μm.

[0026] The distance between the drain electrode and the second N-type GaN layer is 7 - 10 μm.

[0027] In an implementable manner, the doping concentration of the first N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , and the thickness is 1 - 2 μm;

[0028] The doping concentration of the second N-type GaN layer is 1.0×10 15 ~2×10 16 cm -3 , and the thickness is 3 - 5 μm;

[0029] The doping concentration of the P-type GaN layer is 1.0×10 17 ~1×10 18 cm -3 , and the thickness is 200 - 350 nm;

[0030] The doping concentration of the third N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , and the thickness is 200 - 300 nm.

[0031] In an implementable manner, the doping type of the NiO modulation layer is P-type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3 , and the thickness is 100 - 200 nm.

[0032] The second aspect of the present invention provides a preparation method of a MOSFET device based on NiO gate modulation, including the following steps:

[0033] S1: Obtain a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer, and a third N-type GaN layer which are sequentially arranged from bottom to top;

[0034] S2: Etch both ends of the third N-type GaN layer to form a gate step extending from both ends of the upper surface of the third N-type GaN layer to the inside of the second N-type GaN layer;

[0035] S3: Prepare a gate structure on the upper surface of the third N-type GaN layer, the side walls of the gate step, and the bottom of the gate step;

[0036] S4: Etch the upper surface of the third N-type GaN layer to form a source groove extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0037] S5: Fabricate a source electrode in the source groove, and fabricate drain electrodes on the upper surfaces of the first N-type GaN layers on both sides of the second N-type GaN layer; there is a gap between the drain electrode and the second N-type GaN layer;

[0038] S6: Fabricate a NiO modulation layer on the bottom of the gate step, on the side surface of the second N-type GaN layer, and on the upper surface of the first N-type GaN layer.

[0039] In an achievable manner, the specific steps of step S6 include:

[0040] Adopt a magnetron sputtering process to sputter P-type NiO with a thickness of 100 - 200 nm on the bottom of the gate step, on the side surface of the second N-type GaN layer, and on the upper surface of the first N-type GaN layer to obtain a NiO modulation layer; wherein, the target material of the magnetron sputtering process is nickel oxide, and the working gases are O 2 and Ar.

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] For the MOSFET device based on NiO gate modulation of the present invention, the NiO modulation layer depletes the interface states of the second N-type GaN layer and the electrons on the surface of the second N-type GaN layer, generates a depletion region, broadens the electric field distribution range of the device, reduces the peak electric field intensity of the device, and improves the breakdown voltage level of the device. Description of the Drawings

[0043] Figure 1 is a schematic structural diagram of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention;

[0044] Figures 2a to 2i is a schematic diagram of the steps of a preparation method of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0045] Reference Signs:

[0046] 1: Substrate layer; 2: First N-type GaN layer; 3: Second N-type GaN layer; 4: P-type GaN layer; 5: Third N-type GaN layer; 6: Gate dielectric layer; 7: Gate electrode; 8: Source electrode; 9: Drain electrode; 10: NiO modulation layer. Detailed Embodiments

[0047] The following further describes the present invention in detail with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0048] Embodiment 1

[0049] Please refer to Figure 1 , Figure 1It is a schematic structural diagram of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0050] A MOSFET device based on NiO gate modulation provided by this embodiment includes: a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4, a third N-type GaN layer 5, a gate step, a gate structure, a source groove, a source electrode 8, a drain electrode 9, and a NiO modulation layer 10. Among them, the substrate layer 1, the first N-type GaN layer 2, the second N-type GaN layer 3, the P-type GaN layer 4, and the third N-type GaN layer 5 are arranged in sequence from bottom to top. The gate step extends from both ends of the upper surface of the third N-type GaN layer 5 to the inside of the second N-type GaN layer 3. The gate structure extends from the upper surface of the third N-type GaN layer 5 to the bottom of the gate step. The source groove extends from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. The source electrode 8 is located in the source groove. The drain electrode 9 is located on the upper surfaces of the first N-type GaN layers 2 on both sides of the second N-type GaN layer 3, and there is a gap between the drain electrode 9 and the second N-type GaN layer 3. The NiO modulation layer 10 extends from the bottom of the gate step to the upper surface of the first N-type GaN layer 2.

[0051] Specifically, the gate structure extends from the upper surface of the third N-type GaN layer 5, passes through the sidewalls of the gate step to the bottom of the gate step. The depth of the gate step is greater than or equal to the sum of the thicknesses of the P-type GaN layer 4 and the third N-type GaN layer 5. It should be understood that the sidewalls of the gate step are the side surfaces of the third N-type GaN layer 5 and the P-type GaN layer 4, and the bottom of the gate step is the upper surface of the third N-type GaN layer 5. The NiO modulation layer 10 extends from the bottom of the gate step through the side surface of the second N-type GaN layer 3 to the upper surface of the first N-type GaN layer 2. The gate structure is located at one end of the gate step close to the third N-type GaN layer 5, and the NiO modulation layer 10 extends from the end of the gate step far from the third N-type GaN layer 5 to the upper surface of the first N-type GaN layer 2 between the drain electrode 9 and the second N-type GaN layer 3. The device provided in this embodiment has an axisymmetric layout, and the axis of symmetry is the central axis of the device, that is, the central axes of the substrate layer 1, the first N-type GaN layer 2, the second N-type GaN layer 3, the P-type GaN layer 4, and the third N-type GaN layer 5. The source electrode 8 is located at the middle position at the top of the device, and the two gate steps are symmetrically arranged on the left and right sides of the device. Correspondingly, there are two gate structures, drain electrodes 9, and NiO modulation layers 10, and they are symmetrically arranged on the left and right sides of the device. In this embodiment, a PN junction is formed between the NiO modulation layer 10 and the second N-type GaN layer 3, depleting the interface states of the second N-type GaN layer 3 and the electrons near the surface of the second N-type GaN layer 3, generating a depletion region, broadening the electric field distribution from the gate structure of the device to both sides of the device, reducing the electric field peak value at the gate structure, alleviating the electric field crowding phenomenon near the gate structure, preventing premature breakdown, and improving the breakdown voltage level of the device.

[0052] In this embodiment, the source electrode 8 extends from within the source groove to the upper surface of the third N-type GaN layer 5, and there is a gap between the source electrode 8 and the gate structure. The length of the gate structure at the bottom of the gate step is 0.1 - 6 μm. The length of the NiO modulation layer 10 at the bottom of the gate step is 2 - 8 μm. The length of the NiO modulation layer 10 on the upper surface of the first N-type GaN layer 2 is 5 - 8 μm. The distance between the drain electrode 9 and the second N-type GaN layer 3 is 7 - 10 μm.

[0053] Specifically, the length of the gate step is 2 - 10 μm, and the distance between the NiO modulation layer 10 on the gate step and the gate structure is 0 - 2 μm. It should be understood that the device provided in this embodiment has an axisymmetric layout and has two gate steps. Correspondingly, there are two gate structures, NiO modulation layers 10, and drain electrodes 9. In this embodiment, the length is the length of a single structure, and the distance is the distance between two structures on one side of the device. Exemplarily, in this embodiment, the length of each gate step is 2 - 10 μm, the total length of the gate steps on the left and right sides of the device is 4 - 20 μm, the length of the NiO modulation layer 10 at the bottom of the gate steps on the left and right sides of the device is 2 - 8 μm, and the total length of the NiO modulation layer 10 at the bottom of the gate steps on the left and right sides of the device is 4 - 16 μm. The distance between the drain electrode 9 on the left side of the device and the left sidewall of the second N-type GaN layer 3 is 7 - 10 μm, and the distance between the drain electrode 9 on the right side of the device and the right sidewall of the second N-type GaN layer 3 is 7 - 10 μm.

[0054] In this embodiment, the gate structure includes: a gate dielectric layer 6 and a gate electrode 7. Among them, the gate dielectric layer 6 extends from the upper surface of the third N-type GaN layer 5 to the bottom of the gate step. The gate electrode 7 is located on the surface of the gate dielectric layer 6.

[0055] In this embodiment, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3 and the thickness is 1 - 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 15 ~2×10 16 cm -3 and the thickness is 3 - 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3 and the thickness is 200 - 350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 and the thickness is 200 - 300 nm. The material of the gate dielectric layer 6 includes Al 2 O 3 . The material of the gate electrode 7 includes Ni / Au. The material of the source electrode 8 includes Ti / Al / Ni / Au. The material of the drain electrode 9 includes Ti / Al / Ni / Au. The doping type of the NiO modulation layer 10 is P-type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3, with a thickness of 100 - 200 nm. The doping ions of the first N-type GaN layer 2, the second N-type GaN layer 3, and the third N-type GaN layer 5 are all Si ions, and the doping ions of the P-type GaN layer 4 are Mg ions.

[0056] Specifically, Ni / Au is Ni and Au stacked layer by layer from bottom to top. Among them, the thickness of Ni is 30 - 50 nm, and the thickness of Au is 300 - 450 nm. Ti / Al / Ni / Au is Ti, Al, Ni, and Au stacked in sequence from bottom to top. Among them, the thickness of Ti is 20 - 30 nm, the thickness of Al is 140 - 180 nm, the thickness of Ni is 40 - 60 nm, and the thickness of Au is 30 - 50 nm.

[0057] In this embodiment, the MOSFET device further includes a device isolation region, which is located on both sides of the first N-type GaN layer 2 and has a depth of 1 - 2 μm.

[0058] The MOSFET device provided in this embodiment has two PN junctions. The third N-type GaN layer 5 and the P-type GaN layer 4 form the J1 junction, and the P-type GaN layer 4 and the second N-type GaN layer 3 form the J2 junction. When no bias voltages are applied to the gate electrode 7, the source electrode 8, and the drain electrode 9 of the device, that is, when the gate voltage Vgate, the source voltage Vsource, and the drain voltage Vdrain are all 0, the N-type inversion channel inside the MOSFET is not turned on, and both the J1 junction and the J2 junction are in the zero-bias state, and no current is generated inside the device.

[0059] When no bias voltages are applied to the source electrode 8 and the gate electrode 7 of the device, while a positive voltage is applied to the drain electrode 9 (Vdrain > 0, Vsource = 0, Vgate = 0), the J2 junction formed by the P-type GaN layer 4 and the second N-type GaN layer 3 is in the reverse-bias state. The second N-type GaN layer 3 serves as the drift region of the device and has a low doping concentration, while the P-type GaN layer 4 has a high doping concentration. Therefore, when the J2 junction is reverse-biased, the depletion layer mainly extends into the low-doped second N-type GaN layer 3. So, the breakdown voltage of the MOSFET depends to a large extent on the structural parameters of the second N-type GaN layer 3, such as the thickness and doping concentration of the drift region, etc. In this embodiment, the doping concentration of the second N-type GaN layer 3 is set to 1.0×10 15 ~2×10 16 cm -3 , with a thickness of 3 - 5 μm, which can ensure that the device has a high breakdown voltage in this state.

[0060] When no bias voltage is applied to the source electrode 8 of the device, while a positive voltage is applied to the gate electrode 7 and the drain electrode 9 (Vdrain > 0, Vsource = 0, Vth > Vgate > 0), where Vth is the threshold voltage when the device is turned on. When Vgate is greater than 0 but less than Vth, holes on the surface of the P-type GaN layer 4 are transferred inward under the drive of the gate voltage, and some negatively charged acceptor Mg ions appear on the channel surface. At this time, the conduction channel between the source and the drain is still closed, and the device is in the blocking state. As Vgate continues to increase, when Vgate is greater than Vth (Vdrain > 0, Vsource = 0, Vgate > Vth), with the downward bending of the energy band on the surface of the P-type GaN layer 4, a large number of minority carriers (electrons) appear on the side surface of the P-type GaN layer 4, forming an electron accumulation layer, that is, a strong inversion state appears. At this time, the part of the P-type GaN layer 4 close to the gate is equivalent to N-type, thus forming a current path between the third N-type GaN layer 5 and the second N-type GaN layer 3. Therefore, under the action of the forward-biased drain electrode 9, electrons enter the inversion channel from the third N-type GaN layer 5, then flow into the lower second N-type GaN layer 3 in a direction perpendicular to the substrate layer 1 and are finally collected by the drain electrode 9, forming an output current between the source and the drain.

[0061] The MOSFET device based on NiO gate modulation provided in this embodiment depletes the interface states of the second N-type GaN layer 3 and the electrons on the surface of the second N-type GaN layer 3 through the NiO modulation layer 10, generates a depletion region, broadens the electric field distribution range of the device, reduces the peak electric field intensity of the device, and improves the breakdown voltage level of the device.

[0062] Embodiment 2

[0063] Please refer to Figures 2a to 2i , Figures 2a to 2i which is a schematic diagram of the steps of a preparation method of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0064] A preparation method of a MOSFET device based on NiO gate modulation provided in this embodiment includes the following steps:

[0065] S1: Obtain a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4, and a third N-type GaN layer 5 sequentially arranged from bottom to top.

[0066] Specifically, as Figure 2a shown, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3, with a thickness of 1 - 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 15 ~2×10 16 cm -3 , with a thickness of 3 - 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3 , with a thickness of 200 - 350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 - 300 nm.

[0067] S2: Etch both ends of the third N-type GaN layer 5 to form gate steps extending from both ends of the upper surface of the third N-type GaN layer 5 into the second N-type GaN layer 3.

[0068] Specifically, as Figure 2b shown, etch both ends of the third N-type GaN layer 5 through an inductively coupled plasma (ICP) process. Among them, the etch gas is BCl 3 / Cl 2 , and the etch depth is 600 - 900 nm to completely etch away both ends of the P-type GaN layer 4 and the third N-type GaN layer 5, so that the bottom of the gate step is inside the second N-type GaN layer 3. In this embodiment, the length of each gate step is 2 - 10 μm.

[0069] S3: Prepare a gate structure on the upper surface of the third N-type GaN layer 5, the side walls of the gate steps, and the bottom of the gate steps.

[0070] In this embodiment, step S3 includes:

[0071] S301: As Figure 2c shown, grow Al 2 O 3 with a thickness of 45 - 55 nm on the bottom of the gate step, the side walls of the gate step, and the surface of the third N-type GaN layer 5 through an atomic layer deposition (ALD) process to form a gate dielectric layer 6. The length of the gate dielectric layer 6 at the bottom of the gate step is 0.1 - 6 μm.

[0072] S302: As Figure 2d shown, sputter Ni / Au on the surface of the gate dielectric layer 6 at both ends of the upper surface of the third N-type GaN layer 5, and on the surface of the gate dielectric layer 6 at the bottom and side walls of the gate step to form a gate electrode 7. Among them, the thickness of Ni is 30 - 50 nm, and the thickness of Au is 300 - 450 nm.

[0073] S302: As shown in Figure 2e , the gate dielectric layer 6 not covered by the gate electrode 7 is removed by ICP etching. Among them, the etching gas is CF 4 gas. The gate dielectric layer 6 and the gate electrode 7 form a gate structure.

[0074] S4: Etching is performed on the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5.

[0075] Specifically, as shown in Figure 2f , through the ICP process, etching is performed at the center of the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. Among them, the etching gas is BCl 3 / Cl 2 , and the etching depth is 200 - 300 nm.

[0076] S5: A source electrode 8 is prepared in the source groove, and a drain electrode 9 is prepared on the upper surfaces of the first N-type GaN layers 2 on both sides of the second N-type GaN layer 3; there is a gap between the drain electrode 9 and the second N-type GaN layer 3. The distance between the drain electrode 9 and the second N-type GaN layer 3 is 7 - 10 μm.

[0077] Specifically, as shown in Figure 2g , through the ICP process, both ends of the second N-type GaN layer 3 are etched away to form a drain groove, and through the ICP process, both ends of the first N-type GaN layer 2 are etched away to form a device isolation region. As shown in Figure 2h , Ti / Al / Ni / Au is evaporated in the source groove and the drain groove. Among them, the thickness of Ti is 20 - 30 nm, the thickness of Al is 140 - 180 nm, the thickness of Ni is 40 - 60 nm, and the thickness of Au is 30 - 50 nm. In this embodiment, the distance between the drain electrode 9 and the second N-type GaN layer 3 is 7 - 10 μm, the etching depth of the drain groove is 4 - 6 μm, and the etching depth of the device isolation region is 1 - 2 μm.

[0078] S6: A NiO modulation layer 10 is prepared on the bottom of the gate step, the side surface of the second N-type GaN layer 3, and the upper surface of the first N-type GaN layer 2.

[0079] In this embodiment, the specific steps of step S6 include:

[0080] Using a magnetron sputtering process, P-type NiO with a thickness of 100 - 200 nm is sputtered on the bottom of the gate step, the side surface of the second N-type GaN layer 3, and the upper surface of the first N-type GaN layer 2 between the second N-type GaN layer 3 and the drain electrode 9 to obtain the NiO modulation layer 10. Among them, the target material for the magnetron sputtering process is nickel oxide, and the working gases are O 2 and Ar. Further, the proportion of O 2 in the working gases is 0 - 66%, and by adjusting the proportion of O 2 in the working gases, the doping concentration of the grown P-type NiO is 1.0×10 15 -1×10 18 cm -3 . The length of the NiO modulation layer 10 at the bottom of the gate step is 2 - 8 μm, the distance between the NiO modulation layer 10 on the gate step and the gate structure is 0 - 2 μm, and the length of the NiO modulation layer 10 on the upper surface of the first N-type GaN layer 2 is 5 - 8 μm.

[0081] A preparation method of a MOSFET device based on NiO gate modulation provided in this embodiment depletes the interface states of the second N-type GaN layer 3 and the electrons on the surface of the second N-type GaN layer 3 by preparing the NiO modulation layer 10 on the bottom of the gate step, the side surface of the second N-type GaN layer 3, and the upper surface of the first N-type GaN layer 2, generates a depletion region, broadens the electric field distribution range of the device, reduces the peak electric field intensity of the device, and improves the breakdown voltage level of the device. Moreover, the NiO modulation layer 10 in this embodiment can be prepared by a magnetron sputtering process, with a simple process and low production cost, meeting the production requirements.

[0082] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A MOSFET device based on NiO gate modulation, characterized in that: include: A substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4) and a third N-type GaN layer (5) are arranged in sequence from bottom to top; A gate step extending from two ends of the upper surface of the third N-type GaN layer (5) to the interior of the second N-type GaN layer (3); A gate structure extending from the upper surface of the third N-type GaN layer (5) to the bottom of the gate step; A source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); A source electrode (8), located in the source groove; a drain electrode (9) located on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3), and a gap exists between the drain electrode (9) and the second N-type GaN layer (3); A NiO modulation layer (10) extends from the bottom of the gate step to the upper surface of the first N-type GaN layer (2).

2. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The source electrode (8) extends from the source groove to the upper surface of the third N-type GaN layer (5), and there is a gap between the source electrode (8) and the gate structure.

3. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The gate structure comprises: a gate dielectric layer (6) and a gate electrode (7), wherein: The gate dielectric layer (6) extends from the upper surface of the third N-type GaN layer (5) to the bottom of the gate step; The gate electrode (7) is located on the surface of the gate dielectric layer (6).

4. A MOSFET device based on NiO gate modulation according to claim 3, characterized in that: The material of the substrate layer (1) includes one or more of Si, SiC, and sapphire; The material of the gate dielectric layer (6) includes Al2O3; The material of the gate electrode (7) includes Ni / Au; The material of the source electrode (8) includes Ti / Al / Ni / Au; The material of the drain electrode (9) includes Ti / Al / Ni / Au.

5. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The length of the gate structure located at the bottom of the gate step is 0.1-6 μm.

6. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The length of the NiO modulation layer (10) located at the bottom of the gate step is 2 to 8 μm; The length of the NiO modulation layer (10) located on the upper surface of the first N-type GaN layer (2) is 5 to 8 μm; The distance between the drain electrode (9) and the second N-type GaN layer (3) is 7 to 10 μm.

7. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The doping concentration of the first N-type GaN layer (2) is 1.0×10 19 ~1×10 20 cm -3 , thickness is 1 to 2 μm; The doping concentration of the second N-type GaN layer (3) is 1.0×10 15 ~2×10 16 cm -3 , thickness is 3-5 μm; The doping concentration of the P-type GaN layer (4) is 1.0×10 17 ~1×10 18 cm -3 , thickness is 200~350nm; The doping concentration of the third N-type GaN layer (5) is 1.0×10 19 ~1×10 20 cm -3 , thickness is 200~300nm.

8. A MOSFET device based on NiO gate modulation according to claim 1, characterized in that: The doping type of the NiO modulation layer (10) is P type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3 , thickness is 100~200nm.

9. A method for preparing a MOSFET device based on NiO gate modulation, characterized in that: The following steps are involved: S1: obtaining a substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4), and a third N-type GaN layer (5) arranged in sequence from bottom to top; S2: etching at both ends of the third N-type GaN layer (5) to form gate steps extending from both ends of the upper surface of the third N-type GaN layer (5) to the interior of the second N-type GaN layer (3); S3: preparing a gate structure on the upper surface of the third N-type GaN layer (5), the sidewall of the gate step and the bottom of the gate step; S4: etching the upper surface of the third N-type GaN layer (5) to form a source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); S5: preparing a source electrode (8) in the source groove, and preparing a drain electrode (9) on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3); a gap exists between the drain electrode (9) and the second N-type GaN layer (3); S6: Preparing a NiO modulation layer (10) at the bottom of the gate step, the side surface of the second N-type GaN layer (3), and the upper surface of the first N-type GaN layer (2).

10. The method for preparing a MOSFET device based on NiO gate modulation according to claim 9, characterized in that: The specific steps of step S6 include: A magnetron sputtering process is used to sputter P-type NiO with a thickness of 100 to 200 nm at the bottom of the gate step, the side surface of the second N-type GaN layer (3) and the upper surface of the first N-type GaN layer (2) to obtain a NiO modulation layer (10); wherein the target material of the magnetron sputtering process is nickel oxide, and the working gas is O2 and Ar.

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