Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of this specification provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate; the substrate comprises a substrate and a gate structure; the substrate is formed with a well region, a source-drain region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source-drain region and the channel region; a contact structure; the contact structure is arranged on the surface of the source-drain region; wherein an air gap located on the lightly doped region is formed between the contact structure and the gate structure. In this way, ions can be supplemented into the lightly doped region through the air gap to compensate for the loss of ions in the lightly doped region during the preparation process.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for preparing the same. Background Art

[0002] In order to achieve the target values ​​of threshold voltage Vt and off current Ioff, existing MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices usually increase the size of the gate material and the thickness of the gate sidewall, resulting in insufficient size of the contact structure (Contact, CT) in the source and drain regions.

[0003] In the related art, in order to increase the size of the contact structure of the source and drain regions, it is usually necessary to perform a process of removing the gate sidewall before manufacturing the contact structure of the source and drain regions.

[0004] However, in the process of removing the gate sidewall and subsequently forming the contact structure of the source and drain regions, due to over-etching, alignment errors, etc., the ions that have been injected into the lightly doped drain (LDD) will be damaged to a certain extent, resulting in high resistance in the channel direction of the MOSFET device, affecting the device performance. For example, in a pull-up transistor (PU), the high resistance of the MOSFET device in the channel direction can easily cause the pull-up transistor to fail under high-voltage working conditions. Summary of the invention

[0005] In view of this, multiple embodiments of the present specification are directed to providing a semiconductor structure and a method for manufacturing the same, which can reduce the impact of the loss of ions in the lightly doped region during the manufacturing process on device performance.

[0006] One embodiment of the present specification provides a semiconductor structure, comprising: a substrate; the substrate comprising a substrate and a gate structure; the substrate is formed with a well region, a source / drain region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source / drain region and the channel region; a contact structure; the contact structure is arranged on the surface of the source / drain region; wherein an air gap located on the lightly doped region is formed between the contact structure and the gate structure.

[0007] Optionally, the width of the air gap is consistent with the width of the lightly doped region.

[0008] Optionally, the contact structure includes a metal contact portion and a contact connection portion; the contact connection portion includes a bottom connection layer formed on the surface of the source and drain region, and a connection side wall located at the edges of both sides of the bottom connection layer; wherein the bottom connection layer and the connection side wall form a contact window; the metal contact portion is filled and formed in the contact window.

[0009] Optionally, the contact connection portion is made of metal silicide.

[0010] One embodiment of the present specification provides a method for preparing a semiconductor structure, the method comprising: providing a substrate; the substrate comprising a substrate and a gate structure; the substrate is formed with a well region, a source-drain doped region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source-drain doped region and the channel region; isolation sidewalls are formed on both sides of the gate structure; the isolation sidewalls are located on the lightly doped region; a contact structure in contact with the source-drain doped region is formed on the side of the isolation sidewall; and the isolation sidewalls are removed to form an air gap located on the lightly doped region between the gate structure and the contact structure.

[0011] Optionally, the step of removing the isolation spacer includes: removing the isolation spacer based on an etching process; wherein the isolation spacer has a high etching selectivity ratio relative to both the gate structure and the contact structure.

[0012] Optionally, the step of forming a contact structure on the side of the isolation side wall that contacts the source and drain doped regions includes: forming a polysilicon side wall on the side of the isolation side wall; the polysilicon side wall is located on the edge of the source and drain doped regions close to the lightly doped regions; making metal silicide on the surface of the polysilicon side wall and the source and drain doped regions to form a contact connection portion; wherein the contact connection portion includes a connection side wall formed by the polysilicon side wall, and a bottom connection layer formed by the substrate located in the source and drain regions; the bottom connection layer and the connection side wall form a contact window; and a metal contact portion is filled and set in the contact window to form the contact structure.

[0013] Optionally, the method for preparing the semiconductor structure further includes: supplementally injecting ions into the lightly doped region through the air gap.

[0014] Optionally, the step of providing a substrate includes: providing an intermediate structure; the intermediate structure includes the substrate, a gate intermediate structure formed on the surface of the channel region, and at least one layer of gate sidewall formed on the surface of the lightly doped region; wherein the gate intermediate structure includes a gate material and a gate oxide layer; removing the at least one layer of gate sidewall; forming a dielectric layer on the gate intermediate structure; and etching the dielectric layer to form the substrate.

[0015] Optionally, the step of etching the dielectric layer to form the gate structure includes: stacking a hard mask layer, at least one anti-reflective layer, and a photoresist layer on the dielectric layer; exposing and developing the photoresist layer corresponding to the position of the source and drain doping regions; forming an opening aligned with the etching position after development; wherein the width of the opening is greater than the width of the source and drain doping regions; etching the dielectric layer using the opening as a position reference; and removing the at least one anti-reflective layer and the hard mask layer to obtain the substrate.

[0016] The unexpected effect of the multiple implementations provided in this specification is that after an air gap is set between the contact structure and the gate structure on the lightly doped region, ions can be injected into the lightly doped region through the air gap to compensate for the loss of ions in the lightly doped region during the preparation process, thereby avoiding to a certain extent the high resistance in the channel direction caused by the loss of ions in the lightly doped region and reducing the impact on device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a semiconductor structure provided for one embodiment of the present specification.

[0018] Figure 2 A schematic diagram of a method for preparing a semiconductor structure provided in accordance with another embodiment of the present disclosure.

[0019] Figure 3 This is a schematic diagram of an intermediate structure in the method for preparing a semiconductor structure provided in this specification.

[0020] Figure 4 This is a schematic diagram of removing the gate sidewall in the method for preparing the semiconductor structure provided in this specification.

[0021] Figure 5 This is a schematic diagram of forming a dielectric layer in the method for preparing a semiconductor structure provided in this specification.

[0022] Figure 6 This is a schematic diagram of etching a dielectric layer in the method for preparing a semiconductor structure provided in this specification.

[0023] Figure 7A schematic diagram of a substrate formed in the method for preparing a semiconductor structure provided in this specification.

[0024] Figure 8 This is a schematic diagram of forming isolation sidewalls and polysilicon sidewalls in the method for preparing a semiconductor structure provided in this specification.

[0025] Fig. 9 This is a schematic diagram of forming a contact connection portion in the method for preparing a semiconductor structure provided in this specification.

[0026] Fig.10 This is a schematic diagram of providing a metal contact portion in the method for preparing a semiconductor structure provided in this specification.

[0027] Fig.11 This is a schematic diagram of removing the isolation sidewall in the method for preparing the semiconductor structure provided in this specification.

[0028] Fig.12 This is a schematic diagram of sealing an air gap in the method for preparing a semiconductor structure provided in this specification.

[0029] Description of reference numerals:

[0030] 10. Semiconductor structure; 11. Base; 12. Substrate; 13. Gate structure; 121. Well region; 122. Source and drain region; 123. Lightly doped region; 124. Channel region; 14. Contact structure; 15. Air gap; 16. Metal contact; 161. Transition layer; 162. Metal material; 17. Contact connection; 171. Bottom connection layer; 172. Connection sidewall; 18. Contact window; 20. Intermediate structure; 21. Gate intermediate structure; 211. Gate material; 212. Gate oxide layer; 22. Gate sidewall; 23. Dielectric layer; 24. Hard mask layer; 25. Anti-reflective coating; 251. Silicon oxynitride; 252. Silicon dioxide; 253. Bottom anti-reflective coating; 26. Photoresist layer; 27. Opening; 28. Source and drain doped region; 29. ​​Isolation sidewall; 31. Polysilicon sidewall. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of this specification will be described clearly and completely below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0032] In this specification, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0033] Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this specification embodiment and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0034] In the description of this specification, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this specification, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] In the description of this specification, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of simplified description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0036] In the description of this specification, unless otherwise clearly defined, the terms "install", "connect", "connect", "fix", "set", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0037] In the description of this specification, unless otherwise clearly defined, a first feature being “on”, “above”, “above”, “below”, “below”, “below” or “below” a second feature may mean that the first feature is in direct contact with the second feature, or the first feature and the second feature are in indirect contact with each other through an intermediate medium. Moreover, a first feature being “on”, “above” or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than the horizontal height of the second feature. A first feature being “below”, “below” or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the horizontal height of the first feature is lower than the horizontal height of the second feature.

[0038] In the preparation process of MOS devices, based on the front-end process, a well region, a gate oxide layer, a gate polysilicon, a gate sidewall, a lightly doped region, a pocket region, a source and drain region and a metal silicide can be formed.

[0039] At this time, in order to increase the size of the contact structure of the source and drain regions, it is usually necessary to perform a gate sidewall removal process and then make the contact structure. However, in the process of removing the gate sidewall and subsequently forming the contact structure of the source and drain regions, the ions that have been injected into the lightly doped drain (LDD) region will be damaged to a certain extent. Specifically, on the one hand, the gate sidewall removal process, as well as the alignment error and over-etching phenomenon in the etching process may cause damage to the doped ions in the LDD region; on the other hand, when metal silicides, such as nickel silicide (NiSi), are formed in the source and drain regions, they may interact with the doped ions in the LDD region, such as boron ions, and may also cause loss to the doped ions in the LDD region. In turn, the doping concentration in the LDD region is reduced, resulting in high resistance in the channel direction of the MOS device, which affects the performance of the MOS device. For example, due to the high resistance in the channel direction, the reliability of the MOS device under high-voltage working conditions is poor.

[0040] Therefore, it is necessary to provide a semiconductor structure that can reduce the impact of ion loss in the lightly doped region during the preparation process on device performance.

[0041] See also Figure 1. One embodiment of the present specification provides a semiconductor structure 10, which may be a MOS structure, and includes a base 11 and a contact structure 14. The base 11 includes a substrate 12 and a gate structure 13; the substrate 12 is formed with a well region 121, a source and drain region 122, and a lightly doped region 123; wherein the well region 121 includes a channel region 124; the gate structure 13 is disposed on the surface of the channel region 124; and the lightly doped region 123 is located between the source and drain region 122 and the channel region 124.

[0042] The substrate 12 can serve as the basic structure of the semiconductor structure 10, not only for providing mechanical support, but also for affecting the electrical properties of the device, such as threshold voltage and carrier mobility, by doping ions. Specifically, the substrate 12 can be made of silicon (Si), or can be made of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), etc., as required.

[0043] The gate structure 13 can be used to control the switching behavior of the MOS structure. Specifically, the gate structure 13 can be composed of a gate material and a gate oxide layer. As a gate electrode, the gate material can be polysilicon or a metal (such as aluminum Al). The gate material can be isolated from the substrate by the gate oxide layer. The gate oxide layer can specifically be silicon dioxide SiO2. In some possible embodiments, the gate structure 13 can also include a work function adjustment layer. When a voltage is applied to the gate structure 13, carriers in the channel region 124 can be attracted or repelled, thereby controlling the flow of carriers between the source and the drain.

[0044] The well region (Well) 121 is a doped region formed in the substrate 12, which can be used to isolate different types of MOS structures in the semiconductor structure 10 and provide a suitable electrical environment to ensure that the semiconductor structure 10 operates under correct working conditions. Specifically, the well region 121 can be P-type or N-type, and its type depends on the type of MOS to be constructed (such as NMOS or PMOS). The doping concentration of the well region 121 is usually higher than that of the substrate 12, but lower than that of the source and drain regions 122.

[0045] The source and drain regions (S / D) 122 are highly doped regions in the substrate 12, which are used to form the source and drain, respectively. The doping concentration of the source and drain regions 122 is usually higher than that of the substrate 12 and the well region 121 to ensure low contact resistance and good current transmission. Under working conditions, a conductive channel can be formed between the source and the drain to allow carriers to flow from the source to the drain to form a current. The high concentration doping of the source and drain regions 122 can be used to ensure a low resistance connection between the source and the drain.

[0046] The channel region 124 is located between the source and drain regions 122 on both sides of the gate structure 13. When a proper voltage is applied to the gate, the channel region 124 forms a conductive channel, thereby forming a current between the source and the drain.

[0047] The lightly doped region (LDD, Lightly Doped Drain) 123 is a low-doped region located between the source and drain regions 122 and the channel region 124, and is used to reduce the electric field strength between the source and drain regions 122 and the channel, which can reduce the rate of electron and hole injection, thereby reducing the hot carrier effect and improving the reliability of the MOS structure. The doping concentration of the lightly doped region 123 is lower than that of the source and drain regions 122, but higher than that of the well region 121.

[0048] The contact structure 14 is used to establish an electrical connection between the source and drain regions 122 and an external circuit. The contact structure 14 is arranged on the surface of the source and drain regions 122. The contact structure 14 can be formed by depositing one or more layers of metal. Specifically, the metal used to form the contact structure 14 may include aluminum (Al), copper (Cu), tungsten (W) or other alloys. In some embodiments, the contact structure 14 may also include a metal silicide located between the metal layer and the substrate 12. The metal silicide can be used as a contact connection between the metal layer and the substrate 12 to reduce the contact resistance. Specifically, the metal silicide may be nickel silicide NiSi, or may be titanium silicide TiSi2, cobalt silicide CoSi2, etc.

[0049] In this embodiment, an air gap 15 is formed between the contact structure 14 and the gate structure 13 and is located on the surface of the lightly doped region 123. Specifically, perpendicular to the surface direction of the substrate 12, the air gap 15 corresponds to a region on the substrate 12 that overlaps with the lightly doped region 123. In some possible embodiments, the air gap 15 corresponds to a region on the substrate 12 that partially overlaps with the lightly doped region 123.

[0050] The unexpected effect of this embodiment is that after the contact structure 14 is completed, the consumed doping ions can be replenished into the lightly doped region 123 through the air gap 15 to maintain the original ion concentration of the lightly doped region 123, thereby avoiding high resistance in the channel direction due to ion loss in the lightly doped region 123, thereby affecting the performance of the semiconductor structure 10. In addition, the air gap 15 has a smaller dielectric constant K, which can reduce RC delay.

[0051] At the same time, in the related art, since the gate sidewall is removed, the enlarged contact structure will directly contact part of the lightly doped area, and the alignment error when making the contact structure will also cause the contact structure to directly contact part of the lightly doped area, which will also increase the resistance in the channel direction. By providing an air gap 15 on the lightly doped area 123, it is also possible to reduce or avoid direct contact between the contact structure 14 and the lightly doped area 123.

[0052] To illustrate the technical effect of this embodiment, this specification also provides the simulation data of Table 1 as follows:

[0053]

[0054] Table 1

[0055] In Table 1, the parameters in the columns "LDD ion implantation" and "S / D ion implantation" represent the ion type, energy, and dose implanted in the LDD region and S / D region, respectively. The data in the columns "Z depth" and "Y channel" represent the depth of etching in the Z direction and Y direction, respectively. Vt, Idsat, and Ioff represent the threshold voltage, saturation current, and off current of PMOS, respectively.

[0056] From the data in Table 1, it can be seen that in the case of Schottky contact, as the etching damage to the ion-doped area increases, Idsat decreases. However, by increasing the ion implantation dose in the LDD area and S / D area (the black data in Table 1), Idsat can be increased.

[0057] Optionally, the width of the air gap 15 is consistent with the width of the lightly doped region 123. Specifically, taking the 40nm process node as an example, the width of the air gap 15 ranges from 10nm to 20nm. For example, the width of the air gap 15 can be 10nm or 20nm, or 15nm. It should be noted that, in some possible implementations, the width of the air gap 15 can also be different from the width of the lightly doped region 123, for example, greater than or less than the width of the lightly doped region 123.

[0058] In this embodiment, the contact structure 14 includes a metal contact portion 16 and a contact connection portion 17; the contact connection portion 17 includes a bottom connection layer 171 formed on the surface of the source and drain region 122, and a connection side wall 172 located at the two side edges of the bottom connection layer 171; wherein the bottom connection layer 171 and the connection side wall 172 form a contact window 18; the metal contact portion 16 is formed in the contact window 18.

[0059] The material of the contact connection portion 17 may be metal silicide. Optionally, the contact connection portion 17 is made of nickel silicide.

[0060] The contact window 18 formed by the bottom connection layer 171 and the connection spacer 172 wraps the metal contact portion 16 , which can further reduce the contact resistance compared to only providing the bottom connection layer 171 on the surface of the drain and source regions.

[0061] The metal contact portion 16 is composed of a metal material 162, such as tungsten (W), and a transition layer 161 disposed on the surface of the contact connection portion 17 facing the metal material 162. The transition layer 161 can be made of titanium (Ti) and titanium nitride (TiN), and is used as a barrier and a buffer between the metal material 162 and the contact connection portion 17 to improve the contact performance.

[0062] It should be noted that, in some possible implementations, the contact structure 14 may not include the contact connection portion 17 .

[0063] Optionally, the thickness of the connecting sidewall 172 ranges from 5 nm to 15 nm. Specifically, taking the 40 nm process node as an example, the thickness of the connecting sidewall 172 can be 5 nm, 15 nm, or 10 nm.

[0064] See also Figure 2-Figure 12 One embodiment of the present specification provides a method for preparing a semiconductor structure, and the method may include the following steps.

[0065] S110: Provide a substrate 11; the substrate 11 includes a substrate 12 and a gate structure 13; the substrate 12 is formed with a well region 121, a source-drain doped region 28 and a lightly doped region 123; wherein the well region 121 includes a channel region 124; the gate structure 13 is arranged on the surface of the channel region 124; the lightly doped region 123 is located between the source-drain doped region 28 and the channel region 124.

[0066] Please refer to Figure 7 In this embodiment, the source-drain doping region 28 may include a source-drain region 122. Compared with the source-drain region 122 in the previous embodiment, a bottom connection layer 171 is not formed in the region close to the surface. Other specific structures of the substrate 11 can be explained with reference to the previous embodiment, and will not be repeated here.

[0067] In some embodiments, the step of providing the substrate 11 includes: providing an intermediate structure 20; the intermediate structure 20 includes the substrate 12, a gate intermediate structure 21 formed on the surface of the channel region 124, and at least one layer of gate spacer 22 formed on the surface of the substrate 12; wherein the gate intermediate structure 21 includes a gate material 211 and a gate oxide layer 212; removing the at least one layer of gate spacer 22; forming a dielectric layer 23 on the intermediate structure 20; etching the dielectric layer 23 to form the substrate 11. The remaining portion of the dielectric layer 23 after etching and the gate intermediate structure 21 form the gate structure 13 in the substrate 11.

[0068] refer to Figure 3 . In some embodiments, the intermediate structure 20 can be obtained through a MOS front-end process. As an example, the front-end process may specifically include AA (Active Area), STI (Shallow Trench Isolation), NW (N-well), PW (P-well), GOX (Gate Oxide), Poly (Polysilicon), Spacer (gate sidewall), LDD, Pocket (pocket area), S / D (Source and Drain), etc.

[0069] Optionally, the width of the gate material 211 may be 55 nm.

[0070] In some embodiments, the number of layers of at least one gate sidewall 22 may be two. Specifically, each gate sidewall 22 may be composed of a layer of silicon dioxide and a layer of silicon nitride. At least one gate sidewall 22 is away from the outer edge of the gate material 211 and may be aligned with the boundary between the lightly doped region 123 and the source-drain doped region 28. Optionally, the total thickness of at least one gate sidewall 22 is 30 nm.

[0071] In some embodiments, for Figure 3 The structure shown in FIG. 1 can be completely removed by etching the gate sidewall 22 to obtain Figure 4 The structure shown.

[0072] refer to Figure 5 In some embodiments, for Figure 4 The structure shown may be subjected to oxide deposition, planarization based on a CMP process, and then 600Å TEOS deposition to form a dielectric layer 23 on the intermediate structure 20. Optionally, the thickness of the dielectric layer 23 is retained to be 2100Å.

[0073] In some embodiments, the step of etching the dielectric layer 23 to form the substrate 11 may include: stacking a hard mask layer 24, at least one anti-reflective coating layer 25, and a photoresist layer 26 on the dielectric layer 23; exposing and developing the photoresist layer 26 corresponding to the position of the source and drain doping regions 28; after development, the photoresist layer 26 forms an opening 27 aligned with the etching position; wherein the width of the opening 27 is greater than the width of the source and drain doping regions 28; using the opening 27 as a position reference, etching the dielectric layer 23; removing the at least one anti-reflective coating layer 25 and the hard mask layer 24 to obtain the substrate 11.

[0074] Specifically, refer to Figure 6 As an example, we can Figure 5 The structure shown in the figure is deposited in sequence: amorphous carbon with a thickness of 1900Å as a hard mask layer 24, silicon oxynitride 251 (SiON) with a thickness of 320Å, silicon dioxide 252 (OX) with a thickness of 50Å, and bottom anti-reflective coating 253 (BARC) with a thickness of 200Å as an anti-reflective coating 25, and then a photoresist layer 26 with a thickness of 1000Å is coated on the top. In this way, light reflection and standing wave effects in the photolithography process can be reduced, photolithography errors can be reduced, photolithography accuracy can be improved, and the accuracy of pattern transfer in the etching process can be improved.

[0075] Next, the photoresist layer 26 is exposed and developed to form a Figure 6 In the structure shown, after the photoresist layer 26 is developed, an opening 27 corresponding to the position of the source-drain doped region 28 is formed, and the opening 27 can be used to define the size of the contact structure 14. In order to increase the size of the contact structure 14, the width of the opening 27 needs to be greater than the width of the source-drain doped region 28. Specifically, for example, the width of the opening 27 can be 90nm, and of course it can also be 80nm, 100nm, etc., and can be flexibly set according to actual needs.

[0076] Finally, after multiple etching processes, we can get Figure 7 The substrate 11 shown in the figure, wherein after at least one layer of the anti-reflection coating 25 and the hard mask layer 24 are removed, the remaining portion of the dielectric layer 23 after etching and the gate intermediate structure 21 together form the gate structure 13 in the substrate 11 .

[0077] It should be noted that, in some possible implementations, the substrate 11 may be obtained by other etching processes or by directly etching the dielectric layer 23 formed on the intermediate structure 20. This specification does not specifically limit this.

[0078] S120 : forming isolation spacers 29 on both sides of the gate structure 13 ; the isolation spacers 29 are located on the lightly doped region 123 .

[0079] refer to Figure 8 In this embodiment, it is possible to Figure 7 In the structure shown, a certain thickness of SiN is deposited on the side of the dielectric layer 23 corresponding to the surface of the lightly doped area, and the thickness may be 15 nm to form the isolation sidewall 29, which may be used as an isolation layer when making the contact structure 14. It should be noted that the material used to form the isolation sidewall 29 is not limited to SiN, and may also be other materials used for interlayer isolation. For example, in some possible implementations, materials such as silicon oxynitride or silicon carbide may also be used to form the isolation sidewall 29. This specification does not specifically limit this.

[0080] S130 : forming a contact structure 14 on the side of the isolation spacer 29 , the contact structure 14 being in contact with the source / drain doped region 28 .

[0081] refer to Figure 8-Figure 10 In some embodiments, the step of forming a contact structure 14 on the side of the isolation sidewall 29 that contacts the source-drain doped region 28 may include: forming a polysilicon sidewall on the side of the isolation sidewall 29; the polysilicon sidewall is located on the edge of the source-drain doped region 28 close to the lightly doped region 123; making metal silicide on the surface of the polysilicon sidewall and the source-drain doped region 28 to form a contact connection portion 17; wherein the contact connection portion 17 includes a connection sidewall 172 formed by the polysilicon sidewall and a bottom connection layer 171 formed by the substrate 12 located in the source-drain region 122; the bottom connection layer 171 and the connection sidewall 172 form a contact window 18; and filling and setting a metal contact portion 16 in the contact window 18 to form the contact structure 14.

[0082] Specifically, after forming the isolation sidewall 29, a certain thickness of polysilicon may be deposited on the side of the isolation sidewall 29 away from the gate material 211 to form a polysilicon sidewall 31. The thickness may be 10 nm. Then, the excess SiN and polysilicon in the active area are removed by self-alignment technology to obtain the following: Figure 8 It should be noted that the polysilicon sidewalls 31 are used to form the connecting sidewalls 172 in the contact structure 14, so in some possible implementations, the polysilicon sidewalls 31 may not be provided.

[0083] Next, the source and drain doping regions 28 are used for alignment, and metal silicide is formed on the surface of the polysilicon sidewalls 31 and the source and drain doping regions 28. Specifically, as an example, a pre-cleaning can be performed to remove the natural oxide layer on the surface, and 120Å of NiPt alloy and 50Å of TiN are deposited in sequence, and then a first RTP (Rapid Thermal Processing) is performed to form a high-resistance metal silicide Ni2PtSi (temperature is 290 degrees, duration is 30 seconds), and then a second RTP is performed to form a low-resistance NiPtSi2, and finally the Ni that does not participate in the reaction in the area where NiPtSi2 is not formed is removed, and the following is obtained: Fig. 9 It should be noted that in Fig. 9 In the structure shown, since metal silicide is formed in a portion of the source / drain doping region 28 close to the surface, the remaining region of the source / drain doping region 28 forms the source / drain region 122 .

[0084] Then, a metal contact portion 16 is formed in the contact window 18 formed by the metal silicide. Specifically, as an example, a layer of titanium (Ti) with a thickness of 100Å and a layer of titanium nitride (TiN) with a thickness of 50Å are deposited by physical vapor deposition (PVD), and then a layer of tungsten (W) is deposited by chemical vapor deposition (CVD) and planarized by chemical mechanical polishing (CMP), and the following is obtained: Fig.10 In this way, the metal contact portion 16 is entirely wrapped by the metal silicide, thereby reducing the RC delay.

[0085] S140 : removing the isolation spacer 29 to form an air gap 15 between the gate structure 13 and the contact structure 14 and located on the lightly doped region 123 .

[0086] Specifically, the isolation sidewall 29 can be removed based on an etching process, such as dry etching, wet etching, etc., to obtain Fig.11 The structure shown.

[0087] In some embodiments, the step of removing the isolation spacer 29 includes: removing the isolation spacer 29 based on an etching process; wherein the isolation spacer 29 has a high etching selectivity ratio relative to both the gate structure 13 and the contact structure 14 .

[0088] Specifically, in order to avoid damaging the gate structure 13 and the contact structure 14 on both sides of the isolation sidewall 29 during the etching process, such as etching away part of the connecting sidewall 172 adjacent to the isolation sidewall 29 and thus damaging the contact structure 14, the isolation sidewall 29 can be made to have a high etching selectivity relative to the gate structure 13 and the contact structure 14 by selecting the material of the isolation sidewall 29 and the specific etching process, so that only the isolation sidewall 29 is etched during the etching process. For example, the material of the isolation sidewall 29 can be silicon nitride, and accordingly, wet etching can be used to remove the isolation sidewall 29 using phosphoric acid as an etchant. For another example, the material of the isolation sidewall 29 can also be amorphous carbon, and accordingly, based on the Asher process, the isolation sidewall 29 can be oxidized into gas by using oxygen or ozone under certain temperature conditions (170°C to 330°C) to remove the isolation sidewall 29. Of course, the material of the isolation sidewall 29 and the specific etching process can also be flexibly selected according to the material of the gate structure 13 and the contact structure 14. This specification does not make specific restrictions on this. It is sufficient to enable the isolation sidewall 29 to achieve a high etching selectivity ratio relative to both the gate structure 13 and the contact structure 14.

[0089] In some embodiments, the etching ratio of the isolation spacer 29 to the gate structure 13 and the contact structure 14 may be greater than 10:1. For example, the etching ratio may be 100:1. Of course, in some embodiments, the etching ratio may also be 1:0 to prevent the gate structure 13 and the contact structure 14 from being damaged by etching.

[0090] In this embodiment, since the gate sidewall is removed at the beginning of the provided process flow, the difficulty of the subsequent process of manufacturing the contact structure can be reduced, for example, the difficulty of the patterning and etching process is reduced. At the same time, the process flow provided in this embodiment can avoid the short circuit problem between the contact structure and the gate caused by the self-alignment error, so that the difficulty of the self-alignment process is reduced.

[0091] In some embodiments, the method for preparing the semiconductor structure may further include: supplementally injecting ions into the lightly doped region 123 through the air gap 15 .

[0092] An unexpected effect is that after an air gap 15 located on the lightly doped region 123 is set between the contact structure 14 and the gate structure 13, ions can be replenished into the lightly doped region 123 through the air gap 15 to compensate for the loss of ions in the lightly doped region 123 during the preparation process, thereby avoiding to a certain extent the high resistance in the channel direction caused by the loss of ions in the lightly doped region 123 and reducing the impact on device performance.

[0093] In some embodiments, the method for preparing the semiconductor structure may further include: performing a sealing process on the air gap 15 on the surfaces of the gate structure 13 and the contact structure 14 facing away from the substrate 12 .

[0094] Specifically, as an example, after the lightly doped region 123 is supplemented with ions, SiCN may be deposited on the surface of the gate structure 13 and the contact structure 14 away from the substrate 12 to seal the air gap 15. Since the width of the air gap 15 is small, such as Fig.11 The thickness of the SiCN layer is only 15nm, so the rapid sealing technology of PVD can be used to generate SiCN to form Fig.12 The structure shown.

[0095] An embodiment of the present specification provides a pull-up transistor, comprising the semiconductor structure described in any of the foregoing embodiments.

[0096] In this embodiment, the pull-up transistor is used to provide the current required to pull the output node to a high level, ensuring that the output node can drive subsequent circuits or loads. Specifically, for example, the pull-up transistor can be composed of PMOS. In a CMOS logic circuit, the pull-up transistor can form a pull-up network and work complementary to the pull-down network (composed of NMOS transistors).

[0097] It should be understood that the specific examples herein are only intended to help those skilled in the art to better understand the embodiments of the present specification, rather than to limit the scope of the present invention.

[0098] It can be understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.

[0099] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.

[0100] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0101] The above is only a specific implementation of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; The base comprises a substrate and a gate structure; the substrate is formed with a well region, a source-drain region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on the surface of the channel region; the lightly doped region is located between the source-drain region and the channel region; A contact structure; the contact structure is arranged on the surface of the source and drain regions; the contact structure comprises a metal contact portion and a contact connection portion; the contact connection portion comprises a bottom connection layer formed on the surface of the source and drain regions, and connection sidewalls located at both side edges of the bottom connection layer; wherein the bottom connection layer and the connection sidewalls form a contact window; the metal contact portion is formed in the contact window; An air gap located on the lightly doped region is formed between the contact structure and the gate structure; the air gap is used for supplementary ion injection into the lightly doped region.

2. The semiconductor structure according to claim 1, characterized in that: The width of the air gap is consistent with the width of the lightly doped region.

3. The semiconductor structure according to claim 1, characterized in that: The material of the contact connection portion is metal silicide.

4. A method for preparing a semiconductor structure, characterized in that: The method for preparing the semiconductor structure comprises: A substrate is provided; the substrate comprises a substrate and a gate structure; the substrate is formed with a well region, a source-drain doped region and a lightly doped region; wherein the well region comprises a channel region; the gate structure is arranged on a surface of the channel region; the lightly doped region is located between the source-drain doped region and the channel region; Isolation sidewalls are formed on both sides of the gate structure; the isolation sidewalls are located on the lightly doped region; A polysilicon sidewall is formed on the side of the isolation sidewall; the polysilicon sidewall is located on the edge of the source and drain doping region close to the lightly doped region; Metal silicide is fabricated on the surface of the polysilicon sidewalls and the source-drain doped regions to form a contact connection portion; wherein the contact connection portion comprises a connection sidewall formed by the polysilicon sidewalls and a bottom connection layer formed by a substrate located in the source-drain doped regions; the bottom connection layer and the connection sidewalls form a contact window; Filling and disposing a metal contact portion in the contact window to form a contact structure; The isolation sidewall is removed to form an air gap located on the lightly doped region between the gate structure and the contact structure; the air gap is used to supplement ion injection into the lightly doped region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of removing the isolation sidewall includes: The isolation spacer is removed based on an etching process; wherein the isolation spacer has a high etching selectivity ratio relative to both the gate structure and the contact structure.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that: The method for preparing the semiconductor structure further comprises: Ions are additionally implanted into the lightly doped region through the air gap.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that: The step of providing a substrate comprises: Providing an intermediate structure; the intermediate structure comprises the substrate, a gate intermediate structure formed on the surface of the channel region, and at least one layer of gate sidewall formed on the surface of the substrate; wherein the gate intermediate structure comprises a gate material and a gate oxide layer; Removing the at least one layer of gate sidewall; forming a dielectric layer on the intermediate structure; The dielectric layer is etched to form the substrate.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of etching the dielectric layer to form the substrate comprises: A hard mask layer, at least one anti-reflective coating layer, and a photoresist layer are stacked on the dielectric layer; Corresponding to the position of the source and drain doped regions, the photoresist layer is exposed and developed; after the development, the photoresist layer forms an opening aligned with the etching position; wherein the width of the opening is greater than the width of the source and drain doped regions; Using the opening as a position reference, etching the dielectric layer; The at least one anti-reflective coating layer and the hard mask layer are removed to obtain the substrate.

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