Semiconductor device and manufacturing method thereof, and electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the method comprising: providing a semiconductor substrate; forming a first control gate and a floating gate on the semiconductor substrate, the floating gate being connected to the first control gate via a gate sidewall, and a gap being provided between adjacent floating gates; performing ion implantation to form a first ion implantation region in the semiconductor substrate below the gap; forming a filler in the gap, the material of the filler comprising silicon nitride and silicon oxynitride; forming a second control gate above the first control gate and the floating gate; and removing the filler. The present invention uses a composite material of silicon nitride and silicon oxynitride as a filler between floating gates, which is beneficial to controlling the etching rate of the filler and can effectively avoid etching residues of the filler.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Flash memory devices have been widely used as the best choice for non-volatile memory applications due to their high density, low price, electrically programmable and easy erasable advantages. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced using existing technology nodes. At the same time, as new technology nodes become increasingly mature, flash memory units are also urged to be produced using high-node technology. This means that the size of the flash memory unit needs to be reduced. However, reducing the active area width and channel length of the flash memory unit will affect the performance of the flash memory unit.

[0003] The existing technology nodes mainly use process optimization to compensate for the size reduction. At present, the vertical reduction of Flash is mainly carried out by reducing the distance between adjacent control gates and the filling conditions between subsequent control gates. In Flash technology, the source self-alignment technology (Self-align-source) proposed to increase the density of flash memory cells uses the control gate of flash memory as the basis for alignment. This source self-alignment technology makes the depth between control gates relatively high, the environment is complex, and it is easy to produce filler residues, which affects the filling of subsequent interlayer dielectric layers. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] providing a semiconductor substrate;

[0007] forming a first control gate and a floating gate on the semiconductor substrate, wherein the floating gate is connected to the first control gate via a gate sidewall, and gaps are provided between adjacent floating gates;

[0008] performing ion implantation to form a first ion implantation region in the semiconductor substrate below the gap;

[0009] forming a filler in the gap, wherein the material of the filler comprises silicon nitride and silicon nitride oxide;

[0010] forming a second control gate over the first control gate and the floating gate;

[0011] The filler is removed.

[0012] In some embodiments, forming a first control gate and a floating gate on the semiconductor substrate includes:

[0013] forming a first gate material layer on the semiconductor substrate;

[0014] Etching the first gate material layer to form the first control gate;

[0015] forming a gate spacer on the sidewall of the first control gate;

[0016] forming a second gate material layer between adjacent first control gates;

[0017] The gaps are etched in the second gate material layer to form the floating gates separated by the gaps.

[0018] In some embodiments, before forming the second gate material layer between adjacent first control gates, the method further includes:

[0019] Ion implantation is performed on the semiconductor substrate to form a second ion implantation region in the semiconductor substrate between adjacent first control gates, wherein the depth of the second ion implantation region is greater than the depth of the first ion implantation region.

[0020] In some embodiments, before forming the first control gate and the floating gate, the method further includes:

[0021] A first gate dielectric layer is formed on the semiconductor substrate.

[0022] In some embodiments, after forming a filler in the gap and before forming a second control gate over the first control gate and the floating gate, the method further includes:

[0023] A second gate dielectric layer is formed over the first control gate, the floating gate, and the filler.

[0024] In some embodiments, removing the filler comprises:

[0025] In some embodiments, the etchant used in the wet etching process includes hydrofluoric acid and phosphoric acid.

[0026] In some embodiments, a gate hard mask layer is formed above the first control gate.

[0027] A second aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method described above.

[0028] A third aspect of an embodiment of the present invention provides an electronic device, the electronic device comprising the semiconductor device as described above,

[0029] According to the method for manufacturing a semiconductor device provided by the present invention, a composite material of silicon nitride and silicon oxynitride is used as a filler between floating gates, which is beneficial for controlling the etching rate of the filler and can effectively avoid etching residues of the filler. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0031] Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0032] FIG. 2A to FIG. 2F The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0033] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0034] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In view of the existence of the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, it mainly includes the following steps:

[0039] In step S101, a semiconductor substrate is provided;

[0040] In step S102, a first control gate and a floating gate are formed on the semiconductor substrate, wherein the floating gate is connected to the first control gate via a gate spacer, and a gap is provided between adjacent floating gates;

[0041] In step S103, ion implantation is performed to form a first ion implantation region in the semiconductor substrate below the gap;

[0042] In step S104, a filler is formed in the gap, wherein the material of the filler includes silicon nitride and silicon oxynitride;

[0043] In step S105, a second control gate is formed above the first control gate and the floating gate;

[0044] In step S106, the filler is removed.

[0045] The method for manufacturing a semiconductor device provided by an embodiment of the present invention uses a composite material of silicon nitride and silicon oxynitride as a filler between floating gates, thereby facilitating control of the etching rate of the filler and effectively avoiding etching residues of the filler.

[0046] Embodiment 1

[0047] Below, reference FIG. 2A to FIG. 2F A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: FIG. 2A to FIG. 2F The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0048] First, if Figure 2A As shown, a semiconductor substrate 200 is provided, and the material of the semiconductor substrate 200 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI). As an example, in this embodiment, the semiconductor substrate 200 is made of single crystal silicon material.

[0049] Exemplarily, the semiconductor substrate 200 includes a storage area and a logic area. Figure 2AThe storage area of ​​the semiconductor substrate is shown. Subsequent structures such as the first control gate, the second control gate and the floating gate are formed in the storage area. The storage area further includes an active area and an isolation area, and the isolation area is formed with a shallow trench isolation structure 201, and the active area is located between adjacent shallow trench isolation structures 201. Exemplarily, the semiconductor substrate 200 is etched to form a shallow trench, an isolation material is filled into the shallow trench, and a planarization process is performed to remove the isolation material outside the shallow trench, thereby forming a trench isolation structure 201. Next, ions are implanted into the semiconductor substrate 200 to adjust the threshold voltage (Vt), thereby forming an active area.

[0050] Next, continue to refer to Figure 2A , a plurality of first control gates 203 are formed on the semiconductor substrate 200. Specifically, a first gate material layer can be formed on the semiconductor substrate 200, and the first gate material layer can be etched to form the first control gate 203. The first gate material layer can be a polysilicon layer, and its formation method includes but is not limited to chemical vapor deposition. A gate hard mask layer 204 is formed above the first control gate 203. The gate hard mask layer 204 is deposited before polysilicon etching, and serves as a hard mask layer for gate etching and can protect the first control gate 203 from being lost in subsequent processes. The gate hard mask layer 204 includes a silicon nitride layer, a silicon oxide layer, and the like.

[0051] Before forming the first control gate 203 , a first gate dielectric layer 202 is formed on the semiconductor substrate 200 . The first gate dielectric layer 202 includes a silicon oxide layer or other dielectric layer. The formation method thereof includes thermal oxidation, chemical vapor deposition, and the like.

[0052] Then, if Figure 2B As shown, a gate spacer 205 is formed on the sidewall of the first control gate 203. Specifically, a spacer material layer covering the first control gate 203 and the first gate dielectric layer 202 may be deposited, and the spacer material layer may be etched to remove the spacer material layer located above the first control gate 203 and the first gate dielectric layer 202, and only the spacer material layer located on the sidewall of the first control gate 203, i.e., the gate spacer 205, is retained.

[0053] Next, ion implantation is performed to form a second ion implantation region 206 in the semiconductor substrate 200 between adjacent first control gates 203. Since the distance between adjacent first control gates 203 on the active region is relatively large, after the gate spacers 205 are formed, the spacing between adjacent gate spacers 205 is relatively large, so that ions can be implanted into the semiconductor substrate 200. In comparison, the distance between the first control gate 203 on the active region and the first control gate 203 on the isolation region is relatively small, and there is no spacing between the two after the gate spacers 205 are formed, so an ion implantation region will not be formed in the semiconductor substrate 200 here.

[0054] Then, if Figure 2C As shown, a second gate material layer 207 is formed between adjacent first control gates 203. The second gate material layer 207 may be a polysilicon layer, and its formation method includes but is not limited to chemical vapor deposition. Exemplarily, before forming the second gate material layer 207, the gate sidewall 205 may be etched back to reduce the thickness of the gate sidewall 205.

[0055] Then, if Figure 2D As shown, a gap is etched in the second gate material layer 207 to form a floating gate 207' separated by the etched gap. The floating gate 207' is formed on the sidewall of the first control gate 203, and the first control gate 203 and the floating gate 207' are separated by the gate spacer 205. The first control gate 203 and the floating gate 207' are substantially at the same height.

[0056] For example, a patterned photoresist layer may be formed on the second gate material layer 207 , wherein the photoresist layer has an opening corresponding to the gap to be formed. Then, the second gate material layer 207 is etched using the photoresist layer as a mask to form a gap exposing the first gate dielectric layer 202 .

[0057] Next, ion implantation is performed again to form a first ion implantation region 208 in the semiconductor substrate 200 below the gap, and the first ion implantation region 208 is a source implantation region. Exemplarily, the first ion implantation region 208 is formed in the second ion implantation region 206, and the depth of the first ion implantation region 208 is less than the depth of the second ion implantation region 206. The first ion implantation region 208 and the second ion implantation region 206 together constitute a common source.

[0058] Then, if Figure 2E As shown, a filler 209 is formed in the gap, and the material of the filler 209 includes silicon nitride and silicon oxynitride. In the embodiment of the present invention, a composite material of silicon nitride and silicon oxynitride is used as the filler 209, and the etching rate of the filler 209 can be controlled by adjusting the ratio of silicon nitride and silicon oxynitride to avoid etching residue when removing the filler 209.

[0059] After forming the filling, a second gate dielectric layer 210 is formed on the first control gate 203, the floating gate 207' and the filling 209. The second gate dielectric layer 210 includes a silicon oxide layer or other dielectric layer, and its formation method includes thermal oxidation method, chemical vapor deposition method and the like.

[0060] Next, a second control gate 211 is formed above the first control gate 203 and the floating gate 207'. The second control gate 211 is partially located above the first control gate 203, and partially located above the floating gate 207'. Specifically, the second control gate 211 is formed on the second gate dielectric layer 210, and the second gate dielectric layer 210 and the gate hard mask layer 204 are spaced between the second control gate 211 and the first control gate 203, and the second gate dielectric layer 210 is spaced between the second control gate 211 and the floating gate 207'.

[0061] Then, if Figure 2F As shown, the filler 209 is removed. Before removing the filler 209, the second gate dielectric layer 210 not covered by the second control gate 211 can be removed first, so as to expose the filler 209 under the second gate dielectric layer 210, and then the filler 209 can be removed by a wet etching process. The etchant used in the wet etching process is an etchant for silicon nitride and silicon oxynitride, for example, a mixture of hydrofluoric acid and phosphoric acid. Since the filler 209 is a composite material of silicon nitride and silicon oxynitride, the etching rate can be controlled by adjusting the ratio of silicon nitride and silicon oxynitride.

[0062] Exemplarily, in addition to the storage area, the semiconductor substrate also includes a logic area for forming peripheral logic devices. Usually, the step of removing the storage area filler is performed simultaneously with the step of removing the logic area gate hard mask layer. However, the thickness of the storage area filler is relatively thick, and the thickness of the logic area gate hard mask layer is relatively thin. Therefore, after removing the logic area gate hard mask layer, the storage area filler has not been completely removed; and in order to avoid damaging other device structures in the logic area, it is impossible to avoid etching residues in the storage area by increasing the etching time. Therefore, in an embodiment of the present invention, silicon oxynitride is added on the basis of silicon nitride to form a filler 209. The etching rate of silicon oxynitride in the etchant is higher than that of silicon nitride, thereby improving the overall etching rate of the filler 209, so that the logic area gate hard mask layer and the filler 209 in the storage area can be completely removed under the same etching time.

[0063] After removing the filler 209, dielectric material may be filled in the gaps between the first control gate 203, the floating gate 207' and the second control gate 211 to form an interlayer dielectric layer. Since there is no etching residue, the surface of the interlayer dielectric layer can be flat.

[0064] At this point, the process steps implemented in the manufacturing method of a semiconductor device according to an embodiment of the present invention have been completed. It can be understood that the semiconductor device manufacturing method of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0065] According to the method for manufacturing a semiconductor device provided by the present invention, a composite material of silicon nitride and silicon oxynitride is used as a filler between floating gates, which is beneficial for controlling the etching rate of the filler and can effectively avoid etching residues of the filler.

[0066] Embodiment 2

[0067] The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1.

[0068] Below, reference Figure 2F The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment 1. For specific explanations and descriptions, reference can be made to the description in embodiment 1.

[0069] Specifically, Figure 2F As shown, the semiconductor device of the embodiment of the present invention includes a semiconductor substrate 200, on which a first control gate 203 and a floating gate 207' are formed, the floating gate 207' is connected to the first control gate 203 through a gate sidewall 205, a gap is provided between adjacent floating gates 207', and a first ion implantation region 208 is formed in the semiconductor substrate 200 below the gap; a second control gate 211 is formed above the first control gate 203 and the floating gate 207'.

[0070] By way of example, a first gate dielectric layer 202 is formed on the semiconductor substrate 200 , and a first control gate 203 and a floating gate 207 ′ are formed on the first gate dielectric layer 202 .

[0071] Exemplarily, a second gate dielectric layer 210 is formed above the first control gate 203 and the floating gate 207 ′ and below the second control gate 211 .

[0072] Exemplarily, a second ion implantation region 206 is formed in the semiconductor substrate 200 between adjacent first control gates 203 , and the first ion implantation region 208 is formed in the second ion implantation region 206 .

[0073] Exemplarily, a gate hard mask layer 204 is formed above the first control gate 203 .

[0074] Since the semiconductor device in the embodiment of the present invention is manufactured by the method in the first embodiment, etching residues of fillers can be avoided.

[0075] Embodiment 3

[0076] Another embodiment of the present invention provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0077] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0078] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: providing a semiconductor substrate; forming a first control gate and a floating gate on the semiconductor substrate, wherein the floating gate is connected to the first control gate via a gate sidewall, and gaps are provided between adjacent floating gates; performing ion implantation to form a first ion implantation region in the semiconductor substrate below the gap; forming a filler in the gap, wherein the material of the filler comprises silicon nitride and silicon nitride oxide; forming a second control gate over the first control gate and the floating gate; The filler is removed.

2. The manufacturing method according to claim 1, characterized in that The step of forming a first control gate and a floating gate on the semiconductor substrate comprises: forming a first gate material layer on the semiconductor substrate; Etching the first gate material layer to form the first control gate; forming a gate spacer on the sidewall of the first control gate; forming a second gate material layer between adjacent first control gates; The gaps are etched in the second gate material layer to form the floating gates separated by the gaps.

3. The manufacturing method according to claim 2, characterized in that: Before forming the second gate material layer between adjacent first control gates, the method further includes: Ion implantation is performed on the semiconductor substrate to form a second ion implantation region in the semiconductor substrate between adjacent first control gates, wherein the depth of the second ion implantation region is greater than the depth of the first ion implantation region.

4. The manufacturing method according to claim 1, characterized in that: Before forming the first control gate and the floating gate, the method further includes: forming a first gate dielectric layer on the semiconductor substrate.

5. The manufacturing method according to claim 1, characterized in that: After forming a filler in the gap and before forming a second control gate over the first control gate and the floating gate, the method further includes: A second gate dielectric layer is formed over the first control gate, the floating gate, and the filler.

6. The manufacturing method according to claim 1, characterized in that: The removing of the filler comprises: The filler is removed by a wet etching process.

7. The manufacturing method according to claim 6, characterized in that: The etchants used in the wet etching process include hydrofluoric acid and phosphoric acid.

8. The manufacturing method according to claim 1, characterized in that: A gate hard mask layer is formed above the first control gate.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 9.

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