Semiconductor memory device

By setting the first nitride layer and the second nitride layer in the semiconductor memory device, the diffusion of hydrogen ions is prevented, and the problem of diffusion of hydrogen ions between peripheral circuit elements and the memory cell array is solved, and the performance and reliability of the memory device are improved. .

CN119136557APending Publication Date: 2024-12-13KIOXIA CORP
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202411217634.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2019-09-12
Filing Date
2020-08-03
Publication Date
2024-12-13

AI Technical Summary

Technical Problem

In the existing semiconductor memory devices, the nitride layer structure between the peripheral circuit elements and the memory cell array is difficult to effectively suppress the diffusion of hydrogen ions, resulting in unstable transistor threshold voltage and affecting the performance of the memory device.

Method used

The first nitride layer is arranged between the control circuit and the memory cell array, and the second nitride layer is arranged between the control circuit and the first nitride layer, and the hydrogen content and density of the nitride layer are controlled by different formation methods, so as to Prevent the diffusion of hydrogen ions.

Benefits of technology

It effectively suppresses the arrival of hydrogen ions into transistors in the memory cell array, stabilizes the threshold voltage of the transistor, and improves the performance and reliability of the memory device.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119136557A_ABST
    Figure CN119136557A_ABST
Patent Text Reader

Abstract

Embodiments provide a semiconductor memory device in which defects of peripheral circuit elements are suppressed. A semiconductor memory device (1) according to an embodiment includes: a semiconductor substrate (21); a control circuit (Tr) disposed on the semiconductor substrate; a memory cell array (100) arranged above the control circuit, having a plurality of memory cells arranged in three dimensions, and controlled by the control circuit; a first nitride layer (32) disposed between the control circuit and the memory cell array; and a second nitride layer (31) disposed between the control circuit and the first nitride layer.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Slot machine

    JP2019166165A