Semiconductor device

Abstract

The semiconductor device (1) includes: a semiconductor layer (10) having a main surface (11); a switching element (2) formed on the semiconductor layer; a first electrode (50) disposed on the main surface and electrically connected to the switching element; a second electrode (55) disposed on the main surface with a gap from the first electrode and electrically connected to the switching element; a first terminal electrode (70) having a portion overlapping the first electrode in a top view and a portion overlapping the second electrode, and electrically connected to the first electrode; and a second terminal electrode (75) having a portion overlapping the second electrode in a top view and electrically connected to the second electrode.

Description

[0001] This application is a divisional application; its parent application number is "2021800541246", and its invention title is "Semiconductor Device". Technical Field

[0002] This application corresponds to Japan Patent Application No. 2020-156343 filed with the Japan Patent Office on September 17, 2020, the entire disclosure of which is incorporated herein by reference. This invention relates to semiconductor devices. Background Technology

[0003] Patent document 1 discloses technology related to semiconductor devices comprising SiC substrates.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: U.S. Patent Application Publication No. 2015 / 295079 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] One embodiment provides a semiconductor device capable of mitigating design irregularities caused by electrodes.

[0009] Solution for solving the problem

[0010] One embodiment provides a semiconductor device, comprising: a semiconductor layer having a main surface; a switching element formed on the semiconductor layer; a first electrode disposed on the main surface and electrically connected to the switching element; a second electrode disposed on the main surface with a gap from the first electrode and electrically connected to the switching element; a first terminal electrode having a portion overlapping the first electrode in a top view and a portion overlapping the second electrode, and electrically connected to the first electrode; and a second terminal electrode having a portion overlapping the second electrode in a top view and electrically connected to the second electrode.

[0011] One embodiment provides a semiconductor device comprising: a semiconductor layer having a main surface; a main element formed on the semiconductor layer and generating a main current; a sensing element formed in the semiconductor layer in a region different from the main element and generating a monitoring current for monitoring the main current; a first electrode disposed on the main surface and electrically connected to the main element; a second electrode disposed on the main surface with a gap from the first electrode and electrically connected to the main element; a third electrode disposed on the main surface with a gap from the first electrode and electrically connected to the sensing element; a first terminal electrode electrically connected to the first electrode; a second terminal electrode electrically connected to the second electrode; and a third terminal electrode having a portion overlapping the third electrode in a top view and a portion overlapping the second electrode, and electrically connected to the third electrode.

[0012] One embodiment provides a semiconductor device comprising: a semiconductor layer having a main surface; a switching element formed on the semiconductor layer; a diode formed in the semiconductor layer in a region different from the switching element; a first electrode disposed on the main surface and electrically connected to the switching element; a second electrode disposed on the main surface with a gap from the first electrode and electrically connected to the switching element; a first terminal electrode electrically connected to the first electrode; a second terminal electrode electrically connected to the second electrode; and a polarized terminal electrode having a portion overlapping the diode in a top view and a portion overlapping the second electrode, and electrically connected to the diode.

[0013] One embodiment provides a semiconductor device comprising: a semiconductor layer comprising SiC having a first main surface on one side and a second main surface on the other side; a vertical transistor formed on the semiconductor layer; a first electrode disposed on the first main surface; a second electrode disposed on the first main surface with a gap from the first electrode; a first electrode pad disposed on the side opposite to the first electrode opposite to the semiconductor layer such that at least a portion overlaps with the first electrode when viewed from above, and is electrically connected to the first electrode; and an electrode disposed on the second main surface, wherein the first electrode pad overlaps a portion of the second electrode when viewed from above.

[0014] One embodiment provides a method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor layer comprising SiC, having a first main surface on one side and a second main surface on the other side, and comprising a vertical transistor; a step of forming a first electrode and a second electrode on the first main surface with a gap; and a step of forming a first electrode pad on a side opposite to the first electrode and opposite to the semiconductor layer, such that at least a portion of the first electrode overlaps with and is electrically connected to the first electrode when viewed from above, wherein the first electrode pad overlaps with a portion of the second electrode in the first electrode pad formation step.

[0015] The above-described or other objectives, features, and effects will become clear from the description of the embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view showing the main parts of the semiconductor device according to Embodiment 1.

[0017] Figure 2 It means Figure 1 Cross-sectional view of other major parts of the semiconductor device shown.

[0018] Figure 3 yes Figure 1 A top view of the semiconductor device shown.

[0019] Figure 4 From Figure 2 A top view showing the position of line IV-IV.

[0020] Figure 5 From Figure 2 The top view showing the position of the VV line.

[0021] Figure 6 From Figure 2 A top view showing the position of the VI-VI line.

[0022] Figure 7 From Figure 3 The top view after removing the protective insulation layer.

[0023] Figure 8 This is a top view showing an example of the layout of the through-hole relative to the gate pad.

[0024] Figure 9 This is a top view showing other layout examples of vias relative to gate pads.

[0025] Figure 10 This is a top view showing other layout examples of the main surface gate electrode and the main surface source electrode.

[0026] Figure 11 This is a top view showing another layout example of the main surface gate electrode and the main surface source electrode.

[0027] Figure 12 It means Figure 2 An enlarged cross-sectional view of the outer periphery of the semiconductor device shown.

[0028] Figure 13A It means Figure 2 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0029] Figure 13B It means Figure 13A A cross-sectional view of the subsequent processes.

[0030] Figure 13C It means Figure 13B A cross-sectional view of the subsequent processes.

[0031] Figure 13D It means Figure 13C A cross-sectional view of the subsequent processes.

[0032] Figure 13E It means Figure 13D A cross-sectional view of the subsequent processes.

[0033] Figure 14 It means Figure 2 An enlarged cross-sectional view of a modified example of the outer periphery of the semiconductor device shown.

[0034] Figure 15 This is a cross-sectional view of the semiconductor device according to Embodiment 2.

[0035] Figure 16 yes Figure 15 A top view of the semiconductor device shown.

[0036] Figure 17 From Figure 16 The top view after removing the protective insulation layer.

[0037] Figure 18 From Figure 15 A top view showing the position of the XVIII-XVIII line.

[0038] Figure 19 It means Figure 15 A top view of a modified example of the semiconductor device shown.

[0039] Figure 20 yes Figure 19 A top view of the upper surface of the electrodes of the semiconductor device shown.

[0040] Figure 21 This is a cross-sectional view of the semiconductor device according to Embodiment 3.

[0041] Figure 22 yes Figure 21 A top view of the semiconductor device shown.

[0042] Figure 23 From Figure 22 A top view without the protective insulation layer.

[0043] Figure 24 From Figure 21 A top view showing the position of the XXIV-XXIV line.

[0044] Figure 25 It means Figure 21 A top view of a modified example of the semiconductor device shown.

[0045] Figure 26 yes Figure 25 A top view of the upper surface of the electrodes of the semiconductor device shown.

[0046] Figure 27 It means Figure 21 Top view of other variations of the semiconductor device shown.

[0047] Figure 28 yes Figure 27 A top view of the upper surface of the electrodes of the semiconductor device shown.

[0048] Figure 29 This is a front view of an example of a semiconductor package according to Embodiment 4.

[0049] Figure 30 It means Figure 29 A rear view of an example of a semiconductor package shown.

[0050] Figure 31 yes Figure 29 A front view of another example of a semiconductor package shown.

[0051] Figure 32 It is a cross-sectional view of a semiconductor device having a morphology in which plating layers are formed covering the gate pad and the source pad respectively. Detailed Implementation

[0052] The embodiments described below are all examples, either general or specific. The numerical values, shapes, materials, constituent elements, arrangement positions of constituent elements, connection methods, steps, and order of steps shown in the following embodiments are examples and do not limit the scope of the invention. Furthermore, constituent elements in the constituent elements of the following embodiments that are not described in the independent technical solutions are described as arbitrary constituent elements.

[0053] The accompanying drawings are schematic diagrams and not necessarily strict representations. For example, the scales and other parameters may not be consistent across different drawings. In the drawings, substantially identical structures are labeled with the same symbol, and repetitive descriptions are omitted or simplified.

[0054] In this specification, terms used to describe the relationships between elements such as vertical and horizontal, terms used to describe the shape of elements such as rectangles, and numerical ranges are not merely expressions of a strict meaning, but rather expressions of substantially equivalent ranges. For example, in the shape of a polygon or a polygonal prism, the vertices may also have circles.

[0055] In this specification, the terms "above" and "below" do not refer to the absolute spatial direction of upward (vertical above) and downward (vertical below), but are defined by the relative positional relationship in the stacked structure based on the stacking order. For example, the first main surface of the semiconductor layer is described as the upper side (above), and the second main surface is described as the lower side (below). In actual use of the semiconductor device (vertical transistor), the first main surface can also be the lower side (below), and the second main surface can be the upper side (above). Of course, the semiconductor device (vertical transistor) can also be used with the first and second main surfaces tilted or orthogonal to the horizontal plane.

[0056] The terms “above” and “below” are used not only when two constituent elements are arranged separately in the vertical direction, sandwiching other constituent elements, but also when two constituent elements are arranged in the vertical direction in a close manner.

[0057] In this specification and accompanying drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. In this specification, "stack direction" refers to a direction orthogonal to the principal plane of the semiconductor layer. In this specification, "top view" refers to the view taken from a vertical direction relative to the first principal plane of the semiconductor layer.

[0058] Figure 1 This is a cross-sectional view of the vertical transistor included in the semiconductor device of Embodiment 1. Figure 1 In the accompanying drawings, from an easy-to-observe viewpoint, the grid representing the cross-section of semiconductor layer 10 is not labeled. (Refer to...) Figure 1 Semiconductor device 1 is an example of a switching device, comprising a vertical transistor 2 (switching element). The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0059] Semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40. The semiconductor layer 10 is formed in a cuboid-shaped chip form. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. The semiconductor layer 10 contains SiC (silicon carbide) as its main component. Specifically, the semiconductor layer 10 is an n-type (first conductivity type) SiC semiconductor layer containing SiC single crystals.

[0060] The SiC single crystal can also be a 4H-SiC single crystal. The first principal surface 11 can also be the exposed silicon surface ((0001) surface) of the SiC crystal. The second principal surface 12 can also be the exposed carbon surface ((000-1) surface) of the SiC crystal. The semiconductor layer 10 can also have an offset angle that is tilted from the (0001) surface of the 4H-SiC single crystal at an angle of less than 10° relative to the [11-20] direction. The offset angle can also be greater than 0° and less than 4°.

[0061] The deviation angle can be greater than 0° and less than 4°. The deviation angle can also be 2° or 4°. The deviation angle can also be set within the range of 2° ± 0.2° or 4° ± 0.4°. The x-axis direction can be [11-20] and the y-axis direction can be [1-100]. Alternatively, the x-axis direction can be [1-100] and the y-axis direction can be [11-20].

[0062] Semiconductor layer 10 has a stacked structure comprising an n-type semiconductor substrate 13 and an n-type epitaxial layer 14. Semiconductor substrate 13 comprises a SiC single crystal. The lower surface of semiconductor substrate 13 is a second principal surface 12. Epitaxial layer 14 is stacked on the upper surface of semiconductor substrate 13. Epitaxial layer 14 is an n-type SiC semiconductor layer comprising a SiC single crystal. The upper surface of epitaxial layer 14 is a first principal surface 11.

[0063] The n-type impurity concentration of semiconductor substrate 13 can also be 1.0 × 10⁻⁶. 18 cm －3 Above and 1.0×10 21 cm －3 In this specification, "impurity concentration" refers to the peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is preferably lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 may also be 1.0 × 10⁻⁶. 15 cm －3 Above and 1.0×10 17 cm －3 Below, semiconductor substrate 13 is defined as n. + The drain region is of the n-type shape. Epitaxial layer 14 is set as n. － Type of drain drift region.

[0064] The thickness of the semiconductor substrate 13 can be 1 μm or more and less than 1000 μm. The thickness of the semiconductor substrate 13 can also be any one of 5 μm or more, 25 μm or more, 50 μm or more, or 100 μm or more. The thickness of the semiconductor substrate 13 can also be any one of 700 μm or less, 500 μm or less, 400 μm or less, 300 μm or less, 250 μm or less, 200 μm or less, 150 μm or less, or 100 μm or less. In the vertical transistor 2, current flows along the stacking direction (i.e., the thickness direction) of the semiconductor layer 10. Therefore, by reducing the thickness of the semiconductor substrate 13, the resistance value can be reduced by shortening the current path.

[0065] The thickness of the epitaxial layer 14 can be 1 μm or more and 100 μm or less. The thickness of the epitaxial layer 14 can also be any one of 5 μm or more, 10 μm or more, or 50 μm or less. The thickness of the epitaxial layer 14 can also be any one of 40 μm or less, 30 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. Preferably, the thickness of the epitaxial layer 14 is less than the thickness of the semiconductor substrate 13.

[0066] Reference Figure 1 The semiconductor device 1 includes a p-type (second conductivity type) body region 16, multiple trench gate structures 21, multiple trench source structures 31, an n-type source region 17, and a p-type contact region 18. The body region 16 is a p-type contact region located on the surface portion of the first main surface 11 of the semiconductor layer 10. － A p-type semiconductor region. The main region 16 is formed on the surface portion of the epitaxial layer 14. The p-type impurity concentration of the main region 16 can also be 1.0 × 10⁻⁶. 16 cm －3 Above and 1.0×10 19 cm －3 the following.

[0067] Multiple trench gate structures 21 are arranged spaced apart in the x-axis direction on the first main surface 11 when viewed from above, and are respectively formed as strips extending in the y-axis direction. The multiple trench gate structures 21 are formed to penetrate the main body region 16 from the first main surface 11. The multiple trench gate structures 21 are formed spaced apart in the epitaxial layer 14 from the semiconductor substrate 13 toward the first main surface 11.

[0068] Each trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by excavating the first main surface 11 towards the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in the xz plane and is formed as a recess (groove) extending in a strip in the y-axis direction.

[0069] The gate trench 22 can also have a length on the order of millimeters in the longitudinal direction (y-axis direction). The length of the gate trench 22 can also be more than 1 mm and less than 10 mm. Alternatively, the length of the gate trench 22 can be more than 2 mm and less than 5 mm. The total extension of one or more gate trenches 22 per unit area can also be 0.5 μm / μm. 2 Above and 0.75μm / μm 2 the following.

[0070] The gate insulating layer 23 is formed in a film shape along the sidewalls 22a and bottom wall 22b of the gate trench 22. The gate insulating layer 23 divides concave spaces inside the gate trench 22. The gate insulating layer 23 may also contain at least one of silicon oxide, silicon without impurities, silicon nitride, aluminum nitride, aluminum nitride, or aluminum oxynitride.

[0071] The thickness of the gate insulating layer 23 can be 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 can be uniform or vary depending on the location. The gate insulating layer 23 includes a sidewall portion 23a covering the sidewall 22a of the gate trench 22 and a bottom wall portion 23b covering the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b can also exceed the thickness of the sidewall portion 23a.

[0072] The thickness of the bottom wall portion 23b can be 0.01 μm or more and 0.2 μm or less. The thickness of the sidewall portion 23a can also be 0.05 μm or more and 0.5 μm or less. The gate insulating layer 23 can also be included in the covering portion that covers the first main surface 11 outside the gate trench 22. The thickness of the covering portion can also exceed the thickness of the sidewall portion 23a.

[0073] The gate electrode 20 is buried in the gate trench 22 through the gate insulating layer 23. That is, the gate electrode 20 is buried in the concave space defined by the gate insulating layer 23. The gate electrode 20 may also include at least one of a non-metallic conductor and a metal. The gate electrode 20 may also include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride).

[0074] The aspect ratio of the trench gate structure 21 can also be greater than 0.25 and less than 15.0. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the gate trench 22 is the same as that of the trench gate structure 21.

[0075] The width of the trench gate structure 21 can be 0.2 μm or more and 2.0 μm or less. As an example, the width of the trench gate structure 21 can also be about 0.4 μm. The depth of the trench gate structure 21 can also be 0.5 μm or more and 3.0 μm or less. As an example, the depth of the trench gate structure 21 can also be about 1.0 μm.

[0076] Multiple trench source structures 31 are formed on the first main surface 11 in the region between adjacent trench gate structures 21. The multiple trench source structures 31 are each formed as a strip extending in the y-axis direction. Thus, the multiple trench source structures 31 and the multiple trench gate structures 21 are arranged alternately, one each in the x-axis direction. Figure 1 The diagram shows only the area enclosed by two trench source structures 31 within a single trench gate structure 21. Multiple trench source structures 31, when viewed from above, form a striped pattern with the multiple trench gate structures 21 (see below). Figure 5 ).

[0077] Each trench source structure 31 may also be formed with a gap of 0.3 μm or more and 1.0 μm or less from the adjacent trench gate structure 21. The plurality of trench source structures 31 are formed to extend through the main body region 16 from the first main surface 11, dividing the main body region 16 extending along the y-axis between themselves and the plurality of trench gate structures 21. The plurality of trench source structures 31 are formed in the epitaxial layer 14 with gaps extending from the semiconductor substrate 13 toward the first main surface 11. The plurality of trench source structures 31 are formed deeper than the plurality of trench gate structures 21.

[0078] The trench source structure 31 includes a source trench 32, a barrier layer 33, a source electrode 30, and a deep well region 15. The source trench 32 is formed by excavating the first main surface 11 towards the second main surface 12. The source trench 32 has a rectangular cross-sectional shape in the xz plane and is formed as a recess (groove) extending in a strip in the y-axis direction. The source trench 32 is formed to be deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0079] The source electrode 30 is buried within the source trench 32. The source electrode 30 may also comprise at least one of a non-metallic conductor and a metal. The source electrode 30 may also comprise at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride). The source electrode 30 may also comprise n-type polysilicon with added n-type impurities or p-type polysilicon with added p-type impurities. The source electrode 30 may also be formed from the same material as the gate electrode 20. In this case, the source electrode 30 can be formed using the same process as the gate electrode 20.

[0080] A barrier forming layer 33 is located between the wall of the source trench 32 and the source electrode 30. In this configuration, the barrier forming layer 33 covers the sidewalls 32a and bottom wall 32b of the source trench 32 in a film-like manner, dividing the interior of the source trench 32 into concave spaces. That is, the source electrode 30 is embedded in the concave spaces defined by the barrier forming layer 33.

[0081] The barrier forming layer 33 is formed of a different material than the source electrode 30. The barrier forming layer 33 has a higher potential barrier than the potential barrier between the source electrode 30 and the semiconductor layer 10 (specifically, the deep well region 15 described later). The barrier forming layer 33 can also be a conductive barrier forming layer. In this case, the barrier forming layer 33 may also contain at least one of conductive polycrystalline silicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0082] The barrier forming layer 33 is preferably an insulating barrier forming layer. In this case, the barrier forming layer 33 may also comprise at least one of silicon oxide, impurity-free silicon, silicon nitride, aluminum nitride, aluminum nitride, or aluminum oxynitride. The barrier forming layer 33 may also be formed of the same material as the gate insulating layer 23. In this case, the barrier forming layer 33 may also have the same film thickness as the gate insulating layer 23. For example, when both the gate insulating layer 23 and the barrier forming layer 33 are formed of silicon oxide, the gate insulating layer 23 and the barrier forming layer 33 can be formed simultaneously by a thermal oxidation process.

[0083] The deep well region 15 is formed in the semiconductor layer 10 along the trench source configuration 31. The deep well region 15 is referred to as the breakdown voltage holding region. － A semiconductor region of the type 15. The deep well region 15 can also have a size of 1.0 × 10⁻⁶. 17 cm －3 Above and 1.0×10 19 cm －3 The following p-type impurity concentrations are specified. The p-type impurity concentration in the deep well region 15 is preferably higher than the n-type impurity concentration in the epitaxial layer 14. The p-type impurity concentration in the deep well region 15 may also be equal to the p-type impurity concentration in the main body region 16. Alternatively, the p-type impurity concentration in the deep well region 15 may be lower than the p-type impurity concentration in the main body region 16.

[0084] The deep well region 15 includes a sidewall portion 15a covering the sidewall 32a of the source trench 32, and a bottom wall portion 15b covering the bottom wall 32b of the source trench 32. The sidewall portion 15a is electrically connected to the main body region 16. The bottom wall portion 15b is formed in the epitaxial layer 14 with a gap extending from the semiconductor substrate 13. The thickness (length in the z-axis direction) of the bottom wall portion 15b is preferably greater than or equal to the thickness (length in the x-axis direction) of the sidewall portion 15a. At least a portion of the bottom wall portion 15b may also be located within the semiconductor substrate 13.

[0085] The aspect ratio of the trench source structure 31 is larger than that of the trench gate structure 21. The aspect ratio of the trench source structure 31 can also be 0.5 or higher and 18.0 or lower. Preferably, the aspect ratio of the trench source structure 31 is 1.5 or higher and 4.0 or lower. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31.

[0086] The width of the trench source structure 31 is the sum of the width of the source trench 32 and the width of the sidewall portion 15a of the deep well region 15 located on both sides of the source trench 32. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15.

[0087] The width of the trench source structure 31 can be 0.6 μm or more and 2.4 μm or less. For example, the width of the trench source structure 31 can be approximately 0.8 μm. The depth of the trench source structure 31 can be 1.5 μm or more and 11 μm or less. For example, the depth of the trench source structure 31 can be approximately 2.5 μm. By increasing the depth of the trench source structure 31, the withstand voltage retention effect of the SJ (Super Junction) structure can be improved.

[0088] Source region 17 is formed on the surface portion of the first main surface 11 of semiconductor layer 10. + A semiconductor region of type 16. A source region 17 is formed on the body region 16 (the surface portion of the body region 16) and is connected to the body region 16. The source region 17 is formed along the region of the gate trench 22. The source region 17 covers the gate insulating layer 23 and is opposed to the gate electrode 20 through the gate insulating layer 23.

[0089] Source region 17, when viewed from above, is formed as a strip extending along the y-axis. The width (length along the x-axis) of source region 17 can be greater than 0.2 μm and less than 0.6 μm. For example, the width of source region 17 can also be approximately 0.4 μm. The n-type impurity concentration of source region 17 can also be 1.0 × 10⁻⁶. 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0090] Contact region 18 is the p-type region formed on the surface portion of the first main surface 11 of semiconductor layer 10. +A semiconductor region of type 16. A contact region 18 is formed on the body region 16 (the surface portion of the body region 16) and connected to the body region 16. In addition, the contact region 18 is connected to the source region 17. The contact region 18 is formed along the region of the source trench 32. The contact region 18 covers the barrier formation layer 33 and is opposed to the source electrode 30 through the barrier formation layer 33.

[0091] The contact region 18, when viewed from above, is formed as a strip extending along the y-axis. The width (length along the x-axis) of the contact region 18 can be 0.1 μm or more and 0.4 μm or less. For example, the width of the contact region 18 can be approximately 0.2 μm. The p-type impurity concentration of the contact region 18 can also be 1.0 × 10⁻⁶. 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0092] Semiconductor device 1 includes a drain electrode 40 covering a second main surface 12 of semiconductor layer 10. The drain electrode 40 is electrically connected to semiconductor substrate 13 in the second main surface 12. The drain electrode 40 may also contain at least one of titanium, nickel, copper, aluminum, gold, and silver. The drain electrode 40 may also have a four-layer structure comprising a Ti layer, a Ni layer, an Au layer, and an Ag layer sequentially stacked from the second main surface 12.

[0093] The drain electrode 40 may also have a four-layer structure comprising a Ti layer, an AlCu layer, a Ni layer, and an Au layer sequentially stacked from the second main surface 12. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may also have a four-layer structure comprising a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer sequentially stacked from the second main surface 12. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may also have a single-layer structure composed of a TiN layer instead of a Ti layer, or a stacked structure comprising both Ti and TiN layers.

[0094] The vertical transistor 2 switches between an on-state where drain current flows and an off-state where drain current does not flow, depending on the gate voltage applied to the gate electrode 20. The gate voltage can be 10V or higher and 50V or lower. For example, the gate voltage can also be 30V. The source voltage applied to the source electrode 30 can also be a reference voltage, such as ground voltage (0V), which serves as a reference for circuit operation. The drain voltage applied to the drain electrode 40 is a voltage greater than or equal to the source voltage. The drain voltage can, for example, be 0V or higher and 10000V or lower. The drain voltage can also be 1000V or higher.

[0095] When a gate voltage is applied to the gate electrode 20, in relation to p －A channel is formed at the portion of the main body region 16 where the gate insulating layer 23 is connected. Thus, a current path is formed from the source electrode 30 through the contact region 18, the source region 17, the main body region 16 (channel), the epitaxial layer 14, and the semiconductor substrate 13 to the drain electrode 40.

[0096] The drain electrode 40 has a higher potential than the source electrode 30. Therefore, the drain current flows from the drain electrode 40 through the semiconductor substrate 13, the epitaxial layer 14, the body region 16 (channel), the source region 17, and the contact region 18 to the source electrode 30. In this way, the drain current flows along the thickness direction of the semiconductor device 1.

[0097] A pn junction is formed between the deep well region 15 and the epitaxial layer 14. When the vertical transistor 2 is on, a source voltage is applied to the deep well region 15 via the source electrode 30, and a drain voltage higher than the source voltage is applied to the epitaxial layer 14 via the drain electrode 40. That is, when the vertical transistor 2 is on, a reverse bias voltage is applied to the pn junction, and the depletion layer extends from the pn junction toward the drain electrode 40.

[0098] This improves the breakdown voltage of the vertical transistor 2. Based on the deep well region 15 having a higher p-type impurity concentration than the n-type impurity concentration of the epitaxial layer 14, the depletion layer can be appropriately extended from the interface between the deep well region 15 and the epitaxial layer 14.

[0099] In this method, a trench gate structure is used, but a planar gate structure can also be used. Furthermore, in this embodiment, a trench source structure is formed, but a structure without a trench source structure can also be used. Additionally, in this embodiment, a so-called stripe cell structure is used, but a grid cell structure can also be used.

[0100] In the embodiments described in this specification, a FET (transistor) structure has three regions: a source region, a drain region, and a gate region. It is defined as a structure that controls the current between the source and drain regions by applying a voltage to the gate region and generating an electric field in the channel region. In this context, the FET structure includes not only MOSFETs and MISFETs, but also the concept of a junction-type FET.

[0101] In other words, the FET structure also includes the concept of an IGBT (Insulated Gate Bipolar Transistor) having an "emitter region" and a "collector region" corresponding to the "source region" and the "drain region," respectively. In the embodiment, the FET structure consists of a body region 16, a source region 17, a gate electrode 20, an epitaxial layer 14, etc.

[0102] In the embodiments described in this specification, an active region is a region (divided region) in a semiconductor device in which a FET structure is formed. In a semiconductor device, an active region can be a single region or multiple regions that are mutually divided. Furthermore, when a diode structure, such as a Schottky barrier diode, is formed within a region containing a FET structure, the region containing both the FET and diode structures is defined as an active region. Additionally, when a region containing a diode structure is adjacent to a region containing a FET structure, both the region containing the diode structure and the region containing the FET structure are defined as active regions.

[0103] In the embodiments described in this specification, the non-active region is the region other than the active region. Examples of non-active regions include the region directly below the gate wiring portion, the outer peripheral voltage withstand structure portion, and the region directly below the PN diode structure for a temperature sensor. In the embodiments described in this specification, the FET structure for current sensing is defined as a non-active region.

[0104] Next, the overall structure of the semiconductor device 1 (in particular, the pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30) will be described. Figure 2 It means Figure 1 A cross-sectional view of the other main parts of the semiconductor device 1 shown. Figure 2 In the middle, the following was omitted. Figure 1 This is a diagram illustrating the specific structure of the semiconductor layer 10. Figure 2 In the image, the grid representing the cross-section of semiconductor layer 10 is omitted. Figure 2 Indicates along Figure 3 The cross section of line II-II. Figure 3 yes Figure 1 A top view of the semiconductor device 1 shown. Figure 3 In the diagram, the outer edge 70b of the gate pad 70 (wide portion 72), the outer edge 75a of the source pad 75, and the inner edge 75b of the source pad 75 are shown in dashed lines.

[0105] Figure 4 From Figure 2 A top view of semiconductor device 1 in a plane parallel to the substrate surface, observed at the position of IV-IV line. Figure 4 This is a diagram showing the planar shape of the main surface gate electrode 50 and the planar shape of the main surface source electrode 55. Specifically, Figure 4 It's perspective. Figure 3 The gate pad 70 and source pad 75 are shown, and this is a top view of the semiconductor device 1 viewed from the positive side of the z-axis.

[0106] Figure 5 From Figure 2A top view of semiconductor device 1 in a plane parallel to the substrate surface, observed at the position of the VV line. Figure 5 This diagram shows the configuration of the gate electrode 20 and the source electrode 30 from a top-down view. Specifically, Figure 5 This is a top view of the semiconductor device 1 viewed from the positive z-axis, showing the main surface gate electrode 50, main surface source electrode 55, insulating layer 60, gate pad 70, and source pad 75 (also refer to...). Figure 3 as well as Figure 4 ).

[0107] Figure 6 From Figure 2 The position of the VI-VI line is observed in a top view in a plane parallel to the substrate surface. Figure 6 In the middle, the upper insulating layer 63 and the end insulating layer 65 are shown in white. Figure 6 In the middle, the columnar portion 71 of the main surface gate electrode 50 and the source pad 75 exposed from the gap between the upper insulating layer 63 and the end insulating layer 65 are shown by the mesh portion.

[0108] exist Figure 6 In the diagram, the outer edge 75a and inner edge 75b of the upper part of the gate pad 70 (wide portion 72) and the source pad 75 are shown by dashed lines. Figure 7 From Figure 3 The top view after removing the protective insulation layer 66. Figure 7 This is a diagram showing the planar shapes of the gate pad 70 and the source pad 75. In other words, Figure 7 Is Figure 3 Top view after removing the protective insulation layer 66.

[0109] Reference Figure 2 as well as Figure 3 Semiconductor device 1 is a rectangular semiconductor chip. The length of one side of semiconductor device 1 can be more than 1 mm and less than 10 mm. The length of one side of semiconductor device 1 can also be more than 2 mm and less than 5 mm. Semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a protective insulating layer 66.

[0110] Reference Figure 1 as well as Figure 5 The semiconductor device 1 includes a plurality of gate electrodes 20 and a plurality of source electrodes 30 embedded in a first main surface 11. Each of the gate electrodes 20 and the plurality of source electrodes 30 is formed as an elongated strip extending along the y-axis. When viewed from above, the gate electrodes 20 and the plurality of source electrodes 30 are arranged alternately along the x-axis, forming a stripe structure. Figure 5In the diagram, the number of gate electrodes 20 and source electrodes 30 is schematically illustrated to be countable. However, the number of gate electrodes 20 and source electrodes 30 is much greater than the actual number shown.

[0111] The semiconductor device 1 includes a plurality of gate fingers 20b electrically connected to a plurality of gate electrodes 20. The plurality of gate fingers 20b are respectively disposed at both ends in the y-axis direction on the semiconductor layer 10 and are formed into elongated strips extending in the x-axis direction. The plurality of gate fingers 20b are respectively connected to both ends in the y-axis direction of the plurality of gate electrodes 20.

[0112] The number of gate fingers 20b is arbitrary. Therefore, a single gate finger 20b may be connected only to one end of the plurality of gate electrodes 20 in the y-axis direction. The plurality of gate electrodes 20 may also be separated at the center in the y-axis direction. In this case, the semiconductor device 1 may also include gate fingers 20b disposed in the inner portion of the semiconductor layer 10 when viewed from above. The gate fingers 20b in the inner portion may also extend in the x-axis direction in the region between the plurality of gate electrodes 20 adjacent in the y-axis direction. In addition, the gate fingers 20b in the inner portion may also be electrically connected to the plurality of gate electrodes 20 adjacent in the y-axis direction.

[0113] Semiconductor device 1 includes a main surface gate electrode 50, which is an example of a first electrode, electrically connected to a plurality of gate electrodes 20. The main surface gate electrode 50 is located above (on the positive side in the z-axis direction) the plurality of gate electrodes 20 and is electrically connected to the plurality of gate electrodes 20. The main surface gate electrode 50 may also have an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the main surface gate electrode 50 has an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0114] Reference Figure 4 The main gate electrode 50 can also be formed in an H-shape when viewed from above. Specifically, the main gate electrode 50 includes a power receiving portion 50a, a power supply portion 50b, and a connection portion 50c. The power receiving portion 50a is located directly below the gate pad 70 (described later) and is connected to the columnar portion 71 of the gate pad 70. The portion that overlaps with the columnar portion 71 of the gate pad 70 in the main gate electrode 50 when viewed from above corresponds to the power receiving portion 50a.

[0115] The power supply units 50b are respectively disposed at both ends in the y-axis direction and are formed into elongated strips extending in the x-axis direction. The power supply units 50b are connected to the gate finger 20b via a via conductor (not shown) that penetrates the lower insulating layer 61, which will be described later.

[0116] The connecting portion 50c connects the receiving portion 50a and the power supply portion 50b. The connecting portion 50c is formed as an elongated strip extending along the y-axis. Figure 4 In the example shown, the connecting part 50c extends from the power receiving part 50a to the positive and negative sides in the y-axis direction, respectively, and extends to the power supply part 50b.

[0117] The main gate electrode 50 may also comprise a non-metallic conductor or a metal. The main gate electrode 50 is preferably formed of an aluminum-based metal material. Examples of aluminum-based metal materials include aluminum, aluminum-silicon (Al-Si) alloys, and aluminum-copper (Al-Cu) alloys. Of course, the main gate electrode 50 may also be formed of conductive polycrystalline silicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main gate electrode 50 may also be formed of the same material as the gate electrode 20.

[0118] The main gate electrode 50 may also have a stacked structure comprising multiple metal layers. For example, the main gate electrode 50 may also include a base layer and metal layers stacked sequentially from the semiconductor layer 10 side. The base layer may also be formed of a barrier metal such as titanium. The metal layers may also be formed of an aluminum-based metal material formed on the base layer. The semiconductor device 1 may also include a plating layer covering the surface of the main gate electrode 50.

[0119] Semiconductor device 1 includes a main-surface source electrode 55, which is an example of a second electrode and is electrically connected to a plurality of source electrodes 30. The main-surface source electrode 55 is an electrode located above (on the positive side in the z-axis direction) the plurality of source electrodes 30 and is electrically connected to the plurality of source electrodes 30. (Refer to...) Figure 1 The main source electrode 55 is directly connected to the upper surface of the multiple source electrodes 30.

[0120] The main surface source electrode 55 is disposed with a gap from the main surface gate electrode 50 when viewed from above. The main surface source electrode 55 may also be formed over approximately the entire area of ​​the first main surface 11 when viewed from above, excluding the area where the main surface gate electrode 50 is disposed and the surrounding area of ​​the area where the main surface gate electrode 50 is disposed.

[0121] The main surface source electrode 55 is formed with an area larger than the main surface gate electrode 50 when viewed from above. The main surface source electrode 55 may also have an area of ​​more than 50% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the main surface source electrode 55 has an area of ​​more than 70% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0122] The main surface source electrode 55 may also contain a non-metallic conductor or a metal. The main surface gate electrode 50 is preferably formed of an aluminum-based metal material. The main surface gate electrode 50 may also contain aluminum, aluminum-silicon (Al-Si) alloys, aluminum-copper (Al-Cu) alloys, etc., as examples of aluminum-based metal materials.

[0123] Of course, the main surface gate electrode 50 can also be formed of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main surface source electrode 55 can also be formed of the same material as the main surface gate electrode 50. In this case, the main surface source electrode 55 can be formed by the same process as the main surface gate electrode 50.

[0124] The main surface source electrode 55 may also have a stacked structure comprising multiple metal layers. The main surface source electrode 55 may also include a substrate layer and metal layers stacked sequentially from the semiconductor layer 10 side. The substrate layer may also be formed of a barrier metal such as titanium. The metal layers may also be formed of an aluminum-based metal material formed on the substrate layer. The semiconductor device 1 may also include a plating layer covering the surface of the main surface source electrode 55.

[0125] In this configuration, both the main gate electrode 50 and the main source electrode 55 contain tungsten. That is, the active region 3 is covered by the main source electrode 55, which contains tungsten and has relatively high hardness. This allows the active region 3 to be protected by the main source electrode 55. Furthermore, damage to the FET structure caused by stress from wire bonding, etc., can be suppressed in the active region 3. This configuration is particularly effective when the source pad 75 is wire-bonded with copper wires of relatively high hardness, as described later.

[0126] As another example, the portion of the main gate electrode 50 embedded in the through-hole (gate contact hole) may be formed of tungsten, while the portion outside the through-hole (gate contact hole) in the main gate electrode 50 may be formed of an aluminum-based metal. The portion outside the through-hole (gate contact hole) in the main gate electrode 50 is formed on the lower insulating layer 61, which will be described later. Tungsten can be a pure metal or a tungsten alloy. Alternatively, tungsten can be formed via a barrier film such as titanium / titanium nitride.

[0127] Alternatively, the portion of the main source electrode 55 embedded in the source contact hole 61b may be formed of tungsten, while the portion outside the source contact hole 61b in the main source electrode 55 may be formed of an aluminum-based metal. The portion outside the through-hole (gate contact hole) in the main source electrode 55 is formed on the lower insulating layer 61, which will be described later. Tungsten can be a pure metal or a tungsten alloy. Alternatively, tungsten can be formed via a barrier film such as titanium / titanium nitride.

[0128] In semiconductor device 1, the main surface source electrode 55 is disposed in a region containing the center of the semiconductor layer 10 when viewed from above, and the main surface gate electrode 50 is disposed in a region avoiding the main surface source electrode 55. However, the configuration of the main surface gate electrode 50 and the main surface source electrode 55 is arbitrary and not limited to the above configuration. For example, the main surface gate electrode 50 may also be disposed in a region containing the center of the semiconductor layer 10 when viewed from above, and the main surface source electrode 55 may also be disposed around the main surface gate electrode 50 when viewed from above.

[0129] Reference Figure 2 The insulating layer 60 includes a lower insulating layer 61, an upper insulating layer 63 (an example of a first insulating layer, or first insulator), and an end insulating layer 65. The lower insulating layer 61 is an interlayer insulating film disposed on the first main surface 11. Specifically, the lower insulating layer 61 also covers a plurality of trench gate structures 21. (See reference...) Figure 1 The lower insulating layer 61 is provided to prevent the main surface source electrode 55 from contacting the gate electrode 20.

[0130] The lower insulating layer 61 has a plurality of source contact holes 61b. A portion of the aforementioned main surface source electrode 55 is embedded in the plurality of source contact holes 61b and is electrically connected to the plurality of source electrodes 30 within the plurality of source contact holes 61b. In addition, the main surface source electrode 55 is electrically connected to the source region 17 and the contact region 18 within the plurality of source contact holes 61b.

[0131] Although not shown in the diagram, the lower insulating layer 61 includes at least one (or multiple) through-holes (gate contact holes) that expose the power supply section 50b. The power supply section 50b of the aforementioned main surface gate electrode 50 (see reference...) Figure 4 A portion of the gate contact is embedded in multiple through-holes (gate contact holes), and the gate finger 20b (see reference) is located within the multiple through-holes (gate contact holes). Figure 5 Electrical connection. Thus, the main surface gate electrode 50 is electrically connected to the gate electrode 20.

[0132] Multiple through-holes (gate contact holes) are preferably formed simultaneously with multiple source contact holes 61b. In this case, the material and structure of the main surface gate electrode 50 (power supply section 50b) embedded in the multiple through-holes (gate contact holes) are the same as the material and structure of the main surface source electrode 55 embedded in the multiple source contact holes 61b.

[0133] An upper insulating layer 63 covers a portion of the main surface gate electrode 50 and a portion of the main surface source electrode 55. The upper insulating layer 63 is positioned between the gate pad 70 and the main surface source electrode 55 to prevent the gate pad 70 from contacting the main surface source electrode 55 (described later). Additionally, the upper insulating layer 63 is positioned between the source pad 75 and the main surface gate electrode 50 to prevent the source pad 75 from contacting the main surface gate electrode 50 (described later).

[0134] The upper insulating layer 63 covers the connection portion 50c of the main surface gate electrode 50 and has a through-hole 64 that selectively exposes the power receiving portion 50a. Specifically, the upper insulating layer 63 exposes a portion of the upper surface 52 of the power receiving portion 50a through the through-hole 64. In this manner, a through-hole 64 is formed in the upper insulating layer 63 at a position approximately opposite the center of the gate pad 70.

[0135] The gate pad 70 is connected to the upper surface 52 of the power receiving part 50a only via the through-hole 64. The planar shape of the through-hole 64 (the planar shape of the columnar part 71 described later) can also be square or rectangular. The length of one side of the through-hole 64 when viewed from above can also be more than 5 μm and less than 50 μm. As an example, the planar shape of the through-hole 64 is a square of about 20 μm × 20 μm.

[0136] The through hole 64 can have various layouts. Hereinafter, other layout examples of the through hole 64 will be described. Figure 8 This is a top view showing an example of the layout of the through-hole 64 relative to the gate pad 70. Figure 8 The illustration of protective insulation layer 66 is omitted in the text. (Refer to...) Figure 8 The through-hole 64 can also be positioned near the edge of the gate pad 70. In this case, the bonding lead 303g (shown in dashed lines) is preferably connected to the gate pad 70 in a manner that does not overlap with the through-hole 64 (pillar 71) when viewed from above. With this configuration, stress applied to the through-hole 64 (pillar 71) during lead bonding can be suppressed.

[0137] Figure 9 This is a top view showing another layout example of the through-hole 64 relative to the gate pad 70. (See reference...) Figure 9 The upper insulating layer 63 may also have a plurality of through holes 64 relative to a gate pad 70. In this case, the plurality of through holes 64 (pillar-shaped portions 71) are formed in the region where the gate pad 70 and the main surface gate electrode 50 overlap when viewed from above. This allows the gate pad 70 and the main surface gate electrode 50 to be reliably connected. The bonding leads 303g (shown in dashed lines) are preferably connected to at least a portion of the through holes 64 (pillar-shaped portions 71) in a non-overlapping manner.

[0138] Refer again Figure 2The upper insulating layer 63 is located between the gate pad 70 and the main surface source electrode 55 in the z-axis direction. Thus, the upper insulating layer 63 insulates the gate pad 70 from the main surface source electrode 55. The upper insulating layer 63 is formed by etching (patterning), thereby forming a side surface 63a of the upper insulating layer 63 on a plane extending perpendicularly (in the z-axis direction) to the first main surface 11. Here, "perpendicularly" refers to a substantial perpendicularity, not a strict one.

[0139] An end insulating layer 65 covers the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). The end insulating layer 65 covers the entire circumference of the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). The end insulating layer 65 covers the power supply portion 50b of the main surface gate electrode 50. A portion of the end insulating layer 65 jumps over the lower insulating layer 61 and the main surface source electrode 55.

[0140] The lower insulating layer 61, upper insulating layer 63, and end insulating layer 65 may also contain inorganic insulating materials. Inorganic insulating materials may include silicon oxide, silicon nitride, etc. Silicon oxide includes PSG (Phosphor Silicate Glass) and BPSG (Boron Phosphor Silicate Glass), etc. The lower insulating layer 61, upper insulating layer 63, and end insulating layer 65 may also contain organic insulating materials. Organic insulating materials may include polyimide, PBO (polybenzoxazole), etc.

[0141] The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 can be formed of the same insulating material or of different insulating materials. For example, the lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 can all be formed of silicon oxide. Alternatively, the lower insulating layer 61 can be formed of silicon oxide, while the upper insulating layer 63 and the end insulating layer 65 can be formed of silicon nitride.

[0142] The thickness of both the upper insulating layer 63 and the end insulating layer 65 can be 3 μm or more and 20 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 is preferably 5 μm or more and 15 μm or less. Particularly preferably, the thickness of the upper insulating layer 63 and the end insulating layer 65 is 5 μm or more and 10 μm or less.

[0143] Semiconductor device 1 includes a gate pad 70, which is an example of a first electrode pad (first terminal electrode) electrically connected to a main surface gate electrode 50. The gate pad 70 overlaps with and is electrically connected to the main surface gate electrode 50 when viewed from above. Specifically, the gate pad 70 is configured such that the power receiving portion 50a of the main surface gate electrode 50 is located inside the gate pad 70 when viewed from above. That is, the gate pad 70 completely covers the power receiving portion 50a of the main surface gate electrode 50.

[0144] Reference Figure 2 The gate pad 70 includes a columnar portion 71, which is an example of a lower conductive layer, and a wide portion 72, which is an example of an upper conductive layer. The columnar portion 71 is provided on the main surface gate electrode 50. Specifically, the columnar portion 71 is connected to the upper surface 52 of the current receiving portion 50a and is formed as a column extending in the normal direction (z-axis direction) of the upper surface 52. The height of the columnar portion 71 is equal to the thickness of the portion of the upper insulating layer 63 located on the current receiving portion 50a. When viewed from above, the columnar portion 71 is formed with a gap extending inward from the periphery of the current receiving portion 50a. That is, the side surface 74 of the columnar portion 71 facing the y-axis direction is located inside the main surface gate electrode 50 relative to the side surface 53 of the main surface gate electrode 50 facing the y-axis direction.

[0145] A wide portion 72 is provided at the upper end of the columnar portion 71, connecting the power receiving portion 50a and the columnar portion 71. The wide portion 72 is a portion that expands the size of the upper end of the columnar portion 71. That is, the wide portion 72 is formed with an area larger than the columnar portion 71 when viewed from above. When viewed from above, the wide portion 72 is formed such that the columnar portion 71 is located inside the wide portion 72. When viewed from above, the size and shape of the wide portion 72 are consistent with the size and shape of the gate pad 70.

[0146] The wide portion 72 is formed such that it extends further outward than the power receiving portion 50a when viewed from above. In this configuration, the wide portion 72 is formed in an umbrella shape extending further outward than the main surface gate electrode 50 in a direction orthogonal to the direction extending from the power receiving portion 50a (y-axis direction). In this configuration, the wide portion 72 extends in an umbrella shape towards both the negative and positive sides of the x-axis direction.

[0147] Therefore, the width of the wide portion 72 in the x-axis direction is greater than the width of the main gate electrode 50 in the x-axis direction. That is, the gate pad 70 has an intersection portion that intersects at least one side (in this case, two sides) of the main gate electrode 50 when viewed from above. When viewed from above, the portion of the upper surface 73 of the wide portion 72 that overlaps with the columnar portion 71 is recessed toward the main gate electrode 50.

[0148] The upper surface 73 of the wide portion 72 is used for electrical connections to the semiconductor device 1 and other circuits. For example, the upper surface 73 of the wide portion 72 is electrically connected to a power supply circuit that supplies the gate voltage. Metal wires can also be connected to the upper surface 73 of the wide portion 72 via wire bonding. The metal wires may also include at least one of aluminum, copper, and gold. In this configuration, the aluminum wire is wedge-shapedly bonded to the gate pad 70 (the upper surface 73 of the wide portion 72). Alternatively, a metal plate can be connected to the upper surface 73 of the wide portion 72 via solder instead of wire bonding.

[0149] The gate pad 70 has an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the gate pad 70 has an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The wide portion 72 (the area of ​​the gate pad 70) has an area larger than the area of ​​the powered portion 50a (i.e., the columnar portion 71) when viewed from above. The area of ​​the wide portion 72 may be more than 200 times and less than 40,000 times the area of ​​the powered portion 50a. Preferably, the area of ​​the wide portion 72 is more than 400 times the area of ​​the powered portion 50a. As an example, the area of ​​the wide portion 72 may be about 2,500 times the area of ​​the powered portion 50a.

[0150] For proper wire bonding, the wide portion 72 (gate pad 70) needs to have a certain size. Preferably, the wide portion 72 has an area of ​​800μm × 800μm or more and 1mm × 1mm or less when viewed from above. In this case, the wide portion 72 can also be formed into a square shape when viewed from above. In this case, the direction of the metal wire connection can be set to any direction. Of course, the wide portion 72 can also be formed into a square shape larger than 1mm × 1mm when viewed from above. Alternatively, the wide portion 72 can also be formed into a rectangular shape of 400μm × 800μm or more.

[0151] The columnar portion 71 and the wide portion 72 can also be formed of the same conductive material. Alternatively, the columnar portion 71 and the wide portion 72 can be formed of an aluminum-based metal. Of course, the columnar portion 71 and the wide portion 72 can also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 71 and the wide portion 72 can also be formed of different conductive materials.

[0152] The height of the gate pad 70 can be tens of μm or more but less than hundreds of μm (i.e., more than 20 μm but less than 1000 μm). The height (length in the z-axis direction) of the gate pad 70 is calculated by the sum of the height (length in the z-axis direction) of the columnar portion 71 and the thickness (length in the z-axis direction) of the wide portion 72. Figure 2 The example shown is that the height of the columnar portion 71 is equal to the thickness of the width portion 72, but the height of the columnar portion 71 can be greater than or less than the thickness of the width portion 72.

[0153] Semiconductor device 1 includes a source pad 75, which is electrically connected to a main surface source electrode 55 and serves as an example of a second electrode pad (second terminal electrode). The source pad 75 overlaps with and is electrically connected to the main surface source electrode 55 when viewed from above. The source pad 75 is disposed on the main surface source electrode 55. That is, the source pad 75 covers the upper surface 56 of the main surface source electrode 55. The source pad 75 is formed as a plate extending along the upper surface 56 of the main surface source electrode 55, with the thickness direction being the normal direction (z-axis direction).

[0154] The source pad 75 is disposed in the region containing the center of the semiconductor layer 10 (first main surface 11) when viewed from above. The source pad 75 is disposed in the region that avoids the gate pad 70. In this configuration, the gate pad 70 is disposed in the region containing the center of the semiconductor layer 10 (first main surface 11), and the source pad 75 is disposed to surround the gate pad 70.

[0155] The negative end 79 of the source pad 75 in the x-axis direction jumps from above the main surface source electrode 55 onto the upper insulating layer 63. The side 77 of the source pad 75 is located on the upper insulating layer 63. The source pad 75 has an area smaller than the area of ​​the main surface source electrode 55 when viewed from above. The source pad 75 has an area larger than the area of ​​the gate pad 70 when viewed from above. The source pad 75 has an area of ​​more than 50% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the source pad 75 has an area of ​​more than 70% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0156] The source pad 75 is positioned spaced apart from the gate pad 70 when viewed from above, forming a gap above the main surface source electrode 55 and between it and the gate pad 70, exposing the upper insulating layer 63. The gap is divided by the portion of the side surface of the gate pad 70 above the main surface source electrode 55 and the portion of the side surface 77 of the source pad 75 above the main surface source electrode 55.

[0157] Therefore, above the source electrode 55 on the main surface, short circuits caused by the contact between the gate pad 70 and the source pad 75 can be suppressed, and the source pad 75 can be stably formed. In this manner, the side surface 77 of the source pad 75 is formed as a plane extending perpendicularly or substantially perpendicularly to the first main surface 11. However, the side surface 77 does not necessarily have to be a plane; it can also be a curved or uneven surface.

[0158] The upper surface 76 of the source pad 75 is used for electrical connections to the semiconductor device 1 and other circuits. For example, the upper surface 76 of the source pad 75 is connected to a power supply circuit that supplies source voltage. Metal wires are connected to the upper surface 76 of the source pad 75 via wire bonding. The metal wires may also contain at least one of aluminum, copper, and gold. For example, in this configuration, aluminum wires are wedge-shaped bonded to the source pad 75. Alternatively, a metal plate may be soldered to the source pad 75 instead of wire bonding.

[0159] The source pad 75 is formed of a conductive material. The source pad 75 can also be formed of an aluminum-based metal. Of course, the source pad 75 can also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The source pad 75 can also be formed of the same material as the gate pad 70. In this case, the source pad 75 can be formed using the same process as the gate pad 70. Of course, the source pad 75 can also be formed of a different material than the gate pad 70.

[0160] The gate pad 70 is preferably formed using the same process as the source pad 75. In this case, the structure and material of the gate pad 70 are the same as those of the source pad 75. When the source pad 75 is connected by aluminum wire leads, the source pad 75 is preferably made of an aluminum-based material. In this case, the gate pad 70 is made of an aluminum-based material, just like the source pad 75.

[0161] When the source pad 75 is connected to the metal plate by solder, a plating layer may be formed on the surface of the source pad 75. In this case, the source pad 75 may also be made of an aluminum-based metal. Furthermore, the plating layer may include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure composed of nickel plating, or it may have a multi-layer structure comprising nickel plating and gold plating sequentially stacked from the source pad 75 side.

[0162] In this case, the gate pad 70 may also have the same structure as the source pad 75. That is, a plating layer may also be formed on the surface of the gate pad 70. In this case, the gate pad 70 may also be made of an aluminum-based metal material. In addition, the plating layer may also include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure made of nickel plating, or it may have a multi-layer structure including nickel plating and gold plating sequentially stacked from the gate pad 70 side.

[0163] When the source pad 75 is connected to the metal plate via a sintered component such as Ag, a plating layer may be formed on the surface of the source pad 75. In this case, the source pad 75 may also be made of an aluminum-based metal material. Furthermore, the plating layer may include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may also have a stacked structure comprising nickel plating, palladium plating, and gold plating sequentially stacked from the source pad 75 side.

[0164] In this case, the gate pad 70 may also have the same structure as the source pad 75. That is, a plating layer may also be formed on the surface of the gate pad 70. In this case, the gate pad 70 may also be made of an aluminum-based metal material. In addition, the plating layer may also include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may also have a stacked structure comprising nickel plating, palladium plating, and gold plating sequentially stacked from the gate pad 70 side.

[0165] Here, an example is shown where the gate pad 70 and source pad 75 are made of aluminum-based materials, but the gate pad 70 and source pad 75 may also be formed of metal materials such as copper or nickel instead of aluminum-based materials. That is, the gate pad 70 may also include a columnar portion 71 and a wide portion 72 formed of metal materials such as copper or nickel.

[0166] The main surface gate electrode 50, the main surface source electrode 55, the gate pad 70, and the source pad 75 are not limited to the above structure and can be formed in various arrangements. Figure 10 This is a top view showing other layout examples of the gate pad 70 and the power receiving part 50a. In other words, Figure 10 This is a diagram showing other layout examples of the main surface gate electrode 50 and the main surface source electrode 55. (Refer to...) Figure 10 The power receiving portion 50a of the main gate electrode 50 can also be disposed on the outermost periphery (peripheral portion) of the semiconductor device 1 (chip, semiconductor layer 10).

[0167] The wide portion 72 can also be formed as an umbrella shape extending only to the positive side in the x-axis direction. That is, the gate pad 70 has a cross portion that intersects at least one side (in this case, one side) of the main surface gate electrode 50 when viewed from above. Figure 10 In the layout example, the main surface source electrode 55 is formed into a rectangular shape when viewed from above, and the main surface gate electrode 50 is formed into a rectangular ring surrounding the main surface source electrode 55 when viewed from above.

[0168] Figure 11 This is a top view showing another layout example of the main surface gate electrode 50 and the main surface source electrode 55. Figure 11 Is Figure 10 In one layout example, the main gate electrode 50 also has a portion extending from the power receiving portion 50a along the x-axis direction. Thus, the configuration of the main gate electrode 50 and the main source electrode 55, and the configuration of the gate pad 70 relative to the main gate electrode 50 and the main source electrode 55, can be varied.

[0169] Refer again Figures 2-5 Semiconductor device 1 includes an active region 3 and a non-active region 4. Figure 3 as well as Figure 5 In the diagram, active region 3 is shown as the area enclosed by a double-dotted line. Active region 3 is the region where the FET structure is formed, and it is the main region for the drain current of the vertical transistor 2 to flow. Active region 3 roughly coincides with the region covered by the main surface source electrode 55. Non-active region 4 is the region other than active region 3. The region where the main surface gate electrode 50 is disposed and the outer periphery (peripheral side) voltage-resistant structure region are non-active regions 4.

[0170] In semiconductor devices, a gate pad 70 of a certain size is generally required for wire bonding of metal lines. When the main-side gate electrode 50 is formed to be approximately the same size as the gate pad 70, the main-side source electrode 55 is formed to be relatively small. Since the size of the active region 3 is approximately the same as the size of the main-side source electrode 55, increasing the size of the main-side gate electrode 50 will correspondingly shrink the main-side source electrode 55, and consequently, the active region 3 will become smaller. As a result, the semiconductor layer 10 cannot be effectively utilized, becoming a drawback for miniaturization and cost reduction of semiconductor devices.

[0171] To address this, in the semiconductor device 1, a main gate electrode 50 is formed, and on the other hand, a gate pad 70 (wide portion 72) is provided that intersects the active region 3. With this configuration, the wire bonding object changes from the main gate electrode 50 to the gate pad 70. This allows for a smaller main gate electrode 50 and an expanded active region 3. In other words, in the semiconductor device 1, the gate pad 70 mitigates the design constraints imposed by the main gate electrode 50, increasing design flexibility.

[0172] Specifically, a portion (wide portion 72) of the gate pad 70 overlaps with the main surface source electrode 55 when viewed from above. More specifically, the gate pad 70 has a width in the x-axis direction that is larger than the width of the main surface gate electrode 50 when viewed from above, and overlaps with a portion of the main surface source electrode 55. This allows for a reduction in the area of ​​the main surface gate electrode 50 and an expansion of the area of ​​the active region 3. Furthermore, it avoids design constraints caused by the main surface gate electrode 50 and allows the gate pad 70 to be formed to a certain size or larger. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 1 that is easily miniaturized and cost-effective can be achieved.

[0173] Reference Figure 3The semiconductor device 1 includes a protective insulating layer 66, formed on the upper insulating layer 63, which is an example of a second insulating layer (second insulator). The protective insulating layer 66 covers the boundary portion 80 (gap portion) between the gate pad 70 and the source pad 75. That is, the protective insulating layer 66 is included above the main surface source electrode 55 and covers the upper insulating layer 63 within the boundary portion 80 between the gate pad 70 and the source pad 75. The protective insulating layer 66 has a portion within the boundary portion 80 that faces the main surface source electrode 55 across the upper insulating layer 63.

[0174] The boundary portion 80 is formed into a rectangular ring shape when viewed from above. Therefore, the protective insulating layer 66 is formed into a rectangular ring shape in the portion covering the boundary portion 80. Furthermore, the protective insulating layer 66 covers the entire circumference of the outer periphery (peripheral portion) of the semiconductor device 1 (first main surface 11). The protective insulating layer 66 may also contain an organic insulating material. The protective insulating layer 66 may also contain polyimide, PBO, etc.

[0175] Figure 12 This is an enlarged cross-sectional view of the outer periphery (edge ​​portion) of the semiconductor device 1 (first main surface 11), showing it in more detail. Figure 2 The diagram for region XII. (Refer to...) Figure 12 On the outer periphery (peripheral portion) of the semiconductor device 1 (first main surface 11), the positive end of the end insulating layer 65 in the x-axis direction jumps onto the main surface source electrode 55 in such a way that it is located on the main surface source electrode 55. The negative end of the source pad 75 in the x-axis direction is located on the positive end of the end insulating layer 65 in the x-axis direction. The protective insulating layer 66 covers the positive end of the end insulating layer 65 in the x-axis direction and the negative end of the source pad 75 in the x-axis direction.

[0176] In environments that meet at least one of the following conditions—high voltage, high temperature, and high humidity—there is a possibility of impurity migration within the module gel and water seeping into the module gel. If the structure of the outer periphery (edge ​​portion) of the semiconductor layer 10 deteriorates due to temperature cycling and humidity effects, there is a concern that the aforementioned substances (elements) may enter the device from the deteriorated area, causing problems such as short circuits, discharges, and malfunctions.

[0177] In semiconductor device 1, the outer periphery (peripheral portion) of semiconductor layer 10 is covered in a predetermined pattern by a lower insulating layer 61, a protective insulating layer 66, and an end insulating layer 65 (upper insulating layer 63). Therefore, compared to the case where the outer periphery (peripheral portion) of semiconductor layer 10 is covered by the lower insulating layer 61 and the protective insulating layer 66, degradation of the outer periphery (peripheral portion) is suppressed. That is, the ingress of moisture and the like, starting from the degradation site, is suppressed, and the reliability of semiconductor device 1 is improved.

[0178] Figures 13A-13EThis is a cross-sectional view showing each step of the manufacturing method of semiconductor device 1. Hereinafter, the manufacturing method of the structure above semiconductor layer 10 will be mainly described. The method for forming the trench gate structure 21, the trench source structure 31, and various semiconductor regions (well regions) in semiconductor layer 10 utilizes known methods.

[0179] First, refer to Figure 13A A lower insulating layer 61 having a plurality of source contact holes 61b is formed on the first main surface 11 of the semiconductor layer 10. The formation process of the lower insulating layer 61 includes, for example, a process of forming an insulating film such as silicon oxide by plasma CVD (Chemical Vapor Deposition); and a process of removing a portion of the insulating film (silicon oxide) after film formation by photolithography and etching. Thus, the insulating film is patterned to form a lower insulating layer 61 with a predetermined pattern.

[0180] Next, refer to Figure 13B The main surface gate electrode 50 and the main surface source electrode 55 are formed on the lower insulating layer 61 with a gap. The formation process of the main surface gate electrode 50 and the main surface source electrode 55 includes, for example, a process of forming a metal film on the entire surface of the first main surface 11 by vapor deposition or sputtering to cover the lower insulating layer 61; and a process of removing a portion of the metal film after film formation by photolithography and etching.

[0181] Thus, the metal film is patterned to form a main surface gate electrode 50 and a main surface source electrode 55 with predetermined patterns. The main surface gate electrode 50 and the main surface source electrode 55 can also be formed through different processes by repeatedly performing film formation and patterning processes using metal films of different materials.

[0182] Next, refer to Figure 13C An upper insulating layer 63 having a through hole 64 and an end insulating layer 65 are formed on the lower insulating layer 61. The formation process of the upper insulating layer 63 and the end insulating layer 65 includes, for example, a process of forming an insulating film such as silicon oxide by plasma CVD; and a process of removing a portion of the insulating film (silicon oxide) after film formation by photolithography and etching.

[0183] The upper insulating layer 63 and the end insulating layer 65 may also be formed of an organic insulating material (such as a photosensitive resin material like polyimide). In this case, the formation process of the upper insulating layer 63 and the end insulating layer 65 includes, for example, a process of applying a liquid photosensitive resin material, which forms the basis of each insulating layer, to the upper surface 52 of the main gate electrode 50 and the upper surface 56 of the main source electrode 55 by spin coating; and a process of curing the applied photosensitive resin material by exposure and then removing the cured photosensitive resin material by development (e.g., wet etching).

[0184] Next, refer to Figure 13D A metal film 78 is formed over the entire surface of the first main surface 11 by covering the upper insulating layer 63. The metal film 78 is formed, for example, by vapor deposition or sputtering.

[0185] Next, refer to Figure 13E A portion of the deposited metal film 78 is removed using photolithography and etching. This patterning of the metal film 78 forms gate pads 70 and source pads 75 with predetermined patterns. The gate pads 70 and source pads 75 can also be formed through repeated film-forming and pattern-forming processes using metal films made of different materials.

[0186] Next, the spin coating method was used on Figure 13E The upper surface of the semiconductor layer 10, as shown, is coated with a liquid organic insulating material (photosensitive resin material) that forms the basis of the protective insulating layer 66. Next, the coated photosensitive resin material is cured by exposure, and the cured photosensitive resin material is removed by development (e.g., wet etching). Thus, a protective insulating layer 66 with a predetermined pattern is formed.

[0187] Next, a drain electrode 40 covering the second main surface 12 is formed. The drain electrode 40 is formed (film formation) for example by vapor deposition or sputtering. Then, the semiconductor layer 10 is cut by a wafer-forming process using a cutting blade or a wafer-forming process using laser irradiation, and the semiconductor device 1 is cut out from the semiconductor layer 10. The semiconductor device 1 is manufactured through the processes described above.

[0188] Figure 14 This is a cross-sectional view showing a modified example of the structure of the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). Figure 12The diagram shows an example of a protective insulating layer 66 extending onto the source pad 75. However, the protective insulating layer 66 can also be separated from the source pad 75 in such a way that the end insulating layer 65 is exposed from the area between it and the source pad 75. In this case, the end insulating layer 65 can also be an inorganic insulating film. Alternatively, the source pad 75 can also be an aluminum-based metal. In this case, bonding leads can also be bonded to the source pad 75.

[0189] When the metal plate is bonded to the source pad 75 by soldering, a nickel / gold plating layer or a nickel / palladium / gold plating layer can also be stacked on the source pad 75. Figure 14 The dashed line indicates the plating layer stacked on top of the source pad 75. According to... Figure 14 The structure, and Figure 12 Compared to other structures, it can stably form a coating layer.

[0190] The semiconductor device 1 includes a vertical transistor 2. The semiconductor device 1 includes a semiconductor layer 10, a main-side gate electrode 50, a main-side source electrode 55, a gate pad 70, and a drain electrode 40. The semiconductor layer 10 is primarily composed of SiC and has a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The main-side gate electrode 50 covers a portion of the first main surface 11.

[0191] The main surface source electrode 55 covers a portion of the first main surface 11 with a gap from the main surface gate electrode 50. The gate pad 70 is disposed on the side opposite to the main surface gate electrode 50, such that at least a portion overlaps with the main surface gate electrode 50 when viewed from above, and is electrically connected to the main surface gate electrode 50. The gate pad 70 also overlaps a portion of the main surface source electrode 55 when viewed from above.

[0192] Alternatively, from another viewpoint, the semiconductor device 1 includes a semiconductor layer 10, a vertical transistor 2 (switching element), a main-side gate electrode 50 (first electrode), a main-side source electrode 55 (second electrode), a gate pad 70 (first terminal electrode), a source pad 75 (second terminal electrode), and a drain electrode 40. The semiconductor layer 10 has a first main surface 11 (main surface). The vertical transistor 2 is formed on the semiconductor layer 10. The main-side gate electrode 50 is disposed on the first main surface 11 and electrically connected to the vertical transistor 2.

[0193] The source electrode 55 is disposed on the first main surface 11 with a gap from the gate electrode 50 and is electrically connected to the vertical transistor 2. The gate pad 70 has a portion that overlaps with the gate electrode 50 when viewed from above, and a portion that overlaps with the source electrode 55 when viewed from above, and is electrically connected to the gate electrode 50. The source pad 75 has a portion that overlaps with the source electrode 55 when viewed from above, and is electrically connected to the source electrode 55. The drain electrode 40 is electrically connected to the second main surface 12.

[0194] If, instead of the gate pad 70 described in the above embodiment, the main surface gate electrode 50 is used as the electrode pad for wire bonding (i.e., the conventional structure), a main surface gate electrode 50 of the same size as the gate pad 70 is required. Since the area in the semiconductor layer 10 covered by the main surface gate electrode 50 becomes the non-active region 4, the area that can be utilized as the active region 3 is reduced. As a result, this hinders the effective utilization of the semiconductor layer 10, becoming a drawback for miniaturization and cost reduction.

[0195] To address this, the semiconductor device 1 includes a gate pad 70 that overlaps with the main surface gate electrode 50 and the main surface source electrode 55 when viewed from above. With this configuration, the gate pad 70 mitigates the design constraints of the main surface gate electrode 50, allowing for a reduction in the area of ​​the main surface gate electrode 50. This, in turn, expands the active region 3. Furthermore, this configuration avoids the design constraints imposed by the main surface gate electrode 50 and allows the gate pad 70, for which wire bonding is performed, to be formed to a certain size or larger.

[0196] In other words, in semiconductor device 1, the design constraints caused by the main gate electrode 50, etc., are mitigated, increasing the degree of design freedom. According to this structure, it is not necessary to increase the chip size to expand the active region 3. That is, the active region 3 can be expanded while avoiding an increase in chip size. Therefore, it is possible to provide a semiconductor device 1 that achieves miniaturization and low cost through the efficient utilization of the semiconductor layer 10.

[0197] The vertical transistor 2 may also include a source, a gate, and a drain. Specifically, the vertical transistor 2 may also include: a source region 17 formed on the surface of the first main surface 11 of the semiconductor layer 10; a gate insulating layer 23 (gate insulating film) covering the source region 17; a gate electrode 20 opposite to the source region 17 across the gate insulating layer 23; and a drain region formed within the semiconductor layer 10. In this configuration, the main surface gate electrode 50 is electrically connected to the gate electrode 20, the main surface source electrode 55 is electrically connected to the source region 17, and the drain electrode 40 is electrically connected to the drain region.

[0198] The semiconductor device 1 may also include an upper insulating layer 63 located between the gate pad 70 and the source electrode 55 on the main surface in a direction perpendicular to the first main surface 11. According to this configuration, the upper insulating layer 63 enables a structure in which the gate pad 70 partially overlaps with a portion of the source electrode 55 on the main surface when viewed from above. The side surface 63a of the upper insulating layer 63 may also be a plane extending in a direction perpendicular to the first main surface 11. According to this configuration, the upper insulating layer 63 can be formed by etching.

[0199] When the source pad 75 is electrically connected to the main surface source electrode 55, the end 79 of the source pad 75 on the gate pad 70 side is preferably located on the upper insulating layer 63. With this configuration, the source pad 75 can be stably formed. Specifically, the shape of the source pad 75 can be easily adjusted.

[0200] The semiconductor device 1 may also include a protective insulating layer 66 covering the boundary 80 (gap) between the gate pad 70 and the source pad 75. With this configuration, the intrusion of moisture and other substances into the boundary 80 can be suppressed, thereby improving the reliability of the semiconductor device 1. In this case, the portion of the protective insulating layer 66 located at the boundary 80 may also be positioned opposite the main surface source electrode 55, separated by the upper insulating layer 63.

[0201] The method for manufacturing semiconductor device 1 includes a first step, a second step, and a third step. In the first step, a semiconductor layer 10 is prepared, which contains SiC as its main component and has a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The semiconductor layer 10 includes a vertical transistor 2. In the second step, a main surface gate electrode 50 and a main surface source electrode 55 are formed on the first main surface 11 with a gap.

[0202] In the third step, a gate pad 70 is formed on the region opposite to the semiconductor layer 10, in a manner electrically connected to the main gate electrode 50. The gate pad 70 is formed such that, when viewed from above, it overlaps with at least a portion of the main gate electrode 50 and a portion of the main source electrode 55. According to this manufacturing method, a semiconductor device 1 capable of expanding the active region 3 can be manufactured and provided while avoiding an increase in chip size.

[0203] In Embodiment 1, an example is shown where the wide portion 72 extends in an umbrella shape on both the negative and positive sides of the x-axis (see reference). Figure 3 (etc.). However, the wide portion 72 may also have a structure that extends in an umbrella shape only on the positive side in the x-axis direction (see reference). Figure 10 In this structure, the gate pad 70 (wide portion 72) is arranged to overlap with the active region 3 (main surface source electrode 55) when viewed from above.

[0204] In Embodiment 1, an example is shown where the main surface gate electrode 50 extends from the power receiving portion 50a along the y-axis direction (see reference). Figure 3 (etc.). However, the main gate electrode 50 may also have a structure extending along the x-axis direction in addition to extending from the power receiving portion 50a along the y-axis direction (see reference). Figure 11 In this structure, the gate pad 70 (wide portion 72) is arranged to overlap with the active region 3 (main surface source electrode 55) when viewed from above.

[0205] Figure 15 This is a cross-sectional view of the semiconductor device 101 according to Embodiment 2. Figure 15 Indicates along Figure 16 The cross-section of the XV-XV line. Figure 16 This is a top view of the semiconductor device 101 according to Embodiment 2. Figure 16 In the diagram, the outer edge 70b of the gate pad, the outer edge 75a of the source pad 75, the inner edge 75b of the source pad 75, and the outer edge 170b of the current sensing pad 170 are shown by dashed lines.

[0206] Figure 17 From Figure 16 The top view shown is the top view after removing the protective insulation layer 66. Figure 17 In the diagram, the main surface source electrode 55 is shown by a dashed line. Figure 18 From Figure 15 A top view of the upper surface of the electrode of semiconductor device 101 in a plane parallel to the substrate surface, observed at the position of the XVIII-XVIII lines. Figure 18 It's perspective. Figure 16 The gate pad 70, source pad 75, and current sensing pad 170 are shown, and this is a top view of the semiconductor device 101 viewed from the positive side of the z-axis.

[0207] Although Figures 15-18 Not shown, but similar to Embodiment 1, the semiconductor device 101 includes a vertically oriented transistor 2 that allows current to flow in the thickness direction of the semiconductor layer 10. Semiconductor device 101 (Embodiment 2) also includes an electrode for current detection and an electrode pad connected to the current detection electrode, which is the main difference from semiconductor device 1 (Embodiment 1). In semiconductor device 101, the current detection electrode is formed to be smaller than the electrode pad. Hereinafter, the description will focus on the differences from Embodiment 1, omitting or simplifying the description of commonalities.

[0208] Reference Figures 15-18The semiconductor device 101 includes a main-side gate electrode 50 (first electrode), a main-side source electrode 55 (second electrode), and a current detection electrode 150, which is an example of a third electrode. Compared with Embodiment 1, the configuration or shape of the main-side gate electrode 50 and the main-side source electrode 55 are different, but they are essentially the same. The description of the main-side gate electrode 50 and the main-side source electrode 55 is omitted.

[0209] The current detection electrode 150 is positioned with a gap between the main surface gate electrode 50 and the main surface source electrode 55 when viewed from above. The current detection electrode 150 can also be positioned at the outer periphery (peripheral portion) of the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection electrode 150 can also be positioned in a region that includes the center of the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection electrode 150 can also be positioned in a region surrounded by the main surface source electrode 55 when viewed from above. That is, the main surface source electrode 55 can also be positioned to surround the current detection electrode 150 when viewed from above.

[0210] The current detection electrode 150 corresponds to a portion separated from the main surface source electrode 55 in Embodiment 1. Although not shown in the figure, a FET structure is formed below the current detection electrode 150. The FET structure on the current detection electrode 150 side is formed in the same configuration as the FET structure formed below the main surface source electrode 55 (also referred to). Figure 1 as well as Figure 2 ).

[0211] That is, in this configuration, the FET structure includes a main cell region disposed below the source electrode 55 on the main surface, and a current sensing cell region (sensing cell region) disposed below the current sensing electrode 150. The main cell region conducts the drain current. The current sensing cell region is formed for detecting the drain current. In other words, the semiconductor device 101 includes a main cell region disposed on the first main surface 11, and a current sensing cell region disposed on the first main surface 11 in a region different from the main cell region.

[0212] FET structures are formed in both the main cell region and the current sensing cell region. The FET structure in the main cell region is configured as a main FET structure (main element) that generates the drain current as the main current. The FET structure in the current sensing cell region is configured as a sensing FET structure (sensing element) that generates the sensing current that detects the drain current. In this configuration, the FET structures in the main cell region and the current sensing cell region have the same structure.

[0213] The main source electrode 55 is disposed in a region that overlaps with the main cell region (main FET structure) when viewed from above, and is electrically connected to the source region 17 of the main cell region (main FET structure). The current detection electrode 150 is disposed in a region that overlaps with the current detection cell region (sensing FET structure) when viewed from above, and is electrically connected to the source region 17 of the current detection cell region (sensing FET structure).

[0214] In the vertical transistor 2 of the semiconductor device 101, drain current flows from drain electrode 40 toward source region 17 on the main cell region side, and sensing current flows from drain electrode 40 toward source region 17 on the sensing cell region side. As a result, drain current is output from main surface source electrode 55, and sensing current is output from current detection electrode 150.

[0215] The sensing FET can also be configured to generate a sensing current linked to the drain current by simultaneously controlling its on / off state with that of the main FET. That is, the same gate voltage can be applied simultaneously to both the main cell region and the current sensing cell region. The main cell region has a larger area than the current sensing cell region. In this configuration, the only difference between the main cell region and the current sensing cell region is their area. Therefore, a current flows in the current sensing cell region that corresponds to the area ratio of both the main cell region and the current sensing cell region.

[0216] That is, the sensing current of the sensing FET structure can also be less than the main current of the main FET structure. The area of ​​the main cell region can also be more than 100 times and less than 10,000 times the area of ​​the current sensing cell region. In this case, the current flowing through the current sensing electrode 150 and the source electrode 55 on the main surface (drain current) is more than 1 / 10,000 and less than 1 / 100.

[0217] Therefore, even if a relatively large drain current is generated for some reason, the current flowing through the current detection electrode 150 can be reduced. For example, the maximum amount of current flowing to the current detection electrode 150 can be suppressed to about 1A. Thus, the current detection electrode 150 can be used to appropriately detect an increase in current within a predetermined current detection range.

[0218] The current detection electrode 150 may also comprise a non-metallic conductor or a metal. The current detection electrode 150 is preferably formed of an aluminum-based metallic material. Examples of aluminum-based metallic materials include aluminum, aluminum-silicon (Al-Si) alloys, and aluminum-copper (Al-Cu) alloys. Of course, the current detection electrode 150 may also be formed of conductive polycrystalline silicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The current detection electrode 150 may also be formed of the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0219] Reference Figure 15 The current detection electrode 150 is disposed on the lower insulating layer 61 having one or more source contact holes 61b. The current detection electrode 150 is electrically connected to the source region 17 of the current detection unit region via the source contact holes 61b.

[0220] The current sensing electrode 150 is smaller than the current sensing pad 170 described later when viewed from above. The planar shape of the current sensing electrode 150 can also be square or rectangular. The length of one side of the current sensing electrode 150 can also be more than 5 μm and less than 50 μm. As an example, the planar shape of the current sensing electrode 150 can also be a square of approximately 20 μm × 20 μm. (Refer to...) Figure 18 In this configuration, the current sensing electrode 150 has the same size as the receiving portion 50a of the main gate electrode 50.

[0221] Of course, the size of the current detection electrode 150 can also be smaller than the size of the current receiving portion 50a. The size of the current detection electrode 150 can also be larger than the size of the current receiving portion 50a. The current detection electrode 150 can also have an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the current detection electrode 150 has an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11).

[0222] Reference Figures 15-17 The semiconductor device 101 includes a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current sensing pad 170, which is an example of a third electrode pad. Compared with the case of Embodiment 1, the configuration or shape of the gate pad 70 and the source pad 75 are different, but they are substantially the same. The description of the gate pad 70 and the source pad 75 is omitted.

[0223] The current sensing pad 170 overlaps with and is electrically connected to the current sensing electrode 150 when viewed from above. The current sensing pad 170 is positioned with a gap between the gate pad 70 and the source pad 75. The current sensing pad 170 can also be positioned in the region encompassing the center of the semiconductor layer 10 (first main surface 11) when viewed from above. The current sensing pad 170 can also be positioned in the region surrounded by the source pad 75. That is, the source pad 75 can also be positioned to surround the current sensing pad 170.

[0224] In this configuration, the current sensing pad 170 has the same structure as the gate pad 70. (Refer to...) Figure 15 Specifically, the current sensing pad 170 includes a columnar portion 171, which is an example of a lower conductive layer, and a wide portion 172, which is an example of an upper conductive layer. The columnar portion 171 is provided on the current sensing electrode 150. The columnar portion 171 is connected to the upper surface 152 of the current sensing electrode 150 and is formed as a column extending in the normal direction (z-axis direction) of the upper surface 152. The columnar portion 171 is connected to the current sensing electrode 150 through a through hole 164 provided in the upper insulating layer 63.

[0225] The height (length in the z-axis direction) of the columnar portion 171 is greater than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is equal to the thickness of the portion of the upper insulating layer 63 located on the current detection electrode 150. The side surface 174 of the columnar portion 171 may also be the same as the side surface 153 of the current detection electrode 150. The side surface 174 of the columnar portion 171 may also be located inside the current detection electrode 150 relative to the side surface 153 of the current detection electrode 150.

[0226] A wide portion 172 is provided at the upper end of the columnar portion 171. The wide portion 172 is a portion that expands the size of the upper end of the columnar portion 171. That is, the wide portion 172 is formed with an area larger than the columnar portion 171 when viewed from above. The wide portion 172 is formed such that the columnar portion 171 is located inside the wide portion 172 when viewed from above. When viewed from above, the size and shape of the wide portion 172 are consistent with the size and shape of the current detection pad 170. When viewed from above, the portion of the upper surface 173 of the wide portion 172 that overlaps with the columnar portion 171 is recessed toward the current detection electrode 150.

[0227] The upper surface 173 of the wide portion 172 is used for electrical connections to the semiconductor device 101 and other circuits. For example, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 based on detected current. Metal wires can also be connected to the upper surface 173 of the wide portion 172 via wire bonding. The metal wires may also include at least one of aluminum, copper, and gold. In this configuration, the aluminum wire is wedge-shapedly bonded to the current detection pad 170 (the upper surface 173 of the wide portion 172). Alternatively, a metal plate can be connected to the upper surface 173 of the wide portion 172 via solder instead of wire bonding.

[0228] The current sensing pad 170, when viewed from above, has an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11). Preferably, the current sensing pad 170 has an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The wide portion 172 (i.e., the current sensing pad 170) has an area larger than the area of ​​the current sensing electrode 150 when viewed from above. The area of ​​the wide portion 172 may be more than 200 times and less than 40,000 times the area of ​​the current sensing electrode 150. The area of ​​the wide portion 172 may also be more than 400 times the area of ​​the current sensing electrode 150. As an example, the area of ​​the wide portion 172 may also be about 2,500 times the area of ​​the current sensing electrode 150.

[0229] For proper wire bonding, the wide portion 172 (current sensing pad 170) needs to have a certain size. The wide portion 172 preferably has an area of ​​800μm × 800μm or more and 1mm × 1mm or less when viewed from above. In this case, the wide portion 172 can also be formed into a square shape when viewed from above. In this case, the direction of the metal wire connection can be set to any direction.

[0230] Of course, the wide portion 172 can also be formed into a square shape larger than 1mm × 1mm when viewed from above. Alternatively, the wide portion 172 can also be formed into a rectangular shape of 400μm × 800μm or larger when viewed from above. In this configuration, the size of the wide portion 172 is the same as the size of the wide portion 72 of the gate pad 70. Of course, the size of the wide portion 172 can be either smaller or larger than the size of the wide portion 72.

[0231] The columnar portion 171 and the wide portion 172 can also be formed of the same conductive material. Alternatively, the columnar portion 171 and the wide portion 172 can be formed of an aluminum-based metal. Of course, the columnar portion 171 and the wide portion 172 can also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 171 and the wide portion 172 can also be formed of different conductive materials. The current detection pad 170 can also be formed of the same material as the gate pad 70 and the source pad 75. Therefore, the current detection pad 170, the gate pad 70, and the source pad 75 can be formed using the same process.

[0232] The height (length in the z-axis direction) of the current sensing pad 170 is the sum of the height (length in the z-axis direction) of the columnar portion 171 and the thickness (length in the z-axis direction) of the wide portion 172. The height of the current sensing pad 170 can, for example, be tens of μm or more and hundreds of μm or less (i.e., 20 μm or more and less than 1000 μm). Figure 15 The example shown is that the height of the columnar portion 171 is equal to the thickness of the width portion 172, but the height of the columnar portion 171 can be greater than or less than the thickness of the width portion 172.

[0233] Reference Figure 15 The semiconductor device 101 includes an active region 103 and an active region 104. The active region 103 is the primary region for the drain current flow of the vertical transistor 2. Specifically, the active region 103 is the region that overlaps with the main surface source electrode 55 when viewed from above, and does not include the region overlapping with the main surface gate electrode 50 (in...). Figure 15 (Not shown in the figure) and the area overlapping with the current detection electrode 150. That is, the active region 103 includes the main cell region where the main FET structure is formed, but does not include the region outside the main cell region.

[0234] The non-active region 104 is the region outside the active region 103, and is the region where the drain current of the vertical transistor 2 does not flow. Specifically, the non-active region 104 is the region that overlaps with the main surface gate electrode 50 and the current sensing electrode 150 when viewed from above, but does not include the region that overlaps with the main surface source electrode 55. That is, the non-active region 104 includes the current sensing cell region forming the sensing FET structure, but does not include the main cell region. (Refer to...) Figure 15 The non-active region 104 includes the current detection region 102. The current detection region 102 includes the region that overlaps with the current detection electrode 150 when viewed from above (that is, the current detection unit region).

[0235] In the semiconductor device 101, a current detection electrode 150 is formed, and on the other hand, a current detection pad 170 (wide portion 172) is provided that intersects the active region 103. With this configuration, the wire bonding object changes from the current detection electrode 150 to the current detection pad 170. This allows for a smaller current detection electrode 150 and an expanded active region 103. In other words, in the semiconductor device 101, the current detection pad 170 mitigates the design constraints imposed by the current detection electrode 150, increasing design flexibility.

[0236] Specifically, the current sensing pad 170 has a width greater than that of the current sensing electrode 150 in both the x-axis and y-axis directions, and overlaps with a portion of the main surface source electrode 55 when viewed from above. This avoids design constraints caused by the current sensing electrode 150 and allows the current sensing pad 170 to be formed to a certain size. Furthermore, it reduces the area of ​​the main surface gate electrode 50 and increases the area of ​​the active region 103. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 101 that is easily miniaturized and cost-effective can be achieved.

[0237] The current sensing pad 170 can also be applied in the same manner as the aforementioned variation used with the gate pad 70. For example, Figure 8 as well as Figure 9 The structure shown (the configuration and number of through holes, their positional relationship with the bonding leads, etc.) can also be applied to the current sensing pad 170.

[0238] In this embodiment, the structure in which the current sensing pad 170 overlaps with the current sensing electrode 150 when viewed from above has been described. However, the current sensing pad 170 may also not overlap with the current sensing electrode 150 when viewed from above. In this case, a connection wiring portion (not shown) extending from the current sensing pad to above the current sensing electrode may be provided, such that it is connected to the current sensing electrode 150 via a through-hole. In this case, the main surface source electrode 55 may also be disposed in the area below the current sensing pad and the connection wiring portion.

[0239] In summary, the semiconductor device 101 includes a vertical transistor 2. The semiconductor device 101 includes an active region 103, an active region 104, a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), a current detection electrode 150 (third electrode), a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current detection pad 170 (third electrode pad).

[0240] An active region 103 is disposed on the semiconductor layer 10. The active region 103 includes a main cell region that conducts the drain current. An active region 104 is disposed in a region of the semiconductor layer 10 that is different from the active region 103. The active region 104 includes a current sensing cell region (sensing cell region) that conducts a sensing current for detecting the drain current. The main surface gate electrode 50 is configured to overlap with the region outside the main cell region when viewed from above. The main surface source electrode 55 is configured to overlap with the main cell region with a gap from the main surface gate electrode 50 when viewed from above.

[0241] The gate pad 70 is disposed on the side opposite to the semiconductor layer 10 such that at least a portion overlaps with the main gate electrode 50 when viewed from above, and is electrically connected to the main gate electrode 50. The gate pad 70 also partially overlaps with the main source electrode 55 when viewed from above. The source pad 75 is disposed with a gap from the gate pad 70. The source pad 75 is disposed on the side opposite to the semiconductor layer 10 such that at least a portion overlaps with the main source electrode 55 when viewed from above, and is electrically connected to the main source electrode 55.

[0242] The current sensing pad 170 is configured with a gap between the gate pad 70 and the source pad 75 when viewed from above. The current sensing pad 170 is disposed on the side opposite to the current sensing electrode 150, such that at least a portion overlaps with the current sensing electrode 150 when viewed from above, and is electrically connected to the current sensing electrode 150. In this configuration, the current sensing pad 170 further overlaps with a portion of the main surface source electrode 55 when viewed from above.

[0243] If, instead of the current sensing pad 170 in the above embodiment, a current sensing electrode 150 is used as the electrode pad for wire bonding, then a current sensing electrode 150 of the same size as the current sensing pad 170 is required. Since the area in the semiconductor layer 10 covered by the current sensing electrode 150 becomes a non-active region 104, the area that can be used as an active region 103 is reduced. Therefore, this hinders the effective utilization of the semiconductor layer 10, becoming a drawback for miniaturization and cost reduction.

[0244] To address this, the semiconductor device 101 includes a current detection pad 170 that overlaps with the current detection electrode 150 and the main surface source electrode 55 when viewed from above. This configuration mitigates the design constraints of the current detection electrode 150 by using the current detection pad 170, allowing for a smaller area of ​​the current detection electrode 150. This, in turn, expands the active region 103. Furthermore, this configuration avoids design constraints imposed by the current detection electrode 150 and allows the current detection pad 170, which performs wire bonding, to be formed to a certain size or larger.

[0245] In other words, in the semiconductor device 101, the design constraints caused by the current detection electrode 150, etc., are mitigated, increasing the degree of design freedom. According to this structure, it is not necessary to increase the chip size to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, the semiconductor layer 10 can be effectively utilized, providing a semiconductor device 101 that can achieve miniaturization and low cost.

[0246] Semiconductor device 101 is manufactured using the same manufacturing method as semiconductor device 1. Specifically, semiconductor device 101 is manufactured by modifying the following steps in the manufacturing method of semiconductor device 1, corresponding to semiconductor device 101: patterning steps for the main surface gate electrode 50, main surface source electrode 55, and current detection electrode 150; patterning steps for the insulating layer 60; and patterning steps for the gate pad 70, source pad 75, and current detection pad 170.

[0247] Figure 19 This is a top view of the semiconductor device 101a, a modified example of Embodiment 2 (the protective insulating layer 66 is not shown). Figure 20 This is a top view of the upper surface of the electrode of the semiconductor device 101a, a modified example of Embodiment 2. Figure 19 as well as Figure 20 respectively with Figure 17 as well as Figure 18 Correspondingly. In the above-described Embodiment 2, an example was described in which the gate pad 70 has a wide portion 72 and the current detection pad 170 has a wide portion 172. However, it is also possible to... Figure 19 as well as Figure 20 As shown, the gate pad 70 does not have a wide portion 72, while the current sensing pad 170 has a wide portion 172.

[0248] Specifically, in semiconductor device 101a, the gate pad 70a has the same size and shape as the main gate electrode 50A when viewed from above. That is, the main gate electrode 50A of semiconductor device 101a has a larger size than the current-receiving portion 50a of the main gate electrode 50 of semiconductor device 101 when viewed from above. The structure of the current detection electrode 150 and the current detection pad 170 is the same as that of semiconductor device 101. That is, semiconductor device 101a includes a current detection electrode 150 as an example of a first electrode and a current detection pad 170 as an example of a first electrode pad.

[0249] In summary, the semiconductor device 101a employs a structure that increases the area of ​​the current sensing electrode 150 when viewed from above (specifically, the current sensing pad 170). That is, the current sensing electrode 150 of the semiconductor device 101a overlaps with a portion of the main surface source electrode 55 when viewed from above, and is electrically connected to one of the plurality of source electrodes 30. In this case, the current sensing electrode can be considered an example of a first electrode, and the current sensing pad 170 can be considered an example of a first electrode pad.

[0250] Thus, according to the semiconductor device 101a, a current detection pad 170 is formed that overlaps with the current detection electrode 150 and the main surface source electrode 55 when viewed from above. With this configuration, the current detection pad 170 mitigates the design constraints of the current detection electrode 150, allowing for a smaller area of ​​the current detection electrode 150. This, in turn, expands the active region 103. Furthermore, with this configuration, the design constraints imposed by the current detection electrode 150 can be avoided, and the current detection pad 170 for wire bonding can be formed to a certain size or larger.

[0251] In other words, in the semiconductor device 101a, the design constraints caused by the current detection electrode 150, etc., are mitigated, increasing the degree of design freedom. According to this structure, it is not necessary to increase the chip size to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, the semiconductor layer 10 can be effectively utilized, providing a semiconductor device 101a that can achieve miniaturization and low cost.

[0252] Figure 21 This is a cross-sectional view of the semiconductor device 201 according to Embodiment 3. Figure 21 Indicates along Figure 22 The cross-section of the XXI-XXI line. Figure 22 This is a top view of the semiconductor device 201 according to Embodiment 3. Figure 22 In the figure, the outer edge 70b of the gate pad, the outer edge 75a of the source pad 75, the inner edge 75b of the source pad 75, the outer edge 270a of the anode pad 270, and the outer edge 275a of the cathode pad 275 are shown by dashed lines. Figure 23 From Figure 22 A top view excluding the protective insulation layer 66. Figure 23 In the diagram, the main surface source electrode 55 is shown by a dashed line.

[0253] Figure 24 From Figure 21 A top view of the semiconductor device 201 in a plane parallel to the substrate surface, observed at the position of the XXIV-XXIV lines. Specifically, Figure 24 It's perspective. Figure 23The diagram shows the gate pad 70, source pad 75, anode pad 270, and cathode pad 275, and is a top view of the semiconductor device 201 viewed from the positive side of the z-axis.

[0254] Reference Figures 21-24 Semiconductor device 201 (Embodiment 3) includes a diode 290 (first conductive layer), which is the main difference from semiconductor device 1 (Embodiment 1). Hereinafter, the differences from Embodiment 1 will be mainly described, and the description of the common points will be omitted or simplified. Specifically, semiconductor device 201 includes: an insulating layer 260 covering a portion of the first main surface 11 of semiconductor layer 10; and a diode 290 disposed on the insulating layer 260.

[0255] In this configuration, diode 290 is a pn diode comprising polysilicon, a p-type semiconductor layer 291 formed on the polysilicon, and an n-type semiconductor layer 292 formed on the polysilicon. For example, p-type semiconductor layer 291 is polysilicon with p-type impurities added, and n-type semiconductor layer 292 is polysilicon with n-type impurities added. The n-type semiconductor layer 292 is connected to the p-type semiconductor layer 291, forming a pn junction (pn diode).

[0256] Diode 290 is used as a temperature sensor (temperature-sensing diode) to detect the temperature of semiconductor device 201 (semiconductor layer 10) based on the voltage between p-type semiconductor layer 291 and n-type semiconductor layer 292. That is, diode 290 can also have a forward voltage characteristic that changes linearly with temperature. The temperature of semiconductor layer 10 is indirectly detected by the voltage characteristic of diode 290.

[0257] Semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270 (first polarity terminal electrode), and a cathode electrode pad 275 (second polarity terminal electrode). The anode electrode pad 270 and the cathode electrode pad 275 are each formed as an example of a diode electrode pad (polarity terminal electrode). Compared to Embodiment 1, the configuration or shape of the gate pad 70 and the source pad 75 are different, but they are substantially the same. Description of the gate pad 70 and the source pad 75 is omitted.

[0258] Viewed from above, the anode electrode pad 270 is disposed spaced apart from the gate pad 70 and the source pad 75 in the region overlapping with the p-type semiconductor layer 291, and is electrically connected to the p-type semiconductor layer 291. In this configuration, the anode electrode pad 270 has the same structure as the gate pad 70.

[0259] Reference Figure 21Specifically, the anode electrode pad 270 includes a columnar portion 271, which is an example of a lower conductive layer, and a wide portion 272, which is an example of an upper conductive layer. The columnar portion 271 is disposed on the p-type semiconductor layer 291. The columnar portion 271 is connected to the upper surface of the p-type semiconductor layer 291 and is formed as a column extending in the normal direction (z-axis direction) of the upper surface of the p-type semiconductor layer 291.

[0260] A wide portion 272 is provided at the upper end of the columnar portion 271. The wide portion 272 is a portion that expands the size of the upper end of the columnar portion 271. That is, the wide portion 272 is formed with an area larger than the columnar portion 271 when viewed from above. The wide portion 272 is formed such that the columnar portion 271 is located inside the wide portion 272 when viewed from above. When viewed from above, the size and shape of the wide portion 272 are consistent with the size and shape of the anode electrode pad 270.

[0261] The upper surface 273 of the wide portion 272 is used for electrical connections to the semiconductor device 201 and other circuits. Metal wires can also be connected to the upper surface 273 of the wide portion 272 via wire bonding. The metal wires may also contain at least one of aluminum, copper, and gold. In this configuration, the aluminum wire is wedge-shapedly bonded to the anode electrode pad 270 (the upper surface 273 of the wide portion 272).

[0262] For proper wire bonding, the width portion 272 (anode electrode pad 270) needs to have a certain size. The planar shape and size of the width portion 272 can also be the same as the planar shape and size of the width portion 72 of the gate pad 70. Of course, either or both of the planar shape and size of the width portion 272 can be different from the width portion 72.

[0263] The columnar portion 271 and the wide portion 272 can also be formed of the same conductive material. Alternatively, the columnar portion 271 and the wide portion 272 can be formed of an aluminum-based metal. Of course, the columnar portion 271 and the wide portion 272 can also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. Furthermore, the columnar portion 271 and the wide portion 272 can also be formed of different conductive materials.

[0264] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 can be, for example, tens of μm or more and hundreds of μm or less (i.e., 20 μm or more and less than 1000 μm). The height of the columnar portion 271 can be greater than or less than the thickness of the wide portion 272. Alternatively, the height of the columnar portion 271 can be equal to the thickness of the wide portion 272.

[0265] The cathode electrode pad 275 is disposed in a region that overlaps with the n-type semiconductor layer 292 with a gap from the gate electrode pad 70, the source electrode pad 75, and the anode electrode pad 270, and is electrically connected to the n-type semiconductor layer 292. In this configuration, the cathode electrode pad 275 has the same structure as the gate electrode pad 70 and the anode electrode pad 270.

[0266] Reference Figure 21 Specifically, the cathode electrode pad 275 includes a columnar portion 276, which is an example of a lower conductive layer, and a wide portion 277, which is an example of an upper conductive layer. The columnar portion 276 is disposed on the n-type semiconductor layer 292. The columnar portion 276 is connected to the upper surface of the n-type semiconductor layer 292 and is formed as a column extending in the normal direction (z-axis direction) of the n-type semiconductor layer 292.

[0267] A wide portion 277 is provided at the upper end of the columnar portion 276. The wide portion 277 is a portion that expands the size of the upper end of the columnar portion 276. That is, the wide portion 277 is formed with an area larger than the columnar portion 276 when viewed from above. The wide portion 277 is formed such that the columnar portion 276 is located inside the wide portion 277 when viewed from above.

[0268] Viewed from above, the size and shape of the wide portion 277 are identical to those of the cathode electrode pad 275. The upper surface 278 of the wide portion 277 is used for electrical connections to the semiconductor device 201 and other circuits. In this configuration, the upper surface 278 of the wide portion 277 is connected to a voltmeter or similar device. Alternatively, metal wires can be connected to the upper surface 278 of the wide portion 277 via wire bonding.

[0269] The anode electrode pad 270 and the cathode electrode pad 275 may each have an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. Preferably, the anode electrode pad 270 and the cathode electrode pad 275 have an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0270] Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be disposed on the outer periphery (peripheral portion) of the semiconductor layer 10 (first main surface 11) when viewed from above. Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may also be disposed in the region that includes the center position of the semiconductor layer 10 (first main surface 11) when viewed from above.

[0271] Either or both of the anode electrode pad 270 and the cathode electrode pad 275 can be disposed in the area surrounded by the source electrode pad 75. That is, the source electrode pad 75 can also be formed in a manner that surrounds either or both of the anode electrode pad 270 and the cathode electrode pad 275.

[0272] The anode electrode pad 270 and cathode electrode pad 275 are formed, for example, of the same material as the gate pad 70 and source pad 75. Therefore, the anode electrode pad 270, cathode electrode pad 275, gate pad 70, and source pad 75 can be formed using the same process. The shape, material, etc., of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 can also be the same as those of the anode electrode pad 270. (Explanation regarding the shape, material, etc., of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 is omitted.)

[0273] Reference Figure 21 The semiconductor device 201 includes an active region 203 and an active region 204. The active region 203 is the main region for the drain current of the vertical transistor 2 to flow. The active region 203 is the region that overlaps with the main surface source electrode 55 when viewed from above.

[0274] The non-active region 204 is the area outside the active region 203 when viewed from above; it is the region where the vertical transistor 2 does not operate (the region where drain current does not flow). The diode 290 described above is disposed in the non-active region 204. That is, in this configuration, the anode electrode pad 270 and the cathode electrode pad 275 are disposed in the region overlapping with the non-active region 204 such that they partially overlap with the active region 203 when viewed from above.

[0275] In the semiconductor device 201, a portion (wide portion 272) of the anode electrode pad 270 overlaps with the main surface source electrode 55 when viewed from above. This avoids design constraints caused by the diode 290 and allows the anode electrode pad 270 to be formed to a certain size or larger. Furthermore, it allows for a reduction in the area of ​​the diode 290 and an expansion of the area of ​​the active region 203. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective is achieved.

[0276] Furthermore, in the semiconductor device 201, a portion (wide portion 277) of the cathode electrode pad 275 overlaps with the main surface source electrode 55 when viewed from above. This avoids design constraints caused by the diode 290 and allows the cathode electrode pad 275 to be formed to a certain size or larger. Additionally, it allows for a reduction in the area of ​​the diode 290 and an expansion of the area of ​​the active region 203. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective can be achieved.

[0277] The semiconductor device 201 includes an insulating layer 260, a diode 290, an anode electrode pad 270 (first polarity terminal electrode), and a cathode electrode pad 275 (second polarity terminal electrode). The insulating layer 260 covers a portion of the first main surface 11. The diode 290 is disposed on the insulating layer 260. The diode 290 includes a p-type semiconductor layer 291 (first polarity layer) and an n-type semiconductor layer 292 (second polarity layer) that forms a pn junction with the p-type semiconductor layer.

[0278] The anode electrode pad 270 has a portion that overlaps with and is electrically connected to the p-type semiconductor layer 291 when viewed from above. The cathode electrode pad 275 has a portion that overlaps with and is electrically connected to the n-type semiconductor layer 292 when viewed from above. In this configuration, either or both of the anode electrode pad 270 and the cathode electrode pad 275 overlap with a portion of the main surface source electrode 55 when viewed from above.

[0279] According to this configuration, design constraints caused by the diode 290 can be avoided, and either or both of the anode electrode pad 270 and the cathode electrode pad 275 can be formed to a certain size or larger. Furthermore, according to this configuration, the area of ​​the diode 290 can be reduced, while the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easily miniaturized and cost-effective can be achieved.

[0280] Semiconductor device 201 is manufactured using the same manufacturing method as semiconductor device 1. Specifically, semiconductor device 201 is manufactured by modifying the following processes accordingly: patterning process of main surface gate electrode 50 and main surface source electrode 55; patterning process of insulating layer 60; and patterning process of gate pad 70, source pad 75, anode electrode pad 270 and cathode electrode pad 275.

[0281] Figure 25 This is a top view of the semiconductor device 201a, a modified example of Embodiment 3 (the protective insulating layer 66 is not shown). Figure 26 This is a top view of the upper surface of the electrode of the semiconductor device 201a, a modified example of Embodiment 3. Figure 25 as well as Figure 26 Each is different from Implementation Method 3 Figure 23 as well as Figure 24 Corresponding. In Figure 25 In the diagram, the main surface source electrode 55 is shown by a dashed line.

[0282] In the semiconductor device 201, an example has been described where the gate pad 70 has a wide portion 72, the anode electrode pad 270 has a wide portion 272, and the cathode electrode pad 275 has a wide portion 277. However, it is also possible to... Figure 25 as well as Figure 26 As shown, the gate pad 70 does not have a wide portion 72, the anode electrode pad 270 has a wide portion 272, and the cathode electrode pad 275 has a wide portion 277.

[0283] The gate pad 70a of the semiconductor device 201a has the same size and shape as the main gate electrode 50A when viewed from above. That is, the main gate electrode 50A of the semiconductor device 201a has a larger size than the power receiving portion 50a of the main gate electrode 50 of the semiconductor device 201 when viewed from above.

[0284] As described above, the area of ​​the diode 290 can be reduced and the area of ​​the active region 203 can be expanded by utilizing the limited area of ​​the semiconductor layer 10. Therefore, the semiconductor device 201a, which is easy to miniaturize and reduce cost, can be realized by effectively utilizing the limited area of ​​the semiconductor layer 10.

[0285] Figure 27 as well as Figure 28 This is a diagram showing a semiconductor device 201b, which is a further variation of embodiment 3. Figure 27 This is a top view of semiconductor device 200b (the protective insulating layer 66 is not shown). Figure 28 This is a top view of the upper surface of the electrode in semiconductor device 201b. Figure 27 In the diagram, the main surface source electrode 55 is shown by a dashed line. Figure 28 The configuration of the diode 290 on the main surface source electrode 55 is shown in the figure.

[0286] Reference Figure 27 as well as Figure 28 Similar to semiconductor device 201, semiconductor device 201b includes diode 290, anode electrode pad 270, and cathode electrode pad 275. In this configuration, diode 290 is positioned near the center of the chip (near the center of the first main surface 11) when viewed from above.

[0287] In this configuration, the anode electrode pad 270 and the cathode electrode pad 275 are disposed at the periphery of the chip (peripheral portion of the first main surface 11) when viewed from above. Either or both of the anode electrode pad 270 and the cathode electrode pad 275 (both in this configuration) are disposed with a gap between them and the diode 290, so as not to overlap with the diode 290 when viewed from above. In this configuration, the entire anode electrode pad 270 overlaps with the main surface source electrode 55 when viewed from above. Similarly, the entire cathode electrode pad 275 overlaps with the main surface source electrode 55 when viewed from above.

[0288] Semiconductor device 201b includes a first connection portion 250a, a first finger portion 250, a second connection portion 255a, and a second finger portion 255. The first connection portion 250a is located directly above the p-type semiconductor layer 291 of diode 290. The first finger portion 250 is located between anode electrode pad 270 and the first connection portion 250a, connecting the anode electrode pad 270 and the first connection portion 250a.

[0289] The first finger 250 extends in a linear (strip-like) shape in the region between the anode electrode pad 270 and the first connection portion 250a when viewed from above. In this manner, the first finger 250 extends in the x-axis direction when viewed from above. At least a portion of the first finger 250 overlaps with the main surface source electrode 55 when viewed from above.

[0290] The second connection portion 255a is located directly above the n-type semiconductor layer 292 of the diode 290. The second finger portion 255 is located between the cathode electrode pad 275 and the second connection portion 255a, connecting the cathode electrode pad 275 and the second connection portion 255a. When viewed from above, the second finger portion 255 extends in a linear (strip) shape in the area between the cathode electrode pad 275 and the second connection portion 255a.

[0291] In this configuration, the second finger 255, when viewed from above, is spaced apart from the first finger 250 in the y-axis direction and extends in the x-axis direction. That is, the second finger 255 extends parallel to the first finger 250 when viewed from above. At least a portion of the second finger 255 overlaps with the main surface source electrode 55 when viewed from above.

[0292] The central portion of the chip (semiconductor layer 10) tends to get hotter than its peripheral portion. Therefore, when a diode 290, which functions as a temperature sensor, is provided, the diode 290 is preferably positioned in the central portion of the chip (semiconductor layer 10) when viewed from above. On the other hand, from the viewpoint of ease of mounting such as wire bonding, the electrode pads are preferably positioned at the ends (peripherals) of the chip where there are fewer obstructions.

[0293] In the existing configuration, the regions directly below the multiple electrode pads of the temperature sensor located at the ends (peripherals) of the chip (semiconductor layer 10), and the regions directly below the wiring from these electrode pads to the center of the chip (semiconductor layer 10), are formed as non-active regions. In this respect, according to the structure of the semiconductor device 201b, in addition to the regions directly below the anode electrode pads 270 and the cathode electrode pads 275, the regions directly below the first finger 250 and the second finger 255 can also be used as active regions 203.

[0294] Figure 29 as well as Figure 30 This is a diagram showing the semiconductor package 300 according to Embodiment 4. Figure 30 It means Figure 29 The semiconductor package 300 shown is from and Figure 29 A diagram showing the internal structure of the situation observed on the opposite side.

[0295] Semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. Semiconductor package 300 includes package body 301, terminals 302d, 302g, 302s, bonding leads 303g, bonding leads 303s, and semiconductor device 1. Hereinafter, terminals 302d, 302g, and 302s are sometimes simply referred to as "terminals 302d to 302s".

[0296] The package body 301 is formed in a cuboid shape. The package body 301 is formed, for example, of an epoxy resin containing carbon and glass fiber. Terminals 302d to 302s protrude from the bottom of the package body 301 and are arranged side-by-side in a row. Terminals 302d to 302s may also be formed of aluminum. Terminals 302d to 302s may also be formed of other metallic materials such as copper.

[0297] The semiconductor device 1 is built into the package body 301. That is, the package body 301 is configured as a sealing body to encapsulate the semiconductor device 1. The gate pad 70 of the semiconductor device 1 is electrically connected to the terminal 302g inside the package body 301 via bonding leads 303g and the like.

[0298] The source pad 75 of the semiconductor device 1 is electrically connected to the terminal 302s via bonding leads 303s, etc. The drain electrode 40 of the semiconductor device 1 is bonded to the terminal 302d via solder, a sintering layer, etc. The sintering layer may also include silver, copper, etc. In this manner, the drain electrode 40 is bonded to the wide portion of the terminal 302d located within the package body 301.

[0299] The semiconductor package 300 may also include semiconductor devices 101, 101a, 201, 201a, or 201b instead of semiconductor device 1. In this case, the semiconductor package 300 may also include at least one terminal other than terminals 302d to 302s. For example, when semiconductor device 101 is included, the semiconductor package 300 may also include a terminal connected to the current sensing pad 170. In addition, when semiconductor device 201 is included, the semiconductor package 300 may also include a terminal for connecting to the anode electrode pad 270 and a terminal for connecting to the cathode electrode pad 275.

[0300] In summary, the semiconductor package 300 includes semiconductor devices 1, 101, 101a, 201, 201a, or 201b. As described above, miniaturization can be achieved by effectively utilizing the semiconductor layer 10, etc. Therefore, the semiconductor package 300 can be easily miniaturized in accordance with the miniaturization of the semiconductor device 1, etc.

[0301] Furthermore, according to the semiconductor device 1, the active regions 3, 103, and 203 can be expanded. Therefore, according to the semiconductor package 300, the allowable current can be increased compared to a general semiconductor package of the same size. In the semiconductor package 300, an example is shown where the semiconductor device 1 is electrically connected to a terminal via bonding leads. However, in the semiconductor package 300, the semiconductor device 1 can also be electrically connected to a terminal via a bonding material.

[0302] Figure 31 This is a diagram showing the semiconductor package 400 according to Embodiment 4. (Refer to...) Figure 31 The semiconductor package 400 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, multiple terminals 402, and a semiconductor device 1.

[0303] The package body 401 is formed in a cuboid shape. The package body 401 is formed, for example, of an epoxy resin containing carbon, glass fiber, etc. A plurality of terminals 402 are arranged side-by-side along the long side of the package body 401. The plurality of terminals 402 protrude outward from the long side of the package body 401. The plurality of terminals 402 may also be formed of aluminum, for example. The plurality of terminals 402 may also be formed of other metallic materials such as copper.

[0304] The semiconductor device 1 is housed within the package body 401. That is, the package body 401 serves as a sealing material for encapsulating the semiconductor device 1. The gate pad 70, source pad 75, and drain electrode 40 of the semiconductor device 1 are electrically connected to corresponding terminals 402 within the package body 401 via bonding leads or the like. The semiconductor package 400 may also contain multiple semiconductor devices 1. That is, multiple semiconductor devices 1 may be housed within the package body 401.

[0305] Of course, the semiconductor package 400 may replace the semiconductor device 1, or may include at least one of semiconductor devices 101, 101a, 201, 201a, and 201b in addition to the semiconductor device 1. When the semiconductor device 101 is included, the current sensing pad 170 is electrically connected to the corresponding terminal 402 inside the package body 401 via bonding leads or the like. Furthermore, when the semiconductor device 201 is included, the anode electrode pad 270 and the cathode electrode pad 275 are respectively electrically connected to the corresponding terminal 402 inside the package body 401 via bonding leads or the like.

[0306] In summary, the semiconductor package 400 includes at least one of semiconductor devices 1, 101, 101a, 201, 201a, and 201b. As described above, according to the semiconductor device 1, miniaturization can be achieved by effectively utilizing the semiconductor layer 10. Therefore, according to the semiconductor package 300, miniaturization can be easily achieved in accordance with the miniaturization of the semiconductor device 1, etc.

[0307] Furthermore, according to the semiconductor device 1, the active regions 3, 103, and 104 can be expanded. Therefore, according to the semiconductor package 300, the allowable current can be increased compared to a general semiconductor package of the same size. In the semiconductor package 400, an example is shown where the semiconductor device 1 is electrically connected to a terminal via bonding leads. However, in the semiconductor package 400, the semiconductor device 1 can also be electrically connected to a terminal via a bonding material.

[0308] Figure 32 This is a cross-sectional view of a modified semiconductor device 501. (Refer to...) Figure 32 As an example of a metal layer, a plating layer 90 (metal plating layer) can also be formed on the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. Figure 32 In addition to the plating layer 90, the figure also shows an example of a bonding lead 303g, bonding material 502, and metal plate 503 as a connection component (bonding mechanism) to an external terminal.

[0309] In the semiconductor device 501, bonding leads 303g are connected to the gate pad 70, and bonding material 502 is bonded to the source pad 75. The bonding material 502 is positioned between the metal plate 503 and the source pad 75 in a manner that bonds the metal plate 503 and the source pad 75. Examples of bonding material 502 include solder and sintered metal components. Sintered metal components may also include silver, copper, etc.

[0310] The plating layer 90 is formed of a metal material different from the metal material forming the gate pad 70 and the source pad 75. For example, the plating layer 90 is a metal layer whose main component includes nickel. Specifically, the plating layer 90 is a metal layer composed of nickel monomers.

[0311] The plating layer 90 may also have a two-layer structure comprising a nickel layer and a palladium layer stacked on the nickel layer (i.e., a NiPd layer). The plating layer 90 may also have a three-layer structure comprising a nickel layer, a palladium layer stacked on the nickel layer, and a gold (Au) layer stacked on the palladium layer (i.e., a NiPdAu layer). Of course, the plating layer 90 may also have a stacked structure comprising other metal layers instead of a gold (Au) layer. The NiPd layer and NiPdAu layer are not limited to applications involving wire bonding; they are also suitable for applications where external terminals are bonded by silver sintering or solder bonding.

[0312] The plating layer 90 can also be applied to semiconductor devices 101, 101a, 201, 201a and 201b. That is, the plating layer 90 can also be provided on the upper surface of the current detection pad 170, the anode electrode pad 270 and the cathode electrode pad 275.

[0313] In summary, the embodiments described above have been explained, but these embodiments can also be implemented in other ways. For example, the semiconductor package in which semiconductor devices 1, 101, 101a, 201, 201a, 201b, and 501 are mounted is not limited to the manner of semiconductor package 300 and semiconductor package 400. As a semiconductor package, SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package) can also be used. Of course, various similar semiconductor packages can also be used.

[0314] In embodiments 1 to 4 described above, an example was given where the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type". However, it is also possible for the "first conductivity type" to be "p-type" and the "second conductivity type" to be "n-type". The specific structure of this case is obtained by replacing "n-type region" with "p-type region" and "p-type region" with "n-type region" in the above description and drawings. "First conductivity type" and "second conductivity type" are merely representations used to clarify the order of explanation; it is also possible to represent "n-type" as "second conductivity type" and "p-type" as "first conductivity type".

[0315] In the above-described embodiments 1 to 4, p can also be used. + To replace n-type SiC semiconductor substrates + A semiconductor substrate 13 of the type is provided. In this case, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) as a vertical transistor 2 can be provided. In this case, in the specification and drawings, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The emitter (emitter electrode) of the IGBT is an example of a first main electrode, and the collector (collector electrode) of the IGBT is an example of a second main electrode. The semiconductor device according to the above embodiments can achieve the same effect as described above when an IGBT is included instead of a MISFET.

[0316] The structures of embodiments 1 to 4 and their variations can be appropriately combined for implementation. For example, in a semiconductor device including a gate pad, a current sensing pad, and a temperature sensing pad, the structures described in the above embodiments can also be applied to each of the gate pad, the current sensing pad, and the temperature sensing pad. Thus, a high-functionality semiconductor device that integrates current sensing and temperature sensing functions without reducing the area of ​​the active region can be provided.

[0317] The following are examples of features extracted from this specification and accompanying drawings. The numbers in parentheses below indicate corresponding constituent elements in the above embodiments, but are not intended to limit the scope of each item. The term "semiconductor device" in the following items may also be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "wide bandgap semiconductor switching device," or "SiC semiconductor switching device."

[0318] Existing semiconductor devices include gate pads and source pads for wire bonding. Below the source pads is an active region containing a FET structure. Below the gate pads is a non-active region without a FET structure. To ensure sufficient bonding area with the wires, the gate pads need to be formed to a certain size. Therefore, expanding the active region without changing the size of the gate pads requires increasing the overall chip size.

[0319] Therefore, one objective of the following projects is to provide a semiconductor device that can mitigate design constraints caused by electrodes. Another objective of the following projects is to provide a semiconductor device that can expand the active region without increasing chip size.

[0320] [A1] A semiconductor device 1, 101, 101a, 201, 201a, 201b, 501: hereinafter simply referred to as "semiconductor device 1, etc.", includes:

[0321] Semiconductor layer 10, comprising SiC, having a first main surface 11 on one side and a second main surface 12 on the other side;

[0322] Vertical transistor 2 is formed on the semiconductor layer 10;

[0323] The first electrode 50 / 150 is disposed on the first main surface 11;

[0324] The second electrode 55 is disposed on the first main surface 11 with a gap from the first electrode 50 / 150.

[0325] The first electrode pad 70 / 170 is disposed on the side opposite to the semiconductor layer 10, such that at least a portion of it overlaps with the first electrode 50 / 150 when viewed from above, and is electrically connected to the first electrode 50 / 150; and

[0326] The electrode 40 is disposed on the second main surface 12.

[0327] When viewed from above, the first electrode pad 70 / 170 overlaps with a portion of the second electrode 55.

[0328] [A2] According to the semiconductor device 1, etc. described in A1,

[0329] It also includes a first insulating layer 63, which is located between the first electrode pads 70 / 170 and the second electrode 55 in a direction z perpendicular to the first main surface 11.

[0330] [A3] According to the semiconductor device 1, etc. described in A2,

[0331] The side surface of the first insulating layer 63 is formed as a plane extending in the vertical direction z.

[0332] [A4] Semiconductor device 1, etc., as described in A2 or A3,

[0333] It also includes a second electrode pad 75 electrically connected to the second electrode 55, wherein the end of the second electrode pad 75 on the side of the first electrode pad 70 / 170 is located on the first insulating layer 63.

[0334] [A5] According to the semiconductor device 1, etc. described in A4,

[0335] It also includes a second insulating layer 66, which covers the boundary 80 between the first electrode pads 70 / 170 and the second electrode pads 75.

[0336] [A6] The semiconductor device 1, etc., described in any one of A1 to A5

[0337] The aforementioned vertical transistor 2 includes a source region 17 formed on the surface of the first main surface 11, a gate insulating film 23 covering the source region 17, a gate electrode 20 facing the source region 17 through the gate insulating film 23, and drain regions 10, 13, and 14 formed in the semiconductor layer 10. The first electrode 50 / 150 is electrically connected to the gate electrode 20, the second electrode 55 is electrically connected to the source region 17, and the electrode 40 is electrically connected to the drain regions 10, 13, and 14.

[0338] [A7] According to the semiconductor device 1, etc. described in A6,

[0339] The aforementioned vertical transistor 2 includes a main cell region 103 that generates drain current when viewed from above, and a current detection cell region 104 that generates a sensing current for detecting the drain current. The aforementioned second electrode 55 is disposed in a region that overlaps with the aforementioned main cell region 103 when viewed from above.

[0340] [A8] The semiconductor device 1, etc., described in A7 also includes:

[0341] The third electrode 150, when viewed from above, is disposed with a gap between the first electrode 50 and the second electrode 55 in a region overlapping with the current detection unit region 104; and

[0342] The third electrode pad 170 is disposed on the side opposite to the semiconductor layer 10, such that at least a portion of it overlaps with the third electrode 150 when viewed from above, and is electrically connected to the third electrode 150.

[0343] [A9] According to the semiconductor device 1, etc. described in A8,

[0344] The aforementioned third electrode pad 170 overlaps with a portion of the aforementioned second electrode 55 when viewed from above.

[0345] [A10] The semiconductor device 1, etc., as described in any one of A1 to A9, further includes:

[0346] Insulating layer 260, which covers a portion of the aforementioned first main surface 11;

[0347] The diode 290 is disposed on the insulating layer 260 and has a first polarity portion 291 and a second polarity portion 292 that forms a pn junction with the first polarity portion 291.

[0348] The first polarity electrode pad 270 is electrically connected to the first polarity portion 291 above the diode 290; and

[0349] The second polarity electrode pad 275 is electrically connected to the second polarity portion 292 above the diode 290.

[0350] [A11] According to the semiconductor device 1, etc. described in A10,

[0351] At least one of the first polarity electrode pad 270 and the second polarity electrode pad 275 overlaps with a portion of the second electrode 55 when viewed from above.

[0352] [A12] A method for manufacturing a semiconductor device 1, etc., comprising:

[0353] The process of preparing a semiconductor layer 10, which includes SiC, has a first main surface 11 on one side and a second main surface 12 on the other side, and includes a vertical transistor 2.

[0354] The process of forming the first electrode 50 / 150 and the second electrode 55 with gaps on the first main surface 11; and

[0355] The process of forming a first electrode pad 70 / 170 on the side opposite to the semiconductor layer 10, such that at least a portion of it overlaps with and is electrically connected to the first electrode 50 / 150 when viewed from above.

[0356] In the process of forming the first electrode pad 70 / 170, the first electrode pad 70 / 170 is formed to overlap with a portion of the second electrode 55.

[0357] [B1] A semiconductor device 1, etc., comprising:

[0358] Semiconductor layer 10, having a main surface 11;

[0359] Switching element 2 is formed on the semiconductor layer 10;

[0360] The first electrode 50 / 150 is disposed on the main surface 11 and is electrically connected to the switching element 2.

[0361] The second electrode 55 is disposed on the main surface 11 with a gap from the first electrode 50 / 150 and is electrically connected to the switching element 2.

[0362] The first terminal electrode 70 / 170 has a portion that overlaps with the first electrode 50 / 150 when viewed from above, and a portion that overlaps with the second electrode 55, and is electrically connected to the first electrode 50 / 150; and

[0363] The second terminal electrode 75 has a portion that overlaps with the second electrode 55 when viewed from above, and is electrically connected to the second electrode 55.

[0364] [B2] According to the semiconductor device 1, etc. described in B1,

[0365] The aforementioned semiconductor layer 10 comprises SiC.

[0366] [B3] The semiconductor device 1, etc., as described in B1 or B2,

[0367] The first terminal electrode 70 / 170 is connected to the first electrode 50 / 150 with a first area and has an electrode surface 73 that exceeds the first area.

[0368] [B4] The semiconductor device 1, etc., described in any one of B1 to B3.

[0369] The second terminal electrode 75, when viewed from above, has an area of ​​more than 170 of the first terminal electrode 70.

[0370] [B5] The semiconductor device 1, etc., as described in any one of B1 to B4

[0371] The aforementioned first terminal electrode 70 / 170 intersects with at least a portion of the aforementioned first electrode 50 / 150 when viewed from above.

[0372] [B6] The semiconductor device 1, etc., as described in any one of B1 to B5

[0373] The second terminal electrode 75 has a portion that overlaps with the first electrode 50 / 150 when viewed from above.

[0374] [B7] The semiconductor device 1, etc., as described in any one of B1 to B6.

[0375] The first electrode 50 / 150 is a control electrode that transmits the control signal of the switching element 2, and the second electrode 55 is a non-control electrode.

[0376] [B8] The semiconductor device 1, etc., as described in any one of B1 to B7

[0377] The aforementioned switching element 2 includes a gate 20 and a source 17. The first electrode 50 / 150 is electrically connected to the gate 20, and the second electrode 55 is electrically connected to the source 17.

[0378] [B9] The semiconductor device 1, etc., as described in any one of B1 to B8

[0379] It also includes a first insulator 63 covering the second electrode 55, the first terminal electrode 70 / 170 having a portion opposite to the second electrode 55 through the first insulator 63, and the second terminal electrode 75 having a portion opposite to the second electrode 55 through the first insulator 63.

[0380] [B10] According to the semiconductor device 1, etc., described in B9,

[0381] The first terminal electrode 70 / 170 has a side surface that is disposed above the second electrode 55 in a manner that is opposite to the second electrode 55 through the first insulator 63. The second terminal electrode 75 has a side surface that is disposed above the second electrode 55 in a manner that is opposite to the second electrode 55 through the first insulator 63, and a gap 80 is formed between the side surface of the first terminal electrode 70 / 170 to expose the first insulator 63.

[0382] [B11] According to the semiconductor device 1, etc., described in B10,

[0383] It also includes a second insulator 66, which covers the first insulator 63 within the gap 80 and is opposed to the second electrode 55 through the first insulator 63.

[0384] [B12] The semiconductor device 1, etc., as described in any one of B9 to B11

[0385] The first insulator 63 covers the first electrode 50 / 150, the first terminal electrode 70 / 170 has a portion that faces the first electrode 50 / 150 through the first insulator 63, and the second terminal electrode 75 has a portion that faces the first electrode 50 / 150 through the first insulator 63.

[0386] [B13] The semiconductor device 1, etc., as described in any one of B1 to B12, further includes:

[0387] Active regions 3, 103, and 203 are disposed in the aforementioned semiconductor layer 10; and

[0388] Non-active regions 4, 104, and 204 are regions located outside the active regions 3, 103, and 203 in the semiconductor layer 10.

[0389] The aforementioned switching element 2 is formed in the aforementioned active regions 3, 103, and 203. The aforementioned first electrode 50 / 150 is disposed in the region that overlaps with the aforementioned non-active regions 4, 104, and 204 when viewed from above. The aforementioned second electrode 55 is disposed in the region that overlaps with the aforementioned active regions 3, 103, and 203 when viewed from above. The aforementioned first terminal electrode 70 / 170 is disposed in the region that overlaps with the aforementioned active regions 3, 103, and 203 and the aforementioned non-active regions 4, 104, and 204 when viewed from above. The aforementioned second terminal electrode 75 is disposed in the region that overlaps with the aforementioned active regions 3, 103, and 203 when viewed from above.

[0390] [B14] According to the semiconductor device 1, etc., described in B13,

[0391] The active regions 3, 103, and 203 include the main cell region 103 disposed in the semiconductor layer 10. The non-active regions 4, 104, and 204 include the sensing cell region 104 disposed in the semiconductor layer 10 in a region different from the main cell region 103. The switching element 2 includes a main switching element 2 formed in the main cell region 103 to generate a main current, and a sensing switching element 2 formed in the sensing cell region 104 to generate a monitoring current for detecting the main current.

[0392] [B15] According to the semiconductor device 1, etc., described in B14,

[0393] The first electrode 50 / 150 is electrically connected to the main switching element 2. The second electrode 55 is disposed in the area that overlaps with the main unit area 103 when viewed from above, and is electrically connected to the main switching element 2. The first terminal electrode 70 / 170 is disposed in the area that overlaps with the main unit area 103 and the non-active areas 4, 104, and 204 when viewed from above. The second terminal electrode 75 is disposed in the area that overlaps with the main unit area 103 when viewed from above.

[0394] [B16] The semiconductor device 1, etc., as described in B14 or B15,

[0395] The first electrode 50 / 150 is electrically connected to the sensing switch element 2.

[0396] [B17] The semiconductor device 1, etc., as described in any one of B14 to B16, further includes:

[0397] The third electrode 150, when viewed from above, is disposed with a gap between the first electrode 50 and the second electrode 55 in a region overlapping the sensing unit region 104, and is electrically connected to the sensing switch element 2; and

[0398] The third terminal electrode 170 has a portion that overlaps with the third electrode 150 when viewed from above, and is electrically connected to the third electrode 150.

[0399] [B18] The semiconductor device 1, etc., as described in any one of B13 to B17, further includes:

[0400] Diode 290, which is formed in the aforementioned non-active regions 4, 104, and 204; and

[0401] The polarized terminal electrodes 270 and 275 have portions that overlap with the diode 290 when viewed from above, and are electrically connected to the diode 290.

[0402] [B19] A semiconductor device 1, etc., comprising:

[0403] Semiconductor layer 10, having a main surface 11;

[0404] Main component 2, which is formed on the semiconductor layer 10, generates main current;

[0405] The sensing element 2 is formed in the semiconductor layer 10 in a region different from the main element 2, and generates a monitoring current to monitor the main current.

[0406] The first electrode 50 is disposed on the main surface 11 and is electrically connected to the main component 2.

[0407] The second electrode 55 is disposed on the main surface 11 with a gap from the first electrode 50 and is electrically connected to the main component 2.

[0408] The third electrode 150 is disposed on the main surface 11 with a gap between it and the first electrode 50 and the second electrode 55, and is electrically connected to the sensing element 2.

[0409] A first terminal electrode 70 is electrically connected to the first electrode 50 above the first electrode 50.

[0410] The second terminal electrode 75 is electrically connected to the second electrode 55 above it; and

[0411] The third terminal electrode 170 has a portion that overlaps with the third electrode 150 when viewed from above, and a portion that overlaps with the second electrode 55, and is electrically connected to the third electrode 150.

[0412] [B20] A semiconductor device 1, etc., comprising:

[0413] Semiconductor layer 10, having a main surface 11;

[0414] Switching element 2 is formed on the semiconductor layer 10;

[0415] Diode 290 is formed in the semiconductor layer 10 in a region different from the switching element 2 described above;

[0416] The first electrode 50 / 150 is disposed on the main surface 11 and is electrically connected to the switching element 2.

[0417] The second electrode 55 is disposed on the main surface 11 with a gap from the first electrode 50 / 150 and is electrically connected to the switching element 2.

[0418] The first terminal electrode 70 / 170 is electrically connected to the first electrode 50 / 150 above the first electrode 50 / 150.

[0419] The second terminal electrode 75 is electrically connected to the second electrode 55 above it; and

[0420] The polarized terminal electrodes 270 and 275 have portions that overlap with the diode 290 when viewed from above, and portions that overlap with the second electrode 55, and are electrically connected to the diode 290.

[0421] [C1] A semiconductor device 1, etc., comprising:

[0422] Semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side, and comprises SiC;

[0423] Active regions 3, 103, and 203 are located on the aforementioned first main surface 11;

[0424] Non-active regions 4, 104, and 204 are located outside the active regions 3, 103, and 203 in the first main surface 11.

[0425] A first insulating layer 61 covers the aforementioned first main surface 11;

[0426] The first main electrode layer 55 is disposed on the first insulating layer 61 in such a way that it overlaps with the active regions 3, 103, and 203 when viewed from above.

[0427] The first conductive layer 50 / 150 / 290 is disposed on the first insulating layer 61 with a gap from the first main electrode layer 55, in a manner that overlaps with the non-active regions 4, 104, and 204 when viewed from above, and is electrically separated from the first main electrode layer 55.

[0428] The second insulating layer 63 covers the first main electrode layer 55 and the first conductive layer 50 / 150 / 290.

[0429] The second conductive layer 70 / 170 / 270 / 275 is disposed on the second insulating layer 63 such that it overlaps with the first main electrode layer 55 when viewed from above, is electrically separated from the first main electrode layer 55, and is electrically connected to the first conductive layer 50 / 150 / 290; and

[0430] Electrode 40, which covers the aforementioned second main surface 12.

[0431] [C2] According to the semiconductor device 1, etc., described in C1,

[0432] It also includes a switching element 2 formed in the semiconductor layer 10 in the active regions 3, 103, and 203, and the first conductive layer 50 / 150 / 290 and the second conductive layer 70 / 170 / 270 / 275 are electrically connected to the switching element 2.

[0433] [C3] According to the semiconductor device 1, etc. described in C2,

[0434] The aforementioned switching element 2 includes at least one of MISFET (Metal Insulator Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor).

[0435] [C4] According to the semiconductor device 1 described in C3,

[0436] The first conductive layer 50 / 150 and the second conductive layer 70 / 170 are electrically connected to the gate of the switching element 2 to form a first transmission path for the gate voltage.

[0437] [C5] According to the semiconductor device 1, etc., described in C1,

[0438] It also includes a current detection element 2 formed on the semiconductor layer 10, and the first conductive layer 150 and the second conductive layer 170 are electrically connected to the current detection element 2 to form a second transmission path for the signal generated by the current detection element 2.

[0439] [C6] According to the semiconductor device 1, etc., described in C5,

[0440] The aforementioned current sensing element 2 is formed in the aforementioned non-active regions 4, 104, and 204.

[0441] [C7] According to the semiconductor device 1, etc., described in C1,

[0442] The first conductive layer 290 is composed of a diode 290, and a third transmission path for the current flowing in the diode 290 is formed between it and the second conductive layer 270 / 275.

[0443] [C8] According to the semiconductor device 1 described in C7,

[0444] The diode 290 mentioned above is a temperature-sensing diode 290, and the third transmission path mentioned above transmits a signal for detecting the temperature of the semiconductor layer 10.

[0445] [C9] The semiconductor device 1, etc., as described in C7 or C8,

[0446] The aforementioned diode 290 is formed in the aforementioned non-active regions 4, 104, and 204.

[0447] [C10] The semiconductor device 1, etc., as described in any one of C1 to C9.

[0448] The first conductive layer 50 / 150 / 290 is made of substantially the same thickness and substantially the same material as the first main electrode layer 55.

[0449] The phrase "substantially identical" as used here means that the first main electrode layer 55 and the first conductive layers 50 / 150 / 290 are formed through the same process (manufacturing steps) and thus have the same structure (thickness and material).

[0450] [C11] The semiconductor device 1, etc., as described in any one of C1 to C10

[0451] It also includes a second main electrode layer 75, which overlaps with the first main electrode layer 55 when viewed from above, and is disposed on the second insulating layer 63 with gaps between it and the second conductive layer 70 / 170 / 270 / 275.

[0452] [C12] According to the semiconductor device 1, etc., described in C11,

[0453] The second main electrode layer (75) is made of substantially the same thickness and substantially the same material as the second conductive layer 70 / 170 / 270 / 275. "Substantially the same" means that the second main electrode layer 75 and the second conductive layer 70 / 170 / 270 / 275 are formed through the same process (manufacturing steps), thus having the same structure (thickness and material).

[0454] [C13] The semiconductor device 1, etc., as described in C11 or C12,

[0455] At least one of the aforementioned second conductive layer 70 / 170 / 270 / 275 and the aforementioned second main electrode layer 75 is exposed to the outside in such a way as to be electrically connected to external terminals 302d, 302g, 302s, 402.

[0456] [C14] According to the semiconductor device 1, etc., described in C13,

[0457] At least one of the second conductive layer 70 / 170 / 270 / 275 and the second main electrode layer 75 is configured to be electrically connected to the external terminals 302d, 302g, 302s, and 402 via bonding leads 303g, 303s, solder 502, or sintered metal 502.

[0458] [C15] The semiconductor device 1, etc., as described in C13 or C14,

[0459] The aforementioned external terminals 302d, 302g, 302s, and 402 are lead frames.

[0460] [C16] The semiconductor device 1, etc., as described in any one of C1 to C10

[0461] The aforementioned first main electrode layer 55 is exposed to the outside in a manner that is electrically connected to external terminals 302d, 302g, 302s, and 402.

[0462] [C17] According to the semiconductor device 1, etc., described in C16,

[0463] The first main electrode layer 55 is configured to be electrically connected to the external terminals 302d, 302g, 302s, and 402 via bonding leads 303g, 303s, solder 502, or sintered metal 502.

[0464] [C18] The semiconductor device 1, etc., as described in C16 or C17,

[0465] The aforementioned external terminals 302d, 302g, 302s, and 402 are lead frames.

[0466] The semiconductor device [C1] to [C18] may also include at least one of the first transmission path, the second transmission path, and the third transmission path [C4] to [C8]. That is, in the semiconductor device, the first transmission path, the second transmission path, and the third transmission path may be provided individually or in combination. Specifically, a semiconductor device may also be used that includes only any one of the first transmission path, the second transmission path, and the third transmission path.

[0467] Alternatively, a semiconductor device comprising any two of the first, second, and third transmission paths may be used. Alternatively, a semiconductor device comprising all of the first, second, and third transmission paths may be used. When multiple transmission paths are provided, it is preferable that at least one transmission path has the structure described above [C1]. In this case, it is particularly preferable that all of the multiple transmission paths have the structure described above [C1].

[0468] [D1] A semiconductor device comprising a vertical transistor, comprising:

[0469] A semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and containing SiC as the main component;

[0470] The first electrode covers a portion of the aforementioned first main surface;

[0471] The second electrode is disposed at a distance from the first electrode when viewed from above, and covers a portion of the first main surface;

[0472] A first electrode pad, disposed on the side opposite to the semiconductor layer relative to the first electrode, at least partially overlaps with the first electrode when viewed from above, and is electrically connected to the first electrode; and

[0473] Electrodes, which are disposed on the aforementioned second main surface,

[0474] The first electrode pad mentioned above overlaps with a portion of the second electrode when viewed from above.

[0475] [D2] Based on the semiconductor device described in D1,

[0476] It also includes a first insulating layer, which is located between the first electrode pad and the second electrode in a direction perpendicular to the first main surface.

[0477] [D3] Based on the semiconductor device described in D2,

[0478] The side surface of the first insulating layer is a plane in a direction perpendicular to the first main surface.

[0479] [D4] The semiconductor device described in D2 or D3,

[0480] It also includes a second electrode pad that is electrically connected to the second electrode, wherein the end of the second electrode pad on the side of the first electrode pad is located on the first insulating layer.

[0481] [D5] Based on the semiconductor device described in D4,

[0482] It also has a second insulating layer that covers the boundary between the first electrode pad and the second electrode pad.

[0483] [D6] The semiconductor device described in any one of D1 to D5

[0484] The aforementioned vertical transistor includes: a source region formed on the surface of the first main surface of the semiconductor layer; a gate electrode adjacent to the source region via a gate insulating film; and a drain region formed on the semiconductor layer, wherein the first electrode is electrically connected to the gate electrode and the second electrode is electrically connected to the source region.

[0485] [D7] According to the semiconductor device described in D6,

[0486] Viewed from above, the aforementioned vertical transistor has a main cell region for conducting drain current and a current detection cell region for detecting drain current, and the aforementioned second electrode is configured corresponding to the aforementioned main cell region.

[0487] The aforementioned semiconductor device also includes:

[0488] The third electrode, when viewed from above, is positioned with a gap between it and the first and second electrodes, and is configured corresponding to the current detection unit area; and

[0489] The third electrode pad is disposed on the side opposite to the semiconductor layer, and at least a portion of it overlaps with the third electrode when viewed from above, and is electrically connected to the third electrode.

[0490] The aforementioned third electrode pad overlaps with a portion of the aforementioned second electrode when viewed from above.

[0491] [D8] The semiconductor device according to D6 or D7 further comprises:

[0492] A diode disposed on an insulating layer covering a portion of the first main surface; an anode electrode pad electrically connected to the p-type semiconductor layer of the diode; and a cathode electrode pad electrically connected to the n-type semiconductor layer of the diode, wherein at least one of the anode electrode pad and the cathode electrode pad overlaps with a portion of the second electrode when viewed from above.

[0493] [D9] A method for manufacturing a semiconductor device, comprising:

[0494] In the first step, a first electrode and a second electrode are formed, spaced apart from each other, covering a portion of the first main surface of the semiconductor layer. The semiconductor layer has a first main surface and a second main surface opposite to the first main surface, and contains SiC as its main component.

[0495] In the second step, a first electrode pad electrically connected to the first electrode is formed on the side opposite to the semiconductor layer, such that at least a portion of the first electrode pad overlaps with the first electrode when viewed from above.

[0496] The first electrode pad mentioned above overlaps with a portion of the second electrode when viewed from above.

[0497] [E1] A semiconductor device comprising:

[0498] A semiconductor layer having a first main surface having an active region and a non-active region, and a second main surface opposite to the first main surface, and comprising SiC as the main component.

[0499] A first insulating layer is formed on the aforementioned first main surface;

[0500] A first main electrode layer is formed on the first insulating layer and in the region corresponding to the active region.

[0501] A first conductive layer is formed on the first insulating layer, electrically separated from the first main electrode layer, and formed in the region corresponding to the non-active region.

[0502] A second insulating layer is formed on the first main electrode layer and the first conductive layer.

[0503] A second conductive layer, formed on the second insulating layer, is electrically connected to the first conductive layer and electrically separated from the first main electrode layer, a portion of which is formed in a region overlapping the first main electrode layer in the thickness direction of the semiconductor layer; and

[0504] Electrodes are formed on the aforementioned second principal surface.

[0505] [E2] A semiconductor device has an insulated gate driven type switching element including a MOSFET or an IGBT, wherein a first conductive layer and a second conductive layer constitute a transmission path for a control signal used to control the insulated gate driven type switching element.

[0506] [E3] That is, the first conductive layer and the second conductive layer can also be connected to the gate electrode of the switching element to form a first transmission path as a transmission path for the control signal of the gate voltage.

[0507] [E4] In addition, the first conductive layer and the second conductive layer can also be connected to the source electrode (emitter electrode) of the current detection element to form a second transmission path as a transmission path for detecting the current flowing to the semiconductor device.

[0508] [E5] In addition, the first conductive layer and the second conductive layer can also be connected to the electrodes of the diode used for temperature detection of the semiconductor device to form a third transmission path as a transmission path for a detection signal used to detect the temperature of the semiconductor device.

[0509] [E6] The first, second, and third transmission paths can be individually located in the semiconductor device or multiple paths can be provided.

[0510] [E7] Specifically, it can be a structure that only provides a first transmission path, or it can provide a second or third transmission path in addition to the first transmission path, or it can be a semiconductor device that has all of the first, second and third transmission paths.

[0511] [E8] When multiple transmission paths are provided, it is preferable to adopt a structure that satisfies the above notes for all of the transmission paths, but it is also possible to satisfy the above notes for at least one transmission path.

[0512] [E9] The first main electrode layer and the first conductive layer may also be made of substantially the same thickness and material. “Substantially the same” means that the first main electrode layer and the first conductive layer are formed through the same process, thus becoming the same structure.

[0513] [E10] Alternatively, a second main electrode layer may be formed on top of the first main electrode layer.

[0514] [E11] In this case, the second main electrode layer and the second conductive layer can also be made of substantially the same thickness and material.

[0515] [E12] The second conductive layer and the second main electrode layer are exposed on the surface of the semiconductor device for connection with the corresponding external terminals.

[0516] [E13] Furthermore, in the absence of a second main electrode layer, the first main electrode layer may also be exposed on the surface of the semiconductor device for connection with external terminals.

[0517] [E14] The connection between the second conductive layer and the second main electrode layer and the corresponding external terminals such as lead frames is made by lead bonding, but the second conductive layer and the second main electrode layer can also be bonded to the external terminals by soldering or sintering metal.

[0518] [E15] The connection between the second conductive layer and the external terminal is made by wire bonding, but the second main electrode layer and the external terminal can also be bonded by soldering or sintering metal.

[0519] In summary, one or more embodiments of a semiconductor device and a method for manufacturing a semiconductor device have been described based on the embodiments described above, but the present invention is not limited to these embodiments. Various modifications, substitutions, additions, omissions, etc., can be applied to each of the above embodiments within the scope of the technical solution or its equivalents. Various modifications that can be conceived by those skilled in the art, and combinations of various constituent elements in different embodiments, are also included within the scope of the present invention, as long as they do not depart from the spirit of the present invention. As for industrial applicability, the present invention can be used in semiconductor devices and semiconductor packages, etc.

[0520] Explanation of symbols

[0521] 1—Semiconductor device, 2—Vertical transistor, 3—Active region, 4—Non-active region, 10—Semiconductor layer, 11—First main surface, 12—Second main surface, 13—Semiconductor substrate, 14—Epiaxial layer, 17—Source region, 20—Gate electrode, 23—Gate insulating layer, 40—Drain electrode, 50—Main surface gate electrode, 55—Main surface source electrode, 63—Upper insulating layer, 66—Protective insulating layer, 70—Gate pad, 75—Source pad, 80—Boundary region, 101—Semiconductor device, 101a—Semiconductor device, 103—Active region, 104—Non-active region 150—Current sensing electrode, 170—Current sensing pad, 201—Semiconductor device, 201a—Semiconductor device, 201b—Semiconductor device, 203—Active region, 204—Non-active region, 260—Insulating layer, 270—Anode electrode pad, 275—Cathode electrode pad, 290—Diode, 291—P-type semiconductor layer, 292—N-type semiconductor layer, 302d—Terminal, 302g—Terminal, 302s—Terminal, 402—Terminal, 303g—Bond lead, 303s—Bond lead, 501—Semiconductor device, 502—Bond material.

Claims

1. A semiconductor device, characterized by comprising: have: A semiconductor layer having a main surface and having an active region and an active region disposed outside the active region; A switching element formed in the active region of the semiconductor layer and having a gate electrode, a source region and a drain region. The first electrode is disposed on the main surface in the non-active region and is electrically connected to the gate electrode of the switching element. The first insulating layer has multiple contact holes in the aforementioned active region; The second electrode, when viewed from above, is disposed on the main surface of the active region through the first insulating layer with a gap from the first electrode, and is electrically connected to the source region of the switching element through the contact hole. A second insulating layer is disposed on the aforementioned second electrode; A first terminal electrode has a portion overlapping the first electrode when viewed from above, and a portion overlapping the second electrode; it is electrically connected to the first electrode and electrically insulated from the second electrode by the second insulating layer; and The second terminal electrode has a portion that overlaps with the aforementioned second electrode when viewed from above, and is electrically connected to the aforementioned second electrode. The second electrode has a first portion embedded in the first insulating layer and a second portion formed on the first insulating layer. The first part mentioned above contains tungsten or tungsten alloys. The second part mentioned above contains aluminum or aluminum alloy. The second electrode is arranged to surround the first electrode when viewed from above.

2. The semiconductor device according to claim 1, characterized in that, The first part mentioned above is formed by a barrier film made of titanium or titanium nitride.

3. The semiconductor device according to claim 2, characterized in that, The second part includes a first base layer formed on the first insulating layer and a first metal layer made of aluminum or an aluminum alloy formed on the first base layer.

4. The semiconductor device according to claim 3, characterized in that, The first substrate layer is formed by a barrier film, which is made of titanium.

5. The semiconductor device according to claim 4, characterized in that, It also includes a gate finger that is connected to the gate electrode of the switching element and has a portion that overlaps with the first electrode. The first electrode mentioned above contains aluminum or an aluminum alloy. The first electrode is electrically connected to the gate finger via a through hole provided in the first insulating layer.

6. The semiconductor device according to claim 4, characterized in that, The first electrode includes a second base layer formed on the first insulating layer and a second metal layer made of aluminum or an aluminum alloy formed on the second base layer.

7. The semiconductor device according to claim 6, characterized in that, The second substrate layer is formed of a barrier film, which is formed of titanium.

8. The semiconductor device according to claim 4, characterized in that, The aforementioned semiconductor layer contains SiC.

9. The semiconductor device according to claim 8, characterized in that, It also includes an end insulating layer that covers the outer periphery of the semiconductor layer. The first insulating layer covers the outer periphery of the semiconductor layer. The aforementioned end insulating layer covers the semiconductor layer at the outer periphery of the aforementioned semiconductor layer via the aforementioned first insulating layer.

10. The semiconductor device according to claim 9, characterized in that, The aforementioned end insulation layer is formed of the same insulating material as the aforementioned second insulation layer.

11. The semiconductor device according to claim 8, characterized in that, The first terminal electrode includes: a connecting portion formed in a through hole formed in the second insulating layer and connected to the first electrode; and a wide portion extending outward from the connecting portion. The aforementioned connecting portion and the aforementioned wide portion are formed of the same conductive material.

12. The semiconductor device according to claim 11, characterized in that, The portion of the first terminal electrode that overlaps with the connecting portion is recessed toward the first electrode.

13. The semiconductor device according to claim 8, characterized in that, The above first terminal electrode has 640000 μm 2 The above and 1000000 μm 2 The following area.

14. The semiconductor device according to claim 8, characterized in that, It also includes a bonding lead, which is bonded to the aforementioned first terminal electrode. The first terminal electrode includes: a connecting portion formed in a through hole formed in the second insulating layer and connected to the first electrode; and a wide portion extending outward from the connecting portion. The aforementioned connecting lead is joined to an area that does not overlap with the aforementioned connecting portion when viewed from above.

15. The semiconductor device according to claim 8, characterized in that, The first terminal electrode has a side surface disposed above the second electrode, facing it through the second insulating layer. The second terminal electrode is disposed above the second electrode in such a way that it is opposite to the second electrode through the second insulating layer, and a side surface is formed between it and the side surface of the first terminal electrode, exposing the second insulating layer.

16. The semiconductor device according to claim 15, characterized in that, It also includes a third insulating layer that covers the second insulating layer within the aforementioned gap and is positioned opposite the second electrode through the second insulating layer.

17. The semiconductor device according to claim 16, characterized in that, It also includes an end insulating layer that covers the outer periphery of the semiconductor layer. The first insulating layer covers the outer periphery of the semiconductor layer. The aforementioned end insulating layer covers the semiconductor layer at its outer periphery via the aforementioned first insulating layer. The third insulating layer covers the semiconductor layer at its outer periphery via the first insulating layer and the end insulating layer.

18. The semiconductor device according to claim 17, characterized in that, The aforementioned end insulation layer is formed of the same insulating material as the aforementioned second insulation layer.

19. The semiconductor device according to claim 8, characterized in that, The first electrode includes: a receiving portion arranged to overlap with the first terminal electrode in a top view and electrically connected to the first terminal electrode; a power supply portion extending in a direction in a top view; and a connecting portion connecting the receiving portion and the power supply portion and extending in a direction orthogonal to the first direction.

20. The semiconductor device according to any one of claims 1 to 19, characterized in that, It also has: A metal plate, electrically connected to the aforementioned second terminal electrode; and A bonding material, which is located between the second terminal electrode and the metal plate, A first plating layer is formed on the upper surface of the second terminal electrode. The first plating layer and the metal plate are joined together by the bonding material.

21. The semiconductor device according to claim 20, characterized in that, The aforementioned first plating layer includes a metal layer whose main component is nickel.

22. The semiconductor device according to claim 21, characterized in that, A second plating layer is formed on the upper surface of the first terminal electrode.

23. The semiconductor device according to claim 1, characterized in that, The second terminal electrode is arranged to surround the first terminal electrode when viewed from above.

24. The semiconductor device according to claim 1, characterized in that, The second terminal electrode described above has a smaller area than the area of ​​the second electrode described above when viewed from above.

25. The semiconductor device according to claim 1, characterized in that, It also includes a third insulating layer, which, when viewed from above, forms a rectangular ring around the boundary between the first terminal electrode and the second terminal electrode.

26. The semiconductor device according to claim 1, characterized in that, It also includes a third insulating layer that covers the outer periphery of the semiconductor layer throughout its entire circumference.

27. The semiconductor device according to claim 1, characterized in that, The first insulating layer covers the first electrode. The first terminal electrode has a portion that faces the first electrode through the first insulating layer. The second terminal electrode has a portion that is opposite to the first electrode through the first insulating layer.

28. A semiconductor device, comprising: have: A semiconductor layer having a main surface and having an active region and an active region disposed outside the active region; A switching element formed in the active region of the semiconductor layer and having a gate electrode, a source region and a drain region. The first electrode is disposed on the main surface in the non-active region and is electrically connected to the gate electrode of the switching element. The first insulating layer has multiple contact holes in the aforementioned active region; The second electrode, when viewed from above, is disposed on the main surface of the active region through the first insulating layer with a gap from the first electrode, and is electrically connected to the source region of the switching element through the contact hole. A second insulating layer is disposed on the aforementioned second electrode; A first terminal electrode has a portion overlapping the first electrode when viewed from above, and a portion overlapping the second electrode; it is electrically connected to the first electrode and electrically insulated from the second electrode by the second insulating layer; and The second terminal electrode has a portion that overlaps with the aforementioned second electrode when viewed from above, and is electrically connected to the aforementioned second electrode. The second electrode has a first portion embedded in the first insulating layer and a second portion formed on the first insulating layer. The first part mentioned above contains tungsten or tungsten alloys. The second part mentioned above contains aluminum or aluminum alloy. The first part mentioned above is formed by a barrier film made of titanium or titanium nitride. The second part includes a first base layer formed on the first insulating layer and a first metal layer made of aluminum or an aluminum alloy formed on the first base layer. The first substrate layer is formed by a barrier film, which is made of titanium. The aforementioned semiconductor layer contains SiC. The second electrode is arranged to surround the first electrode when viewed from above.

29. The semiconductor device according to claim 28, characterized in that, It also has: A metal plate, electrically connected to the aforementioned second terminal electrode; and A bonding material, which is located between the second terminal electrode and the metal plate, A first plating layer is formed on the upper surface of the second terminal electrode. The first plating layer and the metal plate are joined together by the bonding material.

30. The semiconductor device according to claim 29, characterized in that, The aforementioned first plating layer includes a metal layer whose main component is nickel.

31. The semiconductor device according to claim 30, characterized in that, A second plating layer is formed on the upper surface of the first terminal electrode.

32. The semiconductor device according to claim 28, characterized in that, The second terminal electrode is arranged to surround the first terminal electrode when viewed from above.

33. The semiconductor device according to claim 28, characterized in that, The second terminal electrode described above has a smaller area than the area of ​​the second electrode described above when viewed from above.

34. The semiconductor device according to claim 28, characterized in that, It also includes a third insulating layer, which, when viewed from above, forms a rectangular ring around the boundary between the first terminal electrode and the second terminal electrode.

35. The semiconductor device according to claim 28, characterized in that, It also includes a third insulating layer that covers the outer periphery of the semiconductor layer throughout its entire circumference.

36. The semiconductor device according to claim 28, characterized in that, The first insulating layer covers the first electrode. The first terminal electrode has a portion that faces the first electrode through the first insulating layer. The second terminal electrode has a portion that is opposite to the first electrode through the first insulating layer.

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