Method and system for direct memory access

Abstract

A method and apparatus are described. The method includes receiving a data packet and address data, the data packet including data to be written to the memory of the computing system, the address data including an address in a set of addresses of a first address space of the computing system, identifying a subset of the set of addresses identified by a subset of addresses in a second address space associated with the memory of the computing system, determining an address from another subset of addresses in the second address space, writing the data to a region of the memory associated with the determined address, and updating an address translation table on the computing system based on the determined address.

Description

[0001] This application is a divisional application. The original application has the application number 202080042864.3 and the original application date is May 28, 2020. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a system and method for writing data to the memory of a computing system. More particularly, this disclosure relates to a system and method for performing direct memory access operations on the memory of a computing system. Background Technology

[0003] Direct memory access (DMA) allows devices or subsystems in a computing system to directly read from and write data to the system's physical memory. DMA can be implemented in a computing system through devices such as graphics processing units or sound cards, or through other processor cores in a multi-core system. DMA frees up computing resources in the computing system. In particular, DMA operations can be performed concurrently while a program is running on the main processor.

[0004] Remote direct memory access (RDMA) allows a computing system to read data from or write data to the memory of another computing system over a network. RDMA can improve network performance, thereby enabling higher throughput and lower network latency on systems that do not implement RDMA. Summary of the Invention

[0005] This disclosure aims to provide a method for a computing system, such as one that can be used to perform direct memory access operations on the memory of the computing system.

[0006] The foregoing and other objectives are achieved through the features of the independent claims. Further implementations will be apparent from the dependent claims, the specification, and the drawings.

[0007] In a first aspect, a method is provided. The method includes receiving a data packet and address data, the data packet including data to be written to the memory of a computing system, and the address data including addresses in a set of addresses in a first address space of the computing system. The method includes identifying a subset of the address set by a subset of addresses in a second address space associated with the memory of the computing system; determining an address from another subset of addresses in the second address space; writing the data to a region of the memory associated with the determined address; and updating an address translation table on the computing system based on the determined address.

[0008] The method described in the first aspect writes data into the memory of the computing system, for example, when the destination address of the data packet is not mapped and an address has not yet been allocated in a second address space. The method improves latency and reduces the overhead of performing direct memory access operations in the computing system.

[0009] According to a second aspect, an apparatus for a computing system is provided. The apparatus is arranged to identify addresses in a set of addresses from a first address space of the computing system, the data packets including data to be written to memory of the computing system, and the address data including the addresses; and to identify a subset of the set of addresses identified by a subset of addresses in a second address space associated with memory of the computing system. The apparatus is arranged to determine addresses from another subset of addresses in the second address space; write the data to a region of memory associated with the determined addresses; and send a message to the computing system to update an address translation table on the computing system based on the determined addresses.

[0010] In one implementation, identifying the address subset identified using the address subset in the second address includes accessing the address translation table; and identifying the subset based on the address translation table.

[0011] In another implementation, the second address space is the physical address space of the physical memory of the computing system.

[0012] In another implementation, the first address space is a virtual address space.

[0013] In another implementation, determining an address from another subset of addresses in the second address space includes storing address data in one or more addresses of the other subset; and determining an address from the other subset of the stored address data.

[0014] The method described in this implementation provides a method for selecting an address from a storage address pool to map an unmapped address in a first address space to the address.

[0015] In another implementation, determining an address from another subset of addresses in the second address space includes sending a query to the computing system including a request to identify addresses from the other subset; and receiving a response including address data for the addresses from the other subset of addresses in the computing system.

[0016] The method described in this implementation provides an alternative approach for determining an address from an available address pool to map an unmapped address to that address.

[0017] In another implementation, the method includes removing a defined address from the other subset of the second address space.

[0018] The method described according to this implementation provides a way to remove the determined addresses from the other subset of the second address space, and thus no longer be available to map unmapped addresses to that address.

[0019] In another implementation, the method includes determining the number of addresses in the second address space within the other subset; and supplementing the other subset when the number of addresses is below a threshold.

[0020] The address pool is supplemented according to the method described in this implementation to ensure that there are enough addresses in the pool to handle a large number of requests, including unmapped addresses in the first address space.

[0021] In another implementation, the additional subset is supplemented by determining the availability of addresses in the second address space based on a criterion; and including the addresses in the additional subset based on the determination.

[0022] In another implementation, the standard includes a standard for the computing system to use the address.

[0023] The method described in this implementation provides a standard based on memory address usage for determining address availability to replenish the address pool. This implementation of the method ensures that underutilized addresses in the computing system are reclaimed and included in a pool for mapping unmapped addresses.

[0024] In another implementation, the method includes storing address data for the other subset.

[0025] In another implementation, the address of the data packet is the destination address of the direct memory access (DMA) request.

[0026] In another implementation, the address of the data packet is the destination address of the direct memory access (DMA) request.

[0027] In another implementation, the method includes accessing at least one other address translation table, each table including an entry for each address in the set, and updating the entry of the at least one other address translation table corresponding to the packet address to identify the address of the packet using the determined address.

[0028] In another implementation, the address translation table is stored in the computing system.

[0029] In another implementation, the address translation table is stored in a device that performs direct memory access or remote direct memory access requests to the computing system.

[0030] The above and other aspects of this application will become apparent from the embodiments described below. Attached Figure Description

[0031] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0032] Figure 1 A computing system based on an example is shown.

[0033] Figure 2A This is a schematic diagram of a remote direct memory access request based on an example.

[0034] Figure 2B This is a schematic diagram of a remote direct memory access request based on an example.

[0035] Figure 3 A flowchart illustrating a method for computing a system, based on an example, is shown. Detailed Implementation

[0036] The exemplary embodiments will be described in full detail below to enable those skilled in the art to realize and implement the systems and processes described herein. It should be understood that embodiments may be embodied in many different forms, and their interpretation should not be limited to the examples described herein.

[0037] Therefore, embodiments can be modified in various ways and take various alternative forms, specific embodiments of which are illustrated in the accompanying drawings and described in detail below by way of example. This document is not intended to limit the specific forms disclosed. Rather, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. In the drawings and appropriate detailed description, elements of exemplary embodiments are consistently designated by the same reference numerals.

[0038] The terminology used to describe embodiments herein is not intended to be limiting. The articles “a,” “an,” and “the” are singular in form and therefore have a single reference; however, their use herein should not preclude the existence of multiple references. In other words, unless the context explicitly indicates otherwise, an element expressed in the singular may be numbered one or more. It should be further understood that, when used in this specification, the terms “comprises,” “includes,” and / or “comprises” specify the presence of the stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, parts, and / or combinations thereof.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall be interpreted in accordance with the conventions of the art. It should be further understood that, unless explicitly defined herein, commonly used terms shall also be interpreted as those commonly used in the relevant field, rather than as idealized or overly formalized meanings.

[0040] Figure 1 This is a block diagram of device 100. Device 100 includes a computing system 110. Device 100 can be used with the methods and systems described herein. Computing system 110 includes a central processing unit (CPU) 120. CPU 120 includes logic for reading data or writing data to memory and for executing processes on computing system 110. CPU 120 is connected to other components of computing system 110 via bus 130. Bus 130 enables data transfer between interconnected components of computing system 110.

[0041] The computing system 110 includes a storage device 140. The storage device 140 may include any type of non-transitory storage device used to store data, programs, and other information, and making that data, programs, and other information accessible via a bus 130. The storage device 140 may include at least one type of device such as a solid-state drive, hard disk drive, disk drive, or optical disk drive. The storage device 140 is connected to other components of the computing system 110 via the bus 130.

[0042] The computing system 110 includes physical memory 150. Memory 150 may include any type of non-transitory system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. Memory 150 includes multiple memory cells. Each memory cell has an address used to identify its location within memory 150. The discrete address range of memory 150 is called the physical address space.

[0043] Normally, only system software such as the BIOS and operating system, which are in the boot state, directly access physical memory 150. For other processes, the computing system 110 maintains a virtual address space. The virtual address space is similar to the physical address space, but the addresses do not correspond to locations in physical memory 150. The virtual address space provides a contiguous address space appearance for processes. The mapping from virtual addresses to physical addresses is stored in a data structure called a page table. Each entry in the page table can be called a page table entry. A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory, represented by a single page table entry. A frame is a fixed-length contiguous block of physical memory mapped from a page.

[0044] In addition to providing a contiguous address space appearance, virtual addressing can also create virtual partitions of memory 150 in two uncontiguous regions. A first region, called kernel space, is reserved for protected processes such as the BIOS and operating system. A second region, called user space, is allocated to other processes. The computing system 110 maintains the separation between kernel space and user space by preventing processes executing in user space from addressing in kernel space.

[0045] Figure 1 The CPU 120 shown includes a memory management unit (MMU) 160. The MMU 160 performs address translation to map the virtual address of a page addressed by processing to the physical address of the corresponding frame in memory 150. The MMU 160 also performs virtual memory management for processes running on the computing system 110. When pages move between different physical memory locations, the MMU 160 manages the corresponding page table entries, updating the page tables as needed.

[0046] A virtual memory management process called paging is used to move data stored at virtual addresses between physical memory 150 and other memory (such as storage device 140). When a process requests a page in the virtual address space, MMU 160 determines whether the requested page is available in memory 150 by performing address translation. If the page is available, the physical address is returned, and computation is performed on CPU 120. If the page is not available in memory 150, MMU 160 returns a page fault. Software running on the operating system (called the page manager) accesses storage device 140, restores the frame corresponding to the virtual address of the page that caused the page fault, and updates the page table in MMU 160 with the new mapping between virtual and physical addresses, where the page has been restored to memory 150.

[0047] Paging, by extending the virtual address space to secondary storage devices such as storage device 140, allows a computing system to allocate contiguous ranges of virtual addresses to processes that exceed the available space in physical memory 150. However, when all frames are in use in physical memory 150, the operating system must select a frame to reuse as the page needed by the process. The paging manager can use page replacement algorithms such as Least Recently Used (LRU) or First In First Out (FIFO) to determine which memory location in memory 150 should be freed of the requested page. The paging manager can swap pages from memory 150 to storage device 140 according to the page replacement algorithm. The paging manager updates the page table so that the page requested by the process points to the freed location in memory. The area of ​​storage device 140 reserved for this purpose is called swap space. In some cases, a page can be locked or "pinned" in memory 150 to prevent it from being swapped out to storage device 140.

[0048] The computing system 110 also includes a direct memory access (DMA) device 170. The DMA device 170 can be a disk drive, graphics card, sound card, or other hardware device. In other examples, the DMA device 170 can be another processing core similar to CPU 120. The DMA device 170 is connected to bus 130 and can interact with other components of the computing system 110 via bus 130. The DMA device 170 can execute DMA requests to memory 150. DMA requests from device 170 to memory 150 are operations such as data write operations, which are independent of CPU 120 and performed directly on locations in memory 150. Without DMA, when CPU 120 uses programmed input / output, CPU 120 would be completely occupied throughout the read or write operation and unable to perform other work. DMA allows CPU 120 to perform other operations while processing DMA requests originating from device 170. DMA is beneficial for tasks such as performing large data transfers between device 170 and memory 150. Once the DMA operation on memory 150 is complete, device 170 sends an interrupt request back to CPU 120, allowing CPU 120 to process the data from device 170, which was written to memory 150 after the DMA operation.

[0049] Similar to processes running on computing system 110, DMA requests from DMA device 170 can specify addresses in the virtual address space. In some examples, DMA device 170 is configured to perform address translation for addresses specified in the DMA request. For example, in some cases, DMA device 170 and / or computing system 110 include an input-output memory management unit (IOMMU). Figure 1 (Not shown in the image), this input / output memory management unit performs address translation for I / O devices in computing system 110, and the address translation method is similar to that performed by MMU 160 for CPU 120. In other examples, DMA device 170 uses remote process calls to the operating system to trace or query page table entries.

[0050] The computing system 110 further includes a network interface controller (NIC) 180 that connects the computing system 110 to a network 190. The NIC 180 may include a wired or wireless link to the network 190, such as Ethernet or a wireless transmitter and receiver. In some examples, the network 190 may be a local area network (LAN). In other examples, the network 190 may be a wide area network (WAN). The network 190 enables the computing system 110 to communicate with remote devices, such as other computing systems, network servers, and remote storage and data processing devices.

[0051] exist Figure 1 In this example, computing system 110 communicates with remote computing device 195 across network 190. According to the example, NIC 180 supports Remote Direct Memory Access (RDMA) requests from remote device 195 to memory 150. Similar to DMA requests from DMA device 170, RDMA requests from remote device 195 are requests to perform direct operations on locations in memory 150, bypassing the operating system of computing system 110. RDMA enables high-throughput, low-latency networking between computing system 110 and remote device 195 by using zero-copy data to memory 150 without requiring CPU 120 to copy data to other memory locations.

[0052] Similar to processes running on computing system 110 and DMA requests from DMA device 170, RDMA requests received at NIC 180 may include addresses in the virtual address space. In some examples, NIC 180 is configured to perform address translation for the addresses specified in the RDMA request. In other examples, NIC 180 uses, for example, an onboard IOMMU to trace or query page table entries. Once the physical address is determined, NIC 180 can directly write the data from the RDMA request to memory 150.

[0053] The methods and systems described herein can be used to perform DMA (or RDMA) operations because DMA requests sent to unmapped virtual addresses do not have corresponding physical addresses in memory 150.

[0054] One approach to address (R)DMA requests for unmapped virtual addresses is to pin a subset of virtual addresses that can be used by the DMA device 170 or NIC 180 to physical addresses in memory 150. This ensures that (R)DMA operations never encounter unmapped memory. However, this comes at a cost because the pinned memory cannot be used by other processes or devices in computing system 120. Furthermore, memory consumption in this scenario can impair performance because additional memory must be swapped from memory 150 to storage device 140 more frequently to accommodate the required space.

[0055] Another approach to using fixed memory allocation for DMA operations is to provide temporary fixed buffers in memory 150 for the purpose of the DMA operation. Each buffer can be reused once the last DMA request is complete. For example, input data for an RDMA request from device 195 can first be placed in a fixed buffer in memory 150 and then copied to another buffer in a subspace of the virtual address space addressed by the process. The original fixed buffer can then be reused in further DMA requests.

[0056] Unfortunately, this method also has many drawbacks. First, the latency reduction is significant due to the additional copying operation of the fixed buffer. However, this operation is necessary; otherwise, the buffer would be unavailable for other DMA requests. Furthermore, a dedicated fixed buffer pool needs to be allocated, thus incurring management overhead in the computing system 110, similar to the previously described fixed method. Other similar methods also suffer from latency penalties or large memory footprints due to excessive fixed areas in the memory 150 region.

[0057] The method and system described in this paper write data from an (R)DMA request to a buffer and then remap the virtual address to point to the buffer address. This method does not require stopping or further copying data to the buffer.

[0058] Figure 2A A simplified diagram of an example 200 of an RDMA request according to the method described herein. Figure 2A Example 200 shown is by Figure 1 The RDMA request processed by the NIC 180 shown. Figure 1 The DMA requests of the DMA device 170 shown are handled in a similar manner, and Figure 2A The examples shown are not intended to limit the other methods and examples described in this article to RDMA requests.

[0059] In Example 200 shown in 2A, Figure 1 The NIC 180 shown receives RDMA request 210. RDMA request 210 can be received by, for example... Figure 1 The remote device 195 shown receives the request. The RDMA request 210 includes a destination (virtual) address 211, which is, for example, the virtual address space address of a target process running on computing system 110, and data 212 to be written to memory 150 of computing system 110. In some cases, the data 212 may be divided into one or more packets, where the virtual address of each packet is determined by an offset from the virtual address of a first packet, represented by the virtual address 211 of the RDMA request 210. When NIC 180 receives the RDMA request 210, NIC 180 performs address translation (either by itself or using, as previously described, an onboard IOMMU) to identify the address in memory 150 for the destination virtual address 211.

[0060] Box 220 illustrates an example of translating the destination address 211. Three examples are shown in this document. When the virtual address 211 requested by RDMA has already been mapped to physical memory 150, NIC 180 simply performs address translation and writes data 212 to the corresponding location in memory 150. For example, in Figure 2AIf virtual address 211 is mapped to physical address 221 or 223, then NIC 180 writes data 212 to location 221 or 223 in memory 150, respectively. If NIC 180 determines that the page at destination address 211 is not mapped, then NIC 180 determines address 222 to write data 212 from the available address pool corresponding to the physical memory location in memory 150, and writes the data to buffer 230 located at physical address 222 in memory 150.

[0061] Figure 2B It shows the relationship with Figure 2A The same example 200 is shown. Figure 2B The diagram illustrates virtual address space 240 and process 241 addressing address ranges within virtual address space 240. Once NIC 180 determines the write... Figure 2A In the RDMA request 210, the address 222 of data 212 is sent, and NIC 180 notifies CPU 120 to update the address translation table of process 241. In some examples, CPU 120 (re)maps the virtual address in address translation table 250 of process 241 to point to the physical address 222 of buffer 230. As an illustrative example, Figure 2B The diagram illustrates the remapping of the virtual address to address 222, which previously pointed to a location in the swap space of storage device 140. In some cases, NIC 180 is configured to update address translation table 250.

[0062] Figure 3 This is a block diagram of method 300 as shown in the example. Figure 3 The method 300 shown can be used in conjunction with other methods and systems described herein. In particular, method 300 can be used in… Figure 1 The computing system 110 shown is implemented to handle DMA and RDMA requests to memory 150.

[0063] At box 310, the data packet includes data to be written to the memory of the computing system, and address data for receiving addresses from the address set in the first address space of the computing system. According to the example, the data packet can be a DMA request or an RDMA request data packet. The computing system and memory can be... Figure 1 The computing system 110 and memory 150 are shown. According to the example, the first address space is the virtual address space of the computing system.

[0064] At box 320, a subset of the address set is identified by a subset of addresses in a second address space associated with the memory of the computing system. The second address space can be the physical address space associated with the memory of the computing system. According to the example, the subset can be identified from an address translation table, which identifies a subset of the address set from the first address space by a subset of addresses in the second address space. The address translation table includes an entry for each address in the set. In other examples, the identification of the subset can be determined by accessing the output of a function that maps addresses in the first address space to addresses in the second address space.

[0065] At box 330, addresses from another subset of addresses in the second address space are determined. According to the example, determining addresses in another subset of the second address space includes accessing stored address data to obtain at least one address from the other subset, and determining the address from the stored address data. For example, when method 300... Figure 1 When implemented on the computing system 110 shown, the NIC 180 can store an address pool that is used as data to write an RDMA request in the event that the request contains an unmapped virtual address.

[0066] In box 340, data is written to the memory region associated with a specific address in the second address space. In box 350, the entry in the address translation table is updated based on the specific address. For example, when method 300... Figure 1 When implemented on the device shown, the NIC180 instructs the CPU 120 to update the address translation table. In some examples, the CPU 120 (re)maps the virtual addresses in the address translation table to point to buffer addresses in a second (physical) address space.

[0067] As an example, determining addresses from a different subset within a second address space can include sending a request to the computing system to identify addresses from the other subset, and receiving a response from the computing system that includes address data for the data from the other address subset. For instance, the NIC 180 can determine the buffer address of the IOMMU without storing the address locally.

[0068] In some examples, method 300 also includes removing a determined subset of addresses from the second address space. Method 300 may also include determining the number of addresses in the second address space within the other subset, and supplementing the other subset when the number of addresses falls below a threshold. Supplementing the other subset may include determining the availability of addresses in the second address space based on criteria, and including addresses in the other subset based on the determination. According to examples, the criteria may include standards for address usage by the computing system. These examples enable the computing system to maintain a buffer supply, writing data from DMA requests to the system on demand without interruption, without copying data to other buffers.

[0069] The methods and examples described herein provide resource-friendly and efficient (R)DMA operations. Specifically, the methods provide control flow for processing (R)DMA operations destined for unmapped memory locations. Furthermore, the methods and systems described herein utilize movable buffers that act as explicit destinations for (R)DMA operations. (R)DMA operations already mapped to memory remain unaffected.

[0070] The method described in this paper can be implemented on any device with (R)DMA capability, and is not limited to certain device types. The method and system can also be used with virtual machines as well as regular process pages. Systems implementing the method described in this paper achieve performance close to that of systems that pin the entire address space to memory, while also allowing for memory over-subscription and paging.

[0071] It should be understood that one or more steps of the methods provided in the embodiments herein can be performed by corresponding units or modules. Each unit or module can be hardware, software, or a combination thereof. For example, one or more of these units or modules can be integrated circuits, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0072] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0073] This application may be embodied in other specific devices and / or methods. The described embodiments should be considered illustrative rather than restrictive in all respects. In particular, the scope of this application is defined by the appended claims rather than by the description and drawings herein. All variations within the meaning and equivalent scope of the claims should be included within their scope.

Claims

1. A method for accessing memory, characterized in that, include: Receive data packets and address data, wherein the data packets include data to be written to the memory of the computing system, and the address data includes addresses in the address set of the first address space of the computing system; A subset of the address set is identified based on a subset of addresses in a second address space associated with the memory of the computing system; Determine addresses from another subset of addresses in the second address space; The data is written to the memory region associated with the determined address; as well as Update the address translation table on the computing system based on the determined address; The method further includes: Determine the number of addresses in the second address space within the other subset; as well as When the number of addresses falls below a threshold, the availability of addresses in the second address space is determined based on a standard; and The address is included in the other subset according to the determination, and the criteria include the criteria by which the computing system uses the address.

2. The method according to claim 1, characterized in that, Identifying the subset of addresses identified by the subset of addresses in the second address includes: Access the address translation table; and The subset is identified based on the address translation table.

3. The method according to claim 1, characterized in that, The second address space is the physical address space of the physical memory of the computing system.

4. The method according to claim 1, characterized in that, The first address space is a virtual address space.

5. The method according to claim 1, characterized in that, Determining a subset from another subset of addresses in the second address space includes: Access stored address data for one or more addresses in the other subset; and Determine the address from the other subset of the stored address data.

6. The method according to claim 1, characterized in that, Determining addresses from another subset of addresses in the second address space includes: Send a request to the computing system to identify addresses from the other subset; and Receive a response including address data for addresses from another subset of the computing system.

7. The method according to claim 1, characterized in that, This includes removing specific addresses from another subset of addresses in the second address space.

8. The method according to claim 1, characterized in that, The address of the data packet is the destination address of the direct memory access (DMA) request.

9. The method according to claim 1, characterized in that, The address of the data packet is the destination address of the remote direct memory access (RDMA) request.

10. The method according to claim 1, characterized in that, include: Access one or more other address translation tables, each table including an entry for each address in the set; as well as Update the entries in one or more other address translation tables corresponding to the address of the data packet so that the address of the data packet can be identified by the determined address.

11. The method according to claim 1, characterized in that, The address translation table is stored in the computing system.

12. The method according to claim 1, characterized in that, The address translation table is stored in the device, which performs direct memory access or remote direct memory access requests to the computing system.

13. An apparatus for a computing system, characterized in that, Arranged as: Receive data packets and address data, wherein the data packets include data to be written to the memory of the computing system, and the address data includes addresses in the address set of the first address space of the computing system; Identify addresses in the address set of the first address space of the computing system from data packets and address data; A subset of the address set identified based on a subset of addresses in the second address space associated with the memory of the computing system; Determine addresses from another subset of addresses in the second address space; The data is written to the memory region associated with the determined address; as well as The message is sent to the computing system to update the address translation table on the computing system based on the determined address; The device is further arranged as follows: Determine the number of addresses in the second address space within the other subset; and When the number of addresses falls below a threshold, the availability of addresses in the second address space is determined based on a standard; and The address is included in the other subset according to the determination, and the criteria include the criteria by which the computing system uses the address.

14. The apparatus according to claim 13, characterized in that, In order to identify the subset of addresses identified using the subset of addresses in the second address, the means is arranged as follows: Access the address translation table; and The subset is identified based on the address translation table.

15. The apparatus according to claim 13, characterized in that, The second address space is the physical address space of the physical memory of the computing system.

16. The apparatus according to claim 13, characterized in that, The first address space is the virtual address space of the computing system.

17. The apparatus according to claim 13, characterized in that, To determine addresses from another subset of addresses in the second address space, the means is arranged as follows: Store the address data in one or more addresses of the other subset; as well as Determine the address from the other subset of the stored address data.

18. The apparatus according to claim 13, characterized in that, To determine addresses from another subset of addresses in the second address space, the means is arranged as follows: Send a query, including a request, to the computing system to identify addresses from the other subset; and Receive a response including address data for addresses from another subset of the computing system.

19. The apparatus according to claim 13, characterized in that, The device is configured to send a message to the computing system including a request to remove the determined addresses from the other subset of the second address space.

20. The apparatus according to claim 13, characterized in that, The device is arranged as follows: Access one or more other address translation tables, each table including an entry for each address in the set; and Update the entries in one or more other address translation tables corresponding to the address of the data packet to identify the address of the data packet by the determined address.

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