Display driving chip, display control method and electronic device

Abstract

The application provides a display driving chip, a display control method and an electronic device. The display driving chip comprises a refresh content determination circuit and a control signal generation circuit. The refresh content determination circuit is configured to determine pixels that have changed in an image. The control signal generation circuit is configured to generate a clock signal based on the pixels that have changed in the image, the clock signal being used to turn off an electrical balance function when the display screen displays the pixels that have changed in the image, and turn on the electrical balance function when the display screen displays pixels that have not changed in the image. Thus, when there are pixels that have changed in a frame of image displayed by the display screen, there is a time period when the electrical balance function is turned on and a time period when the electrical balance function is turned off during the display of the frame of image by the display screen, so that the turning on and turning off of the electrical balance function is controlled in units of pixels in the frame of image, the electrical balance function is optimized, and the power consumption of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driver chip, a display control method, and an electronic device. Background Technology

[0002] Currently, display driver chips in electronic devices reduce power consumption by enabling the EQ (equalizer) function. The display driver chip enables and disables the EQ function on a frame-by-frame basis. If the display driver chip determines that the image to be displayed is a refresh frame, it disables the EQ function, allowing the displayed content to change. If the image to be displayed is a hold frame, it enables the EQ function, keeping the displayed content unchanged. Although the display driver chip can control the EQ function on and off on a frame-by-frame basis, reducing power consumption to some extent, the problem of high power consumption still exists. Summary of the Invention

[0003] This application provides a display driver chip, a display control method, and an electronic device, which further reduces device power consumption by optimizing the EQ function. Some embodiments of this application provide the following technical solutions:

[0004] Firstly, this application provides a display driver chip, comprising: a refresh content determination circuit and a control signal generation circuit; the refresh content determination circuit is used to determine pixels that have changed in an image; the control signal generation circuit is used to generate a clock signal based on the pixels that have changed in the image, the clock signal being used to disable the power balancing function when the display screen shows pixels that have changed in the image, and to enable the power balancing function when the display screen shows pixels that have not changed in the image. Thus, when there are pixels that have changed in a frame of an image displayed on the display screen, there are times when the power balancing function is enabled and times when it is disabled during the display of one frame of an image, thereby achieving the control of enabling and disabling the power balancing function on a pixel-by-pixel basis. Compared to controlling the power balancing function on or off on a frame-by-frame basis, this optimizes the power balancing function and reduces device power consumption. For example, in some examples, the display driver chip controls the power balancing function on or off on a row-by-row basis in a frame of an image; in some examples, the display driver chip can control the power balancing function on or off on a column-by-column basis in a frame of an image. Displaying one frame of an image on the display screen can also be referred to as refreshing one frame of an image on the display screen. Furthermore, the power balancing function can be dynamically switched on and off as changes occur in the pixels of the image, ensuring that the control of the power balancing function matches the changes in the pixels and preventing erroneous control. The changed pixels in the image can be those pixels that have changed relative to the previous frame in the frame to be displayed. For example, the frame to be displayed can be called the first frame, and the previous frame the second frame. The changed pixels in the first frame are those pixels that are in the same position but have different pixel values ​​in both the first and second frames.

[0005] In one possible implementation, the display driver chip further includes: a refresh mode determination circuit, used to determine the refresh mode of the display screen when displaying an image; a control signal generation circuit, used to generate a clock signal based on the full-screen refresh mode when the refresh mode is a global refresh mode, and the clock signal is used to control the display screen to perform a global refresh and disable the power balancing function when the refresh mode is a global refresh mode; and a control signal generation circuit, used to generate a clock signal based on the local refresh mode and the pixels that have changed in the image when the refresh mode is a local refresh mode, and the clock signal is used to disable the power balancing function when the display screen displays pixels that have changed in the image, and to enable the power balancing function when the display screen displays pixels that have not changed in the image, thereby achieving a power balancing function control mode that matches the refresh mode during global refresh and local refresh, and allowing for a period of time when the power balancing function is enabled during local refresh, so as to reduce device power consumption by optimizing the power balancing function. Furthermore, after performing at least one partial refresh, the display can perform a global refresh. A global refresh refreshes all pixels in the image displayed on the display, thereby reducing or eliminating errors in the content displayed on the display caused by device characteristic drift.

[0006] In one possible implementation, a control signal generation circuit is used to determine the activation timing of the power balancing function based on the pixels that have changed in the image, and to generate a clock signal based on the activation timing of the power balancing function, so that the clock signal can turn off the power balancing function when the display screen shows pixels that have changed in the image, and turn on the power balancing function when the display screen shows pixels that have not changed in the image.

[0007] In one possible implementation, a control signal generation circuit is used to determine a first time period in the clock signal corresponding to a pixel in the image that has changed, where the first time period is the off-time for the power balancing function; and to determine a second time period in the clock signal corresponding to a pixel in the image that has changed, where the second time period is the on-time for the power balancing function. The first time period in the clock signal corresponding to a pixel in the image is the time period during which the clock signal controls the display screen to show the changed pixels in the image, and the second time period in the clock signal corresponding to a pixel in the image is the time period during which the clock signal controls the display screen to show the unchanged pixels in the image. Thus, the control signal can accurately control the display screen to turn the power balancing function on and off when displaying pixels.

[0008] In one possible implementation, the control signal generation circuit includes: a core controller, a level shifter, a switching circuit, and an array substrate row drive controller. The core controller generates an electrical balance control signal based on pixels that have changed in the image. This signal disables the electrical balance function when the display shows pixels that have changed, and enables it when the display shows pixels that have not changed. The array substrate row drive controller generates a raw clock signal, which does not have electrical balance control functionality. The level shifter generates an intermediate clock signal based on the raw clock signal and the electrical balance control signal, and converts the intermediate clock signal from digital to analog using the level shifter and the switching circuit to obtain the final clock signal. Thus, the core controller, level shifter, switching circuit, and array substrate row drive controller generate an analog clock signal that can be applied to the display screen.

[0009] In one possible implementation, the control signal generation circuit further includes: a video timing controller and a logic combination processor; the video timing controller is used to generate a partial refresh reset reference signal based on the global refresh rate and partial refresh rate sent by the core controller, the partial refresh reset reference signal including a first control signal and a second control signal, the first control signal being used to control the display screen to perform a global refresh, and the second control signal being used to control the display screen to perform a partial refresh, wherein the proportion of the first control signal and the second control signal in the partial refresh reset reference signal is generated based on the partial refresh rate and the global refresh rate, and the period of the partial refresh reset reference signal is generated based on the global refresh rate; the logic combination processor is used to logically combine the partial refresh reset reference signal and the power balance control signal to generate a power balance switch signal, the power balance switch signal being used to disable the power balance function during a global refresh, and to control the power balance function to be turned on and off according to the pixels that change in the image during a partial refresh; and a level converter is used to generate an intermediate clock signal based on the original clock signal and the power balance switch signal. Therefore, under the action of a partial refresh reset reference signal, the display screen can perform one global refresh and multiple partial refreshes. After multiple partial refreshes, a global refresh is performed to uniformly refresh all pixels on the display screen, thereby reducing or eliminating errors in the displayed content caused by device characteristic drift. Furthermore, the EQ function can be optimized during the partial refresh process, reducing device power consumption.

[0010] In one possible implementation, the display driver chip further includes a storage controller and a frame buffer; the storage controller is used to receive image data sent by the core controller and store the image data in the frame buffer.

[0011] In one possible implementation, the refresh content determination circuit is a command receiving processor. The command receiving processor receives control commands sent by the application processor in the electronic device and determines the pixels in the image that have changed based on the coordinates of the pixels to be refreshed carried in the control commands.

[0012] Secondly, this application provides an electronic device, which includes: one or more processors and a display screen; the display driver chip, through which the processor controls the display screen.

[0013] Thirdly, this application provides a display control method, which includes: determining pixels that have changed in an image; generating a clock signal based on the pixels that have changed in the image, wherein the clock signal is used to disable the power balancing function when the display screen shows the pixels that have changed in the image, and to enable the power balancing function when the display screen shows the pixels that have not changed in the image. Thus, when there are pixels that have changed in a frame of an image displayed on the screen, there are times when the power balancing function is enabled and times when it is disabled during the display of that frame. This allows for control of the power balancing function on and off on a pixel-by-pixel basis, which optimizes the power balancing function compared to controlling it on or off on a frame-by-frame basis, thereby reducing device power consumption. Furthermore, the enabling and disabling of the power balancing function can dynamically change with the changes in the pixels that have changed in the image, ensuring that the control of the power balancing function matches the changes in the pixels and preventing erroneous control of the power balancing function.

[0014] In one possible implementation, the method further includes: determining the refresh mode of the display screen when displaying an image; generating a clock signal based on the pixels that have changed in the image, including: generating a clock signal based on the full-screen refresh mode when the refresh mode is global refresh, wherein the clock signal is used to control the display screen to perform a global refresh and disable the power balancing function; generating a clock signal based on the local refresh mode and the pixels that have changed in the image when the refresh mode is local refresh, wherein the clock signal is used to disable the power balancing function when the display screen displays pixels that have changed in the image, and to enable the power balancing function when the display screen displays pixels that have not changed in the image, thereby achieving a power balancing function control mode that matches the refresh mode during global and local refresh processes, and allowing for a period of time when the power balancing function is enabled during local refresh, ensuring that there is a period of time when the power balancing function is enabled within the refresh time of one frame of image, so as to reduce device power consumption by optimizing the power balancing function. Furthermore, the display screen can perform a global refresh after at least one local refresh, and the global refresh can refresh all pixels in the image displayed on the display screen, thereby reducing or eliminating errors in the content displayed on the display screen caused by device characteristic drift.

[0015] In one possible implementation, generating a clock signal based on pixels that have changed in the image includes: determining the activation timing of the power balancing function based on the pixels that have changed in the image, and generating a clock signal based on the activation timing of the power balancing function, such that the clock signal can turn off the power balancing function when the display shows pixels that have changed in the image, and turn on the power balancing function when the display shows pixels that have not changed in the image.

[0016] In one possible implementation, the time period in the clock signal corresponding to the pixels that have changed in the image is the time when the power balancing function is turned off, and the time period in the clock signal corresponding to the pixels that have changed in the image is the time when the power balancing function is turned on. Specifically, the first time period in the clock signal corresponding to the pixels that have changed in the image is the time period during which the clock signal controls the display screen to show the pixels that have not changed in the image, and the second time period in the clock signal corresponding to the pixels that have changed in the image is the time period during which the clock signal controls the display screen to show the pixels that have not changed in the image. Thus, the control signal can accurately control the power balancing function to be turned on and off when the display screen is showing pixels.

[0017] In one possible implementation, generating a clock signal based on pixels that have changed in the image includes: generating an electrical balance control signal based on pixels that have changed in the image, wherein the electrical balance control signal is used to disable the electrical balance function when the display screen shows pixels that have changed in the image, and to enable the electrical balance function when the display screen shows pixels that have not changed in the image; generating an original clock signal, wherein the original clock signal does not have an electrical balance control function; generating an intermediate clock signal based on the original clock signal and the electrical balance control signal, and converting the intermediate clock signal from a digital signal to an analog signal to obtain the clock signal.

[0018] In one possible implementation, generating the clock signal based on the changed pixels in the image further includes: generating a local refresh reset reference signal according to the global refresh rate and local refresh rate of the display screen, the local refresh reset reference signal including a first control signal and a second control signal, the first control signal being used to control the display screen to perform a global refresh, and the second control signal being used to control the display screen to perform a local refresh, wherein the proportion of the first control signal and the second control signal in the local refresh reset reference signal is generated based on the local refresh rate and the global refresh rate, and the period of the local refresh reset reference signal is generated based on the global refresh rate; logically combining the local refresh reset reference signal and the power balance control signal to generate a power balance switch signal, the power balance switch signal being used to disable the power balance function during a global refresh, and to control the power balance function to be turned on and off according to the changed pixels in the image during a local refresh; generating an intermediate clock signal according to the original clock signal and the power balance control signal includes: generating an intermediate clock signal according to the original clock signal and the power balance switch signal. Therefore, under the action of a partial refresh reset reference signal, the display screen can perform one global refresh and multiple partial refreshes. After multiple partial refreshes, a global refresh is performed to uniformly refresh all pixels on the display screen, thereby reducing or eliminating errors in the displayed content caused by device characteristic drift. Furthermore, the EQ function can be optimized during the partial refresh process, reducing device power consumption. Attached Figure Description

[0019] Figure 1 A waveform diagram of the clock signal provided in the embodiments of this application;

[0020] Figure 2 A schematic diagram of global refresh provided in an embodiment of this application;

[0021] Figure 3 This is a waveform diagram of partial refresh provided in an embodiment of this application;

[0022] Figure 4 A circuit structure diagram of a display driver chip provided in an embodiment of this application;

[0023] Figure 5 A waveform diagram generated by the display driver chip provided in the embodiments of this application;

[0024] Figure 6 Another circuit structure diagram of the display driver chip provided in the embodiments of this application;

[0025] Figure 7 This is a schematic diagram of another waveform generated by the display driver chip provided in the embodiments of this application;

[0026] Figure 8A hardware structure diagram of the electronic device provided in the embodiments of this application;

[0027] Figure 9 This is a schematic diagram illustrating the connection between the AP and the display screen in an electronic device provided in an embodiment of this application;

[0028] Figure 10 A flowchart of a display control method provided in an embodiment of this application;

[0029] Figure 11 Another flowchart of the display control method provided in the embodiments of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "an," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0031] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0032] The "multiple" mentioned in the embodiments of this application refers to two or more. It should be noted that in the description of the embodiments of this application, terms such as "first" and "second" are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0033] The Display Driver Integrated Circuit (DDIC) outputs two out-of-phase clock signals (GCK and GCB) to the Gate on Array (GOA) circuit in the display panel. The GOA circuit, under the influence of these clock signals, outputs a write drive signal, which refreshes the content displayed on the screen. The GOA circuit acts as the row drive circuit for one row of pixels in the pixel array of the display panel; the pixel array is the display area. The row drive circuit is also called a linear controller. The composition of the clock signal is related to whether the EQ function is enabled. The EQ function adds an intermediate voltage to the signal to facilitate the transition between the lowest and highest voltage levels. Figure 1 As shown, when the EQ function is off, the waveform of the clock signal is as follows: Figure 1 As shown by the dashed line, the clock signal includes the lowest voltage (VGLO) and the highest voltage (VGHO); when the EQ function is enabled, the waveform of the clock signal is as follows. Figure 1 As shown by the solid line, the clock signal includes VGLO, VGHO, and the intermediate voltage (V). EQ The intermediate voltage is used to transition between the lowest and highest voltages, thereby reducing the power consumption loss of the GOA control circuit caused by the peak charging and discharging current due to level switching.

[0034] Assuming the current generated by the voltage change from VGLO to VGHO is I, the device power consumption P0 = I*(VGHO - VGLO) when the EQ function is off. When the EQ function is on, the current I can be considered unchanged, but it is divided into two equal segments, and the device power consumption P1 = 1 / 2I*(VGHO - VGLO). EQ )+1 / 2I*(V EQ If -VGLO), then P0-P1=1 / 2I*(VGHO-VGLO), and (P0-P1)>0. Therefore, after the EQ function is enabled, the power consumption of the device can be reduced by the intermediate voltage.

[0035] DDIC enables and disables the EQ function on a frame-by-frame basis. The EQ function is disabled when the display refreshes content, and enabled when the display maintains its content. The display can either refresh the entire screen (all pixels) or partially refresh only a portion of the screen.

[0036] A diagram illustrating full-screen content refresh is shown below. Figure 2As shown, the DDIC stores the data displayed on the screen into a buffer. The GOA circuit converts the DDIC's serial clock into sequential write pulses (i.e., write drive signals) with driving capability. Under the action of the write drive signals, it reads data from the buffer and writes the data to the screen. For example, scanning can start from the first row of the pixel array and go to the last row, or vice versa. Each scanned row is controlled by the corresponding GOA circuit to write the data displayed in that row from the buffer to the screen. Assuming the screen has 12*10 pixels (12 rows and 10 columns), there are 12 GOA circuits on the screen side. These 12 GOA circuits control the data writing to the screen in a row-by-row scanning manner, resulting in a 100% refresh rate, meaning all pixels on the entire screen are refreshed.

[0037] exist Figure 2 In this display, the content that changes is the heart shape in the center (16 pixels, occupying 6 rows). The display can refresh the 6 rows of pixels occupied by the heart shape to achieve partial content refresh. For example, the write drive signal for the 6 rows of pixels occupied by the heart shape is valid, while the write drive signal for the other rows of pixels is invalid. When the write drive signal is valid, data can be written to the display; when the write drive signal is invalid, data writing to the display is prohibited. This allows for partial content refresh through the control of the write drive signal.

[0038] In some examples, DDIC can generate a partial refresh action signal, which instructs a portion of the pixels in the pixel array to be refreshed. This partial refresh action signal can be related to the display's frame rate, which controls the time interval for refreshing frames. Assuming the display's frame rate is 8.3 ms, the display can perform a partial refresh every 8.3 ms using the partial refresh action signal. The positions of the pixels refreshed in each partial refresh can be the same or different in the pixel array; this embodiment does not impose limitations.

[0039] like Figure 3 The Partial_act_Y shown is the partial refresh action signal, and Base_Vsync is the base frame rate synchronization signal. The period of the base frame rate synchronization signal is the same as the display's frame rate. Figure 3The Base_Vsync period is 8.3ms, so the display frame rate is 8.3ms. Partial_act_Y is used to indicate a partial refresh of a portion of the pixel array. Assuming there are Y rows of pixels requiring partial refresh, each black pulse in Partial_act_Y represents a refresh of row Y pixels. For example, with a display frame rate of 8.3ms, the display can perform a partial refresh of row Y pixels every 8.3ms using Partial_act_Y. Therefore, under the action of Partial_act_Y, the write drive signal is effective when writing data to the Y rows of pixels indicated by Partial_act_Y, but ineffective when writing data to other rows of pixels, thus achieving a partial refresh of the display by refreshing only the Y rows of pixels indicated by Partial_act_Y.

[0040] When the display performs a partial refresh, it can refresh only the Y-row pixels at a time, while the remaining rows that do not need to be refreshed remain unchanged. This reduces the number of refreshes and the refresh cycles, thereby reducing power consumption. During global or partial refreshes, the DDIC can enable or disable the EQ function. Enabling and disabling the EQ function is done on a frame-by-frame basis, where a frame represents the content displayed on the screen. Figure 3 Taking partial refresh as an example, the display performs a partial refresh every 8.3ms. The EQ function is turned off each time a partial refresh is performed. Therefore, the EQ function is also turned off continuously when the display is continuously performing partial refresh, which increases the power consumption of the device, especially the power consumption of the display driver.

[0041] To address this issue, embodiments of this application provide a display driver chip that can control the activation and deactivation of the EQ function based on the refresh position of each frame, thereby allowing for EQ function activation time during frame refresh. Figure 2 For example, the Figure 2 The frame shown has a refreshable position of 6 rows of pixels occupied by the heart shape, with other positions being content-maintaining positions. The display driver chip provided in this embodiment can disable the EQ function when refreshing the heart shape and enable the EQ function when maintaining the content outside the heart shape, thus controlling the EQ function even while refreshing the heart shape. Therefore, compared to enabling and disabling the EQ function on a frame-by-frame basis, this reduces device power consumption, especially the display drive power consumption, thereby maximizing the benefits of power reduction through EQ function optimization. Furthermore, when refreshing a frame, the display driver chip disables the EQ function at the refreshable position and enables the EQ function at the content-maintaining position. The pixels at the refreshable position are those that have changed in the image, such as pixels whose pixel values ​​have changed. Figure 2For example, Figure 2 The six rows of pixels occupied by the heart shape represent the pixels that changed in the image.

[0042] One structure of the display driver chip is as follows: Figure 4 As shown, the display driver chip may include: an RX command processor, a core controller, a video timing controller, a logic combination processor, a level shifter, a switch circuit, and a GOA controller. The display driver chip may also include: a memory controller and a frame buffer.

[0043] The RX command processor interacts with the electronic device's processor (such as the application processor, AP). Specifically, the RX command processor receives data sent by the processor, including control data and image data. Image data is used for display on the screen, while control data is used to control the display. Image data is stored in the frame buffer via the memory controller, and is read from the frame buffer by the memory controller when the screen refreshes.

[0044] Control data includes information such as the position to be refreshed and the refresh rate. The position to be refreshed is used to indicate the pixels that the display screen should refresh. For example, the position to be refreshed is sent via CMD_2Ah and CMD_2Bh. One of CMD_2Ah and CMD_2Bh represents the row coordinate (x-direction coordinate) and the other represents the column coordinate (y-direction coordinate). The refresh rate is used to determine the frame rate of the display screen.

[0045] The RX command processor sends control data to the core controller. The core controller generates an EQ control signal based on the refresh position information. This EQ control signal is used to disable the EQ function at the refresh position indicated by the refresh position information. In other words, the core controller can determine the areas where the EQ function is enabled and disabled in the EQ control signal based on the refresh position information. The refresh position information points to the refresh position within a frame. That is, when the display shows a frame, the core controller determines the areas where the EQ function is enabled and disabled in the EQ control signal based on the refresh position information of that frame.

[0046] The core controller can also send refresh rates to the video timing controller. These refresh rates include a global refresh rate and a partial refresh rate. The global refresh rate instructs the display to perform a global refresh, while the partial refresh rate instructs the display to perform a partial refresh. Based on the global and partial refresh rates, the video timing controller generates a partial refresh reset reference signal. This signal includes a first control signal and a second control signal. The first control signal controls the display to perform a global refresh, and the second control signal controls the display to perform a partial refresh. The proportions of the first and second control signals in the partial refresh reset reference signal are generated based on the local and global refresh rates, and the period of the partial refresh reset reference signal is generated based on the global refresh rate. For example, if the global refresh rate is 30Hz and the local refresh rate is 120Hz, the display can perform a global refresh every 33.3ms and a local refresh every 8.3ms. Therefore, the period of the local refresh reset reference signal is 33.3ms. The duty cycle of the first control signal and the second control signal is 1:3. Correspondingly, this local refresh reset reference signal can include one first control signal and multiple second control signals. Under the action of one local refresh reset reference signal, the display can perform one global refresh and multiple local refreshes. After multiple local refreshes, a global refresh is performed to uniformly refresh all pixels on the display, thereby reducing or eliminating errors in the displayed content caused by device characteristic drift. The positions of the first and second control signals in the local refresh reset reference signal are not limited.

[0047] The core controller sends the EQ control signal to the logic combination, and the video timing controller sends the partial refresh reset reference signal to the logic combination. The logic combination performs logical combination processing on the EQ control signal and the partial refresh reset reference signal to generate the EQ switch signal. Because all positions in a frame are to be refreshed during a global refresh, the EQ switch signal disables the EQ function during a global refresh; during a partial refresh, the EQ switch signal can disable the EQ function at the to-be-refreshed position in the frame and enable the EQ function at the content-maintained position in the frame. This enables control of the EQ function during both global and partial refreshes, and allows for EQ function activation during partial refreshes. This further reduces device power consumption while minimizing or eliminating errors in the displayed content caused by device characteristic drift.

[0048] The logic combination sends the EQ switch signal to the level shifter. The level shifter also receives the raw clock signal from the GOA controller. The raw clock signal consists of two signals with opposite phases, denoted as GCK' and GCB'. GCK' and GCB' are generated by the GOA controller receiving a signal generation instruction from the video timing controller. This signal generation instruction specifies the signal shape of GCK' and GCB'. The GOA controller generates GCK' and GCB' with this signal shape. GCK' and GCB' are used to control the display refresh, but they do not indicate when the EQ function is turned on or off.

[0049] The Level Shifter generates an intermediate clock signal based on the EG switch signal and the original clock signal. This intermediate clock signal also includes two signals with opposite phases. Relative to the two signals in the original clock signal, the two signals of the intermediate clock signal instruct the display to perform a global refresh under the first control signal of the local refresh reset reference signal; and instruct the display to perform a local refresh under the second control signal of the local refresh reset reference signal, and also indicate when the EQ function is enabled and disabled. The original clock signal is a digital signal, which can consist of 1s and 0s. The intermediate clock signal can be further converted from digital to analog by the Level Shifter; for example, a low voltage (VGL) in the intermediate clock signal corresponds to the digital number 0, and a high voltage (VGH) in the intermediate clock signal corresponds to the digital number 1.

[0050] However, the Level Shifter lacks the function of assigning intermediate voltages. The intermediate clock signal can be processed by the Switch circuit, which assigns an intermediate voltage value to the intermediate clock signal to generate clock signals (GCK and GCB) that can act on the GOA circuit at the display screen. Under the action of this clock signal, the display screen is refreshed, and during partial refresh, the EQ function can be controlled to be turned on and off. This allows the EQ function to be turned on or off in sections, line by line, within the same frame. The intermediate voltage can be selected from AVDD, GND, and AVEE. In addition, the Switch circuit can further select the highest and lowest voltages, such as replacing VGL with VGLO and VGH with VGHO. If VGL = VGLO and VGH = VGHO, no replacement is required.

[0051] Combination Figure 5 The diagram shown illustrates the waveforms generated by a portion of the circuitry in the display driver chip. Figure 4 In this code, Partial_GOA_EQ_ON is the EQ control signal, Partial_rst is the partial refresh reset reference signal, Partial_GOA_EQ_ON_OUT is the EQ switch signal, and GCK and GCB are the clock signals sent to the GOA circuit on the display screen. Partial_act_Y is the partial refresh action signal, and Base_Vsync is the base frame rate synchronization signal. Each black pulse in Partial_act_Y represents a refresh of the Y-row pixels; that is, the position of the black pulse is the position to be refreshed, and the other positions are the content maintenance positions. With a Base_Vsync period of 8.3ms, the display screen can perform a partial refresh of the Y-row pixels every 8.3ms using Partial_act_Y.

[0052] At each black pulse position in Partial_act_Y, Partial_GOA_EQ_ON is high, indicating that the EQ function is off. At other positions, Partial_GOA_EQ_ON is low, indicating that the EQ function is on. This allows the EQ function of the display screen to be controlled during partial refresh via Partial_GOA_EQ_ON.

[0053] The partial refresh reset reference signal Partial_rst is in Figure 5 In Partial_rst, a pulse signal is used to represent the signal. A high level of this pulse signal serves as the first control signal, and a low level serves as the second control signal. That is, Partial_rst_H in Partial_rst is the first control signal, and Partial_rst_L is the second control signal. Figure 5In the Partial_rst shown, the duty cycle of Partial_rst_H and Partial_rst_L is 1:3, and the period of Partial_rst is 4 times the period of Base_Vsync (i.e., the period of Partial_rst is 33.3ms). Thus, the display can perform three partial refreshes after one global refresh. The combination of global refresh and partial refresh can reduce power consumption while improving the accuracy of the content displayed on the display.

[0054] When Partial_rst_H is active, Partial_act_Y is disabled, prohibiting partial refresh of the display. Correspondingly, Partial_GOA_EQ_ON is also disabled, meaning that the EQ function cannot be enabled when Partial_rst_H is active. Based on this, Partial_GOA_EQ_ON_OUT is low, indicating that the EQ function is disabled.

[0055] When Partial_rst_L, Partial_act_Y is valid, and correspondingly, Partial_GOA_EQ_ON is also valid, thus enabling the EQ function during Partial_rst_L. Partial_GOA_EQ_ON indicates whether the EQ function is enabled or disabled when Partial_act_Y is valid; therefore, Partial_GOA_EQ_ON_OUT can be set to high or low levels during Partial_rst_L by referring to Partial_GOA_EQ_ON. Figure 5 When Partial_GOA_EQ_ON is low (EQ function enabled), Partial_GOA_EQ_ON_OUT is high to enable the EQ function; when Partial_GOA_EQ_ON is high (EQ function disabled), Partial_GOA_EQ_ON_OUT is low to disable the EQ function. Figure 5 The EQ function is enabled when Partial_GOA_EQ_ON_OUT is high. In some examples, the EQ function is enabled when Partial_GOA_EQ_ON_OUT is low. In this embodiment, it is not limited to whether the high level or the low level is active. Here, "active" means that the EQ function is enabled.

[0056] The clock signal generated based on Partial_GOA_EQ_ON_OUT is as follows Figure 5As shown in GCK and GCB, global refresh is performed at Partial_rst_H, partial refresh at Partial_rst_L, and EQ function control is achieved through GCK and GCB. For example, a global refresh is performed at Frame N, and partial refreshes are performed at Frame N+1 and Frame N+2. The partial refresh refreshes the Y rows of pixels in Partial_act_Y. When these Y rows of pixels are refreshed, the EQ function is turned off, while the other rows of pixels remain unchanged and the EQ function is turned on. The duration of the clock signals GCK and GCB is the same as the period of the base frame rate synchronization signal. Figure 5 The duration of the clock signals GCK and GCB is 8.3ms. Figure 5 The diagram shows the waveforms of clock signals GCK and GCB in detail. The original clock signal has the same waveform shape as the clock signals GCK and GCB corresponding to Frame N. The difference between the two is that the original clock signal is a digital signal, while the original clock signal is an analog signal.

[0057] Because a global refresh occurs during Partial_rst_H and a partial refresh occurs during Partial_rst_L, and each partial refresh refresh updates the pixels in row Y, and the Y-row pixels are also refreshed during the global refresh, the high refresh area and low refresh area in the display's pixel array can be determined through Partial_rst. The high refresh area is the Y-row pixels corresponding to Partial_act_Y, and the low refresh area is the pixels excluding the high refresh area during the global refresh. An illustration of the high refresh area and low refresh area is shown below. Figure 5 As shown in Partial_update_L and Global_update_L, the dark gray area represents the high refresh rate area, and the light gray area represents the low refresh rate area.

[0058] Through the above Figure 4 and Figure 5 As shown, the display driver chip provided in this application embodiment disables the EQ function during global refresh; during partial refresh, it can disable the EQ function at the refresh position and enable the EQ function at the content maintenance position, thereby controlling the EQ function during global and partial refresh. Furthermore, there can be a time when the EQ function is enabled during partial refresh, so that there is a time when the EQ function is enabled within the time of one frame image refresh. This can further reduce the power consumption of the device while reducing or eliminating errors in the content displayed on the screen caused by the drift of device characteristics.

[0059] Figure 6This illustration shows another structure of a display driver chip provided in an embodiment of this application. The display driver chip may include: an RX command processor, a core controller, a video timing controller, a GOA controller, a level shifter, a switch circuit, a memory controller, and a frame buffer. (Similar to the above...) Figure 4 The difference shown is that the driver chip is different. Figure 6 The illustrated display driver chip describes the EQ function control during a partial refresh process. In this control process, the display does not perform a global refresh. The Video timing controller sends a signal generation instruction to the GOA controller, which indicates the signal shapes of GCK' and GCB'. The GOA controller generates a raw clock signal, which includes GCK' and GCB' with the specified signal shapes. GCK' and GCB' are used to control the display to perform a partial refresh. GCK' and GCB do not specify when the EQ function is turned on and off.

[0060] The core controller sends the EQ control signal to the level shifter. Based on the EQ control signal and the original clock signal, the level shifter generates an intermediate clock signal. This intermediate clock signal consists of two signals with opposite phases. Relative to the two signals in the original clock signal, the two signals in the intermediate clock signal instruct the display to perform partial refreshes and indicate when the EQ function is enabled or disabled. The original clock signal is a digital signal, which can consist of 1s and 0s. The intermediate clock signal undergoes a digital-to-analog conversion via the level shifter; for example, a low voltage (VGL) in the intermediate clock signal corresponds to the digital number 0, and a high voltage (VGH) corresponds to the digital number 1. The intermediate clock signal can be processed by a switch circuit, which assigns an intermediate voltage value to it to generate clock signals (GCK and GCB) that can act on the GOA circuitry at the display. Under the influence of these clock signals, the display is controlled to perform partial refreshes, and during these partial refreshes, the EQ function can be enabled or disabled in sections, line by line, within the same frame.

[0061] Figure 6 The waveform generated by the display driver chip is shown below. Figure 7As shown, at each black pulse position in Partial_act_Y (the black pulse position is the position to be refreshed), Partial_GOA_EQ_ON is high, indicating that the EQ function is off. At other positions (other positions are content maintenance positions), Partial_GOA_EQ_ON is low, indicating that the EQ function is on. This allows Partial_GOA_EQ_ON to control the EQ function of the display during partial refresh. Then, Partial_GOA_EQ_ON is used to generate GCK and GCB in the GOA circuit at the display end, so that the EQ function is controlled during partial refresh. For example, when performing partial refresh in Frame N, Frame N+1, and Frame N+2, the pixels in the Y row of Partial_act_Y are refreshed and the EQ function is off, while the pixels in other rows remain unchanged and the EQ function is on. Each partial refresh refreshes the pixels in the Y row, so the area where the pixels in the Y row are located on the display is the high refresh area. Figure 7 As shown in Partial_update_L. Through the above... Figure 6 and Figure 7 As shown, the display driver chip can disable the EQ function at the refresh position and enable the EQ function at the content maintenance position during partial refresh. This allows for a period of EQ function activation during partial refresh, ensuring that the EQ function is active within a single frame refresh time, further reducing device power consumption. Furthermore, the EQ function's activation and deactivation can dynamically change with the refresh position, ensuring that the EQ function control matches the refresh position and preventing erroneous EQ function control.

[0062] In some examples, the display driver chip provided in this application embodiment may include an RX commandProcessor, a Core controller, a GOA controller, a Level shifter, a Switch circuit, a Memory controller, and a Frame Buffer. (As described above...) Figure 6The difference in the display driver chip shown is that it eliminates the need for a video timing controller. Instead, the core controller sends signal generation instructions to the GOA Controller to generate the raw clock signals GCK' and GCB'. The core controller can also send EQ control signals to the level shifter. Based on the EQ control signals and the raw clock signals, the level shifter generates an intermediate clock signal. This intermediate clock signal is processed by the switch circuit to generate clock signals (GCK and GCB) that can act on the GOA circuit at the display screen. Under the action of these clock signals (GCK and GCB), the display screen is controlled to perform partial refreshes. During partial refreshes, the EQ function can be turned on and off, thus enabling the EQ function to be turned on or off in sections, line by line, within the same frame.

[0063] The display driver chip in the above embodiments can enable or disable the EQ function on a row-by-row basis during the time it takes to refresh one frame of image. That is, the EQ function is disabled when the display shows at least one row of pixels that has changed in a frame of image, and enabled when it shows at least one row of pixels that has not changed in the same frame of image. In some examples, the display driver chip can enable or disable the EQ function on a column-by-column basis during the time it takes to display one frame of image; the principle is the same as described above. Figures 4 to 7 The explanation is as follows. Regardless of whether the EQ function is based on rows or columns of an image frame, the display driver chip can control the EQ function to be turned on and off on a pixel-by-pixel basis within an image frame. This allows the EQ function to be enabled while the display is refreshing an image frame, thereby reducing device power consumption.

[0064] In this embodiment, the aforementioned display driver chip can be applied to an electronic device to control the activation and deactivation of the EQ function during partial refresh of the electronic device's display screen. In some embodiments, the electronic device may be a mobile phone, tablet computer, desktop computer, laptop computer, notebook computer, ultra-mobile personal computer (UMPC), handheld computer, netbook, personal digital assistant (PDA), wearable electronic device, smartwatch, etc. This embodiment does not impose any special limitations on the specific form of the electronic device.

[0065] like Figure 8As shown, the electronic device may include: a processor, an external memory interface, internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, antenna 1, antenna 2, a mobile communication module, a wireless communication module, a sensor module, buttons, a motor, an indicator, a camera, a display screen, and a subscriber identification module (SIM) card interface, etc. The audio module may include a speaker, a receiver, a microphone, a headphone jack, etc., and the sensor module may include a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a proximity sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0066] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0067] A processor may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units can be independent devices or integrated into one or more processors. The processor is the nerve center and command center of an electronic device. The controller generates operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0068] An external memory interface can be used to connect external memory cards, such as Micro SD cards, to expand the storage capacity of electronic devices. The external memory card communicates with the processor through the external memory interface to perform data storage. Internal memory can be used to store executable program code, which includes instructions. The processor executes the instructions stored in the internal memory to perform various functions of the electronic device and data processing.

[0069] The display screen is used to display images, videos, and a series of graphical user interfaces (GUIs). In some embodiments, the display screen may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a minimized display, a microLED, a micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device may include one or more display screens.

[0070] In some examples, the display is connected to the processor via a DDIC. For example... Figure 9 As shown, the AP in the processor is connected to the display screen via DDIC. The AP can send control data and image data to DDIC. DDIC uses the control data to generate clock signals (GCK and GCB). Under the action of the clock signals, the display screen can read image data from the DDIC's Frame Buffer to control the display screen refresh. During the partial refresh of a frame on the display screen, the clock signals can also control the EQ function to be turned on and off, thus enabling the EQ function to be turned on or off in sections, line by line, within the same frame.

[0071] Corresponding to the aforementioned display driver chip, this application embodiment also provides a display control method, the flowchart of which is shown below. Figure 10 As shown, the following steps may be included:

[0072] S101. Determine the pixels in the image that have changed. Here, the coordinates of the pixels to be refreshed are carried in the control command sent by the application processor in the electronic device; the pixels to be refreshed are the pixels in the image that have changed.

[0073] S102. Based on the pixels that have changed in the image, a clock signal is generated. The clock signal is used to turn off the EQ function when the screen displays pixels that have changed in the image, and to turn on the EQ function when the screen displays pixels that have not changed in the image.

[0074] In one possible implementation, the clock signal is generated by determining the activation timing of the EQ function based on the pixels that have changed in the image, and then generating the clock signal based on the activation timing of the EQ function. Specifically, the time period in the clock signal corresponding to the changed pixels in the image is the deactivation timing of the EQ function, and the time period corresponding to the changed pixels in the image is the activation timing of the EQ function. In this embodiment, the first time period in the clock signal corresponding to the changed pixels in the image is the time period during which the clock signal controls the display screen to show the changed pixels in the image, and the second time period in the clock signal corresponding to the changed pixels in the image is the time period during which the clock signal controls the display screen to show the unchanged pixels in the image. Therefore, the control signal can accurately control the activation and deactivation of the EQ function when the display screen is showing pixels, so that the clock signal can deactivate the EQ function when the display screen shows changed pixels in the image, and activate the EQ function when the display screen shows unchanged pixels in the image.

[0075] Therefore, when there are changing pixels in a frame of an image displayed on the screen, the display includes periods for the EQ function to be on and off during the display of that frame. This allows for pixel-by-pixel control of the EQ function, optimizing the EQ function compared to frame-by-frame control, thus reducing device power consumption. Furthermore, the EQ function's on / off state can dynamically change according to the changes in the pixels within the image, ensuring that the EQ function control matches the changing pixels and preventing erroneous EQ control.

[0076] Figure 11 This application illustrates another flow of the display control method provided in an embodiment, which may include the following steps:

[0077] S201. Determine the pixels in the image that have changed. Step S201 is the same as step S101, and will not be described again here.

[0078] S202. Determine the refresh mode of the display screen when displaying an image. The refresh mode can be either a global refresh mode or a local refresh mode.

[0079] S203. When the refresh mode is global refresh, a clock signal is generated based on the full-screen refresh mode. When the refresh mode is global refresh, the clock signal is used to control the display screen to perform a global refresh and disable the EQ function.

[0080] S204. When the refresh mode is partial refresh, a clock signal is generated based on the partial refresh mode and the pixels that have changed in the image. When the refresh mode is partial refresh, the clock signal is used to turn off the EQ function when the screen displays pixels that have changed in the image, and to turn on the EQ function when the screen displays pixels that have not changed in the image.

[0081] In this embodiment, steps S203 and S204 introduce a refresh method into the clock signal generation process, which is a feasible way to generate the clock signal in step S102 above. Figure 11 The display control method shown implements an EQ (Emergency Response) function control mode that matches the refresh method during global and partial refresh processes. Furthermore, the EQ function can be activated for a period during partial refresh, ensuring that there is an EQ function active within the refresh time of one frame, thereby reducing device power consumption through EQ optimization. After at least one partial refresh, the display can perform a global refresh, which refreshes all pixels in the image displayed on the screen, thus reducing or eliminating errors in the displayed content caused by device characteristic drift.

[0082] Furthermore, in one possible implementation, generating a clock signal based on the changed pixels in the image includes: generating an EQ control signal based on the changed pixels in the image, wherein the EQ control signal is used to disable the EQ function when the changed pixels in the image are displayed on the screen, and to enable the EQ function when the changed pixels in the image are displayed on the screen; generating an original clock signal, wherein the original clock signal does not have EQ control function; generating an intermediate clock signal based on the original clock signal and the EQ control signal, and converting the intermediate clock signal from a digital signal to an analog signal to obtain the clock signal.

[0083] In one possible implementation, generating the clock signal based on the changed pixels in the image further includes: generating a local refresh reset reference signal according to the global refresh rate and local refresh rate of the display screen, the local refresh reset reference signal including a first control signal and a second control signal, the first control signal being used to control the display screen to perform a global refresh, and the second control signal being used to control the display screen to perform a local refresh, wherein the proportion of the first control signal and the second control signal in the local refresh reset reference signal is generated based on the local refresh rate and the global refresh rate, and the period of the local refresh reset reference signal is generated based on the global refresh rate; logically combining the local refresh reset reference signal and the EQ control signal to generate an EQ switch signal, the EQ switch signal being used to disable the EQ function during a global refresh, and to control the EQ function to be turned on and off according to the changed pixels in the image during a local refresh; generating an intermediate clock signal according to the original clock signal and the EQ control signal includes: generating an intermediate clock signal according to the original clock signal and the EQ switch signal. Therefore, under the action of a partial refresh reset reference signal, the display screen can perform one global refresh and multiple partial refreshes. After multiple partial refreshes, a global refresh is performed to uniformly refresh all pixels on the display screen, thereby reducing or eliminating errors in the displayed content caused by device characteristic drift. Furthermore, the EQ function can be optimized during the partial refresh process, reducing device power consumption.

[0084] The aforementioned clock signals, EQ control signals, EQ switch signals, and partial refresh reset reference signals can be found in [reference needed]. Figures 4 to 7 The relevant explanations in the document will not be repeated here.

[0085] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display driver chip, characterized in that, The display driver chip includes: a refresh content determination circuit and a control signal generation circuit; The refresh content determination circuit is used to determine the pixels in the image that have changed; The control signal generation circuit is used to generate a clock signal based on the pixels that have changed in the image. The clock signal is used to turn off the power balancing function when the display screen shows a row or column of pixels that have changed in the image, and to turn on the power balancing function when the display screen shows a row or column of pixels that have not changed in the image.

2. The display driver chip according to claim 1, characterized in that, The display driver chip further includes: a refresh mode determination circuit, which is used to determine the refresh mode of the display screen when the display screen displays the image; The control signal generation circuit is used to generate the clock signal based on the global refresh mode when the refresh mode is global refresh mode. When the refresh mode is global refresh mode, the clock signal is used to control the display screen to perform a global refresh and turn off the power balancing function. The control signal generation circuit is used to generate the clock signal based on the local refresh mode and the changed pixels in the image when the refresh mode is a local refresh mode. When the refresh mode is a local refresh mode, the clock signal is used to turn off the power balancing function when the display screen shows a row or column of changed pixels in the image, and to turn on the power balancing function when the display screen shows a row or column of unchanged pixels in the image.

3. The display driver chip according to claim 1, characterized in that, The control signal generation circuit is used to determine the activation timing of the power balancing function based on the pixels that have changed in the image, and to generate the clock signal based on the activation timing of the power balancing function.

4. The display driver chip according to claim 3, characterized in that, The control signal generation circuit is used to determine a first time period in the clock signal corresponding to the row or column of pixels in the image that have changed, the first time period being the time when the power balancing function is turned off, and to determine a second time period in the clock signal corresponding to the row or column of pixels in the image that have not changed, the second time period being the time when the power balancing function is turned on.

5. The display driver chip according to claim 1 or 3, characterized in that, The control signal generation circuit includes: a core controller, a level converter, a switching circuit, and an array substrate row drive controller; The core controller is used to generate an electrical balance control signal based on the pixels that have changed in the image. The electrical balance control signal is used to turn off the electrical balance function when the display screen shows a row or column of pixels that have changed in the image, and to turn on the electrical balance function when the display screen shows a row or column of pixels that have not changed in the image. The array substrate row drive controller is used to generate a raw clock signal, which does not have an electrical balance control function. The level converter is used to generate an intermediate clock signal based on the original clock signal and the electrical balance control signal, and to convert the intermediate clock signal from a digital signal to an analog signal through the level converter and the switching circuit to obtain the clock signal.

6. The display driver chip according to claim 5, characterized in that, The control signal generation circuit further includes: a video timing controller and a logic combination processor; The video timing controller is used to generate a partial refresh reset reference signal based on the global refresh rate and partial refresh rate sent by the core controller. The partial refresh reset reference signal includes a first control signal and a second control signal. The first control signal is used to control the display screen to perform a global refresh, and the second control signal is used to control the display screen to perform a partial refresh. The proportion of the first control signal and the second control signal in the partial refresh reset reference signal is generated based on the partial refresh rate and the global refresh rate, and the period of the partial refresh reset reference signal is generated based on the global refresh rate. The logic combination processor is used to logically combine the local refresh reset reference signal and the power balance control signal to generate a power balance switch signal. The power balance switch signal is used to disable the power balance function during global refresh and to control the power balance function to be turned on and off according to the pixels that change in the image during local refresh. The level converter is used to generate the intermediate clock signal based on the original clock signal and the electrical balance switch signal.

7. The display driver chip according to any one of claims 1 to 4, characterized in that, The refresh content determination circuit is a command receiving processor. The command receiving processor receives control commands sent by the application processor in the electronic device, and determines the pixels in the image that have changed based on the coordinates of the pixels to be refreshed carried in the control commands.

8. An electronic device, characterized in that, The electronic device includes: One or more processors and a display screen; The display driver chip as described in any one of claims 1 to 7, wherein the processor controls the display screen through the display driver chip.

9. A display control method, characterized in that, The method includes: Identify pixels in the image that have changed; A clock signal is generated based on the pixels that have changed in the image. The clock signal is used to disable the power balancing function when the display shows a row or column of pixels that have changed in the image, and to enable the power balancing function when the display shows a row or column of pixels that have not changed in the image.

10. The method according to claim 9, characterized in that, The method further includes: determining the refresh mode of the display screen when displaying the image; The step of generating a clock signal based on the changed pixels in the image includes: generating the clock signal based on the global refresh mode when the refresh mode is global refresh mode; when the refresh mode is global refresh mode, the clock signal is used to control the display screen to perform a global refresh and turn off the power balancing function. When the refresh mode is a partial refresh mode, the clock signal is generated based on the partial refresh mode and the pixels that have changed in the image. When the refresh mode is a partial refresh mode, the clock signal is used to turn off the power balancing function when the display screen shows rows or columns of pixels that have changed in the image, and to turn on the power balancing function when the display screen shows rows or columns of pixels that have not changed in the image.

11. The method according to claim 9, characterized in that, The step of generating a clock signal based on the changed pixels in the image includes: determining the activation timing of the power balancing function based on the changed pixels in the image, and generating the clock signal based on the activation timing of the power balancing function.

12. The method according to claim 11, characterized in that, The time period in the clock signal corresponding to the row or column of pixels in the image that have changed is the time when the power balancing function is turned off, and the time period in the clock signal corresponding to the row or column of pixels in the image that have not changed is the time when the power balancing function is turned on.

13. The method according to claim 9 or 11, characterized in that, The step of generating a clock signal based on the changed pixels in the image includes: Based on the pixels that have changed in the image, an electrical balance control signal is generated. The electrical balance control signal is used to turn off the electrical balance function when the display screen shows a row or column of pixels that have changed in the image, and to turn on the electrical balance function when the display screen shows a row or column of pixels that have not changed in the image. Generate an original clock signal, which does not have an electrical balance control function; An intermediate clock signal is generated based on the original clock signal and the electrical balance control signal, and the intermediate clock signal is converted from a digital signal to an analog signal to obtain the clock signal.

14. The method according to claim 13, characterized in that, The step of generating a clock signal based on the changed pixels in the image further includes: generating a local refresh reset reference signal according to the global refresh rate and local refresh rate of the display screen. The local refresh reset reference signal includes a first control signal and a second control signal. The first control signal is used to control the display screen to perform a global refresh, and the second control signal is used to control the display screen to perform a local refresh. The proportion of the first control signal and the second control signal in the local refresh reset reference signal is generated based on the local refresh rate and the global refresh rate, and the period of the local refresh reset reference signal is generated based on the global refresh rate. The local refresh reset reference signal and the power balance control signal are logically combined to generate a power balance switch signal. The power balance switch signal is used to turn off the power balance function during global refresh and to control the power balance function to be turned on and off according to the pixels that change in the image during local refresh. The step of generating an intermediate clock signal based on the original clock signal and the electrical balance control signal includes: generating the intermediate clock signal based on the original clock signal and the electrical balance switch signal.

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