A trench type power device and a method for manufacturing the same

Abstract

The present invention provides a trench power device and a preparation method thereof. By setting a conversion structure, the conversion of the function of the trench power device can be achieved only by applying voltages of different magnitudes on a gate. Specifically, the conversion structure consists of an N-type doped first polysilicon and a second polysilicon arranged on both sides of the first polysilicon. The conversion structure is spaced apart from an epitaxial layer by a first oxide layer. The first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from a substrate. The second polysilicon is symmetrical about the second N-type portion. The second polysilicon is spaced apart from the second N-type portion by a second oxide layer, and the thickness of the second oxide layer is greater than that of the first oxide layer. The first polysilicon is connected to a gate. When a low turn-on voltage is applied to the gate, the trench power device can be used conventionally. When a large turn-on voltage is applied to the gate, channels next to the first oxide layer and the second oxide layer are turned on at the same time, and the gate is connected to a drain.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench type power device and a preparation method thereof. Background Art

[0002] In the field of power semiconductors, traditional planar power devices have been widely used for a long time. Planar power devices are mainly based on the manufacturing process of planar structures, and their current mainly flows in the horizontal direction. However, this structure gradually exposes some limitations in high-power and high-frequency application scenarios. In order to overcome the above-mentioned shortcomings of planar power devices, trench power devices came into being. Trench power devices achieve the transformation of current from lateral to longitudinal by etching vertical grooves in semiconductor materials and constructing conductive channels in the grooves.

[0003] With the continuous improvement of manufacturing processes, trench power devices have made significant progress in on-resistance, power density, etc. At present, some advanced manufacturing processes can achieve high-precision trench etching, and effectively reduce on-resistance by optimizing trench structure and doping process.

[0004] With the market demand, the complexity of the system and the diversification of terminal products, traditional single power devices will also be upgraded to meet different needs.

[0005] The existing power MOS devices have a single function. In some specific applications, in addition to conventional use, the MOS tube needs to be connected to the drain and source to take advantage of its characteristics of working in the saturation region and equivalent impedance of 1 / gm (gm is transconductance). The existing technology requires additional circuits to achieve this, which greatly increases the complexity of the circuit and is not conducive to circuit integration. Additional components will also increase costs. Summary of the invention

[0006] Based on this, the object of the present invention is to provide a trench power device and a method for preparing the same, aiming to solve the above-mentioned problems.

[0007] According to a trench power device in an embodiment of the present invention, when the trench power device is an N-type trench power device, it includes a substrate, an epitaxial layer disposed on the substrate, and a conversion structure disposed in the epitaxial layer;

[0008] The epitaxial layer includes a first N-type layer, a P-type layer and a second N-type layer arranged in sequence in a direction away from the substrate, the conversion structure is embedded in the epitaxial layer, the conversion structure is composed of N-type doped first polysilicon and second polysilicon arranged on both sides of the first polysilicon, the conversion structure is spaced from the epitaxial layer by a first oxide layer, the first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from the substrate, and the second polysilicon is symmetrical about the second N-type portion;

[0009] The second polysilicon is spaced from the second N-type portion by a second oxide layer, the second polysilicon includes a P-type portion connected to the first N-type portion, and a third N-type portion connected to the P-type portion, the third N-type portion is used to be electrically connected to a drain, the first N-type portion, the P-type portion and the third N-type portion form an NPN structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer;

[0010] When the trench power device is a P-type trench power device, all doping is inverted.

[0011] Furthermore, the conversion structure is embedded in the epitaxial layer to a depth of 1.5 μm to 2 μm.

[0012] Furthermore, the thickness of the first oxide layer is 200Å~500Å.

[0013] Furthermore, the thickness of the second oxide layer is 800Å~1200Å.

[0014] Furthermore, the height of the second N-type portion is 1 μm to 4 μm.

[0015] Furthermore, the doping impurity in the third N-type portion is As element, the energy is 10Kev~30Kev, and the doping concentration is 1E10cm -3 ~1E15cm -3 .

[0016] Furthermore, the doping concentration of the first N-type layer is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer is 1E13cm -3 ~1E17cm -3 .

[0017] Furthermore, the impurity of the P-type layer is B element, and the doping concentration is 1E10cm -3 ~1E14cm -3 .

[0018] A method for preparing a trench power device according to an embodiment of the present invention is used to prepare the above trench power device, and the method comprises:

[0019] When the trench-type power device is an N-type trench-type power device, an N-type substrate is provided, and a trench is etched on the N-type substrate;

[0020] The substrate with the groove is subjected to thermal oxidation treatment to grow a first oxide layer on the surface of the groove as a dielectric layer of the gate polysilicon sidewall;

[0021] Growing N-type doped first polysilicon on the first oxide layer, grinding and etching back, and then etching both sides of the first polysilicon;

[0022] Performing thermal oxidation treatment in the grooves etched on both sides of the first polysilicon to form an oxide layer, and removing the oxide layer at the bottom of the groove to obtain a second oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer;

[0023] Depositing P-type doped second polysilicon in a groove formed by the first oxide layer, the second oxide layer and the first N-type portion of the first polysilicon, and then performing N-type doping in a predetermined area of ​​the second polysilicon to obtain a third N-type portion, wherein the third N-type portion is used to be electrically connected to the drain;

[0024] Doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer;

[0025] When the trench power device is a P-type trench power device, all doping is inverted.

[0026] The beneficial effects of the present invention are:

[0027] By setting a conversion structure, the function conversion of the trench power device can be achieved by only applying voltages of different magnitudes on the gate. Specifically, the conversion structure is composed of an N-type doped first polysilicon and a second polysilicon arranged on both sides of the first polysilicon. The conversion structure is spaced from the epitaxial layer by a first oxide layer. The first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from the substrate. The second polysilicon is symmetrical about the second N-type portion. The second polysilicon and the second N-type portion are spaced by a second oxide layer, and the thickness of the second oxide layer is greater than that of the first oxide layer. The first polysilicon and the gate The gate is connected. When a low turn-on voltage is applied to the gate, since the second oxide layer is thicker and the turn-on voltage is larger, the channel next to it is not enough to turn on. In addition, an NPN structure is formed in the conversion structure. Since it is an N-type trench power device, the gate voltage is positive. At this time, the NP junction is reverse biased and will not conduct. The drain is also positive voltage, and the NP junction between the drain and the gate is also reverse biased and will not conduct. Therefore, there is no conduction between the gate and the drain, and the trench power device can be used normally; when a large turn-on voltage is applied to the gate, the channels next to the first oxide layer and the second oxide layer are turned on at the same time, and the gate and the drain are connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a trench power device provided by an embodiment of the present invention;

[0029] Figure 2 A flowchart of a method for manufacturing a trench power device provided by an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a process flow for preparing a trench power device provided in an embodiment of the present invention.

[0031] Description of main component symbols:

[0032]

[0033] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0035] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] The embodiment of the present invention provides a trench power device, see Figure 1 , is a schematic diagram of the structure of a trench power device provided by an embodiment of the present invention. It should be noted that the trench power device includes devices such as trench MOS, SGT, SJ, and IBGT. When the trench power device is an N-type trench power device, taking an N-type trench MOS device as an example, the N-type trench MOS device includes a substrate 1, an epitaxial layer disposed on the substrate 1, and a conversion structure disposed in the epitaxial layer;

[0038] The epitaxial layer includes a first N-type layer 2, a P-type layer 3 and a second N-type layer 4 which are sequentially arranged in a direction away from the substrate. The conversion structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4. The impurities of the first N-type layer 2 and the second N-type layer 4 are P (phosphorus) elements, and the doping concentration of the second N-type layer 4 is less than the doping concentration of the first N-type layer 2. The doping concentration of the first N-type layer 2 is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer 4 is 1E13cm -3 ~1E17cm -3 The impurity of P-type layer 3 is B (boron) element, and the doping concentration is 1E10cm -3 ~1E14cm -3 .

[0039] It should be noted that the conversion structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4 to a depth of 1.5μm~2μm. Exemplarily, the conversion structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4 to a depth of 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm or 2μm, but not limited to this. It can be understood that the conversion structure is actually prepared in a groove with a depth of 1.5μm~2μm.

[0040] The conversion structure is composed of an N-type doped first polysilicon 6 and a second polysilicon 7 disposed on both sides of the first polysilicon 6. The conversion structure is spaced from the epitaxial layer by a first oxide layer 51. More specifically, the first polysilicon 6 includes a first N-type portion 61 and a second N-type portion 62 extending from the first N-type portion 61 in a direction away from the substrate. The second polysilicon 7 is symmetrical about the second N-type portion 62. The height of the second N-type portion 62 is 1 μm to 4 μm. Exemplarily, the height of the second N-type portion 62 is 1 μm, 2 μm, 3 μm or 4 μm, but not limited thereto. It can be understood that the N-type doped first polysilicon 6 is a gate, which is in a "convex" shape.

[0041] The second polysilicon 7 and the second N-type portion 62 are separated by a second oxide layer 52. The second polysilicon 7 includes a P-type portion 71 connected to the first N-type portion 61, and a third N-type portion 72 connected to the P-type portion 71. The third N-type portion 72 is used to be electrically connected to the drain. The first N-type portion 61, the P-type portion 71 and the third N-type portion 72 form an NPN structure, wherein the thickness of the second oxide layer 52 is greater than the thickness of the first oxide layer 51. Specifically, the thickness of the first oxide layer 51 is 200Å~500Å. Exemplarily, the thickness of the first oxide layer 51 is 200Å, 300Å, 400Å or 500Å, but not limited thereto. The thickness of the second oxide layer 52 is 800Å~1200Å. Exemplarily, the thickness of the second oxide layer 52 is 800Å, 900Å, 1000Å, 1100Å or 1200Å, but not limited thereto. In addition, the doping impurity in the third N-type portion 72 is As (arsenic) element, the energy is 10 KeV~30 KeV, and the doping concentration is 1E10 cm -3 ~1E15cm -3 .

[0042] In order to make the conversion of device function smoother, that is, it is not easy to be turned on by mistake, the thickness of the first oxide layer 51 and the thickness of the second oxide layer 52 differ by at least 600Å. It can be understood that when the thickness of the first oxide layer 51 is 200Å, the thickness of the first oxide layer 51 is at least 800Å. In this way, the difference between the first turn-on voltage and the second turn-on voltage is better, the window of the gate voltage is also larger, and it is easier to distinguish, so it is not easy to be turned on by mistake.

[0043] It can be understood that G represents the gate, S represents the source, and D represents the drain, wherein the second N-type layer 4 is electrically connected to the source, the first polysilicon 6 is electrically connected to the gate, and the substrate 1 and the third N-type portion 72 are electrically connected to the drain respectively.

[0044] When the trench power device is a P-type trench MOS device, all doping is inverted. Specifically, the epitaxial layer includes a first P-type layer, an N-type layer and a second P-type layer arranged in sequence away from the substrate. The conversion structure is embedded in the first P-type layer, the N-type layer and the second P-type layer, and the doping concentration of the second P-type layer is higher than the doping concentration of the first P-type layer.

[0045] The conversion structure is composed of a third polysilicon doped with a P type and a fourth polysilicon arranged on both sides of the third polysilicon, the conversion structure is separated from the epitaxial layer by a first oxide layer, the third polysilicon includes a first P type portion and a second P type portion extending from the first P type portion in a direction away from the substrate, and the fourth polysilicon is symmetrical about the second P type portion;

[0046] The fourth polysilicon is separated from the second P-type portion by a second oxide layer. The fourth polysilicon includes an N-type portion connected to the first P-type portion, and a third P-type portion connected to the N-type portion. The third P-type portion is used to be electrically connected to the drain. The first P-type portion, the N-type portion and the third P-type portion form a PNP structure.

[0047] In order to prepare the above-mentioned trench power device, the embodiment of the present invention provides a method for preparing a trench power device, please refer to Figure 2 and Figure 3 , Figure 2 A flowchart of a method for manufacturing a trench power device provided by an embodiment of the present invention is provided. Figure 3 A schematic diagram of a manufacturing process flow of a trench power device provided in an embodiment of the present invention. When the trench power device is an N-type trench power device, specifically taking an N-type trench MOS device as an example, the method specifically includes the following steps:

[0048] S100: providing an N-type substrate, and etching a groove on the N-type substrate.

[0049] Specifically, a groove with a depth of 1.5 μm to 2 μm is etched on the N-type substrate 11 , and a conversion structure is subsequently formed in the groove.

[0050] S200: thermally oxidizing the substrate with the trenches to grow a first oxide layer on the surface of the trenches as a dielectric layer of the gate polysilicon sidewalls.

[0051] In this embodiment, a high-quality thin oxide layer is grown as a dielectric layer of the gate polysilicon sidewall by thermal oxidation treatment, that is, oxygen is introduced at a high temperature of 800°C to 1100°C, to obtain a first oxide layer 51 with a thickness of 200Å to 500Å. In addition, the first oxide layer 51 also serves to isolate the substrate.

[0052] S300: growing N-type doped first polysilicon on the first oxide layer, grinding and etching back, and then etching both sides of the first polysilicon.

[0053] Among them, N-type doped first polysilicon 6 is deposited on the first oxide layer 51 of the groove, and after being polished and etched back using the CMP process, small grooves are formed on the left and right sides with a depth of 1μm~1.4μm, that is, the height of the second N-type part 62 in the first polysilicon 6 is 1μm~1.4μm.

[0054] S400: performing thermal oxidation treatment in the grooves etched on both sides of the first polysilicon to form an oxide layer, and removing the oxide layer at the bottom of the groove to obtain a second oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.

[0055] Specifically, the thickness of the second oxide layer 52 is 800Å-1200Å, so as to separate the second polysilicon from the second N-type portion 62 .

[0056] S500: depositing P-type doped second polysilicon in a groove formed by the first oxide layer, the second oxide layer and the first N-type portion of the first polysilicon, and then performing N-type doping in a preset area of ​​the second polysilicon to obtain a third N-type portion, wherein the third N-type portion is used to be electrically connected to the drain.

[0057] It should be noted that P-type doped polysilicon is deposited in the groove formed by the first oxide layer 51, the second oxide layer 52 and the first N-type portion 61 of the first polysilicon, and after being polished and etched back by the CMP process, N-type doping is performed in a preset area of ​​the polysilicon to obtain a second polysilicon 7 consisting of a P-type portion 71 and a third N-type portion 72 connected to the P-type portion 71. Specifically, the doping impurity of the third N-type portion 72 is As (arsenic) element, the energy is 10Kev~30Kev, and the doping concentration is 1E10cm -3 ~1E15cm -3 In some other embodiments of the present invention, the plane of the second polysilicon is 0.1 μm to 0.2 μm lower than the plane of the first oxide layer, in order to ensure that there is no polysilicon residue to cause a short circuit.

[0058] S600: doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer.

[0059] It should be noted that the well region is doped with B (boron) element, the temperature is 700℃~1000℃, and the doping concentration is 1E10cm -3 ~1E14cm -3, and obtain the P-type layer 3; doping the source with P (phosphorus) as the impurity, the temperature is 800℃~1100℃, and the doping concentration is 1E13cm -3 ~1E17cm -3 , a second N-type layer 4 is obtained, and further, an oxide layer is deposited as a dielectric layer, and then through holes are etched, and metal aluminum is deposited to form MOS electrodes.

[0060] In some other embodiments of the present invention, when the trench power device is a P-type trench power device, all doping is inverted.

[0061] The present invention will be further described below with specific embodiments:

[0062] Example 1

[0063] Embodiment 1 of the present invention provides a trench power device, specifically taking an N-type trench MOS device as an example, the N-type trench MOS device includes a substrate, an epitaxial layer disposed on the substrate, and a conversion structure disposed in the epitaxial layer;

[0064] The epitaxial layer includes a first N-type layer, a P-type layer and a second N-type layer arranged in sequence away from the substrate, the conversion structure is embedded in the first N-type layer, the P-type layer and the second N-type layer, the impurities of the first N-type layer and the second N-type layer are P (phosphorus) elements, and the doping concentration of the second N-type layer is less than the doping concentration of the first N-type layer, and the doping concentration of the first N-type layer is 1E18cm -3 , the doping concentration of the second N-type layer is 1E17cm -3 The impurity of the P-type layer is B (boron) element, and the doping concentration is 1E12cm -3 .

[0065] It should be noted that the conversion structure is embedded in the first N-type layer, the P-type layer and the second N-type layer to a depth of 1.5 μm. It can be understood that the conversion structure is actually prepared in a trench with a depth of 1.5 μm.

[0066] The conversion structure is composed of an N-type doped first polysilicon and a second polysilicon disposed on both sides of the first polysilicon. The conversion structure is spaced from the epitaxial layer by a first oxide layer. More specifically, the first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from the substrate. The second polysilicon is symmetrical about the second N-type portion, and the height of the second N-type portion is 2 μm. It can be understood that the N-type doped first polysilicon is a gate and is in a "convex" shape.

[0067] The second polysilicon is separated from the second N-type portion by a second oxide layer. The second polysilicon includes a P-type portion connected to the first N-type portion and a third N-type portion connected to the P-type portion. The third N-type portion is used to electrically connect to the drain. The first N-type portion, the P-type portion and the third N-type portion form an NPN structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer. Specifically, the thickness of the first oxide layer is 200Å, and the thickness of the second oxide layer is 800Å. In addition, the doping impurity in the third N-type portion is As (arsenic) element, with an energy of 20Kev and a doping concentration of 1E12cm -3 .

[0068] It can be understood that G represents the gate, S represents the source, and D represents the drain, wherein the second N-type layer is electrically connected to the source, the first polysilicon is electrically connected to the gate, and the substrate and the third N-type portion are electrically connected to the drain respectively.

[0069] Example 2

[0070] Embodiment 2 of the present invention also provides a trench power device, which differs from Embodiment 1 in that the thickness of the second oxide layer is 1000Å.

[0071] Example 3

[0072] Embodiment 3 of the present invention also provides a trench power device, which differs from Embodiment 1 in that the thickness of the second oxide layer is 1200Å.

[0073] Comparative Example 1

[0074] Comparative Example 1 also provides a trench power device, which differs from Example 1 in that the thickness of the second oxide layer is 200Å.

[0075] Comparative Example 2

[0076] Comparative Example 2 also provides a trench power device, which differs from Example 1 of the present invention in that the thickness of the second oxide layer is 500Å.

[0077] The trench power devices in Examples 1 to 3 and Comparative Examples 1 to 2 were tested under the same conditions, and the specific results are as follows:

[0078]

[0079] It can be seen from the table that the trench power device in the embodiment of the present invention can convert the device function by changing the gate voltage. In addition, the greater the thickness difference between the first oxide layer and the second oxide layer, the greater the turn-on voltage difference, so that the gate voltage window is larger, easier to distinguish, and not easy to be turned on by mistake. In comparative example 1, there is no thickness difference between the first oxide layer and the second oxide layer, and the conversion of the device function cannot be achieved. In comparative example 2, although there is a thickness difference between the first oxide layer and the second oxide layer, the conversion of the device function can be achieved, but the turn-on voltage difference is small, which is easy to be turned on by mistake.

[0080] In summary, the trench power device and the preparation method thereof in the embodiments of the present invention can realize the conversion of the function of the trench power device by setting a conversion structure, only by applying voltages of different magnitudes on the gate. Specifically, the conversion structure is composed of an N-type doped first polysilicon and a second polysilicon arranged on both sides of the first polysilicon. The conversion structure is spaced from the epitaxial layer by a first oxide layer. The first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from the substrate. The second polysilicon is symmetrical about the second N-type portion. The second polysilicon and the second N-type portion are spaced by a second oxide layer, and the thickness of the second oxide layer is greater than that of the first oxide layer. The thickness of the oxide layer is determined by the thickness of the oxide layer. The first polysilicon is connected to the gate. When a low turn-on voltage is applied to the gate, since the second oxide layer is thicker and the turn-on voltage is larger, the channel next to it is not enough to turn on. In addition, an NPN structure is formed in the conversion structure. Since it is an N-type trench power device, the gate voltage is positive. At this time, the NP junction is reverse biased and will not conduct. The drain is also positive voltage. The NP junction between the drain and the gate is also reverse biased and will not conduct. Therefore, there is no conduction between the gate and the drain, and the trench power device can be used conventionally; when a large turn-on voltage is applied to the gate, the channels next to the first oxide layer and the second oxide layer are turned on at the same time, and the gate is connected to the drain.

[0081] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A trench power device, characterized in that: When the trench power device is an N-type trench power device, it includes a substrate, an epitaxial layer arranged on the substrate, and a conversion structure arranged in the epitaxial layer; The epitaxial layer includes a first N-type layer, a P-type layer and a second N-type layer arranged in sequence in a direction away from the substrate, the conversion structure is embedded in the epitaxial layer and extends to the first N-type layer, the conversion structure is composed of N-type doped first polysilicon and second polysilicon arranged on both sides of the first polysilicon, the conversion structure is spaced from the epitaxial layer by a first oxide layer, the first polysilicon includes a first N-type portion and a second N-type portion extending from the first N-type portion in a direction away from the substrate, the first N-type portion extends in a horizontal direction in contact with the first oxide layer, and the second polysilicon is symmetrical about the second N-type portion; The second polysilicon and the second N-type portion are separated by a second oxide layer, the second polysilicon includes a P-type portion connected to the first N-type portion, and a third N-type portion connected to the P-type portion, the second N-type layer is electrically connected to a source, the first polysilicon is electrically connected to a gate, the substrate and the third N-type portion are electrically connected to a drain, respectively, the first N-type portion, the P-type portion and the third N-type portion form an NPN structure, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer; When the trench power device is a P-type trench power device, the structure of the P-type trench power device is kept the same as that of the N-type trench power device, and all doping is inverted.

2. The trench power device according to claim 1, characterized in that: The conversion structure is embedded in the epitaxial layer at a depth of 1.5 μm to 2 μm.

3. The trench power device according to claim 1, characterized in that: The thickness of the first oxide layer is 200Å~500Å.

4. The trench power device according to claim 1, characterized in that: The thickness of the second oxide layer is 800Å~1200Å.

5. The trench power device according to claim 1, characterized in that: The second N-type portion has a height of 1 μm to 4 μm.

6. The trench power device according to claim 1, characterized in that: The doping impurity in the third N-type portion is As element, with an energy of 10Kev~30Kev and a doping concentration of 1E10cm -3 ~1E15cm -3 .

7. The trench power device according to claim 1, characterized in that: The doping concentration of the first N-type layer is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer is 1E13cm -3 ~1E17cm -3 .

8. The trench power device according to claim 1, characterized in that: The impurity of the P-type layer is B element, and the doping concentration is 1E10cm -3 ~1E14cm -3 .

9. A method for preparing a trench power device, characterized in that: For preparing the trench power device according to any one of claims 1 to 8, the method comprises: When the trench-type power device is an N-type trench-type power device, an N-type substrate is provided, and a trench is etched on the N-type substrate; The substrate with the groove is subjected to thermal oxidation treatment to grow a first oxide layer on the surface of the groove as a dielectric layer of the gate polysilicon sidewall; Growing N-type doped first polysilicon on the first oxide layer, grinding and etching back, and then etching both sides of the first polysilicon; Performing thermal oxidation treatment in the grooves etched on both sides of the first polysilicon to form an oxide layer, and removing the oxide layer at the bottom of the groove to obtain a second oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer; Depositing P-type doped second polysilicon in a groove formed by the first oxide layer, the second oxide layer and the first N-type portion of the first polysilicon, and then performing N-type doping in a predetermined area of ​​the second polysilicon to obtain a third N-type portion, wherein the third N-type portion is used to be electrically connected to the drain; Doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer; When the trench power device is a P-type trench power device, the structure of the P-type trench power device is kept the same as that of the N-type trench power device, and all doping is inverted.

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