Display substrate and its preparation method, display device

Abstract

A display substrate and its fabrication method, and a display device thereof. The display substrate includes multiple circuit units, each circuit unit including a pixel driving circuit, the pixel driving circuit including at least multiple transistors; on a plane perpendicular to the display substrate, each circuit unit includes a semiconductor layer disposed on the substrate, the semiconductor layer including at least a first active pattern (10) and a second active pattern (20), the first active pattern (10) including an active layer of at least one transistor, the second active pattern (20) including an active layer of at least one transistor; in at least one circuit unit, the first active pattern (10) and the second active pattern (20) are spaced apart, the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the row direction, and the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the column direction.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit, which includes at least a multiple transistor. On a plane perpendicular to the display substrate, at least one circuit unit includes a semiconductor layer disposed on a substrate and multiple conductive layers disposed on the side of the semiconductor layer away from the substrate. The semiconductor layer includes at least an active layer of multiple transistors. The semiconductor layer includes at least a first active pattern and a second active pattern. The first active pattern includes an active layer of at least one transistor, and the second active pattern includes an active layer of at least one transistor. In at least one circuit unit, the first active pattern and the second active pattern are spaced apart. The active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the cell row direction, and the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the cell column direction.

[0005] In an exemplary embodiment, the first active pattern includes an active layer of two transistors, the active layers of the two transistors being an integral structure interconnected; the second active pattern includes an active layer of seven transistors, the active layers of the seven transistors being an integral structure interconnected.

[0006] In an exemplary embodiment, the pixel driving circuit includes a first transistor and a seventh transistor as initialization transistors, a second transistor as compensation transistors, a third transistor as driving transistors, a fourth transistor as data writing transistors, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors. The first active pattern includes the active layer of the fourth transistor and the active layer of the ninth transistor, and the second active pattern includes the active layers of the first transistor to the third transistor and the active layers of the fifth transistor to the eighth transistor.

[0007] In an exemplary embodiment, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first electrode plate and a third electrode plate, wherein the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate at least partially overlap; the second storage capacitor includes at least a second electrode plate and a fourth electrode plate, wherein the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the fourth electrode plate on the substrate at least partially overlap; the first electrode plate serves as the gate electrode of the third transistor, the second electrode plate is connected to the third electrode plate, and the fourth electrode plate is connected to the first power line.

[0008] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the first electrode plate and the second electrode plate are disposed in the first conductive layer, the third electrode plate and the fourth electrode plate are disposed in the second conductive layer, the first power line is disposed in the fourth conductive layer, and the second electrode plate is connected to the third electrode plate through a connecting electrode disposed in the third conductive layer.

[0009] In an exemplary embodiment, a first electrode connecting line extending toward the fourth electrode is provided on the third electrode plate, and a first groove recessed toward the direction away from the third electrode plate is provided on the fourth electrode plate. The first electrode connecting line is disposed in the first groove, and the end of the first electrode connecting line away from the third electrode plate is connected to the connecting electrode through a through hole.

[0010] In an exemplary embodiment, the pixel driving circuit further includes an additional capacitor, the lower electrode of which is disposed in the semiconductor layer, and the upper electrode of which is disposed in the second conductive layer. The orthographic projection of the upper electrode on the substrate at least partially overlaps with the orthographic projection of the lower electrode on the substrate. The lower electrode is connected to the second electrode, and the upper electrode is connected to the fourth electrode.

[0011] In an exemplary embodiment, the lower electrode plate includes a second region of the active layer of the fourth transistor, and the second electrode plate is connected to the second region of the active layer of the fourth transistor through a connection electrode disposed in the third conductive layer. The upper electrode plate and the fourth electrode plate are an integral structure that is interconnected.

[0012] In an exemplary embodiment, the gate electrode of the first transistor is connected to the fourth scan signal line, the gate electrode of the second transistor is connected to the fifth scan signal line, the gate electrode of the fourth transistor is connected to the third scan signal line, the gate electrodes of the fifth transistor and the sixth transistor are connected to the light emission signal line, the gate electrodes of the seventh transistor and the eighth transistor are connected to the first scan signal line, and the gate electrode of the ninth transistor is connected to the second scan signal line. The second scan signal line and the fifth scan signal line output the same scan signal.

[0013] In an exemplary embodiment, the display substrate further includes a second scan connection line. The second scan signal line and the second scan connection line are disposed in different conductive layers. The orthographic projection of the second scan signal line on the substrate and the orthographic projection of the second scan connection line on the substrate at least partially overlap. The second scan signal line is connected to the second scan connection line through a via, forming a double-layer structure of scan signal lines.

[0014] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the second scan connection line is disposed in the first conductive layer, and the second scan signal line is disposed in the third conductive layer.

[0015] In an exemplary embodiment, the display substrate further includes a fifth scan connection line. The fifth scan signal line and the fifth scan connection line are disposed on different conductive layers. The orthographic projection of the fifth scan signal line on the substrate and the orthographic projection of the fifth scan connection line on the substrate at least partially overlap. The fifth scan signal line is connected to the fifth scan connection line through a via, forming a double-layer structure of scan signal lines.

[0016] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the fifth scan connection line is disposed in the second conductive layer, and the fifth scan signal line is disposed in the third conductive layer.

[0017] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

[0018] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, the orthogonal projection of the second shielding electrode on the substrate at least partially overlapping the orthogonal projections of the second pole of the fourth transistor and the second pole of the ninth transistor on the substrate.

[0019] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

[0020] In an exemplary embodiment, at least one circuit unit further includes a fourth shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

[0021] In an exemplary embodiment, the display substrate further includes at least one first power connection line extending along the cell row direction and at least one first power line extending along the cell column direction; the first power line and the first power connection line are disposed in different conductive layers, and the first power line and the first power connection line are connected through vias to form a mesh structure for transmitting the first power signal.

[0022] In an exemplary embodiment, the display substrate further includes at least one second power connection line extending along the cell row direction and at least one second power line extending along the cell column direction; the second power line and the second power connection line are disposed in different conductive layers, and the second power line and the second power connection line are connected through vias to form a mesh structure for transmitting the second power signal.

[0023] In an exemplary embodiment, the display substrate further includes at least one reference signal connection line extending along the cell row direction and at least one reference signal line extending along the cell column direction; the reference signal line and the reference signal connection line are disposed in different conductive layers, and the reference signal connection line and the reference signal line are connected through vias to form a mesh structure for transmitting reference signals.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; the fabrication method comprising:

[0026] A semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on a substrate; the semiconductor layer includes at least a plurality of active layers of transistors, and the semiconductor layer includes at least a first active pattern and a second active pattern, the first active pattern including an active layer of at least one transistor, and the second active pattern including an active layer of at least one transistor; in at least one circuit cell, the first active pattern and the second active pattern are spaced apart, the active layers of the plurality of transistors in the circuit cell are spaced apart from the active layers of the plurality of transistors in the adjacent circuit cell in the cell row direction, and the active layers of the plurality of transistors in the circuit cell are spaced apart from the active layers of the plurality of transistors in the adjacent circuit cell in the cell column direction.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 This is a schematic diagram of the structure of a display device;

[0030] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0032] Figure 4 An equivalent circuit diagram of a pixel driving circuit is provided as an exemplary embodiment of this disclosure.

[0033] Figure 5 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0034] Figure 6 for Figure 5 Schematic diagram of the middle semiconductor layer;

[0035] Figure 7 for Figure 5 A schematic diagram of the structure of the first and second storage capacitor regions in the middle;

[0036] Figure 8 This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed.

[0037] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0038] Figure 10A and Figure 10B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0039] Figure 11 This is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0040] Figure 12A and Figure 12B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0041] Figure 13 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer pattern according to the present disclosure;

[0042] Figure 14A and 14B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0043] Figure 15 This is a schematic diagram of another planar structure of a display substrate, as an exemplary embodiment of the present disclosure;

[0044] Figure 16 for Figure 15 A schematic diagram of the structure of the second and fifth scan signal lines;

[0045] Figure 17 This is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed;

[0046] Figure 18A and Figure 18B This is a schematic diagram of another display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0047] Figure 19A and Figure 19B This is a schematic diagram of another display substrate after the formation of the second conductive layer pattern according to the present disclosure;

[0048] Figure 20 This is a schematic diagram of another display substrate after the fourth insulating layer pattern has been formed;

[0049] Figure 21A and Figure 21B This is a schematic diagram of another display substrate after the formation of the third conductive layer pattern according to the present disclosure;

[0050] Figure 22 This is a schematic diagram of another display substrate after the fifth conductive layer pattern has been formed;

[0051] Figure 23A and Figure 23B This is a schematic diagram of another display substrate after the fourth conductive layer pattern has been formed.

[0052] Explanation of reference numerals in the attached figures:

[0053] 10—First active pattern; 11—First active layer; 12—Second active layer;

[0054] 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer;

[0055] 16—Sixth active layer; 17—Seventh active layer; 18—Eighth active layer;

[0056] 19—Ninth active layer; 20—Second active pattern; 21—First gate electrode;

[0057] 22—Second gate electrode; 24—Fourth gate electrode; 25—Fifth gate electrode;

[0058] 26—Sixth gate electrode; 29—Ninth gate electrode; 31—First light-emitting signal line;

[0059] 32—Second light-emitting signal line; 33—Repair line; 36—First shielding electrode;

[0060] 37—Second shielding electrode; 38—Third shielding electrode; 39—Fourth shielding electrode;

[0061] 41—First connecting electrode; 42—Second connecting electrode; 43—Third connecting electrode;

[0062] 44—Fourth connecting electrode; 45—Fifth connecting electrode; 46—Sixth connecting electrode;

[0063] 47—Seventh connecting electrode; 48—Eighth connecting electrode; 51—First power supply line;

[0064] 52—Second power supply line; 53—Data signal line; 54—Reference signal connection line;

[0065] 55—Anode connection electrode; 61—First scan signal line; 62—Second scan signal line;

[0066] 62-1—Second scan connection line; 63—Third scan signal line; 64—Fourth scan signal line;

[0067] 65—Fifth scan signal line; 65-1—Fifth scan connection line; 68—First power supply connection line;

[0068] 69—Second power supply connection wire; 71—First electrode plate; 72—Second electrode plate;

[0069] 73—Third plate; 74—Fourth plate; 75—First opening;

[0070] 76—Second opening; 81—First initial signal line; 82—Second initial signal line;

[0071] 91—First reference signal line; 92—Second reference signal line; 101—Substrate;

[0072] 102—Driver circuit layer; 103—Light-emitting structure layer; 104—Packaging structure layer. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0074] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0075] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0076] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0077] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0078] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0079] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0080] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0081] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0082] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0083] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0084] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0085] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0086] Figure 2This is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. Figure 2 As shown, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0087] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0088] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0089] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels within the substrate. Figure 4 As shown, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0090] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit, and the pixel driving circuit can include multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device. The light-emitting device can include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0091] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0092] An exemplary embodiment of this disclosure provides a display substrate including multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit, which includes at least a multiple transistor. On a plane perpendicular to the display substrate, at least one circuit unit includes a semiconductor layer disposed on a substrate and multiple conductive layers disposed on the semiconductor layer on a side away from the substrate. The semiconductor layer includes at least an active layer of multiple transistors. The semiconductor layer includes at least a first active pattern and a second active pattern. The first active pattern includes an active layer of at least one transistor, and the second active pattern includes an active layer of at least one transistor. In the at least one circuit unit, the first active pattern and the second active pattern are spaced apart. The active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the cell row direction, and the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the cell column direction.

[0093] In an exemplary embodiment, the first active pattern includes an active layer of two transistors, the active layers of the two transistors being an integral structure interconnected; the second active pattern includes an active layer of seven transistors, the active layers of the seven transistors being an integral structure interconnected.

[0094] In an exemplary embodiment, the pixel driving circuit includes a first transistor and a seventh transistor as initialization transistors, a second transistor as compensation transistors, a third transistor as driving transistors, a fourth transistor as data writing transistors, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors. The first active pattern includes the active layer of the fourth transistor and the active layer of the ninth transistor, and the second active pattern includes the active layers of the first transistor to the third transistor and the active layers of the fifth transistor to the eighth transistor.

[0095] In an exemplary embodiment, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first electrode plate and a third electrode plate, wherein the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate at least partially overlap; the second storage capacitor includes at least a second electrode plate and a fourth electrode plate, wherein the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the fourth electrode plate on the substrate at least partially overlap; the first electrode plate serves as the gate electrode of the third transistor, the second electrode plate is connected to the third electrode plate, and the fourth electrode plate is connected to the first power line.

[0096] In an exemplary embodiment, the pixel driving circuit further includes an additional capacitor, the lower electrode of which is disposed in the semiconductor layer, and the upper electrode of which is disposed in the second conductive layer. The orthographic projection of the upper electrode on the substrate at least partially overlaps with the orthographic projection of the lower electrode on the substrate. The lower electrode is connected to the second electrode, and the upper electrode is connected to the fourth electrode.

[0097] In an exemplary embodiment, the gate electrode of the ninth transistor is connected to the second scan signal line, the gate electrode of the second transistor is connected to the fifth scan signal line, and the second scan signal line and the fifth scan signal line output the same scan signal.

[0098] In an exemplary embodiment, the display substrate further includes a second scan connection line. The second scan signal line and the second scan connection line are disposed in different conductive layers. The orthographic projection of the second scan signal line on the substrate and the orthographic projection of the second scan connection line on the substrate at least partially overlap. The second scan signal line is connected to the second scan connection line through a via, forming a double-layer structure of scan signal lines.

[0099] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the second scan connection line is disposed in the first conductive layer, and the second scan signal line is disposed in the third conductive layer.

[0100] In an exemplary embodiment, the display substrate further includes a fifth scan connection line. The fifth scan signal line and the fifth scan connection line are disposed on different conductive layers. The orthographic projection of the fifth scan signal line on the substrate and the orthographic projection of the fifth scan connection line on the substrate at least partially overlap. The fifth scan signal line is connected to the fifth scan connection line through a via, forming a double-layer structure of scan signal lines.

[0101] In an exemplary embodiment, the plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the fifth scan connection line is disposed in the second conductive layer, and the fifth scan signal line is disposed in the third conductive layer.

[0102] In an exemplary embodiment, at least one circuit unit further includes a first shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

[0103] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode, the orthogonal projection of the second shielding electrode on the substrate at least partially overlapping the orthogonal projections of the second pole of the fourth transistor and the second pole of the ninth transistor on the substrate.

[0104] In an exemplary embodiment, at least one circuit unit further includes a third shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

[0105] In an exemplary embodiment, at least one circuit unit further includes a fourth shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

[0106] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0107] Figure 4This is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of this disclosure can be a 9T2C structure, which may include 9 transistors (first transistor T1 to ninth transistor T9) and 2 storage capacitors (first storage capacitor C1 and second storage capacitor C2). The pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line DATA and first power supply line VDD).

[0108] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a first storage capacitor C1. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of an eighth transistor T8, and the second terminal of a fifth transistor T5. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminals of a sixth transistor T6 and a seventh transistor T7. The fifth node N5 is connected to the second terminal of a fourth transistor T4, the second terminal of a ninth transistor T9, the second terminal of the first storage capacitor C1, and the second terminal of the second storage capacitor C2.

[0109] In an exemplary embodiment, the first end of the first storage capacitor C1 is connected to the first node N1, the second end of the first storage capacitor C1 is connected to the fifth node N5, the first end of the second storage capacitor C2 is connected to the first power line VDD, and the second end of the second storage capacitor C2 is connected to the fifth node N5.

[0110] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the first node N1. When a conduction signal is applied to the fourth scan signal line S4, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 and the first terminal of the first storage capacitor C1, thereby releasing the charge accumulated in the first storage capacitor C1 and achieving initialization.

[0111] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0112] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first terminal of the first storage capacitor C1. The first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the magnitude of the driving current is determined by the potential difference between its gate electrode and its first terminal.

[0113] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the fifth node N5. When a conduction signal is applied to the third scan signal line S3, the fourth transistor T4 causes the data voltage of the data signal line DATA to be input to the second terminal of the first storage capacitor C1 and the second terminal of the second storage capacitor C2.

[0114] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When a conduction signal is applied to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0115] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. When a conduction signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light-emitting device EL, releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0116] In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, the first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and the second electrode of the eighth transistor T8 is connected to the second node N2. When a conduction signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0117] In an exemplary embodiment, the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and the second electrode of the ninth transistor T9 is connected to the fifth node N5. When a conduction signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0118] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0119] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include both P-type and N-type transistors.

[0120] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0121] Figure 5This is a schematic diagram of a planar structure of a display substrate, illustrating the structure of pixel driving circuits in three circuit units (first circuit unit, second circuit unit, and third circuit unit) of the display substrate, as an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, and the light-emitting structure layer may include at least a plurality of light-emitting units. At least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. In an exemplary embodiment, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In an exemplary embodiment, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or they may not correspond.

[0122] In an exemplary embodiment, a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects with the second direction Y.

[0123] like Figure 5 As shown, in an exemplary embodiment, the driving circuit layer may further include at least one first power connection line 68 extending along the first direction X and at least one first power line 51 extending along the second direction Y. The first power line 51 is connected to the pixel driving circuit in the plurality of circuit units. The first power line 51 is configured to continuously provide a high-level signal to the pixel driving circuit. The first power line 51 extending along the second direction Y is interconnected with the first power connection line 68 extending along the first direction X to form a mesh structure for transmitting the first power signal.

[0124] In an exemplary embodiment, the driving circuit layer may further include at least one second power connection line 69 extending along the first direction X and at least one second power line 52 extending along the second direction Y. The second power line 52 is connected to the cathode of a plurality of light-emitting units. The second power line 52 is configured to continuously provide a low-level signal to the cathode. The second power line 52 extending along the second direction Y is interconnected with the second power connection line 69 extending along the first direction X to form a mesh structure for transmitting the second power signal.

[0125] In an exemplary embodiment, the driving circuit layer may further include at least one first reference signal line 91 extending along a first direction X and at least one reference signal connection line 54 extending along a second direction Y. The first reference signal line 91 is connected to the pixel driving circuit in a plurality of circuit units. The first reference signal line 91 is configured to provide a first reference signal to the pixel driving circuit. The first reference signal line 91 extending along the first direction X and the reference signal connection line 54 extending along the second direction Y are interconnected to form a mesh structure for transmitting the first reference signal.

[0126] In this disclosure, A extending along the direction of B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending in other directions.

[0127] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The first power line 51 and the first power connection line 68 may be disposed in different conductive layers, and the first power line 51 and the first power connection line 68 may be connected via vias. The second power line 52 and the second power connection line 69 may be disposed in different conductive layers, and the second power line 52 and the second power connection line 69 may be connected via vias. The first reference signal line 91 and the reference signal connection line 54 may be disposed in different conductive layers, and the first reference signal line 91 and the reference signal connection line 54 may be connected via vias.

[0128] In an exemplary embodiment, the first power line 51, the second power line 52, and the reference signal connection line 54 can be arranged on the same layer and formed synchronously through the same patterning process. The first power connection line 68, the second power connection line 69, and the first reference signal line 91 can be arranged on the same layer and formed synchronously through the same patterning process.

[0129] In an exemplary embodiment, the first power connection line 68, the second power connection line 69, and the first reference signal line 91 may be disposed in the third conductive layer, and the first power line 51, the second power line 52, and the reference signal connection line 54 may be disposed in the fourth conductive layer.

[0130] Figure 6 for Figure 5 A schematic diagram of the semiconductor layer illustrates the structure of the first and second active patterns in a circuit unit. For example... Figure 6 As shown, at least one circuit unit may include multiple transistors, and the semiconductor layer of at least one circuit unit may include at least the active layer of multiple transistors.

[0131] In an exemplary embodiment, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 and a second active pattern 20. The first active pattern 10 may include an active layer of at least one transistor, and the second active pattern 20 may include an active layer of at least one transistor.

[0132] In an exemplary embodiment, in at least one circuit unit, a first active pattern 10 and a second active pattern 20 are spaced apart, that is, the active layer of the transistor in the first active pattern 10 and the active layer of the transistor in the second active pattern 20 are not connected.

[0133] In an exemplary embodiment, in at least one circuit unit, the active layers of multiple transistors are spaced apart from the active layers of multiple transistors in adjacent circuit units in the cell row direction. That is, in the cell row direction, the active layers of multiple transistors in one circuit unit are not connected to the active layers of multiple transistors in adjacent circuit units.

[0134] In an exemplary embodiment, in at least one circuit unit, the active layers of multiple transistors are spaced apart from the active layers of multiple transistors in adjacent circuit units in the unit column direction. That is, in the unit column direction, the active layers of multiple transistors in one circuit unit are not connected to the active layers of multiple transistors in adjacent circuit units.

[0135] In an exemplary embodiment, the first active pattern 10 may include an active layer of two transistors, the active layers of the two transistors being an integral structure interconnected. The second active pattern 20 may include an active layer of seven transistors, the active layers of the seven transistors being an integral structure interconnected.

[0136] In an exemplary embodiment, the pixel driving circuit in at least one circuit unit may include a first transistor T1 and a seventh transistor T7 as initialization transistors, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 and a sixth transistor T6 as light-emitting transistors, and an eighth transistor T8 and a ninth transistor T9 as reference transistors. The first active pattern 10 may include the active layer of the fourth transistor T4 and the active layer of the ninth transistor T9. The second active pattern 20 may include the active layers of the first transistor T1 to the third transistor T3 and the active layers of the fifth transistor T5 to the eighth transistor T8.

[0137] Figure 7 for Figure 5 A schematic diagram of the structure of the first and second storage capacitor regions. (See attached diagram.) Figure 5 and Figure 7As shown, in an exemplary embodiment, the first storage capacitor may include at least a first electrode 71 and a third electrode 73, wherein the orthographic projection of the third electrode 73 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 71 onto the substrate. The second storage capacitor may include at least a second electrode 72 and a fourth electrode 74, wherein the orthographic projection of the fourth electrode 74 onto the substrate at least partially overlaps with the orthographic projection of the second electrode 72 onto the substrate.

[0138] In an exemplary embodiment, the first electrode 71 can serve as the gate electrode of the third transistor T3, the second electrode 72 is connected to the third electrode 73, and the fourth electrode 74 is connected to the first power line 51.

[0139] In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate. A first electrode 71 and a second electrode 72 may be disposed in the first conductive layer, a third electrode 73 and a fourth electrode 74 may be disposed in the second conductive layer, a first power line 51 may be disposed in the fourth conductive layer, and the second electrode 72 may be connected to the third electrode 73 via a connecting electrode disposed in the third conductive layer.

[0140] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first terminal of the first transistor T1 is connected to the first initial signal line 81, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate 71 of the first storage capacitor, respectively. The gate electrode of the second transistor T2 is connected to the fifth scan signal line 65, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6, respectively. The gate electrode of the third transistor T3 serves as the first plate 71 of the first storage capacitor, and the first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5 and the second terminal of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first terminal of the fourth transistor T4 is connected to the data signal line 53, and the second terminal of the fourth transistor T4 is connected to the second terminal of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor, respectively. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line 31, and the first terminal of the fifth transistor T5 is connected to the first power supply line 51. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scan signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scan signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92. The gate electrode of the ninth transistor T9 is connected to the second scan signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0141] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0142] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light emission signal line 31, the second light emission signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91, and the second reference signal line 92 can be line shapes extending along the first direction X of the main body, and the shapes of the first power line 51 and the data signal line 53 can be line shapes extending along the second direction Y of the main body.

[0143] In an exemplary embodiment, at least one circuit unit may further include an anode connection electrode 55, which is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 respectively, and is also connected to the anode of the light-emitting unit.

[0144] In an exemplary embodiment, the driving circuit layer may further include a repair line 33. The shape of the repair line 33 may be a line shape in which the main body extends along the first direction X. The orthographic projection of the repair line 33 on the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 55 on the substrate. The repair line 33 is configured to input a signal to the anode of the sub-pixel with the bright spot defect when a bright spot defect occurs on the display substrate, so as to repair it into a dark spot.

[0145] In an exemplary embodiment, at least one circuit unit may further include a first connection electrode 41, which is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first plate 71 of the first storage capacitor, respectively. The first connection electrode 41 may serve as the first node of the pixel driving circuit.

[0146] In an exemplary embodiment, at least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51. The orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate, so as to shield the influence of other signals in the pixel driving circuit on the first node.

[0147] In an exemplary embodiment, at least one circuit unit may further include a second connection electrode 42, which is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor, and the second electrode plate 72 of the second storage capacitor, respectively. The second connection electrode 42 may serve as the fifth node N5 in the pixel driving circuit.

[0148] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate, so as to shield the influence of other signals in the pixel driving circuit on the fifth node.

[0149] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36, which is connected to a fourth electrode plate 74. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the effects of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0150] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37, which is connected to the fourth electrode plate 74. The orthographic projection of the second shielding electrode 37 on the substrate at least partially overlaps with the orthographic projections of the second electrodes of the fourth transistor T4 and the ninth transistor T9 on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of data voltage transitions on the fifth node, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0151] In an exemplary embodiment, the fourth electrode 74, the first shielding electrode 36, and the second shielding electrode 37 can be an integral structure that is interconnected.

[0152] In an exemplary embodiment, at least one circuit unit may further include an additional capacitor for the second storage capacitor. The lower electrode of the additional capacitor is disposed in the semiconductor layer, and the upper electrode of the additional capacitor is disposed in the second conductive layer. The orthographic projection of the upper electrode on the substrate and the orthographic projection of the lower electrode on the substrate at least partially overlap. The lower electrode is connected to the second electrode, and the upper electrode is connected to the fourth electrode.

[0153] In an exemplary embodiment, the lower electrode of the additional capacitor is the second region of the active layer of the fourth transistor T4 (which is also the second region of the active layer of the ninth transistor T9), and the upper electrode of the additional capacitor is the second shielding electrode 37. Since the second region of the active layer of the fourth transistor T4 is connected to the second electrode 72 through the second connecting electrode 42, and the second shielding electrode 37 and the fourth electrode 74 are an integral structure connected to each other, an additional capacitor for the second storage capacitor is formed. The additional capacitor is connected in parallel with the second storage capacitor, which can effectively increase the total capacity of the second storage capacitor, improve the working performance of the pixel driving circuit, and improve the display effect.

[0154] In an exemplary embodiment, at least one circuit unit may further include a third shielding electrode 38, which is connected to the second reference signal line 92. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the effect of data voltage transitions on the fourth transistor T4, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0155] In an exemplary embodiment, at least one circuit unit may further include a fourth shielding electrode 39, which is connected to the second reference signal line 92. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the effect of data voltage transitions on the ninth transistor T9, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0156] In an exemplary embodiment, the third shielding electrode 38, the fourth shielding electrode 39, and the second reference signal line 92 can be an integral structure that is interconnected.

[0157] In an exemplary embodiment, at least one circuit unit has a first electrode connecting line 73-1 on the side of the third electrode plate 73 near the fourth electrode plate 74, and the fourth electrode plate 74 has a first groove K1 recessed in the direction away from the third electrode plate 73 on the side of the fourth electrode plate 74 near the third electrode plate 73. The first electrode connecting line 73-1 is disposed in the first groove K1, and the end of the first electrode connecting line 73-1 away from the third electrode plate 73 is connected to the second connecting electrode 42 through a through hole.

[0158] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0159] In an exemplary embodiment, taking three circuit units (first circuit unit, second circuit unit, and third circuit unit) in the nth unit row as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0160] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 8 As shown.

[0161] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, the seventh active layer 17 of the seventh transistor T7, the eighth active layer 18 of the eighth transistor T8, and the ninth active layer 19 of the ninth transistor T9. The first active layer 11 to the third active layer 13, the fifth active layer 15 to the eighth active layer 18 may be an integral structure interconnected with each other, and the fourth active layer 14 and the ninth active layer 19 may be an integral structure interconnected with each other.

[0162] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row can be located on the side of the third active layer 13 near the (n-1)th unit row, that is, the fourth active layer 14 and the ninth active layer 19 can be located on the side opposite to the second direction Y of the third active layer 13 of this circuit unit. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row can be located on the side of the third active layer 13 near the (n+1)th unit row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 can be located on the side of the third active layer 13 of this circuit unit in the second direction Y.

[0163] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 in the second direction Y of this circuit unit, the fifth active layer 15 may be located on one side of the first active layer 11 in the second direction Y of this circuit unit, and the eighth active layer 18 may be located on one side of the fifth active layer 15 in the second direction Y of this circuit unit. The second active layer 12 may be located on one side of the third active layer 13 in the second direction Y of this circuit unit, the sixth active layer 16 may be located on one side of the second active layer 12 in the second direction Y of this circuit unit, and the seventh active layer 17 may be located on one side of the sixth active layer 16 in the second direction Y of this circuit unit.

[0164] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 may be located on one side of the first direction X of this circuit unit (such as the opposite side of the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 may be located on the other side of the first direction X of this circuit unit (such as one side of the first direction X).

[0165] In an exemplary embodiment, the first active layer 11 and the second active layer 12 can be in the shape of an "L", the third active layer 13 can be in the shape of a "C", the fourth active layer 14 and the ninth active layer 19 can be in the shape of an "n", and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be in the shape of an "I".

[0166] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be interconnected, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer can be interconnected, and the first region 13-1 of the third active layer can simultaneously serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, constituting the second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be interconnected, and the second region 13-2 of the third active layer can simultaneously serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, constituting the third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer can be interconnected, and the second region 14-2 of the fourth active layer can serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be interconnected, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, forming the fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer can be set individually. The first region 14-1 of the fourth active layer can be located on the side of the channel region of the fourth active layer near the third active layer 13, and the first region 19-1 of the ninth active layer can be located on the side of the channel region of the ninth active layer near the third active layer 13.

[0167] In an exemplary embodiment, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 and a second active pattern 20. The first active pattern 10 may include the active layer of the fourth transistor T4 and the active layer of the ninth transistor T9. The second active pattern 20 may include the active layers of the first transistor T1 to the third transistor T3 and the active layers of the fifth transistor T5 to the eighth transistor T8.

[0168] In an exemplary embodiment, in at least one circuit unit, a first active pattern 10 and a second active pattern 20 are spaced apart, that is, the active layer of the transistor in the first active pattern 10 and the active layer of the transistor in the second active pattern 20 are not connected.

[0169] In an exemplary embodiment, in at least one cell row, the semiconductor layers in adjacent circuit cells in the first direction X are spaced apart from each other, that is, the semiconductor layer of the first circuit cell in the nth cell row is not connected to the semiconductor layer of the second circuit cell in the nth cell row, and the semiconductor layer of the second circuit cell in the nth cell row is not connected to the semiconductor layer of the third circuit cell in the nth cell row.

[0170] In an exemplary embodiment, in at least one cell column, the semiconductor layers in adjacent circuit cells in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit cell in the (n-1)th cell row is not connected to the semiconductor layer of the first circuit cell in the nth cell row, and the semiconductor layer of the first circuit cell in the nth cell row is not connected to the semiconductor layer of the first circuit cell in the (n+1)th cell row.

[0171] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0172] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first electrode plate 71 of a first storage capacitor, and a second electrode plate 72 of a second storage capacitor.

[0173] In an exemplary embodiment, the first gate electrode 21 may be in the shape of an "L" and may be located on one side of the first electrode plate 71 in the second direction Y. The area where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 in the dual-gate structure.

[0174] In an exemplary embodiment, the second gate electrode 22 may be in the shape of a "T" and may be located on one side of the first electrode plate 71 in the second direction Y. The area where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 in the dual-gate structure.

[0175] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of an "L" and may be located on the side opposite to the second direction Y of the second electrode plate 72. The area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 in a dual-gate structure.

[0176] In an exemplary embodiment, the fifth gate electrode 25 may be a strip shape extending along the second direction Y, and may be located on one side of the first gate electrode 21 in the second direction Y. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0177] In an exemplary embodiment, the shape of the sixth gate electrode 26 may be a strip shape extending along the first direction X, and may be located on one side of the second gate electrode 22 in the second direction Y. The region where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0178] In an exemplary embodiment, the shape of the ninth gate electrode 29 can be a strip shape extending along the first direction X, and it can be located on the side opposite to the second direction Y of the second electrode plate 72. The area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 in a dual-gate structure.

[0179] In an exemplary embodiment, the shape of the first scan signal line 61 can be a line shape extending along the first direction X of the main body portion, and can be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The area where the first scan signal line 61 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the first scan signal line 61 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0180] In an exemplary embodiment, the first electrode 71 of the first storage capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 71 can simultaneously serve as the lower electrode of the first storage capacitor and the gate electrode of the third transistor T3.

[0181] In an exemplary embodiment, the second electrode 72 of the second storage capacitor can be rectangular in shape, with chamfered corners. It can be located on the side opposite to the second direction Y of the first electrode 71, and on the side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y. That is, in the second direction Y, the second electrode 72 is located between the first electrode 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second electrode 72 onto the substrate does not overlap with the orthographic projection of the semiconductor layer onto the substrate. In an exemplary embodiment, the second electrode 72 can serve as the lower electrode of the second storage capacitor.

[0182] In an exemplary embodiment, the areas of the first electrode 71 and the second electrode 72 projected onto the substrate may be the same or different. For example, the area of ​​the second electrode 72 projected onto the substrate may be larger than the area of ​​the first electrode 71 projected onto the substrate.

[0183] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the ninth active layer are both conducted.

[0184] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A A schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0185] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third electrode plate 73 of a first storage capacitor, a fourth electrode plate 74 of a second storage capacitor, and a second reference signal line 92.

[0186] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, and the second reference signal line 92 can be the line shape of the main body extending along the first direction X. The first light-emitting signal line 31, the second light-emitting signal line 32, and the repair line 33 can be located between the first gate electrode 21 and the first scan signal line 61, and the second reference signal line 92 can be located on the side opposite to the second direction Y of the fourth gate electrode 24.

[0187] In an exemplary embodiment, the first light-emitting signal line 31 may be located on one side of the first gate electrode 21 in the second direction Y of this circuit unit, the second light-emitting signal line 32 may be located on one side of the first light-emitting signal line 31 in the second direction Y of this circuit unit, and the repair line 33 may be located on one side of the second light-emitting signal line 32 in the second direction Y of this circuit unit, that is, the second light-emitting signal line 32 may be located between the first light-emitting signal line 31 and the repair line 33.

[0188] In an exemplary embodiment, a first light-emitting connector 31-1 is provided on the side of the first light-emitting signal line 31 near the second light-emitting signal line 32. The first light-emitting connector 31-1 can be disposed in each circuit unit. The first end of the first light-emitting connector 31-1 is connected to the first light-emitting signal line 31, and the second end of the first light-emitting connector 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connector 31-1 is configured to be connected to the fifth gate electrode 25 through a subsequently formed seventh connection electrode. In an exemplary embodiment, the first light-emitting signal line 31 and the plurality of first light-emitting connectors 31-1 can be an integral structure interconnected with each other.

[0189] In an exemplary embodiment, a second light-emitting connector 32-1 is provided on the side of the second light-emitting signal line 32 near the first light-emitting signal line 31. The second light-emitting connector 32-1 can be disposed in each circuit unit. The first end of the second light-emitting connector 32-1 is connected to the second light-emitting signal line 32, and the second end of the second light-emitting connector 32-1 extends toward the first light-emitting signal line 31. The second light-emitting connector 32-1 is configured to be connected to the sixth gate electrode 26 through a subsequently formed eighth connection electrode. In an exemplary embodiment, the second light-emitting signal line 32 and the plurality of second light-emitting connectors 32-1 can be an interconnected integral structure.

[0190] In an exemplary embodiment, a second reference connection block 92-1 is provided on the side of the second reference signal line 92 in the nth unit row away from the second electrode plate 72 in the nth unit row. The second reference connection block 92-1 can be disposed in each circuit unit. The first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and the second end of the second reference connection block 92-1 extends away from the second electrode plate 72, that is, extends towards the (n-1)th unit row. In an exemplary embodiment, the second reference connection block 92-1 of the second reference signal line 92 in the nth unit row is configured to be connected to the first region of the eighth active layer in the (n-1)th unit row through a subsequently formed sixth connection electrode, providing a second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th unit row. In an exemplary embodiment, the second reference signal line 92 and the plurality of second reference connection blocks 92-1 can be an interconnected integral structure.

[0191] In an exemplary embodiment, the outline shape of the third electrode 73 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. It can be located between the first light-emitting signal line 31 and the second reference signal line 92 of this circuit unit. The orthographic projection of the third electrode 73 on the substrate at least partially overlaps with the orthographic projection of the first electrode 71 on the substrate. The third electrode 73 can serve as the upper electrode of the first storage capacitor (the second end of the first storage capacitor C1). The first electrode 71 and the third electrode 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0192] In an exemplary embodiment, the outline shape of the fourth plate 74 of the second storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. It can be located between the second reference signal line 92 and the third plate 73 of this circuit unit. The orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor (the first end of the second storage capacitor C2). The second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0193] In an exemplary embodiment, the areas of the third electrode 73 and the fourth electrode 74 projected onto the substrate may be the same or different. For example, the area of ​​the fourth electrode 74 projected onto the substrate may be larger than the area of ​​the third electrode 73 projected onto the substrate.

[0194] In an exemplary embodiment, a first electrode connection line 73-1 is provided on the side of the third electrode plate 73 near the fourth electrode plate 74. The first end of the first electrode connection line 73-1 is connected to the third electrode plate 73, and the second end of the first electrode connection line 73-1 extends toward the second reference signal line 92. The first electrode connection line 73-1 is configured to be connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through a subsequently formed second connection electrode, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third electrode plate 73 have the same potential.

[0195] In an exemplary embodiment, a second electrode connecting line 74-1 may be provided on one side of the fourth electrode plate 74 in the first direction X or on the side opposite to the first direction X. The first end of the second electrode connecting line 74-1 is connected to the fourth electrode plate 74 of this circuit unit, and the second end of the second electrode connecting line 74-1 extends along the first direction X or the opposite direction of the first direction X and connects to the fourth electrode plate 74 of the adjacent circuit unit, so that the fourth electrode plates 74 of adjacent circuit units in a unit row are interconnected. In an exemplary embodiment, multiple fourth electrode plates 74 and multiple second electrode connecting lines 74-1 can be an integrated structure interconnected. Since the fourth electrode plate 74 is connected to the subsequently formed first power line, the fourth electrode plate 74 of the multiple circuit units in an integrated structure can be reused as a horizontal power line extending along the first direction X. This not only ensures that multiple fourth electrode plates in a unit row have the same potential, but also reduces the voltage drop of the first power signal, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0196] In an exemplary embodiment, a first groove K1 can be formed between the edges of two adjacent fourth plates 74 in the first direction X and the edge of the second plate connection line 74-1. The first groove K1 is configured to accommodate the first plate connection line 73-1. The first plate connection line 73-1 on the third plate 73 extends in the first groove K1 toward the direction of the second reference signal line 92, which can make the subsequently formed twelfth via move as high as possible and as close as possible to the second region of the fourth active layer (which is also the second region of the ninth active layer). The twelfth via is configured to allow the subsequently formed second connection electrode to be connected to the first plate connection line 73-1 through the via. The second connection electrode is also connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the via, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third plate 73 have the same potential.

[0197] In an exemplary embodiment, each circuit unit has a first opening 75 on its third electrode plate 73. The first opening 75 may be located in the middle of the third electrode plate 73 and may be rectangular, thus forming a ring structure with the third electrode plate 73. The first opening 75 exposes a third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 onto the substrate includes the orthographic projection of the first opening 75 onto the substrate. In an exemplary embodiment, the first opening 75 is configured to accommodate a subsequently formed tenth via, which is located within the first opening 75 and exposes the first electrode plate 71, allowing a subsequently formed first connection electrode to be connected to the first electrode plate 71.

[0198] In an exemplary embodiment, each circuit unit has a second opening 76 on its fourth electrode plate 74. The second opening 76 may be located in the middle of the fourth electrode plate 74 and may be rectangular, thus forming a ring structure with the fourth electrode plate 74. The second opening 76 exposes a third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 onto the substrate includes the orthographic projection of the second opening 76 onto the substrate. In an exemplary embodiment, the second opening 76 is configured to accommodate a subsequently formed eleventh via, which is located within the second opening 76 and exposes the second electrode plate 72, allowing a subsequently formed second connection electrode to be connected to the second electrode plate 72.

[0199] In an exemplary embodiment, the first shielding electrode 36 may be T-shaped and may be located on the side of the fourth electrode plate 74 near the first light-emitting signal line 31. The first shielding electrode 36 may be disposed in each circuit unit. The T-shaped first shielding electrode 36 may include a first extension 36-1 and a first shielding section 36-2. The first end of the first extension 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension 36-1 extends toward the first light-emitting signal line 31 and is connected to the first shielding section 36-2. The first shielding segment 36-2 can be a strip extending along the first direction X. For the first shielding end located on the first shielding end of the first extension segment 36-1 on the first direction X side and the second shielding end located on the opposite side of the first extension segment 36-1 on the first direction X side, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate. Similarly, the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of data voltage jumps on the first transistor T1 and the second transistor T2, preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0200] In an exemplary embodiment, the second shielding electrode 37 may be L-shaped and located on the side of the fourth electrode plate 74 near the second reference signal line 92. The second shielding electrode 37 may be disposed in each circuit unit. The L-shaped second shielding electrode 37 may include a second extension segment 37-1 and a second shielding segment 37-2. The first end of the second extension segment 37-1 is connected to the fourth electrode plate 74, and the second end of the second extension segment 37-1 extends toward the second reference signal line 92 and connects to the second shielding segment 37-2. The second shielding segment 37-2 may be a strip shape extending along the first direction X. The orthographic projection of the second shielding segment 37-2 on the substrate at least partially overlaps with the orthographic projections of the second region of the fourth active layer and the second region of the ninth active layer in this circuit unit on the substrate. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of data voltage jumps on the fifth node N5, preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0201] In an exemplary embodiment, the first shielding electrode 36, the second shielding electrode 37, and the fourth electrode plate 74 can be an integral structure that is interconnected.

[0202] In an exemplary embodiment, since the second region of the fourth active layer (the second region of the ninth active layer) is a conductive layer that has undergone conductor treatment, and the second shielding electrode 37 of the second conductive layer is also a conductive layer, the second region of the fourth active layer (the second region of the ninth active layer) and the second shielding electrode 37 can form an additional capacitor for the second storage capacitor. The lower electrode of the additional capacitor is disposed in the semiconductor layer and is connected to the second electrode 72 through a subsequently formed second connection electrode. The upper electrode of the additional capacitor (the second shielding electrode 37) is disposed in the second conductive layer and is an integral structure interconnected with the fourth electrode 74, thus forming an additional capacitor for the second storage capacitor. The additional capacitor is connected in parallel with the second storage capacitor. By forming an additional capacitor for the second storage capacitor, this disclosure can effectively increase the total capacity of the second storage capacitor, improve the working performance of the pixel driving circuit, and improve the display effect.

[0203] In an exemplary embodiment, the third shielding electrode 38 and the fourth shielding electrode 39 may be rectangular in shape and located on the side of the second reference signal line 92 near the fourth electrode plate 74. The third shielding electrode 38 and the fourth shielding electrode 39 may be disposed in each circuit unit. The first ends of the third shielding electrode 38 and the fourth shielding electrode 39 are connected to the second reference signal line 92, and the second ends of the third shielding electrode 38 and the fourth shielding electrode 39 extend towards the fourth electrode plate 74. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit on the substrate. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the effect of data voltage transitions on the fourth transistor T4, and the fourth shielding electrode 39 is configured to shield the effect of data voltage transitions on the ninth transistor T9, thereby preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0204] In an exemplary embodiment, the third shielding electrode 38, the fourth shielding electrode 39, and the second reference signal line 92 can be an integral structure that is interconnected.

[0205] In an exemplary embodiment, the repair line 33 is configured as a pre-set repair signal line to input a signal to the anode of the sub-pixel with the bright spot defect when a bright spot defect occurs on the display substrate, so as to repair it into a dark spot.

[0206] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 11 As shown.

[0207] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22.

[0208] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed first initial signal line to be connected to the first region of the first active layer through the via.

[0209] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer). The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0210] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.

[0211] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the fourth active layer (which is also the second region of the ninth active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the fourth active layer (which is also the second region of the ninth active layer). The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the via.

[0212] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the fifth active layer. The fifth via V5 is configured to allow a subsequently formed fourth connection electrode to be connected to the first region of the fifth active layer through the via.

[0213] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is located within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The sixth via V6 is configured to allow the subsequently formed fifth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0214] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer. The seventh via V7 is configured to allow a subsequently formed second initial signal line to be connected to the first region of the seventh active layer through the via.

[0215] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the eighth active layer onto the substrate. The fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the eighth active layer. The eighth via V8 is configured to allow a subsequently formed sixth connection electrode to be connected to the first region of the eighth active layer through the via.

[0216] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the ninth active layer onto the substrate. The fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the ninth active layer. The ninth via V9 is configured to allow a subsequently formed first reference signal line to be connected to the first region of the ninth active layer through the via.

[0217] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 onto the substrate. The fourth and third insulating layers within the tenth via V10 are etched away, exposing the surface of the first electrode plate 71. The tenth via V10 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 71 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 onto the substrate. The fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the second electrode plate 72. The eleventh via V11 is configured to allow a subsequently formed second connection electrode to be connected to the second electrode plate 72 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the first electrode connection line 73-1 of the third electrode 73 on the substrate. The fourth insulating layer in the twelfth via V12 is etched away, exposing the surface of the first electrode connection line 73-1. The twelfth via V12 is configured to allow the subsequently formed second connection electrode to be connected to the first electrode connection line 73-1 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the fourth electrode plate 74 on the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the fourth electrode plate 74. The thirteenth via V13 is configured to allow the subsequently formed first power connection line to be connected to the fourth electrode plate 74 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the first gate electrode 21 on the substrate. The fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the first gate electrode 21. The fourteenth via V14 is configured to allow the subsequently formed fourth scan signal line to be connected to the first gate electrode 21 through the via.

[0222] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate is within the range of the orthogonal projection of the second gate electrode 22 onto the substrate. The fourth and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second gate electrode 22. The fifteenth via V15 is configured to allow the subsequently formed fifth scan signal line to be connected to the second gate electrode 22 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the fourth gate electrode 24 on the substrate. The fourth insulating layer and the third insulating layer within the sixteenth via V16 are etched away, exposing the surface of the fourth gate electrode 24. The sixteenth via V16 is configured to allow the subsequently formed third scan signal line to be connected to the fourth gate electrode 24 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the fifth gate electrode 25 onto the substrate. The fourth and third insulating layers within the seventeenth via V17 are etched away, exposing the surface of the fifth gate electrode 25. The seventeenth via V17 is configured to allow a subsequently formed seventh connection electrode to be connected to the fifth gate electrode 25 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the sixth gate electrode 26 on the substrate. The fourth and third insulating layers within the eighteenth via V18 are etched away, exposing the surface of the sixth gate electrode 26. The eighteenth via V18 is configured to allow the subsequently formed eighth connection electrode to be connected to the sixth gate electrode 26 through the via.

[0226] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the ninth gate electrode 29 on the substrate. The fourth and third insulating layers within the nineteenth via V19 are etched away, exposing the surface of the ninth gate electrode 29. The nineteenth via V19 is configured to allow the subsequently formed second scan signal line to be connected to the ninth gate electrode 29 through the via.

[0227] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the first light-emitting connecting block 31-1 of the first light-emitting signal line 31 onto the substrate. The fourth insulating layer within the twentieth via V20 is etched away, exposing the surface of the first light-emitting connecting block 31-1. The twentieth via V20 is configured to allow the subsequently formed seventh connecting electrode to be connected to the first light-emitting connecting block 31-1 through the via.

[0228] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second light-emitting connector 32-1 of the second light-emitting signal line 32 on the substrate. The fourth insulating layer inside the 21st via V21 is etched away, exposing the surface of the second light-emitting connector 32-1. The 21st via V21 is configured to allow the subsequently formed eighth connection electrode to be connected to the second light-emitting connector 32-1 through the via.

[0229] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the second reference connection block 92-1 onto the substrate of the second reference signal line 92. The fourth insulating layer within the 22nd via V22 is etched away, exposing the surface of the second reference connection block 92-1. The 22nd via V22 is configured to allow the subsequently formed sixth connection electrode to be connected to the second reference connection block 92-1 through the via.

[0230] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12AA schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0231] In an exemplary embodiment, the third conductive layer pattern of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a first initial signal line 81, a second initial signal line 82, and a first reference signal line 91.

[0232] In an exemplary embodiment, the shapes of the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, and the first reference signal line 91 can be lines extending along the first direction X of the main body. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 can be located on the side opposite to the second direction Y of the fourth electrode plate 74. The fourth scan signal line 64, the fifth scan signal line 65, the first initial signal line 81, and the second initial signal line 82 can be located on the side of the third electrode plate 73 in the second direction Y. The first power connection line 68 can be located in the area where the fourth electrode plate 74 is located. The second power connection line 69 can be located in the area where the third electrode plate 73 is located. The second power connection line 69 can be located on the side of the first power connection line 68 in the second direction Y.

[0233] In an exemplary embodiment, the first reference signal line 91 may be located on the side opposite to the second direction Y of the fourth electrode plate 74, the second scan signal line 62 may be located on the side opposite to the second direction Y of the first reference signal line 91, and the third scan signal line 63 may be located on the side opposite to the second direction Y of the second scan signal line 62.

[0234] In an exemplary embodiment, the fourth scan signal line 64 may be located on one side of the third electrode plate 73 in the second direction Y, the first initial signal line 81 may be located on one side of the fourth scan signal line 64 in the second direction Y, the fifth scan signal line 65 may be located on one side of the first initial signal line 81 in the second direction Y, and the second initial signal line 82 may be located on one side of the fifth scan signal line 65 in the second direction Y.

[0235] In an exemplary embodiment, the first power connection line 68 may be located on the side of the fourth electrode plate 74 close to the third electrode plate 73. The orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate. The first power connection line 68 is configured to connect to the first power line subsequently formed, forming a high-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0236] In an exemplary embodiment, the second power connection line 69 may be located on the side of the third electrode plate 73 near the fourth electrode plate 74. The orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate. The second power connection line 69 is configured to connect to a second power line subsequently formed, forming a low-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0237] In an exemplary embodiment, the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby enabling the second scan signal line 62 to connect to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0238] In an exemplary embodiment, the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby realizing the connection of the fifth scan signal line 65 to the second gate electrode 22 of the second transistor T2. The fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0239] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can extend to the frame area and be connected to the same gate drive circuit to achieve the same scan signal output, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0240] In an exemplary embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing the connection of the third scan signal line 63 to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0241] In an exemplary embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0242] In an exemplary embodiment, the first initial signal line 81 is connected to the first region of the first active layer in each circuit unit through the first via V1, thereby realizing that the first initial signal line 81 is connected to the first pole of the first transistor T1, and the first initial signal line 81 can write the first initial signal into the first pole of the first transistor T1.

[0243] In an exemplary embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby enabling the second initial signal line 82 to connect to the first terminal of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first terminal of the seventh transistor T7.

[0244] In an exemplary embodiment, the first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby enabling the first reference signal line 91 to connect to the first terminal of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal into the first terminal of the ninth transistor T9.

[0245] In an exemplary embodiment, a reference connection block 91-1 is provided on the side of the first reference signal line 91 near the first power connection line 68. The first end of the reference connection block 91-1 is connected to the first reference signal line 91, and the second end of the reference connection block 91-1 extends toward the first power connection line 68. The reference connection block 91-1 is configured to be connected to a reference signal connection line that is subsequently formed.

[0246] In an exemplary embodiment, the first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thus realizing the connection of the first power connection line 68 to the fourth electrode plate 74. Since the first power connection line 68 is connected to the subsequently formed first power line, the first power connection line 68 can write the first power signal to the upper electrode plate (the first end of the second storage capacitor) of the second storage capacitor.

[0247] In an exemplary embodiment, a first power connection block 68-1 is provided on the side of the first power connection line 68 away from the second power connection line 69. The first end of the first power connection block 68-1 is connected to the first power connection line 68, and the second end of the first power connection block 68-1 extends away from the second power connection line 69. In this exemplary embodiment, the first power connection block 68-1 is configured, on the one hand, to connect to the fourth electrode plate 74 through the thirteenth via V13, and on the other hand, to connect to the subsequently formed first power line.

[0248] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on the side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 69-1 may be disposed between the first circuit unit and the second circuit unit.

[0249] In an exemplary embodiment, the first connecting electrode 41 can be a strip shape extending along the second direction Y, and can be located between the fourth scan signal line 64 and the second power connection line 69. The first end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 41 is connected to the first electrode plate 71 through the tenth via V10. In an exemplary embodiment, the first connecting electrode 41 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) have the same potential. The first connecting electrode 41 can serve as the first node N1 of the pixel driving circuit.

[0250] In an exemplary embodiment, the second connection electrode 42 can be shaped like a broken line extending along the second direction Y, and can be located between the first reference signal line 91 and the first power connection line 68. The first end of the second connection electrode 42 is connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the fourth via V4, and the second end of the second connection electrode 42 is connected to the first electrode plate connection line 73-1 through the twelfth via V12. The third end between the first end and the second end is connected to the second electrode plate 72 through the eleventh via V11. In an exemplary embodiment, the second connection electrode 42 makes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second electrode plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) have the same potential. The second connection electrode 42 can serve as the fifth node N5 of the pixel driving circuit.

[0251] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through the third via V3. In an exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the fourth transistor T4 and may be configured to connect to the subsequently formed data signal line.

[0252] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as the first electrode of the fifth transistor T5 and may be configured to connect to the subsequently formed first power line.

[0253] In an exemplary embodiment, the fifth connection electrode 45 can be L-shaped and located between the fifth scan signal line 65 and the second initial signal line 82. The fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the sixth via V6. In an exemplary embodiment, the fifth connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is configured to be connected to the subsequently formed anode connection electrode.

[0254] In an exemplary embodiment, the sixth connection electrode 46 can be a strip shape extending along the first direction X of the main body, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer through the eighth via V8, and the second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 through the twenty-second via V22. In an exemplary embodiment, the sixth connection electrode 46 can serve as the first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8, and the second reference signal line 92 in the nth unit row can write the second reference signal into the first electrode of the eighth transistor T8 in the (n-1)th unit row.

[0255] In an exemplary embodiment, the seventh connecting electrode 47 can be a strip shape extending along the first direction X, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the seventh connecting electrode 47 is connected to the fifth gate electrode 25 through the seventeenth via V17, and the second end of the seventh connecting electrode 47 is connected to the first light-emitting connecting block 31-1 through the twentieth via V20. Since the first light-emitting connecting block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0256] In an exemplary embodiment, the eighth connecting electrode 48 can be a strip shape with its main body extending along the first direction X, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the eighth connecting electrode 48 is connected to the sixth gate electrode 26 through the eighteenth via V18, and the second end of the eighth connecting electrode 48 is connected to the second light-emitting connecting block 32-1 through the twenty-first via V21. Since the second light-emitting connecting block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0257] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 13 As shown.

[0258] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35.

[0259] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the third connecting electrode 43 on the substrate. The fifth insulating layer inside the 31st via V31 is removed, exposing the surface of the third connecting electrode 43. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the third connecting electrode 43 through the via.

[0260] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate. The fifth insulating layer within the 32nd via V32 is removed, exposing the surface of the fourth connecting electrode 44. The 32nd via V32 is configured to allow a subsequently formed first power line to be connected to the fourth connecting electrode 44 through the via.

[0261] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 45 onto the substrate. The fifth insulating layer within the 33rd via V33 is removed, exposing the surface of the fifth connecting electrode 45. The 33rd via V33 is configured to allow the subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 45 through the via.

[0262] In an exemplary embodiment, the orthographic projection of the 34th via V34 on the substrate is within the range of the orthographic projection of the reference connection block 91-1 of the first reference signal line 91 on the substrate. The fifth insulating layer in the 34th via V34 is removed, exposing the surface of the reference connection block 91-1. The 34th via V34 is configured to allow subsequently formed reference signal connection lines to be connected to the reference connection block 91-1 through the via.

[0263] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate. The fifth insulating layer in the 35th via V35 is removed, exposing the surface of the first power connection block 68-1. The 35th via V35 is configured to allow the subsequently formed first power line to be connected to the first power connection block 68-1 through the via.

[0264] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate lies within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 onto the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to allow a subsequently formed second power line to connect to the second power connection block 69-1 through this via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0265] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 14A and 14B As shown, Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0266] In an exemplary embodiment, the fourth conductive layer pattern of multiple circuit units in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54, and an anode connection electrode 55.

[0267] In an exemplary embodiment, the first power line 51, the data signal line 53, and the reference signal connection line 54 can be strip-shaped with the main body extending along the second direction Y. The first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0268] In an exemplary embodiment, the first power line 51 can be shaped as a broken line extending along the second direction Y of the main body. The first power line 51 is connected to the fourth connecting electrode 44 via the thirty-second via V32, and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connecting electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X of the main body and the first power line 51 extending along the second direction Y of the main body are interconnected. This forms a mesh structure on the display substrate, effectively reducing the resistance of the first power line 51 and decreasing the voltage drop of the first power signal. Furthermore, it effectively improves the uniformity of the first power signal in the display substrate, thereby enhancing display uniformity and improving display quality.

[0269] In an exemplary embodiment, a power shielding block 51-1 is provided on the side of the first power line 51 near the reference signal connection line 54. The first end of the power shielding block 51-1 is connected to the first power line 51, and the second end of the power shielding block 51-1 extends towards the reference signal connection line 54. The power shielding block 51-1 can be rectangular in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel driving circuit, the constant-voltage power shielding block 51-1 can effectively shield the first node N1 from the influence of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel driving circuit, thus improving the display effect.

[0270] In an exemplary embodiment, the first power line 51 and the power shield block 51-1 can be an integral structure that is interconnected.

[0271] In an exemplary embodiment, the orthographic projection of the power shield block 51-1 onto the substrate may include the orthographic projection of the first connection electrode 41 onto the substrate.

[0272] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate. Since the second connecting electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage of the first power line 51 can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 in the pixel driving circuit and improving the display effect.

[0273] In an exemplary embodiment, the first power line 51 can be designed with non-uniform width. The non-uniform width design of the first power line 51 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0274] In an exemplary embodiment, the data signal line 53 can be a straight line extending along the second direction Y, and the data signal line 53 is connected to the third connection electrode 43 through the thirty-first via V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0275] In an exemplary embodiment, the reference signal connection line 54 can be a straight line extending along the second direction Y of the main body. The reference signal connection line 54 is connected to the reference connection block 91-1 through the thirty-fourth via V34. Since the reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91 extending along the first direction X of the main body and the reference signal connection line 54 extending along the second direction Y of the main body are interconnected. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, thereby improving display uniformity and display quality.

[0276] In an exemplary embodiment, the anode connection electrode 55 can be rectangular in shape, and it is connected to the fifth connection electrode 45 through a thirty-third via V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a via, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In this exemplary embodiment, the anode connection electrode 55 is configured to connect to a subsequently formed anode, thus enabling the pixel driving circuit to drive the light-emitting device.

[0277] In an exemplary embodiment, the orthographic projection of the anode connection electrode 55 on the substrate at least partially overlaps with the orthographic projection of the repair line 33 on the substrate.

[0278] In an exemplary embodiment, the fourth conductive layer in at least one circuit unit may further include a second power line 52. The second power line 52 may be a straight line extending along the second direction Y of the main body portion, and the second power line 52 is connected to the second power connection block 69-1 through the thirty-sixth via V36. Since the second power connection block 69-1 is connected to the second power connection line 69, the interconnection between the second power connection line 69 extending along the first direction X of the main body portion and the second power line 52 extending along the second direction Y of the main body portion is realized, so that the second power line 52 and the second power connection line 69 form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 52 and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity and display quality. In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0279] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be disposed in each cell row, and the first power line 51 of the fourth conductive layer can be disposed in each cell column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0280] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be disposed in each cell row, and the reference signal connection line 54 of the fourth conductive layer can be disposed in each cell column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0281] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be disposed in each cell row, and the second power line 52 of the fourth conductive layer can be disposed every two cell columns. The multiple second power lines 52 are respectively connected to the multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0282] Subsequent fabrication processes may include forming a first planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connecting electrode onto the substrate. The first planarization layer within the anode vias is removed to expose the surface of the anode connecting electrode. The anode vias are configured to allow the subsequently formed anode to be connected to the anode connecting electrode through the vias.

[0283] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0284] Figure 15 This is a schematic diagram of another planar structure of a display substrate, illustrating the structure of the pixel driving circuits in three circuit units (first circuit unit, second circuit unit, and third circuit unit) of the display substrate. Figure 16 for Figure 15 A schematic diagram of the structure of the second and fifth scan signal lines. (See attached diagram.) Figure 15 and Figure 16 As shown, the main structure of the pixel driving circuit in this exemplary embodiment is basically the same as that in the previous embodiment. The difference is that the second scan connection line 62 and the fifth scan signal line 65 in this embodiment are double-layer scan signal lines.

[0285] In an exemplary embodiment, a first power line 51 extending along the second direction Y is interconnected with a first power connection line 68 extending along the first direction X to form a mesh structure for transmitting a first power signal. A second power line 52 extending along the second direction Y is interconnected with a second power connection line 69 extending along the first direction X to form a mesh structure for transmitting a second power signal. A reference signal connection line 54 extending along the second direction Y is interconnected with a first reference signal line 91 extending along the first direction X to form a mesh structure for transmitting a first reference signal.

[0286] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36, a third shielding electrode 38, and a fourth shielding electrode 39. The orthographic projection of the first shielding electrode 36 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 onto the substrate. The orthographic projection of the first shielding electrode 36 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 onto the substrate. The orthographic projection of the third shielding electrode 38 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 onto the substrate. The orthographic projection of the fourth shielding electrode 39 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 onto the substrate. Since the active layer structures of the fourth transistor T4 and the ninth transistor T9 are different in this embodiment, a second shielding electrode is not provided in this embodiment.

[0287] In an exemplary embodiment, the first scan signal line 61 may be disposed in the first conductive layer, the repair line 33 may be disposed in the second conductive layer, the first light emission signal line 31, the second light emission signal line 32, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 may be disposed in the third conductive layer, and the first power line 51, the second power line 52, the data signal line 53, the reference signal connection line 54 and the anode connection electrode 55 may be disposed in the fourth conductive layer.

[0288] In an exemplary embodiment, the driving circuit layer may further include a second scan connection line 62-1. The shape of the second scan connection line 62-1 may be a line shape in which the main body extends along the first direction X. The orthographic projection of the second scan connection line 62-1 on the substrate and the orthographic projection of the second scan signal line 62 on the substrate at least partially overlap. The second scan signal line 62 and the second scan connection line 62-1 are interconnected to form a double-layer structure of scan signal lines.

[0289] In an exemplary embodiment, the second scan signal line 62 and the second scan connection line 62-1 can be disposed in different conductive layers, and the second scan signal line 62 and the second scan connection line 62-1 can be connected by vias.

[0290] In an exemplary embodiment, the second scan connection line 62-1 may be disposed in the first conductive layer, and the second scan signal line 62 may be disposed in the third conductive layer.

[0291] In an exemplary embodiment, the driving circuit layer may further include a fifth scan connection line 65-1. The shape of the fifth scan connection line 65-1 may be a line shape in which the main body extends along the first direction X. The orthographic projection of the fifth scan connection line 65-1 on the substrate and the orthographic projection of the fifth scan signal line 65 on the substrate at least partially overlap. The fifth scan signal line 65 and the fifth scan connection line 65-1 are interconnected to form a double-layer structure of scan signal lines.

[0292] In an exemplary embodiment, the fifth scan signal line 65 and the fifth scan connection line 65-1 can be disposed in different conductive layers, and the fifth scan signal line 65 and the fifth scan connection line 65-1 can be connected by vias.

[0293] In an exemplary embodiment, the fifth scan connection line 65-1 may be disposed in the second conductive layer, and the fifth scan signal line 65 may be disposed in the third conductive layer.

[0294] In an exemplary embodiment, the substrate fabrication process of this embodiment may include the following operations.

[0295] (21) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 17 As shown.

[0296] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, the seventh active layer 17 of the seventh transistor T7, the eighth active layer 18 of the eighth transistor T8, and the ninth active layer 19 of the ninth transistor T9. The first active layer 11 to the third active layer 13 and the fifth active layer 15 to the eighth active layer 18 may be an integral structure interconnected with each other, and the fourth active layer 14 and the ninth active layer 19 may be an integral structure interconnected with each other.

[0297] In an exemplary embodiment, the structure and connection relationship of the first active layer 11 to the ninth active layer 19 are basically the same as those of the aforementioned embodiment. The difference is that the shape of the fourth active layer 14 can be "n" shaped, and the first region 14-1 of the fourth active layer can be located on the side of the channel region of the fourth active layer close to the third active layer 13. The shape of the ninth active layer 19 can be zigzag, and the first region 19-1 of the ninth active layer can be located on the side of the channel region of the ninth active layer away from the third active layer 13.

[0298] In an exemplary embodiment, the semiconductor layer of at least one circuit unit may include at least a first active pattern 10 and a second active pattern 20. The first active pattern 10 may include the active layer of the fourth transistor T4 and the active layer of the ninth transistor T9. The second active pattern 20 may include the active layers of the first transistor T1 to the third transistor T3 and the active layers of the fifth transistor T5 to the eighth transistor T8.

[0299] In an exemplary embodiment, in at least one circuit unit, a first active pattern 10 and a second active pattern 20 are spaced apart, that is, the active layer of the transistor in the first active pattern 10 and the active layer of the transistor in the second active pattern 20 are not connected.

[0300] In an exemplary embodiment, in at least one cell row, the semiconductor layers in adjacent circuit cells in the first direction X are spaced apart from each other, that is, the semiconductor layer of the first circuit cell in the nth cell row is not connected to the semiconductor layer of the second circuit cell in the nth cell row, and the semiconductor layer of the second circuit cell in the nth cell row is not connected to the semiconductor layer of the third circuit cell in the nth cell row.

[0301] In an exemplary embodiment, in at least one cell column, the semiconductor layers in adjacent circuit cells in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit cell in the (n-1)th cell row is not connected to the semiconductor layer of the first circuit cell in the nth cell row, and the semiconductor layer of the first circuit cell in the nth cell row is not connected to the semiconductor layer of the first circuit cell in the (n+1)th cell row.

[0302] (22) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 18A and Figure 18B As shown, Figure 18B for Figure 18A A schematic diagram of the first conductive layer.

[0303] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a first scan signal line 61, a second scan connection line 62-1, a first electrode plate 71 of a first storage capacitor, and a second electrode plate 72 of a second storage capacitor.

[0304] In an exemplary embodiment, the structure and connection relationship of the first gate electrode 21, the second gate electrode 22, the fifth gate electrode 25, the sixth gate electrode 26, the first scan signal line 61, and the first plate 71 of the first storage capacitor are substantially the same as those in the foregoing embodiments.

[0305] In an exemplary embodiment, the shape of the fourth gate electrode 24 can be a strip shape extending along the first direction X, and it can be located between the second scan connection line 62-1 and the second electrode plate 72. The region where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4 in the dual-gate structure.

[0306] In an exemplary embodiment, the second scan connection line 62-1 can be a line extending along the first direction X, located on the side opposite to the second direction Y of the second electrode plate 72. A gate block 62-10 is disposed on the side of the second scan connection line 62-1 near the second electrode plate 72. The first end of the gate block 62-10 is connected to the second scan connection line 62-1, and the second end of the gate block 62-10 extends toward the second electrode plate 72. The region where the second scan connection line 62-1 and the gate block 62-10 overlap with the ninth active layer can serve as the gate electrode of the ninth transistor T9 in a dual-gate structure. In an exemplary embodiment, the second scan connection line 62-1 can serve as the lower signal line of the second scan signal line in a dual-layer structure.

[0307] In an exemplary embodiment, the second electrode 72 of the second storage capacitor can be rectangular in shape, with chamfered corners, and can be located between the first electrode 71 and the fourth gate electrode 24. The orthographic projection of the second electrode 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In an exemplary embodiment, the second electrode 72 can serve as the lower electrode of the second storage capacitor.

[0308] In an exemplary embodiment, a first groove K1 is provided on the side of the second electrode plate 72 near the first electrode plate 71, and the first groove K1 is configured to accommodate the first electrode plate connecting line 73-1.

[0309] Unlike the previous embodiments, this embodiment has a second scan connection line 62-1 in the first conductive layer, and therefore does not have a ninth gate electrode.

[0310] (23) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 19A and Figure 19B As shown, Figure 19B for Figure 19A A schematic diagram of the second conductive layer.

[0311] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a repair line 33, a first shielding electrode 36, a third shielding electrode 38, a fourth shielding electrode 39, a fifth scan connection line 65-1, a third electrode plate 73 of a first storage capacitor, and a fourth electrode plate 74 of a second storage capacitor.

[0312] In an exemplary embodiment, the fifth scan connection line 65-1 and the repair line 33 can be the shape of a line extending along the first direction X of the main body portion. The fifth scan connection line 65-1 can be located between the first gate electrode 21 and the fifth gate electrode 25, and the repair line 33 can be located between the fifth gate electrode 25 and the first scan signal line 61.

[0313] In an exemplary embodiment, the fifth scan connection line 65-1 may include a straight segment and a bent segment. The straight segment may be a straight line extending along the first direction X, and the bent segment protrudes towards the repair line 33 to avoid the second gate electrode 22, so that the orthographic projection of the fifth scan connection line 65-1 on the substrate does not overlap with the orthographic projection of the second gate electrode 22 on the substrate. In an exemplary embodiment, the fifth scan connection line 65-1 may serve as the lower signal line of a double-layered fifth scan signal line structure.

[0314] In an exemplary embodiment, the location and structure of the repair line 33 are substantially the same as in the foregoing embodiments.

[0315] In an exemplary embodiment, the outline shape of the third plate 73 of the first storage capacitor can be substantially similar to the shape of the first plate 71. The orthographic projection of the third plate 73 on the substrate at least partially overlaps with the orthographic projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor. The first plate 71 and the third plate 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0316] In an exemplary embodiment, the outline shape of the fourth electrode 74 of the second storage capacitor can be substantially similar to the shape of the second electrode 72. The orthographic projection of the fourth electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second electrode 72 on the substrate. The fourth electrode 74 can serve as the upper electrode of the second storage capacitor. The second electrode 72 and the fourth electrode 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0317] In an exemplary embodiment, a first electrode connecting line 73-1 is provided on the side of the third electrode plate 73 near the fourth electrode plate 74. The first end of the first electrode connecting line 73-1 is connected to the third electrode plate 73, and the second end of the first electrode connecting line 73-1 extends toward the fourth electrode plate 74 and is located in the first groove K1 formed by the fourth electrode plate 74. The position, connection structure and function of the first electrode connecting line 73-1 are basically the same as those in the aforementioned embodiments.

[0318] In an exemplary embodiment, a second electrode connecting line 74-1 may be provided on one side of the fourth electrode plate 74 in the first direction X or on the side opposite to the first direction X. The position, connection structure and function of the second electrode connecting line 74-1 are basically the same as those in the aforementioned embodiments.

[0319] In an exemplary embodiment, a first opening 75 is provided on the third electrode plate 73 of each circuit unit, and a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit. The positions, connection structures, and functions of the first opening 75 and the second opening 76 are substantially the same as those in the aforementioned embodiments.

[0320] In an exemplary embodiment, the first shielding electrode 36 may be in the shape of a "T" and may be located near the fifth scanning connection line 65-1 on the fourth electrode plate 74. The first shielding electrode 36 may be disposed in each circuit unit. The "T"-shaped first shielding electrode 36 may include a first extension section 36-1 and a first shielding section 36-2. The position, connection structure and function of the first extension section 36-1 and the first shielding section 36-2 are basically the same as those in the foregoing embodiments.

[0321] In an exemplary embodiment, the third shielding electrode 38 may be L-shaped and located on the side of the fourth electrode plate 74 near the second scan connection line 62-1. The third shielding electrode 38 may be disposed in each circuit unit. The third shielding electrode 38 may include a third extension 38-1 and a third shielding section 38-2. The first end of the third extension 38-1 is connected to the fourth electrode plate 74, and the third end of the third extension 38-1 extends toward the second scan connection line 62-1 and connects to the third shielding section 38-2. The third shielding section 38-2 may be a strip shape extending along the first direction X. The orthographic projection of the third shielding section 38-2 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit on the substrate. The third shielding electrode 38 is configured to shield the influence of data voltage jumps on the fourth transistor T4, preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0322] In an exemplary embodiment, the fourth shielding electrode 39 can be a strip extending along the second direction Y, and can be located on the side of the fourth electrode plate 74 near the second scan connection line 62-1. The fourth shielding electrode 39 can be disposed in each circuit unit. The first end of the fourth shielding electrode 39 is connected to the fourth electrode plate 74, and the second end of the fourth shielding electrode 39 extends toward the second scan connection line 62-1. The orthographic projection of the second end of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the influence of data voltage jumps on the ninth transistor T9, preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0323] In an exemplary embodiment, the fourth electrode 74, the first shielding electrode 36, the third shielding electrode 38, and the fourth shielding electrode 39 can be an integral structure that is interconnected.

[0324] Unlike the previous embodiments, this embodiment has a second scanning connection line 62-1 in the second conductive layer, but does not have a horizontal second reference signal line, a first light-emitting signal line, or a second light-emitting signal line.

[0325] (24) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 20 As shown.

[0326] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a twenty-third via V23, and a twenty-fourth via V24.

[0327] In an exemplary embodiment, the positions, connection structures, and functions of the first via V1 to the eighteenth via V18 are substantially the same as in the aforementioned embodiments. The difference is that the eighth via V8 is configured to allow the subsequently formed second reference signal line to be connected to the first region of the eighth active layer through the via, the seventeenth via V17 is configured to allow the subsequently formed first light-emitting signal line to be connected to the fifth gate electrode 25 through the via, and the eighteenth via V18 is configured to allow the subsequently formed second light-emitting signal line to be connected to the sixth gate electrode 26 through the via.

[0328] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the second scan connection line 62-1 on the substrate. The fourth and third insulating layers within the 23rd via V23 are etched away, exposing the surface of the second scan connection line 62-1. The 23rd via V23 is configured to allow the subsequently formed second scan signal line to be connected to the second scan connection line 62-1 through the via.

[0329] In an exemplary embodiment, the orthographic projection of the 24th via V24 on the substrate is within the range of the orthographic projection of the fifth scan connection line 65-1 on the substrate. The fourth insulating layer within the 24th via V24 is etched away, exposing the surface of the fifth scan connection line 65-1. The 24th via V24 is configured to allow the subsequently formed fifth scan signal line to be connected to the fifth scan connection line 65-1 through the via.

[0330] (25) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 21A and Figure 21B As shown, Figure 21B for Figure 21A A schematic diagram of the third conductive layer.

[0331] In an exemplary embodiment, the third conductive layer pattern of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a first light-emitting signal line 31, a second light-emitting signal line 32, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first power connection line 68, a second power connection line 69, a first initial signal line 81, a second initial signal line 82, a first reference signal line 91, and a second reference signal line 92.

[0332] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91, and the second reference signal line 92 can be line shapes that extend along the first direction X of the main body portion. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 can be located on the side opposite to the second direction Y of the fourth electrode plate 74. The first light emission signal line 31, the second light emission signal line 32, the fourth scan signal line 64, the fifth scan signal line 65, the first initial signal line 81, the second initial signal line 82, and the second reference signal line 92 can be located on the side of the second direction Y of the third electrode plate 73. The first power connection line 68 can be located in the area where the fourth electrode plate 74 is located. The second power connection line 69 can be located in the area where the third electrode plate 73 is located. The second power connection line 69 can be located on the side of the second direction Y of the first power connection line 68.

[0333] In an exemplary embodiment, the third scan signal line 63 may be located on the side opposite to the second direction Y of the fourth electrode plate 74, the second scan signal line 62 may be located on the side opposite to the second direction Y of the third scan signal line 63, and the first reference signal line 91 may be located on the side opposite to the second direction Y of the second scan signal line 62.

[0334] In an exemplary embodiment, the fourth scan signal line 64 may be located on one side of the third electrode plate 73 in the second direction Y, the first initial signal line 81 may be located on one side of the fourth scan signal line 64 in the second direction Y, the fifth scan signal line 65 may be located on one side of the first initial signal line 81 in the second direction Y, the first light emission signal line 31 may be located on one side of the fifth scan signal line 65 in the second direction Y, the second light emission signal line 32 may be located on one side of the first light emission signal line 31 in the second direction Y, the second reference signal line 92 may be located on one side of the second light emission signal line 32 in the second direction Y, and the second initial signal line 82 may be located on one side of the second reference signal line 92 in the second direction Y.

[0335] In an exemplary embodiment, the first power connection line 68 may be located on the side of the fourth electrode plate 74 close to the third electrode plate 73. The orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate. The first power connection line 68 is configured to connect to the first power line subsequently formed, forming a high-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0336] In an exemplary embodiment, the second power connection line 69 may be located on the side of the third electrode plate 73 near the fourth electrode plate 74. The orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate. The second power connection line 69 is configured to connect to a second power line subsequently formed, forming a low-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0337] In an exemplary embodiment, the shape of the first light-emitting signal line 31 can be a straight line extending along the first direction X of the main body. The first light-emitting signal line 31 is connected to the fifth gate electrode 25 of each circuit unit through the seventeenth via V17, thus realizing the connection of the first light-emitting signal line 31 to the fifth gate electrode 25 of the fifth transistor T5. The first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0338] In an exemplary embodiment, the shape of the second light-emitting signal line 32 can be a broken line extending along the first direction X of the main body. The second light-emitting signal line 32 is connected to the sixth gate electrode 26 of each circuit unit through the eighteenth via V18, thus realizing the connection of the second light-emitting signal line 32 to the sixth gate electrode 26 of the sixth transistor T6. The second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0339] In an exemplary embodiment, the second scan signal line 62 can be a zigzag line extending along the first direction X. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the second scan connection line 62-1 on the substrate, and the second scan signal line 62 is connected to the second scan connection line 62-1 through the twenty-third via V23. The second scan signal line 62 can serve as the upper signal line of a double-layer structure. The second scan connection line 62-1 located in the first conductive layer and the second scan signal line 62 located in the third conductive layer constitute a double-layer structure of the second scan signal line, thus realizing the connection of the second scan signal to the gate electrode of the ninth transistor T9. The second scan signal line can control the conduction and disconnection of the ninth transistor T9.

[0340] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line extending along the first direction X of the main body. The third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thus realizing the connection of the third scan signal line 63 to the fourth gate electrode 24 of the fourth transistor T4. The third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0341] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line extending along the first direction X of the main body. The fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thus realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1. The fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0342] In an exemplary embodiment, the fifth scan signal line 65 can be a straight line extending along the first direction X. The orthographic projection of the fifth scan signal line 65 on the substrate at least partially overlaps with the orthographic projection of the fifth scan connection line 65-1 on the substrate. The fifth scan signal line 65 is connected to the second gate electrode 22 through the fifteenth via V15 on one hand, and to the fifth scan connection line 65-1 through the twenty-fourth via V24 on the other hand. The fifth scan signal line 65 can serve as the upper signal line of a double-layered fifth scan signal line. The fifth scan connection line 65-1 located in the second conductive layer and the fifth scan signal line 65 located in the third conductive layer constitute a double-layered fifth scan signal line, thus realizing the connection of the fifth scan signal to the second gate electrode 22 of the second transistor T2. The second scan signal line can control the conduction and disconnection of the second transistor T2.

[0343] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can extend to the frame area and be connected to the same gate drive circuit to achieve the same scan signal output, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0344] This disclosure, by setting a second and fifth scan signal line with a double-layer structure, can effectively reduce the resistance of the signal line, effectively reduce the voltage drop of the scan signal, improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0345] In an exemplary embodiment, the first power connection line 68 can be a straight line extending along the first direction X. The first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thus realizing the connection of the first power connection line 68 to the fourth electrode plate 74. Since the first power connection line 68 is connected to the subsequently formed first power line, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.

[0346] In an exemplary embodiment, a first power connection block 68-1 is provided on the side of the first power connection line 68 away from the second power connection line 69. The first end of the first power connection block 68-1 is connected to the first power connection line 68, and the second end of the first power connection block 68-1 extends away from the second power connection line 69. In this exemplary embodiment, the first power connection block 68-1 is configured, on the one hand, to connect to the fourth electrode plate 74 through the thirteenth via V13, and on the other hand, to connect to the subsequently formed first power line.

[0347] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on the side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 69-1 may be disposed between the first circuit unit and the second circuit unit.

[0348] In an exemplary embodiment, the shape of the first initial signal line 81 can be a straight line extending along the first direction X of the main body. The first initial signal line 81 is connected to the first region of the first active layer in each circuit unit through the first via V1, thereby realizing the connection of the first initial signal line 81 to the first pole of the first transistor T1. The first initial signal line 81 can write the first initial signal into the first pole of the first transistor T1.

[0349] In an exemplary embodiment, the shape of the second initial signal line 82 can be a straight line extending along the first direction X of the main body. The second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing the connection of the second initial signal line 82 to the first pole of the seventh transistor T7. The second initial signal line 82 can write the second initial signal to the first pole of the seventh transistor T7.

[0350] In an exemplary embodiment, the shape of the first reference signal line 91 can be a straight line extending along the first direction X of the main body. The first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing the connection of the first reference signal line 91 to the first pole of the ninth transistor T9. The first reference signal line 91 can write the first reference signal into the first pole of the ninth transistor T9.

[0351] In an exemplary embodiment, a reference connection block 91-1 is provided on the side of the first reference signal line 91 near the second scan signal line 62. The first end of the reference connection block 91-1 is connected to the first reference signal line 91, and the second end of the reference connection block 91-1 extends toward the second scan signal line 62. The reference connection block 91-1 is configured to be connected to a reference signal connection line that is subsequently formed.

[0352] In an exemplary embodiment, the shape of the second reference signal line 92 can be a straight line extending along the first direction X of the main body. The second reference signal line 92 is connected to the first region of the eighth active layer of each circuit unit through the eighth via V8, thereby realizing the connection of the second reference signal line 92 to the first pole of the eighth transistor T8. The second reference signal line 92 in the nth unit row can write the second reference signal into the first pole of the eighth transistor T8 in the nth unit row.

[0353] In an exemplary embodiment, the first connecting electrode 41 can be a strip shape in which the main body extends along the second direction Y, and can be located between the fourth scan signal line 64 and the second power connection line 69. The first end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 41 is connected to the first electrode plate 71 through the tenth via V10. In an exemplary embodiment, the first connecting electrode 41 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) have the same potential. The first connecting electrode 41 can serve as the first node N1 in the pixel driving circuit.

[0354] In an exemplary embodiment, the second connection electrode 42 can be shaped like a broken line extending along the second direction Y, and can be located between the third scan signal line 63 and the first power connection line 68. The first end of the second connection electrode 42 is connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the fourth via V4, and the second end of the second connection electrode 42 is connected to the first electrode plate connection line 73-1 through the twelfth via V12. The third end between the first end and the second end is connected to the second electrode plate 72 through the eleventh via V11. In an exemplary embodiment, the second connection electrode 42 makes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second electrode plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) have the same potential. The second connection electrode 42 can serve as the fifth node N5 of the pixel driving circuit.

[0355] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the third scan signal line 63 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through the third via V3. In an exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the fourth transistor T4 and may be configured to connect to the subsequently formed data signal line.

[0356] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the first light-emitting signal line 31 and the second light-emitting signal line 32. The fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as the first electrode of the fifth transistor T5 and may be configured to connect to the subsequently formed first power line.

[0357] In an exemplary embodiment, the fifth connection electrode 45 can be L-shaped and located between the second light-emitting signal line 32 and the second reference signal line 92. The fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the sixth via V6. In an exemplary embodiment, the fifth connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is configured to be connected to the subsequently formed anode connection electrode.

[0358] Unlike the previous embodiments, this embodiment places the first light-emitting signal line 31, the second light-emitting signal line 32, and the second reference signal line 92 in the third conductive layer. On one hand, the second reference signal line 92 in the third conductive layer is positioned between the first scan signal line 61 and the second initial signal line 82, allowing the second reference signal line 92 to be routed near the eighth transistor T8, simplifying the connection structure. On the other hand, the first reference signal line 91 is positioned on the side of the second scan signal line 62 away from the second storage capacitor, and the second scan signal line 62 is positioned on the side of the third scan signal line 63 away from the second storage capacitor; that is, the second scan signal line 62 is positioned above the third scan signal line 63, and the first reference signal line 91 is positioned above the second scan signal line 62, making the routing layout more rational.

[0359] (26) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 22 As shown.

[0360] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35.

[0361] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the third connecting electrode 43 on the substrate. The fifth insulating layer inside the 31st via V31 is removed, exposing the surface of the third connecting electrode 43. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the third connecting electrode 43 through the via.

[0362] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate. The fifth insulating layer within the 32nd via V32 is removed, exposing the surface of the fourth connecting electrode 44. The 32nd via V32 is configured to allow a subsequently formed first power line to be connected to the fourth connecting electrode 44 through the via.

[0363] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 45 onto the substrate. The fifth insulating layer within the 33rd via V33 is removed, exposing the surface of the fifth connecting electrode 45. The 33rd via V33 is configured to allow the subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 45 through the via.

[0364] In an exemplary embodiment, the orthographic projection of the 34th via V34 on the substrate is within the range of the orthographic projection of the reference connection block 91-1 of the first reference signal line 91 on the substrate. The fifth insulating layer in the 34th via V34 is removed, exposing the surface of the reference connection block 91-1. The 34th via V34 is configured to allow subsequently formed reference signal connection lines to be connected to the reference connection block 91-1 through the via.

[0365] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate. The fifth insulating layer in the 35th via V35 is removed, exposing the surface of the first power connection block 68-1. The 35th via V35 is configured to allow the subsequently formed first power line to be connected to the first power connection block 68-1 through the via.

[0366] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate lies within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 onto the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to allow a subsequently formed second power line to connect to the second power connection block 69-1 through this via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0367] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 23A and Figure 23B As shown, Figure 23B for Figure 23A A schematic diagram of the fourth conductive layer.

[0368] In an exemplary embodiment, the fourth conductive layer pattern of multiple circuit units in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54, and an anode connection electrode 55.

[0369] In an exemplary embodiment, the first power line 51, the data signal line 53, and the reference signal connection line 54 can be strip-shaped with the main body extending along the second direction Y. The first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0370] In an exemplary embodiment, the first power line 51 can be shaped as a broken line extending along the second direction Y of the main body. The first power line 51 is connected to the fourth connecting electrode 44 via the thirty-second via V32, and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connecting electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X of the main body and the first power line 51 extending along the second direction Y of the main body are interconnected. This forms a mesh structure on the display substrate, effectively reducing the resistance of the first power line 51 and decreasing the voltage drop of the first power signal. Furthermore, it effectively improves the uniformity of the first power signal in the display substrate, thereby enhancing display uniformity and improving display quality.

[0371] In an exemplary embodiment, a power shielding block 51-1 is provided on the side of the first power line 51 near the reference signal connection line 54. The first end of the power shielding block 51-1 is connected to the first power line 51, and the second end of the power shielding block 51-1 extends towards the reference signal connection line 54. The power shielding block 51-1 can be rectangular in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel driving circuit, the constant-voltage power shielding block 51-1 can effectively shield the first node N1 from the influence of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel driving circuit, thus improving the display effect.

[0372] In an exemplary embodiment, the orthographic projection of the power shield block 51-1 onto the substrate may include the orthographic projection of the first connection electrode 41 onto the substrate.

[0373] In an exemplary embodiment, a first power connection block 51-2 is provided on the side of the first power line 51 near the reference signal connection line 54. The first end of the first power connection block 51-2 is connected to the first power line 51, and the second end of the first power connection block 51-2 extends toward the reference signal connection line 54 and is connected to the first power connection block 68-1 through the thirty-fifth via V35.

[0374] In an exemplary embodiment, a second power connection block 51-3 is provided on the side of the first power line 51 near the data signal line 53. The first end of the second power connection block 51-3 is connected to the first power line 51, and the second end of the second power connection block 51-3 extends toward the data signal line 53 and is connected to the fourth connection electrode 44 through the thirty-second via V32.

[0375] In an exemplary embodiment, the first power line 51, the power shielding block 51-1, the first power connection block 51-2, and the second power connection block 51-3 can be an integral structure that is interconnected.

[0376] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate. Since the second connecting electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage of the first power line 51 can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 in the pixel driving circuit and improving the display effect.

[0377] In an exemplary embodiment, the first power line 51 can be designed with non-uniform width. The non-uniform width design of the first power line 51 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0378] In an exemplary embodiment, the data signal line 53 can be a straight line extending along the second direction Y, and the data signal line 53 is connected to the third connection electrode 43 through the thirty-first via V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0379] In an exemplary embodiment, the reference signal connection line 54 can be a straight line extending along the second direction Y of the main body. The reference signal connection line 54 is connected to the reference connection block 91-1 through the thirty-fourth via V34. Since the reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91 extending along the first direction X of the main body and the reference signal connection line 54 extending along the second direction Y of the main body are interconnected. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, thereby improving display uniformity and display quality.

[0380] In an exemplary embodiment, the anode connection electrode 55 can be rectangular in shape, and it is connected to the fifth connection electrode 45 through a thirty-third via V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a via, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In this exemplary embodiment, the anode connection electrode 55 is configured to connect to a subsequently formed anode, thus enabling the pixel driving circuit to drive the light-emitting device.

[0381] In an exemplary embodiment, at least one circuit unit may further include a second power line 52. The second power line 52 may be a straight line extending along the second direction Y of the main body portion, and the second power line 52 is connected to the second power connection block 69-1 through the thirty-sixth via V36. Since the second power connection block 69-1 is connected to the second power connection line 69, the interconnection between the second power connection line 69 extending along the first direction X of the main body portion and the second power line 52 extending along the second direction Y of the main body portion is realized, so that the second power line 52 and the second power connection line 69 form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 52 and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity and display quality. In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0382] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be disposed in each cell row, and the first power line 51 of the fourth conductive layer can be disposed in each cell column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0383] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be disposed in each cell row, and the reference signal connection line 54 of the fourth conductive layer can be disposed in each cell column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0384] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be disposed in each cell row, and the second power line 52 of the fourth conductive layer can be disposed every two cell columns. The multiple second power lines 52 are respectively connected to the multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0385] Subsequent fabrication processes may include forming a first planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connecting electrode onto the substrate. The first planarization layer within the anode vias is removed to expose the surface of the anode connecting electrode. The anode vias are configured to allow the subsequently formed anode to be connected to the anode connecting electrode through the vias.

[0386] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0387] In an exemplary embodiment, in a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a fifth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first reference signal line, a second reference signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer sequentially stacked on the substrate.

[0388] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0389] In an exemplary embodiment, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, the second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first planarization layer can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0390] In a display substrate, semiconductor layers in adjacent circuit cells within a cell row are interconnected. For example, the first regions of the ninth active layers of multiple circuit cells in a cell row are interconnected via a first active connection line, and the first regions of the seventh active layers of multiple circuit cells in a cell row are interconnected via a second active connection line. The shapes of the first and second active connection lines can be lines extending along a first direction X. Research shows that the first and second active connection lines affect the aperture (AA) structure of the display area, leading to hole mura (hole ripple) display defects around the apertures. Furthermore, this display substrate also suffers from large voltage drops for the first power signal, the second power signal, and the reference signal.

[0391] This embodiment of the present disclosure divides the semiconductor layer of a circuit unit into a first active pattern and a second active pattern. The active layers of transistors in the first active pattern and the active layers of transistors in the second active pattern are not connected, and the semiconductor layers in adjacent circuit units in the unit row and unit column are isolated from each other. The active connection line structure is eliminated, thereby avoiding the semiconductor layer from affecting the opening structure of the display area, minimizing the display defects caused by hole ripples, and improving the display quality and display performance.

[0392] This embodiment of the present disclosure provides a first power connection line extending along a first direction X and a first power line extending along a second direction Y in the main body portion, with the first power line and the first power connection line interconnected. This forms a mesh structure on the display substrate that transmits the first power signal. This not only effectively reduces the resistance of the first power line and decreases the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0393] This embodiment of the disclosure provides a second power connection line extending along the first direction X and a second power line extending along the second direction Y of the main body, with the second power line and the second power connection line interconnected. This forms a mesh structure on the display substrate that transmits the second power signal. This not only effectively reduces the resistance of the second power signal line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0394] This embodiment of the present disclosure provides a first reference signal line extending along a first direction X and a reference signal connection line extending along a second direction Y in the main body portion, with the first reference signal line and the reference signal connection line interconnected. This forms a mesh structure on the display substrate to transmit the first reference signal, which not only effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0395] This embodiment of the present disclosure, by setting a first shielding electrode, a second shielding electrode, a third shielding electrode, and a fourth shielding electrode, can shield the effects of data voltage jumps on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the fifth node N5, thereby preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0396] The embodiments disclosed herein can effectively increase the total capacity of the second storage capacitor by setting an additional capacitor to form the second storage capacitor with the second shielding electrode and the semiconductor layer, thereby improving the working performance of the pixel driving circuit and enhancing the display effect.

[0397] This embodiment of the invention, by setting a second and fifth scan signal line with a double-layer structure, can effectively reduce the resistance of the signal line, effectively reduce the voltage drop of the scan signal, improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0398] This embodiment of the present disclosure shields the first node N1 and the fifth node N5 by setting a first power line and a power shielding block, which can effectively prevent other signals from affecting the potential of the first node N1 and the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0399] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0400] The structure and its preparation process described above are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be modified or reduced according to actual needs. For example, Figure 5 The second and fifth scan signal lines in the display substrate shown can adopt a double-layer structure. Alternatively, one or more of the first, third, and fourth scan signal lines in the display substrate can adopt a double-layer structure. Furthermore, the reference signal connection lines in the fourth conductive layer can be connected to the second reference signal lines, so that the second reference signal lines and the reference signal connection lines form a mesh-like structure on the display substrate for transmitting the second reference signal. Alternatively, the second power line in the fourth conductive layer can be modified into an initial connection line, which can be connected to either the first or second initial signal line, so that the first initial signal line and the initial connection line form a mesh-like structure on the display substrate for transmitting the first initial signal, or the second initial signal line and the initial connection line form a mesh-like structure on the display substrate for transmitting the second initial signal; this disclosure does not impose any limitations on this.

[0401] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0402] This disclosure also provides a method for preparing a display substrate to prepare the display substrate provided in the above embodiments.

[0403] In an exemplary embodiment, the display substrate includes multiple circuit units forming multiple cell rows and multiple cell columns, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least multiple transistors; the method for fabricating the display substrate may include:

[0404] A semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on a substrate; the semiconductor layer includes at least a plurality of active layers of transistors, and the semiconductor layer includes at least a first active pattern and a second active pattern, the first active pattern including an active layer of at least one transistor, and the second active pattern including an active layer of at least one transistor; in at least one circuit cell, the first active pattern and the second active pattern are spaced apart, the active layers of the plurality of transistors in the circuit cell are spaced apart from the active layers of the plurality of transistors in the adjacent circuit cell in the cell row direction, and the active layers of the plurality of transistors in the circuit cell are spaced apart from the active layers of the plurality of transistors in the adjacent circuit cell in the cell column direction.

[0405] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0406] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor and a seventh transistor as initialization transistors, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors; on a plane perpendicular to the display substrate, at least one circuit unit comprising a semiconductor layer disposed on a substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate, the semiconductor layer comprising at least an active layer of the first transistor to the ninth transistor, the semiconductor layer comprising at least a first active pattern and a second active pattern, the first active pattern being... An active pattern includes the active layer of the fourth transistor and the active layer of the ninth transistor, the active layers of the fourth transistor and the ninth transistor being an integral structure interconnected. A second active pattern includes the active layers of the first transistor to the third transistor and the active layers of the fifth transistor to the eighth transistor, the active layers of the first transistor to the third transistor and the fifth transistor to the eighth transistor being an integral structure interconnected. In at least one circuit unit, the first active pattern and the second active pattern are spaced apart. The active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the row direction, and the active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the column direction.

2. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a first storage capacitor and a second storage capacitor; the first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate at least partially overlap. The second storage capacitor includes at least a second plate and a fourth plate, wherein the orthographic projection of the second plate on the substrate and the orthographic projection of the fourth plate on the substrate at least partially overlap; the first plate serves as the gate electrode of the third transistor, the second plate is connected to the third plate, and the fourth plate is connected to the first power line.

3. The display substrate according to claim 2, wherein, The plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially along a direction away from the substrate; the first electrode plate and the second electrode plate are disposed in the first conductive layer, the third electrode plate and the fourth electrode plate are disposed in the second conductive layer, the first power line is disposed in the fourth conductive layer, and the second electrode plate is connected to the third electrode plate through a connecting electrode disposed in the third conductive layer.

4. The display substrate according to claim 3, wherein, The third electrode plate is provided with a first electrode plate connecting line extending toward the fourth electrode plate. The fourth electrode plate is provided with a first groove recessed away from the third electrode plate. The first electrode plate connecting line is disposed in the first groove. The end of the first electrode plate connecting line away from the third electrode plate is connected to the connecting electrode through a through hole.

5. The display substrate according to claim 3, wherein, The pixel driving circuit further includes an additional capacitor, the lower electrode of which is disposed in the semiconductor layer, and the upper electrode of which is disposed in the second conductive layer. The orthographic projection of the upper electrode on the substrate and the orthographic projection of the lower electrode on the substrate at least partially overlap. The lower electrode is connected to the second electrode, and the upper electrode is connected to the fourth electrode.

6. The display substrate according to claim 5, wherein, The lower electrode plate includes the second region of the active layer of the fourth transistor. The second electrode plate is connected to the second region of the active layer of the fourth transistor through a connection electrode disposed in the third conductive layer. The upper electrode plate and the fourth electrode plate are an integral structure that is interconnected.

7. The display substrate according to claim 1, wherein, The gate electrode of the first transistor is connected to the fourth scan signal line, the gate electrode of the second transistor is connected to the fifth scan signal line, the gate electrode of the fourth transistor is connected to the third scan signal line, the gate electrodes of the fifth transistor and the sixth transistor are connected to the light emission signal line, the gate electrodes of the seventh transistor and the eighth transistor are connected to the first scan signal line, and the gate electrode of the ninth transistor is connected to the second scan signal line. The second scan signal line and the fifth scan signal line output the same scan signal.

8. The display substrate according to claim 7, wherein, The display substrate further includes a second scan connection line. The second scan signal line and the second scan connection line are disposed in different conductive layers. The orthographic projection of the second scan signal line on the substrate and the orthographic projection of the second scan connection line on the substrate at least partially overlap. The second scan signal line is connected to the second scan connection line through a via, forming a double-layer structure of scan signal lines.

9. The display substrate according to claim 8, wherein, The plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially along a direction away from the substrate; the second scan connection line is disposed in the first conductive layer, and the second scan signal line is disposed in the third conductive layer.

10. The display substrate according to claim 7, wherein, The display substrate also includes a fifth scan connection line. The fifth scan signal line and the fifth scan connection line are disposed on different conductive layers. The orthographic projection of the fifth scan signal line on the substrate and the orthographic projection of the fifth scan connection line on the substrate at least partially overlap. The fifth scan signal line is connected to the fifth scan connection line through a via, forming a double-layer structure of scan signal lines.

11. The display substrate according to claim 10, wherein, The plurality of conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially along a direction away from the substrate; the fifth scan connection line is disposed in the second conductive layer, and the fifth scan signal line is disposed in the third conductive layer.

12. The display substrate according to claim 1, wherein, At least one circuit unit further includes a first shielding electrode, the orthographic projection of the first shielding electrode on the substrate at least partially overlapping the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlapping the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor on the substrate.

13. The display substrate according to claim 1, wherein, At least one circuit unit further includes a second shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projections of the second pole of the fourth transistor and the second pole of the ninth transistor on the substrate.

14. The display substrate according to claim 1, wherein, At least one circuit unit further includes a third shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor on the substrate.

15. The display substrate according to claim 1, wherein, At least one circuit unit further includes a fourth shielding electrode, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor on the substrate.

16. The display substrate according to any one of claims 1 to 15, wherein, The display substrate further includes at least one first power connection line extending along the cell row direction and at least one first power line extending along the cell column direction; the first power line and the first power connection line are disposed in different conductive layers, and the first power line and the first power connection line are connected through vias to form a mesh structure for transmitting the first power signal.

17. The display substrate according to any one of claims 1 to 15, wherein, The display substrate further includes at least one second power connection line extending along the cell row direction and at least one second power line extending along the cell column direction; the second power line and the second power connection line are disposed in different conductive layers, and the second power line and the second power connection line are connected through vias to form a mesh structure for transmitting the second power signal.

18. The display substrate according to any one of claims 1 to 15, wherein, The display substrate further includes at least one reference signal connection line extending along the cell row direction and at least one reference signal line extending along the cell column direction; the reference signal line and the reference signal connection line are disposed in different conductive layers, and the reference signal connection line and the reference signal line are connected through vias to form a mesh structure for transmitting reference signals.

19. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 18.

20. A method for fabricating a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor and a seventh transistor as initialization transistors, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light-emitting transistors, and an eighth transistor and a ninth transistor as reference transistors; the fabrication method comprising: A semiconductor layer and a plurality of conductive layers are formed on a substrate. The semiconductor layer includes at least the active layers of the first transistor to the ninth transistor, and at least the first active pattern and the second active pattern. The first active pattern includes the active layers of the fourth transistor and the ninth transistor, which are interconnected as a single structure. The second active pattern includes the active layers of the first transistor to the third transistor and the active layers of the fifth transistor to the eighth transistor, which are interconnected as a single structure. In at least one circuit unit, the first active pattern and the second active pattern are spaced apart. The active layers of multiple transistors in the circuit unit are spaced apart from the active layers of multiple transistors in adjacent circuit units in the row direction and from the active layers of multiple transistors in adjacent circuit units in the column direction.

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