Battery management system

Abstract

A relay for a battery management system (BMS) is described. The relay includes a bus connection point, a stack connection point, a primary solid state relay (SSR) electrically connected to the bus connection point and the stack connection point, and a secondary SSR electrically connected to the bus connection point and the stack connection point. The primary SSR includes a first measurement point usable by the BMS to determine a first SSR state. The secondary SSR is connected in parallel with the primary SSR and includes a second measurement point usable by the BMS to determine a second SSR state.

Description

Technical Field

[0001] The present disclosure relates to energy storage units such as batteries, and in particular to battery management systems. Background Art

[0002] Batteries are an integral part of many devices, including motor vehicles. Motor vehicles are typically equipped with a single battery, such as a lead-acid battery, for starting the vehicle's motor and for powering other vehicle systems, such as the charging system, runtime operations, lighting, accessories, etc. The reliability and safety of a battery typically depends on the battery's health, i.e., the condition of the battery, which may be linked to the condition of the battery's components.

[0003] Conventional systems may not provide the ability to effectively diagnose and / or control battery components (e.g., relays, switches, transistors, etc.). For example, some conventional systems that use relays to ensure battery safety are unable to effectively diagnose or control these relays. In some cases, a controller configured to operate a relay may fail without being detected by any other component, which may result in an unsafe condition for the battery, vehicle, etc. Summary of the invention

[0004] Some embodiments advantageously provide methods, apparatus, and systems for battery management, such as a battery management system (BMS).

[0005] According to one aspect, a relay of a battery management system (BMS) is described. The relay includes a bus connection point, a stack connection point, a main solid-state relay (SSR) electrically connected to the bus connection point and the stack connection point, and a secondary SSR electrically connected to the bus connection point and the stack connection point. The main SSR includes a first measurement point that can be used by the BMS to determine a state of a first SSR. The secondary SSR is connected in parallel with the main SSR and includes a second measurement point that can be used by the BMS to determine a state of a second SSR.

[0006] In some embodiments, the master SSR includes a first transistor and a second transistor. The first transistor has a first source and a first drain, and the second transistor has a second source and a second drain. The second transistor is connected in series with the first transistor. The first drain is electrically connected to the second drain. The first source is electrically connected to the stack connection point. The second source is electrically connected to the bus connection point.

[0007] In some other embodiments, one or more of the following conditions are met: the first measurement point is located between the first drain and the second drain, the first transistor includes a first control point, which is arranged to receive a first control signal that triggers the first transistor to be disconnected or connected, and the second transistor includes a second control point, which is arranged to receive a second control signal that triggers the second transistor to be disconnected or connected.

[0008] In some embodiments, the sub-SSR includes a third transistor and a fourth transistor. The third transistor has a third source and a third drain. The fourth transistor has a fourth source and a fourth drain and is connected in series with the third transistor. The third drain is electrically connected to the fourth drain. The third source is electrically connected to the stack connection point. The fourth source is electrically connected to the bus connection point.

[0009] In some other embodiments, one or more of the following conditions are met: the second measurement point is located between the third drain and the fourth drain, the third transistor includes a third control point, which is arranged to receive a third control signal that triggers the third transistor to be turned off or turned on, and the fourth transistor includes a fourth control point, which is arranged to receive a fourth control signal that triggers the fourth transistor to be turned off or turned on.

[0010] In some embodiments, the slave SSR is arranged to supply power when the master SSR is in a diagnostic or disconnected state.

[0011] In some other embodiments, the main SSR is a first metal oxide semiconductor field effect transistor (MOSFET) SSR, and the sub-SSR is a second MOSFET SSR.

[0012] According to another aspect, a battery management system (BMS) is described. The BMS includes a solid-state relay (SSR) and a processing circuit system including a microcontroller unit (MCU). The processing circuit system is electrically connected to the SSR and is configured to determine a fault mode associated with the MCU based on one or more parameters, and cause the SSR to perform one or more actions based on the fault mode without MCU intervention.

[0013] In some embodiments, the processing circuit system further includes a cell monitoring unit (CMU) electrically connectable to one or more battery cells and a power management integrated circuit (PMIC) in communication with the CMU. One or both of the CMU and the PMIC are configured to cause the SSR to perform one or more actions based on the fault mode.

[0014] In some other embodiments, the CMU is configured to determine one or more parameters associated with one or more battery cells.

[0015] In some embodiments, the MCU is in communication with the CMU, and the MCU is configured to determine parameter thresholds associated with one or more parameters and transmit the parameter thresholds to the CMU.

[0016] In some other embodiments, the CMU is configured to determine a fault indication and transmit the fault indication to the MCU and the PMIC to cause the MCU and the PMIC to enter an active operation mode.

[0017] In some embodiments, the PMIC is configured to determine a failure mode associated with the MCU based on a watchdog process that is operable to monitor one or more MCU processes.

[0018] In some other embodiments, the processing circuitry further includes a secondary current unit (SCU) configured to detect an overcurrent condition based on a predetermined hardware current threshold.

[0019] In some embodiments, the SCU is further configured to cause the SSR to perform one or more actions based on the detected overcurrent condition and a predetermined hardware current threshold.

[0020] In some other embodiments, the SSR relay includes a bus connection point, a stack connection point, and a master solid-state relay (SSR) electrically connected to the bus connection point and the stack connection point. The master SSR includes a first measurement point that can be used by the BMS to determine a first SSR state.

[0021] In some embodiments, the SSR relay further includes a slave SSR electrically connected to the bus connection point and the stack connection point, wherein the slave SSR is connected in parallel with the main SSR and includes a second measurement point that can be used by the BMS to determine a second SSR state.

[0022] In some other embodiments, the one or more actions include one of the following actions: disabling the SSR, enabling the SSR, disconnecting the SSR, and switching on the SSR.

[0023] According to one aspect, a battery is described. The battery includes one or more battery cells and a battery management system (BMS). The BMS is electrically connected to the one or more battery cells and includes a solid-state relay (SSR) electrically connected to the one or more battery cells and a processing circuit system including a microcontroller unit (MCU). The processing circuit system is electrically connected to the SSR and is configured to determine a fault mode associated with the MCU based on one or more parameters, and cause the SSR to perform one or more actions based on the fault mode without MCU intervention.

[0024] In some embodiments, the processing circuit system further includes: a battery cell monitoring unit (CMU), which can be electrically connected to one or more battery cells and configured to determine one or more parameters associated with the one or more battery cells; and a power management integrated circuit (PMIC) communicating with the CMU, wherein one or both of the CMU and the PMIC are configured to cause the SSR to perform one or more actions based on the fault mode; and / or, the MCU communicates with the CMU and is configured to determine parameter thresholds associated with one or more parameters and transmit the parameter thresholds to the CMU; and / or, the CMU is configured to determine a fault indication and transmit the fault indication to the MCU and the PMIC so that the MCU and the PMIC enter an active operating mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A fuller sense of the embodiments described herein and their attendant advantages and features will be more readily appreciated by reference to the following detailed description considered in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a block diagram of an example battery constructed according to the principles of the present disclosure;

[0027] Figure 2 An example system according to the principles of the present disclosure is shown;

[0028] Figure 3 is a block diagram of some entities in a system according to some embodiments of the present disclosure;

[0029] Figure 4 An example battery management system according to some embodiments of the present disclosure is shown;

[0030] Figure 5 is an example battery management system architecture according to the principles of the present disclosure;

[0031] Figure 6 shows a portion of an example BMS architecture according to the principles of the present disclosure;

[0032] Figure 7 shows another portion of an example BMS architecture according to the principles of the present disclosure; and

[0033] Figure 8 Shown are example arrangements of circuit elements according to principles of the present disclosure. DETAILED DESCRIPTION

[0034] Before describing the exemplary embodiments in detail, it should be noted that these embodiments are primarily directed to combinations of apparatus components and process steps associated with a battery management system (such as may be used in conjunction with lead-acid or lithium-ion batteries). Accordingly, system and method components are represented by conventional symbols in the accompanying drawings where appropriate, and only those specific details relevant to understanding the embodiments of the present disclosure are shown so as not to obscure the present disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0035] As used herein, relational terms such as "first" and "second", "top" and "bottom", etc. may be used only to distinguish one entity or element from another entity or element, without necessarily requiring or implying any physical or logical relationship or order between these entities or elements. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the concepts described herein. As used herein, the singular forms "a / an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that when the term "comprises / comprising / includes / including" is used herein, it specifies the presence of stated features, wholes, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0036] In some embodiments, the term VSTACK is used, which may refer to the voltage potential across a stack of battery cells (e.g., a plurality of battery cells connected in series). In some other embodiments, the term "VSTACK power unit" is used, which may refer to a power unit that performs one or more steps, such as steps associated with the voltage potential across a battery cell stack and / or associated with other parameters. Similarly, the term "VSTACK regulator" may be used, which may refer to an element that performs one or more steps, such as steps associated with regulating the voltage potential across a battery cell stack and / or associated with other parameters.

[0037] In some embodiments, the term VBUS is used, which may refer to the voltage potential between the external battery terminals (the terminals may be electrically isolated from each other by relays). In some other embodiments, the term "VBUS unit" is used, which may refer to a power unit that performs one or more steps, such as steps associated with the voltage potential between the external battery terminals and / or associated with other parameters. Similarly, the term "VBUS regulator" may be used, which may refer to an element that performs one or more steps, such as steps associated with regulating the voltage potential between the external battery terminals and / or associated with other parameters.

[0038] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should be further understood that, unless explicitly defined herein, the terms used herein should be interpreted as having a meaning consistent with the context of this specification and the meaning in the relevant field, and will not be interpreted in an idealized or overly formal sense.

[0039] In the embodiments described herein, connection terms such as "in communication with..." may be used to indicate electrical communication or data communication, which may be implemented, for example, by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling, or optical signaling. Those skilled in the art will appreciate that multiple components may interoperate, and that modifications and changes to the implementation of electrical and data communications are possible.

[0040] Referring now to the drawings, in which like reference numerals refer to like elements, Figure 1 1 shows a battery 10 constructed according to the principles of the present disclosure. The battery 10 includes a housing 12 in which one or more battery cells 14 are disposed. The battery cells 14 may be electrically interconnected, such as via a conductive bus bar system (not shown), which electrically interconnects the battery cells 14 in electrical series, in electrical parallel, or in a combination of electrical series and electrical parallel, depending on the expected voltage and current requirements.

[0041] A battery monitoring system (BMS) 16 may be included. In some embodiments, the BMS 16 may determine certain battery parameters, such as voltage, temperature, pressure, power, current, etc., and provide the data to an external system. The BMS 16 may also be connected to one or more battery cells 14. For example, the BMS 16 may be physically and / or electrically connected to a plurality of leads 26 (e.g., a lead assembly), wherein each lead 26 is physically and / or electrically connected to the battery cell 14. That is, the BMS 16 may be configured to determine (e.g., measure) one or more parameters of each battery cell 14 via the leads 26. The plurality of leads 26 may be included in the battery 10 and / or the BMS 16 (e.g., as part thereof). Further, the BMS 16 may include and / or be coupled to a monitoring connector 18 that implements an external connection, such as to a data bus of the vehicle or to some other communication device. In some embodiments, the monitoring connector 18 may be integrated with the housing 12, such as in a cover 20 of the housing 12. The battery 10 also includes terminals, such as a negative terminal 22a and a positive terminal 22b (collectively referred to as terminals 22), to provide contact points for electrically connecting the battery 10 to the vehicle to provide auxiliary power to the vehicle. The terminals 22 are arranged to extend through the housing 12, such as through the cover 20. The terminals 22 can be electrically connected to a bus bar inside the housing 12 and / or directly connected to the battery cell 14 (not shown in the figure). In some embodiments, the housing 12 includes one or more vents 24 to allow exhaust from one or more battery cells 14.

[0042] The battery 10 can be arranged to provide a number of power capacities and physical sizes, and to operate under various parameters and parameter ranges. It should also be noted that some embodiments of the battery 10 can be scaled to provide various capacities. Power capacity scaling can be achieved, for example, by using battery cells 14 of higher or lower power capacity in the housing 12 and / or by using fewer or more battery cells 14 in the housing 12. In some embodiments, the battery 10 can be incorporated as part of a vehicle such as an electric vehicle (EV) or another type of vehicle that requires battery power. Other electrical parameters of the battery 10 can be adjusted / regulated by using battery cells 14, which can be accumulated to have desired operating characteristics, such as voltage, charge capacity / rate, discharge rate, etc. Thermal performance can be managed based on the characteristics of the battery cells 14, using heat sinks and / or heat energy discharge plates inside or outside the housing 12, etc.

[0043] Figure 2An example system 30 according to the principles of the present disclosure is shown. The system 30 may include one or more of each of the following: a BMS 16, a network 32, a server 34, a device 36. In this non-limiting example, the BMS 16 may be configured to communicate with the network 32 and / or the server 34 and / or the device 36. The network 32 may be configured to provide communication functions and / or network functions to the BMS 16 and / or the server 34 and / or the device 36, such as access to one or more servers (e.g., the server 34) and / or server functions. The server 34 may be any server, computer, client device, network node, network device, etc. The server 34 may be configured to communicate with the BMS 16 and / or the network 32 and / or the device 36. The server 34 may be independent, integrated with the BMS 16 and / or the network 32 and / or the device 36, etc. Similarly, the BMS 16 may be independent, part of the device 36, part of the battery 10, integrated with the network 32 and / or the server 34, etc. Further, the BMS 16 (and / or the network 32 and / or the server 34 and / or the device 36) may be configured to perform any of the steps and / or tasks and / or methods and / or processes and / or features described herein, such as determining one or more parameters of the battery 10 and / or performing communication functions, such as sending / receiving one or more messages associated with one or more parameters. The BMS 16 may include a processing circuit system, such as a processing unit (e.g., a processor) and a memory to perform one or more functions described herein. The BMS 16 may include a communication unit (e.g., a communication interface) to communicate with sensors that monitor other operating parameters of the battery cells 14 and the battery 10, and / or to communicate with external elements (such as the network 32 and / or the server 34 and / or the device 36).

[0044] In particular, as a supplement or alternative to a processor (such as a central processing unit) and a memory, the processing circuit system may include an integrated circuit system for processing and / or control, for example, one or more processors and / or processor cores and / or an FPGA (field programmable gate array) and / or an ASIC (application-specific integrated circuit system) adapted to execute instructions. The processor may be configured to access the memory (e.g., write to the memory and / or read from the memory), which may include any type of volatile and / or non-volatile memory, for example, a cache and / or buffer memory and / or a RAM (random access memory) and / or a ROM (read-only memory) and / or an optical memory and / or an EPROM (erasable programmable read-only memory).

[0045] Now refer to Figure 31 and 2 are used to describe example implementations of the BMS 16, the device 36, and the server 34 discussed in the previous paragraphs according to an embodiment. The BMS 16 may have hardware 40, which may include a communication interface 42 configured to communicate with one or more entities in the system 30 via wired and / or wireless communications. The communication may be a protocol-based communication.

[0046] Hardware 40 includes processing circuit system 44. Processing circuit system 44 may include processor 46 and memory 48. In particular, in addition to or in place of a processor (such as a central processing unit) and memory, processing circuit system 44 may include an integrated circuit system for processing and / or control, for example, one or more processors and / or processor cores and / or an FPGA (field programmable gate array) and / or an ASIC (application-specific integrated circuit system) adapted to execute instructions. Processor 46 may be configured to access memory 48 (e.g., write to and / or read from memory), which may include any kind of volatile and / or non-volatile memory, for example, cache and / or buffer memory and / or RAM (random access memory) and / or ROM (read-only memory) and / or optical memory and / or EPROM (erasable programmable read-only memory).

[0047] Thus, the BMS 16 may further include software 60 stored, for example, in the memory 48, or in an external memory (e.g., a database, etc.) accessible by the BMS 16. The software 60 may be executed by the processing circuitry 44. The software 60 may include a software application 62 and / or firmware 64.

[0048] The processing circuit system 44 may be configured to control any method and / or process described herein and / or cause such method and / or process to be performed, for example, by the BMS 16. The processor 46 corresponds to one or more processors 46 for performing the BMS 16 functions described herein. The BMS 16 includes a memory 48 configured to store data, programming software code, and / or other information described herein. In some embodiments, the software 60 may include instructions that, when executed by the processor 46 and / or the processing circuit system 44, cause the processor 46 and / or the processing circuit system 44 to perform the processes described herein with respect to the BMS 16. For example, the processing circuit system 44 of the BMS 16 may include a BMS management unit 50 that is configured to perform any steps and / or tasks and / or processes and / or methods and / or features described in the present disclosure, for example, determining one or more parameters, steps, and / or processes associated with the battery 10. Although the BMS management unit 50 is illustrated as being part of the BMS 16 , the BMS management unit 50 and associated functionality described herein may be implemented in a device different than the BMS 16 , such as in the battery 10 or another device.

[0049] The hardware 40 may also include one or more circuit elements 70 , such as resistors, capacitors, inductors, diodes, transistors, ground connections, source elements, sink elements, etc. The circuit elements 70 may be arranged in any configuration or connection, such as in series, in parallel, combinations thereof, etc., and may be connected to any other device, such as a component of the system 30 .

[0050] The device 36 may have hardware 80 that may include a communication interface 82 configured to communicate with one or more entities in the system 30 (and / or external to the system 30) via wired and / or wireless communications. The communication may be protocol-based communication. The device 36 may also be configured to be electrically connected to the battery 10, for example, electrically connected to the device 36 (e.g., to power the device 36) and / or receive at least one parameter (and / or parameter data) from the battery 10 and / or display the at least one parameter.

[0051] Hardware 80 includes processing circuit system 84. Processing circuit system 84 may include processor 86 and memory 88. In particular, in addition to or in place of a processor (such as a central processing unit) and memory, processing circuit system 84 may include an integrated circuit system for processing and / or control, for example, one or more processors and / or processor cores and / or an FPGA (field programmable gate array) and / or an ASIC (application-specific integrated circuit system) adapted to execute instructions. Processor 86 may be configured to access memory 88 (e.g., write to and / or read from memory), which may include any kind of volatile and / or non-volatile memory, for example, cache and / or buffer memory and / or RAM (random access memory) and / or ROM (read-only memory) and / or optical memory and / or EPROM (erasable programmable read-only memory).

[0052] The device 36 may further include software 100 stored, for example, in the memory 88, or in an external memory (eg, a database, etc.) accessible by the device 36. The software 100 may be executed by the processing circuitry 84.

[0053] The processing circuit system 84 may be configured to control any method and / or process described herein and / or cause such a method and / or process to be performed, for example, by the device 36. The processor 86 corresponds to one or more processors 86 for performing the functions of the device 36 described herein. The device 36 includes a memory 88 configured to store data, programming software code, and / or other information described herein. In some embodiments, the software 100 may include instructions that, when executed by the processor 86 and / or the processing circuit system 84, cause the processor 86 and / or the processing circuit system 84 to perform the processes described herein with respect to the device 36. For example, the processing circuit system 84 of the device 36 may include a device unit 90 configured to perform any steps and / or tasks and / or processes and / or methods and / or features described in the present disclosure, for example, determining one or more parameters, steps and / or processes associated with the battery 10. The device 36 may also include a display 110 configured to display an indication associated with at least one parameter measured / determined, such as an indication associated with the battery 10. The at least one parameter may include a state of charge, a voltage, a current, etc. Display 110 may include lights (such as light emitting diodes (LEDs)), a monitor, a screen, and / or any other type of display.

[0054] In some embodiments, device 36 and / or any components thereof (such as display 110 ) may be included in and / or powered by BMS 16 (and / or battery 10 ).

[0055] Further, the server 34 includes hardware 120, and the hardware 120 may include a communication interface 122 for performing wired and / or wireless communications with the BMS 16 and / or the device 36 and / or any other device. For example, the communication interface 122 of the server 34 may communicate with the communication interface 82 of the device 36 via a communication link 91. In addition, the communication interface 122 of the server 34 may communicate with the communication interface 42 of the BMS 16 via a communication link 93. Similarly, the communication interface 42 may communicate with the communication interface 82 via a communication link 95. At least one of the communication links 91, 93, 95 may refer to a wired / wireless connection (such as WiFi, Bluetooth, etc.).

[0056] In the illustrated embodiment, the hardware 120 of the server 34 includes a processing circuit system 124. The processing circuit system 124 may include a processor 126 and a memory 128. In particular, in addition to or in place of a processor (such as a central processing unit) and a memory, the processing circuit system 124 may include an integrated circuit system for processing and / or control, for example, one or more processors and / or processor cores and / or an FPGA (field programmable gate array) and / or an ASIC (application-specific integrated circuit system) adapted to execute instructions. The processor 126 may be configured to access the memory 128 (e.g., write to the memory and / or read from the memory), which may include any type of volatile and / or non-volatile memory, for example, a cache and / or buffer memory and / or a RAM (random access memory) and / or a ROM (read-only memory) and / or an optical memory and / or an EPROM (erasable programmable read-only memory).

[0057] Therefore, the server 34 further has software 140, which is stored internally, for example, in the memory 128, or stored in an external memory (e.g., a database, etc.) accessible by the server 34 via an external connection. The software 140 can be executed by the processing circuit system 124. The processing circuit system 124 can be configured to control any method and / or process described herein and / or cause such a method and / or process to be executed, for example, by the server 34. The processor 126 corresponds to one or more processors 126 for performing the functions of the server 34 described herein. The memory 128 is configured to store data, programming software code, and / or other information described herein. In some embodiments, the software 140 may include instructions that, when executed by the processor 126 and / or the processing circuit system 124, cause the processor 126 and / or the processing circuit system 124 to perform the process described herein with respect to the server 34. For example, the processing circuitry 124 of the server 34 may include a server management unit 130 configured to perform one or more server 34 functions described herein, such as determining one or more parameters, steps, and / or processes associated with the battery 10 .

[0058] In some embodiments, device 36 may be included in BMS 16 and / or battery 10 (eg, Figure 1 In some other embodiments, the device 36 may be configured to perform any BMS function. In some embodiments, the device 36 and the battery 10 are included in the vehicle, and the device 36 may be connected to the battery 10 and / or the BMS 16.

[0059] although Figure 3 One or more "units" such as the BMS management unit 50, the equipment unit 90, the server management unit 130, etc. are shown as being located within the corresponding processor, but it is conceivable that these units can be implemented so that a portion of the unit is stored in a corresponding memory within the processing circuit system. In other words, these units can be implemented in hardware, software, or a combination of hardware and software within the processing circuit system.

[0060] Figure 4 An example BMS 16 is shown. The BMS 16 may include one or more components that may be related to Figure 3The BMS 16 may include a solid-state relay (SSR) 150 (which may be a circuit element 70 and / or may be referred to as a relay 150), a VSTACK power unit 152, a relay control unit (RCU) 154, a VBUS unit 156, a cell monitoring unit (CMU) 160, a sensor 162 (e.g., such as a temperature sensor), a VSTACK regulator 164, a VBUS regulator 166, a short circuit protection / current monitor 168, a current measurement regulator (CMC) 170, a shunt 172, a microcontroller (MCU) 180, a power management (and / or control) integrated circuit (PMIC) 190, a relay driver unit (RDU) 192, a secondary current unit (SCU) 194, and a power supply (PS) 196. The SSR 150 may be configured as a switch to disconnect and connect an electrical connection, such as an electrical connection from a positive cell terminal to a battery terminal. The SSR 150 may be arranged to receive a signal that triggers the SSR 150 to be disconnected or connected. In some embodiments, the SSR 150 may refer to more than one SSR, such as a main SSR and a secondary SSR. The VSTACK power unit 152 may be configured to perform one or more steps associated with one or more parameters, such as voltage (e.g., the voltage of the battery bus). The RCU 154 may be configured to perform relay control functions, such as receiving diagnostic signaling, supply voltage, etc. from the MCU 180, the PMIC 190. The VBUS power unit may be configured to perform one or more steps associated with one or more parameters, such as voltage (e.g., the voltage of the battery bus).

[0061] Further, CMU 160 can be configured to perform monitoring functions, such as battery cell monitoring devices (CMDs), battery cells and battery monitors, etc. In some embodiments, CMU 160 (and / or other BMS components) can be configured to monitor and control SSR 150 (and / or any other BMS components) without MCU 180 intervention (i.e., without MCU 180 performing any actions associated with SSR 150). Sensor 162 can be any sensor, such as a temperature sensor. VSTACK regulator 164 can be configured to provide electrical regulation of signals (e.g., signals associated with a battery stack). Similarly, VBUS regulator 166 can be configured to provide electrical regulation of signals (e.g., signals associated with a battery bus). Short circuit protection / current monitors can be configured to monitor circuit conditions and / or parameters (e.g., short circuit conditions, current values, etc.), and perform one or more actions to protect the circuit. Current measurement regulator 170 can be configured to perform regulation functions associated with the measurement of any parameter (e.g., current). The shunt 172 may be arranged to provide a current path (eg, a current path having a predetermined resistance, such as a low resistance) that may allow the current to flow to another point in the circuit.

[0062] MCU 180 can be configured to provide monitoring functions, such as main monitoring, which monitors vehicle interface, secondary VSTACK, current and VBUS measurement, etc. PMIC 190 is configured to provide supply voltage, receive fault indication, transmit SSR control signal, and provide power supply and watchdog process features. RDU 192 can be configured to provide relay driver features. In some embodiments, RDU 192 is included in RCU 154 (that is, RCU 154 is configured to perform one or more functions associated with RDU 192). SCU 194 can be configured to perform regulation functions to regulate current. Power supply (PS) 196 can be arranged to provide power to one or more elements. In some embodiments, PMIC 190 can include PS196 and / or perform one or more functions associated with PS196. In some other embodiments, PMIC 190 can be PS196 of BMS16, and can be configured to power (and interface with) other BMS components (such as MCU 180), for example, to perform safety supervision functions. Any component of the BMS 16 may be configured to receive one or more inputs (eg, input signals), perform one or more actions / decisions, and generate one or more outputs (eg, output signals).

[0063] In some embodiments, Figure 4 One or more of the components shown are included in and / or are part of the battery management unit 50 and / or the circuit element 70 .

[0064] Figure 5 An example battery management system (BMS) architecture according to the principles of the present disclosure is shown. The example battery management system architecture may be an electronic 12V auxiliary BMS architecture. The BMS 16 may include a battery management unit (BMU) 50. In some embodiments, BMS refers to BMU, i.e., the two terms may be used interchangeably.

[0065] It is worth noting that although Figure 5 A BMS block diagram with four battery cells is shown, but these details are provided only to aid understanding and are not intended to be limiting of the embodiments. It is contemplated that the concepts / arrangements shown and described herein may be applicable to more or less than four battery cells 14. Embodiments of the BMS 16 may be implemented in 12 volt systems as well as non-12 volt based systems.

[0066] The BMS 16 may include one or more logic components, actuation components, and sensing components. The logic components may include at least one of the following: an MCU 180, which may be configured as a primary monitor, a vehicle interface, a secondary VSTACK, current, and VBUS measurement; a communication interface (CI) 42, which includes a transceiver, such as a controller area network (CAN) FD transceiver, which may be configured to communicate with the MCU 180 and / or the vehicle, for example, using CAN FD; and a PMIC 190, which may be configured as a power supply and a watchdog timer. The actuation components may include at least one of the following: a power supply component (such as a VSTACK power unit 152), an RCU 154, a VBUS unit (VU) 156, and / or a relay (such as an SSR 150). The sensing components may include at least one sensor 162 (such as an SSR temperature sensor), a VSTACK regulator 164, a VBUS regulator 166, a short circuit protection and / or current monitor 168, a current measurement regulator 170, a shunt 172 and / or a CMU 160 (e.g., battery cells and battery monitor).

[0067] The CMU 160 may be configured to provide at least one of: cell monitoring, cell balancing, master VSTACK measurement, shunt current monitor, master VBUS monitor, safety monitoring, temperature sensor readings, and / or any other type of monitoring / sensing / management functionality associated with the battery 10 (and / or its components) and / or the vehicle. The CMU 160 may be further configured to electrically connect to one or more cells 14 (e.g., via leads 26), and / or any other battery / vehicle components (e.g., via one or more leads), and / or measure / manage / monitor / control any battery / cell parameter, such as temperature, voltage, current, pressure, etc. Although some connections between some components are shown, any component (e.g., logic components, actuation components, and sensing components) may be connected (e.g., electrically connected and / or in communication) with any other component. Any of the components shown may send and / or receive one or more signals (e.g., control signals, indications, information, etc.).

[0068] In a non-limiting example, the CMU 160 may be configured to receive SSR current feedback via connection 200. The RCU 154 may be connected to the SCPCM 168 via connection 202, such as for monitoring and protecting the RCU. The RCU 154 may provide / receive SSR diagnostics via connection 204, receive SSR control via connection 206, and receive supply voltage via connection 208. In addition, the CMU 160 may send / receive data and / or signals to / from the MCU 180 via connection 210 (i.e., via a serial peripheral interface (SPI)), and provide fault information to the PMIC 190 via connection 212. The MCU 180 may exchange independent faults with the PMIC 190 via connection 214. The MCU 180 may also exchange SPI with the PMIC 190 via connection 216. SPI may refer to an industry standard interface that may be used between components such as integrated circuits (ICs). Further, the SPI may be configured as an interface that uses multiple wires or conductors to communicate between ICs. For example, the SPI may be a 4-wire interface.

[0069] In some embodiments, Figure 5 An example BMS architecture may include one or more of the following features / options:

[0070] Integrated BMS (single printed circuit board assembly (PCBA)).

[0071] Flexible, wired, direct-mount cell voltage and temperature connections.

[0072] Power architecture:

[0073] ○Powered by internal 12V lithium-ion battery.

[0074] ○There is a 12V common ground at the battery terminals.

[0075] Battery disconnection:

[0076] o Solid-state relay (SSR) (eg, metal oxide semiconductor field effect transistor (MOSFET)).

[0077] ○ Bistable electromechanical.

[0078] ○Monostable electromechanical.

[0079] Integrated shunt current measurement:

[0080] ○Reduce system integration costs.

[0081] ○High signal-to-noise immunity.

[0082] Functional safety strategy in accordance with ISO 26262:

[0083] ○Supports Automotive Safety Integrity Level (ASIL) C / D.

[0084] ○Dual supervisors and single microcontroller with external watchdog solution.

[0085] Automotive Open System Architecture (AUTOSAR).

[0086] ·Cybersecurity.

[0087] • Over-the-air (OTA) communications, for example, to perform OTA programming of the BMS 16 and / or any of its components (such as the MCU 180 ).

[0088] In one or more embodiments, an operational arrangement associated with the BMS 16 is provided. The BMS 16 may be included in and / or be a part of the battery 10. In some embodiments, the example operational arrangement is Figure 5 The example operational deployment is associated with the BMS16 shown. In some other embodiments, the example operational deployment may refer to the software and / or hardware of the BMS16. In some embodiments, the example operational deployment refers to the BMS16 (and / or BMU). The BMS16 may include a processing circuit system, which may include a processor, a memory, a communication interface and / or software such as an operating system (OS). More specifically, in the example operational deployment, at least one of the following (which may exist in software and / or hardware) is included: a microcontroller (e.g., a processor, a processing circuit system), software 60 (e.g., battery software (BSW), such as firmware 64), an RTE, a boot loader, and an application (such as a software application 62).

[0089] In some embodiments, Figure 5One or more of the components shown (e.g., battery, hardware, etc.) may be combined (e.g., integrated) with any other components, for example, to provide management functions, such as battery management functions of the battery 10. In non-limiting examples, the components may be used to provide / determine the state of charge, function, health of the battery, and / or provide diagnostic and / or management / control functions. Figure 1 and Figure 5 The battery cells shown in FIG. are managed (e.g., by Figure 5 CMU 160 and / or any other microcontroller) and / or control.

[0090] In another non-limiting example, when a battery / cell parameter (e.g., measured by any sensing component) is below a predetermined threshold and / or equal to a predetermined state (e.g., determined by any component of the system 30 (e.g., BMS 16)), the solid-state relay (SSR) 150 can be closed (e.g., triggered by an input from a relay of a sensing component or logic component), thereby allowing the battery cell 14 and the battery 10 to provide power at the positive terminal. Similarly, when a battery / cell parameter (e.g., measured by any sensing component) is greater than a predetermined threshold and / or is not equal to a predetermined state (e.g., determined by any component of the system 30 (e.g., BMS 16)), the SSR 150 can be opened (e.g., triggered by an input from a relay of a sensing component or logic component), thereby cutting off power at the positive terminal. Further, any status, diagnostic, parameter, determination, information, etc. can be transmitted to another component (software and / or hardware), such as via a CAN FD transceiver of the communication interface 42.

[0091] Figure 6A portion of an example BMS architecture is shown. The CMU 160 can be configured to determine one or more parameters of the battery cell 14, such as via at least one connection 220 to the battery interface 306, which can be included in or as part of the lead 26. In some embodiments, the CMU 160 is arranged to measure battery cell parameters of five battery cells (e.g., CELLS0, CELLS1, CELLS2, CELLS3, CELLS4) and another parameter, such as voltage (e.g., CELL_VDD), via connection 222. Further, the CMU 160 can be configured to measure the temperature of the battery cell 14 via connections 224, 226 (via sensor 162). Connections 224, 226 can refer to temperature connection returns (e.g., TMEP1_RET) and temperature (e.g., TEMP1). The CMU 160 can be further configured to determine the current of the battery pack, such as a negative current via connection 230 and a positive current via connection 232. Connections 230, 232 may be referred to as IPAC_NEG and IPACK_POS. Resistors 304a, 304b (i.e., circuit element 70) may be connected in parallel to pads 302a, 302b and grounded to a ground connection. CMU 160 may also provide signaling associated with cell monitoring or exchange signaling with VSTACK regulator 164 via connection 234, such as bus voltage (i.e., VBUS_CMD). VSTACK regulator 164 may be connected to or provide bus voltage (i.e., VBUS connection). VSTACK regulator 164 may also exchange signaling with MCU 180, such as signals to enable one or more measurements (via VBUS_CMD_MEAS_EN of connection 236, VBUS_MCU_MEAS_EN of connection 238) and / or other signaling (e.g., via VBUS_MCU of connection 240). CMU 160 and MCU 180 may exchange reset signals, such as via connection 242, SPI via connection 244 (ie, CMD_SPI). Additionally, CMU 160 may be configured to send / receive fault indications via connection 246 (ie, CMD_FLT).

[0092] MCU 180 may also receive / send test signaling (i.e., TEST_SC) via connection 248, which may be sent / received by SCU 194. Further, secondary currents (and / or secondary current values) may be exchanged between SCU 194 and MCU 180 via connection 250. Further, MCU 180 may exchange SSR signaling (such as control and fault information) with RDU 192 via connections 251, 252, respectively. Further, MCU 180 may send / receive faults to / from PS196 via connection 254. Other signals, such as PS_SPI, MCU reset, analog power signals, PMIC-MCU related signals, may be exchanged between MCU 180 and PS196 via connections 256, 258, 260, 262. SCU 194 may also send / receive power-related signals to / from RDU 192 via connection 264. In some embodiments, RDU 192 may be part of RCU 154. Further, MCU 180 may exchange CAN and LIN data / information with communication interface (CI) 42 via connections 266, 268. CMU 160 may also exchange SSR related signaling with RDU 192 via connection 278.

[0093] Figure 7 Shows Figure 6 Another part of the example BMS architecture. The figure shows CI 42, PS196 and RDU 192, any of which can be connected to Figure 6 180. For example, CI 42 may be connected to (and / or receive / send signals via) MCU 180 using connections 266, 268, as described in the present disclosure. PS 196 may be connected to MCU 180 using connections 246, 254, 256, 258, 260, 260, as described in the present disclosure. Further, RDU 192 may be connected to MCU 180 and SCU 194 via connection 250, to MCU 180 via connections 251, 252, and to CMU 160 via connection 278. Further, PS 196 may be connected to RDU 192 via connections 254, 276, 264 to exchange fault, voltage (i.e., V_RVP), and SSR signals (i.e., SSR_GD_EN), respectively.

[0094] CI 42 can send / receive indications associated with protocols (such as CAN / LIN) via connections 270, 272, 274 and well pads 302d, 302e, 302g, i.e., CANH_FD, CAN1L_FD, LIN_BUS. Pad 302c can be grounded via resistor 304c. In addition, in addition to pad 302h, RDU 192 can also be connected to (via connection 280) and / or receive and / or send VSTACK (i.e., stack voltage). Similarly, in addition to pad 302i, RDU 192 can also be connected to (via connection 282) and / or receive and / or send VBUS (i.e., bus voltage).

[0095] Some embodiments provide protection for the battery 10 and associated vehicle. The CMU 160 (eg, CMD) may be used with the PMIC 190 to provide protection associated with functional safety (FuSa) requirements for a vehicle in a predetermined connection mode (ie, key-off).

[0096] The BMS 16 (e.g., CMU 160 and / or PMIC 190) can be configured to disable the SSR 150 without MCU intervention, such as when the MCU 180 is not awake or has a certain failure mode. Disabling the SSR 150 in this way can provide a higher automotive safety integrity level (ASIL). In addition, the BMS 16 can be configured to detect a short circuit (SC), such as when the system component (and / or the vehicle) is in sleep mode, and disconnect the SSR 150 to provide functional safety measures. In some embodiments, SC protection-low Iq (i.e., low quiescent current) fast action is provided, wherein SC detection and protection can be provided without MCU intervention to achieve sleep state protection. Low Iq fast action short circuit detection and protection that can achieve sleep state protection without MCU intervention can detect a short circuit event and directly disconnect the relay without MCU intervention.

[0097] In some other embodiments, the battery 10 and the vehicle can be protected from conditions that may exist when the vehicle is turned off and the vehicle controls are in a dormant state and the battery provides power to the vehicle's off-state loads. When the MCU 180 is in a sleep state or cannot be awakened from a sleep state to provide intelligent protection, the battery 10 can be protected from adverse conditions such as short circuits, battery overcharging, or other possible battery / cell failures (e.g., overtemperature).

[0098] In some embodiments, CMU 160 detects battery cell voltage and temperature. MCU 180 can set overvoltage and overtemperature limits via SPI. CMU 160 can have a fault line (i.e., connection 246, CMD_FLT) for waking up MCU 180 and PMIC 190. If MCU 180 does not take action within a specified time period, PMIC 190 can detect and disable SSR 150 and / or disconnect SSR 150. PMIC 190 detects failure of the MCU through an intelligent watchdog that monitors the MCU function.

[0099] In some other embodiments, the SCU 194 (e.g., secondary current block) is configured to detect overcurrent or short circuit based on a preset hardware current threshold. If a hard short circuit occurs, the RDU 192 (e.g., relay driver) detects and disconnects the SSR to protect the battery 10 and the BMS 16. If there is a resistive short circuit, the MCU 180 may have time to wake up and provide appropriate protection.

[0100] Conventional solutions do not allow power to be provided to the vehicle when the primary MCU 180 is not responding or do not use the secondary MCU 180 or logic devices to handle faults or bad conditions.

[0101] In some embodiments, the SSR 150 is arranged to be scalable from low current to high current. Various MOSFET pairs may be used to provide various ranges of scalability to manage current pulses and the power dissipation associated therewith. In some other embodiments, one or more pairs of MOSFETs (e.g., five pairs) may meet a 12V auxiliary power requirement, such as 200A for 300 seconds. In some embodiments, the size of the heat sink may have an impact on the total power that can be dissipated.

[0102] In some other embodiments, the BMS 16 includes one or more shunts (e.g., a pair of 200uOhm shunts in parallel, such as resistors 304a, 304b). The total resistance and power rating of the shunts allow operation within a maximum current range defined by a predetermined margin. For lower current applications, one of the shunts may be omitted.

[0103] In some embodiments, in the case of FuSa, the BMS architecture may include CMU 160, MCU 180, and PMIC 190, which can achieve from ASIL QM to ASIL D based on the diagnostic coverage implemented in the utilized software design and software development practices. The BMS 16 can operate the battery 10 in a safe state with or without MCU 180 intervention, and in an operating state or a sleep state. The CMU 160 design provides redundancy with the PMIC 190 to meet FuSa requirements and can be extended to lower or higher ASIL capabilities beyond the current 12V auxiliary power supply target. The PMIC 190 is arranged to provide various levels of watchdog functions to ensure the operation of the MCU 180.

[0104] In some other embodiments, MCU 180 provides memory (e.g., a portion of memory 48, such as non-volatile memory, such as flash memory and random access memory (RAM)) for software 60 to implement an AUTOSAR operating system. MCU 180 allows operation during reprogramming, supporting over-the-air (OTA) updates. Further, the memory associated with MCU 180 may be mutable.

[0105] In some embodiments, the CMU 160 (e.g., a cell monitoring device (CMD)) can be configured to provide cell and battery monitoring functions and can be expanded to accommodate different numbers of cells 14 (e.g., 4, 6, 14 cell devices) using the same software interface. The CMU 160 can also accommodate different levels of balancing current (e.g., up to 300mA total per device). In some other embodiments, the PMIC 190 can be expanded based on the safety level. The PMIC 190 can also be power expanded. In some embodiments, the communication interface 42 may include a CAN transceiver configured to provide high-speed CAN (HS CAN) and CAN flexible data rate (CAN FD) capabilities.

[0106] Some embodiments provide solutions to problems in the known art regarding the ability to diagnose SSRs for functional safety reasons. SSR diagnostics can include ensuring whether the SSR can be triggered to disconnect and connect (e.g., the SSR cannot be disconnected and connected). In addition, in order to meet battery current requirements, SSRs typically require an electrical parallel configuration of MOSFETs to handle the current. However, when there are many MOSFETs in parallel, it may be difficult to determine whether a MOSFET is blocked in the disconnected state. Further, if it is not diagnosed, other MOSFETs may overheat. In addition, some arrangements include two MOSFETs in series to handle bidirectional current blocking, requiring both series MOSFETs to be diagnosable to ensure proper charge and discharge blocking.

[0107] One or more embodiments of the present disclosure provide for performing diagnostics when the battery 10 is connected to the vehicle bus (e.g., performing diagnostics on a BMS relay such as an SSR). In some embodiments, any disconnected or shorted MOSFET or MOSFET pair can be detected. In some embodiments, the arrangement of circuit elements 70 includes a secondary secondary current MOSFET SSR that can supply power when diagnosing the main SSR. The arrangement can also provide the ability to measure parameters before and after the (multiple) common drain points individually and determine whether there is a MOSFET that is blocked in disconnection or blocked in connection (e.g., via software control). In some other embodiments, the arrangement can be used to determine whether any MOSFET is disconnected.

[0108] In some embodiments, a secondary SSR utilizing a p-channel device is used. The drain connection between the MOSFET pair can be disconnected and a measurement of each drain voltage taken. Independent charge and discharge control can be provided, for example, so that each MOSFET can be diagnosed. One or more conditions can be diagnosed via software / hardware elements, for example, by executing one or more steps associated with the measurement and control process.

[0109] Figure 8 An example arrangement of circuit elements 70 is shown, which may be part of the SSR 150 (and / or the RCU 154 and / or the RDU 192) and / or any other component of the BMS 16. In a non-limiting example, four transistors 400, 402, 404, 406 are shown. The transistors may be metal oxide semiconductor field effect transistors (MOSFETs). The transistors 400, 404 may be connected to VSTACK on one side (i.e., at connection point 412) and to transistors 402, 406, respectively, on the other side. Further, the transistors 402, 406 may be connected to VBUS (i.e., at connection point 414). Measurement points 408, 410 may be provided and connected to the BMS 16 to measure parameters (e.g., voltages) associated with the transistors 400, 402, 404, 406 and / or VSTACK and / or VBUS. For example, the voltages on both sides of the measurement points 408, 410 may be measured. In another example, the voltages at both sides of the measurement point 408 (or the measurement point 410) and another point may be measured. In some embodiments, the transistor state (e.g., disconnected, connected) may be determined based on the voltage changes measured at the measurement points 408, 410. In some other embodiments, each common drain point (i.e., measurement points 408, 410) measured before and after each charge and discharge control state is used to determine whether the MOSFET (i.e., transistors 400, 402, 404, 406) is in an operating state.

[0110] Further, each transistor has a control point (e.g., a gate). For example, transistor 400 may have a control point 416, transistor 402 may have a control point 418, transistor 404 may have a control point 420, and transistor 406 may have a control point 422. Each control point (e.g., a gate) may be configured to control the flow of current between the drain and source of the transistor. For example, a voltage may be applied to the control point, which may generate an electric field, thereby controlling the flow of current through the channel between the drain and the source. In one or more embodiments, charge control (i.e., CHARGE_CNTL) refers to energizing the corresponding transistor, such as turning on one or both of transistors 400, 406, which will allow the battery 10 to be charged. In other words, control points 416, 422 may be enabled or energized, which enables transistors 400, 406 to be used to charge the battery 10. In some other embodiments, discharge control (i.e., DISCHARGE_CNTL) refers to energizing the corresponding transistor to allow the battery 10 to discharge. That is, control points 418, 420 may be enabled or powered on, which enables the corresponding transistors to be used to discharge battery 10. However, embodiments of the present disclosure are not limited thereto, and any of control points 416, 418, 420, 422 may be powered on for charging, discharging, or any other function.

[0111] In some embodiments, transistors 402, 402 may be considered as a primary SSR 450, and transistors 404, 406 may be considered as a secondary SSR 452. In some other embodiments, Figure 8 Any component (e.g., transistor, SSR) in the example arrangement may be connected to other components (e.g., in parallel) to increase current passing capability. In some embodiments, one or more diagnostics (e.g., diagnostics of the main SSR 450, the secondary SSR 452) may be performed using the example arrangement. For example, one or more of the following steps may be performed (e.g., by the BMS 16):

[0112] Perform secondary SSR diagnostics before testing the primary SSR 450;

[0113] · performing diagnostics when the vehicle associated with the battery 10 is in a sleep state and low current (ie, in a predetermined mode);

[0114] Verify that the slave SSR 452 is not blocked in the on state (ie, closed) by reading the common drain voltage;

[0115] Verify that the slave SSR 452 is not stuck in the off state by (e.g., independently) enabling and disabling the stack and bus sides of the slave SSR 452 and reading the common drain voltage;

[0116] With the master SSR 450 enabled, measure the common drain voltage;

[0117] Disable the main SSR 450 and measure the common drain voltage to determine if any MOSFET pair is stuck in the on or shorted state;

[0118] Enable the charging MOSFETs and measure the common drain measurement to verify if any MOSFET is stuck in the off state.

[0119] Disable the charging MOSFET; and

[0120] Enable the discharge MOSFETs and measure the common drain measurement to verify if any MOSFET is stuck in the off state.

[0121] One or more embodiments are beneficial at least because the example arrangements provide one or more of the following:

[0122] Low current secondary SSR 452;

[0123] Each main MOSFET pair includes a common drain that is isolated from other parallel pairs;

[0124] The primary and secondary SSR paths are diagnosable;

[0125] Can diagnose whether each MOSFET pair is blocked in the on or short circuit state;

[0126] Can diagnose whether each MOSFET is blocked in disconnection or open circuit state;

[0127] Scalable design;

[0128] Functional safety (FuSa) architecture vehicle shutdown relay closed;

[0129] Solid-state relay protection and diagnostic design; and

[0130] BMU / BMS fail-safe design for connected vehicle shutdown mode.

[0131] It should be understood that all specification values ​​shown and described herein are non-limiting examples of embodiments of batteries 10, battery cells 14, BMS 16 (and / or BMU) constructed according to the principles of the disclosure provided herein. Those skilled in the art will understand that the present embodiment is not limited to what has been specifically shown and described above. In addition, unless otherwise mentioned above, it should be noted that all drawings are not drawn to scale. In view of the above teachings, various modifications and variations are possible without departing from the scope of the appended claims.

Claims

1. A relay (150) of a battery management system (BMS) (16), the relay (150) comprising: Bus connection point (414); HEAP_JOIN_POINT(412); A main solid-state relay SSR (450) electrically connected to the bus connection point (414) and the stack connection point (412), the main SSR (450) comprising: a first measurement point (408) usable by the BMS (16) to determine a first SSR state; and A secondary SSR (452) electrically connected to the bus connection point (414) and the stack connection point (412), the secondary SSR (452) being connected in parallel with the primary SSR (450) and comprising: A second measurement point (410) is used by the BMS (16) to determine a second SSR state.

2. The relay according to claim 1, wherein: The main SSR (450) comprises: a first transistor (400) having a first source and a first drain; and A second transistor (402) having a second source and a second drain, the second transistor (402) being connected in series with the first transistor (400), the first drain being electrically connected to the second drain, the first source being electrically connected to the stack connection point (412), and the second source being electrically connected to the bus connection point (414).

3. The relay according to claim 2, wherein: One or more of the following conditions are met: The first measurement point (408) is located between the first drain and the second drain; The first transistor (400) comprises a first control point, the first control point being arranged to receive a first control signal, the first control signal triggering the first transistor (400) to be turned off or on; and The second transistor (402) comprises a second control point, the second control point being arranged to receive a second control signal, the second control signal triggering the second transistor (402) to be turned off or on.

4. The relay according to any one of claims 1 to 3, wherein: The secondary SSR (452) comprises: a third transistor (404) having a third source and a third drain; and A fourth transistor (406) having a fourth source and a fourth drain, the fourth transistor (406) being connected in series with the third transistor (404), the third drain being electrically connected to the fourth drain, the third source being electrically connected to the stack connection point (412), and the fourth source being electrically connected to the bus connection point (414).

5. The relay according to claim 4, wherein: One or more of the following conditions are met: The second measurement point (410) is located between the third drain and the fourth drain; The third transistor (404) comprises a third control point, the third control point being arranged to receive a third control signal, the third control signal triggering the third transistor (404) to be turned off or on; and The fourth transistor (406) comprises a fourth control point, the fourth control point being arranged to receive a fourth control signal, the fourth control signal triggering the fourth transistor (406) to be turned off or on.

6. The relay according to any one of claims 1 to 5, wherein: The slave SSR (452) is arranged to supply power when the master SSR (450) is in one of a diagnostic and disconnected state.

7. The relay according to any one of claims 1 to 6, wherein: The main SSR (450) is a first metal oxide semiconductor field effect transistor MOSFET SSR, and the sub-SSR (452) is a second MOSFET SSR.

8. A battery management system BMS (16), comprising: Solid state relay SSR (150); as well as A processing circuit system (44) comprising a microcontroller unit MCU (180), the processing circuit system (44) being electrically connected to the SSR (150) and configured to: determining a failure mode associated with the MCU (180) based on the one or more parameters; and The SSR (150) is caused to perform one or more actions based on the failure mode without intervention by the MCU (180).

9. The BMS (16) according to claim 8, wherein: The processing circuit system further comprises: A battery cell monitoring unit (CMU) (160) electrically connectable to one or more battery cells; and A power management integrated circuit (PMIC) (190) is in communication with the CMU (160), one or both of the CMU (160) and the PMIC (190) being configured to cause the SSR (150) to perform the one or more actions based on the failure mode.

10. The BMS (16) according to claim 9, wherein: The CMU (160) is configured to determine one or more parameters associated with the one or more battery cells.

11. The BMS (16) according to claim 10, wherein: The MCU (180) is in communication with the CMU (160), and the MCU (180) is configured to determine parameter thresholds associated with the one or more parameters and transmit the parameter thresholds to the CMU (160).

12. The BMS (16) according to any one of claims 9 to 11, wherein: The CMU (160) is configured to determine a fault indication and transmit the fault indication to the MCU (180) and the PMIC (190) to cause the MCU (180) and the PMIC (190) to enter an active operation mode.

13. The BMS (16) according to any one of claims 9 to 12, wherein: The PMIC (190) is configured to determine a failure mode associated with the MCU (180) based on a watchdog process operable to monitor one or more MCU processes.

14. The BMS (16) according to any one of claims 8 to 12, wherein: The processing circuitry (44) further includes a secondary current unit SCU (194) configured to detect an overcurrent condition based on a predetermined hardware current threshold.

15. The BMS (16) according to claim 14, wherein: The SCU (194) is further configured to cause the SSR (150) to perform one or more actions based on the detected overcurrent condition and the predetermined hardware current threshold.

16. The BMS (16) according to any one of claims 8 to 15, wherein: The SSR (150) comprises: Bus connection point (414); Heap connection points (412); and A main solid-state relay SSR (450) electrically connected to the bus connection point (414) and the stack connection point (412), the main SSR (450) comprising: A first measurement point (408) is usable by the BMS (16) to determine a first SSR state.

17. The BMS (16) according to claim 16, wherein: The SSR (150) further comprises: A secondary SSR (452) electrically connected to the bus connection point (414) and the stack connection point (412), the secondary SSR (452) being connected in parallel with the primary SSR (450) and comprising: A second measurement point (410) is used by the BMS (16) to determine a second SSR state.

18. The BMS (16) according to any one of claims 8 to 17, wherein: The one or more actions include one of disabling the SSR (150), enabling the SSR (150), turning off the SSR (150), and turning on the SSR (150).

19. A battery comprising: One or more battery cells (14); A battery management system BMS (16) electrically connected to the one or more battery cells (14), the BMS (16) comprising: a solid state relay SSR (150) electrically connected to the one or more battery cells (14); A processing circuit system (44) comprising a microcontroller unit MCU (180), the processing circuit system (44) being electrically connected to the SSR (150) and configured to: determining a failure mode associated with the MCU (180) based on the one or more parameters; and The SSR (150) is caused to perform one or more actions based on the failure mode without MCU intervention.

20. The battery according to claim 19, wherein One or more of the following conditions are met: The processing circuit system further comprises: a cell monitoring unit (CMU) (160) electrically connectable to one or more battery cells (14) and configured to determine one or more parameters associated with the one or more battery cells (14); and a power management integrated circuit (PMIC) (190) in communication with the CMU (160), one or both of the CMU (160) and the PMIC (190) being configured to cause the SSR (150) to perform the one or more actions based on the fault mode; The MCU (180) is in communication with the CMU (160) and is configured to determine parameter thresholds associated with the one or more parameters and transmit the parameter thresholds to the CMU (160); and The CMU (160) is configured to determine a fault indication and transmit the fault indication to the MCU (180) and the PMIC (190) to cause the MCU (180) and the PMIC (190) to enter an active operation mode.

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