A process method for improving wide-line marks in monocrystalline silicon wafer cutting.

Abstract

This invention discloses a process method for improving wide-line marks in the cutting of monocrystalline silicon wafers, comprising the following steps: S1: deriving the maximum linear velocity V1 based on the linear velocity model of the cutting cycle and Newton's second law; S2: deriving F based on the force model of silicon wafer cutting. 1y S3: Measure the acceleration / deceleration time t for the width of a well-cut texture using steps S1 and S2 above; S4: Calculate the texture width = cutting depth / (cycle * cycle time) based on the cutting process parameter model; S5: Measure the cycle for the width of a well-cut texture using step S4 above; S6: Calculate the texture width = average table speed * (average wire supply + average wire return) / average wire speed using step S4 above and the cutting process parameter model; S7: Measure the table speed and wire speed for a well-cut texture using step S6 above. By analyzing the key parameters affecting the texture marks, optimize the process parameters such as wire speed, table speed, acceleration / deceleration time, and cutting cycle to reduce the texture marks generated during the cutting process.

Description

Technical Field

[0001] This invention belongs to the field of monocrystalline silicon wafer manufacturing technology in the solar photovoltaic industry, and specifically relates to a process method for improving the cutting of wide lines on monocrystalline silicon wafers. Background Technology

[0002] Monocrystalline silicon, a key semiconductor material, has undergone a transformation in its production process from polycrystalline silicon to monocrystalline silicon, primarily achieved through the crystal pulling process. In crystal pulling, molten elemental silicon crystallizes under specific conditions to form monocrystalline silicon, creating columnar silicon ingots. These ingots then need to be divided into smaller blocks for further processing into thin wafers. This cutting process typically employs diamond wire cutting technology. The diamond wire moves in a reciprocating linear motion during the cutting process, while the silicon block slowly sinks and is cut into wafers. To ensure cutting efficiency, a continuous jet of cutting fluid is required to assist the cutting operation. However, existing cutting processes have some shortcomings. First, regarding auxiliary materials, the diamond wire wears down as the silicon ingot is continuously cut, and the concentration of the slurry (a mixture of cutting fluid, pure water, and silicon powder) gradually increases, leading to a decrease in the lubrication and cooling performance of the cutting fluid and the diamond wire's ability to carry the slurry. Second, regarding equipment, changes in slurry concentration require changes in the position and flow rate of the slurry pipe, further affecting the cutting effect. Finally, process parameters such as line speed, table speed, process cycle time, and acceleration / deceleration time all significantly impact dicing quality. The combined effect of these factors makes it difficult to achieve an ideal dicing state, leading to deeper damage on the silicon wafer surface, manifested as an increased proportion of wide line marks. The presence of wide line marks not only reduces the aesthetics of the silicon wafer but, more importantly, affects its functionality and reliability, thus impacting the quality and performance of the final product. Therefore, finding a new process that can effectively reduce or eliminate wide line marks is crucial. This invention is proposed against this backdrop, aiming to improve silicon wafer dicing quality and yield by optimizing the dicing process. Summary of the Invention

[0003] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a process method for improving the cutting of wide lines on monocrystalline silicon wafers. By optimizing the cutting process, the cutting quality and yield of silicon wafers can be improved.

[0004] To solve the above problems, the technical solution adopted by the present invention is as follows: A process method for improving wide-line marks in the cutting of monocrystalline silicon wafers, comprising the following steps:

[0005] S1: The maximum linear velocity V1 is obtained based on the cutting period linear velocity model and Newton's second law;

[0006] S2: Based on the stress model of silicon wafer cutting, F is derived. 1y ;

[0007] S3: Measure the acceleration and deceleration time t for the width of the well-cut texture through the above steps S1 and S2;

[0008] S4: Based on the cutting process parameter model, the texture width = cutting depth / (cycle * cycle time);

[0009] S5: Measure the period of the width of the well-cut texture through the above step S4;

[0010] S6: Based on the above step S4 and the cutting process parameter model, the texture width is obtained as: average table speed * (average wire supply + average wire return) / average wire speed.

[0011] S7: Measure the table speed and linear speed for cutting well-defined patterns using the steps above, S6.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: By analyzing the key parameters affecting the etch marks, the present invention proposes to optimize the etch process parameters such as line speed, table speed, acceleration and deceleration time, and etch cycle, which effectively reduces the etch marks generated during the etch process, thereby improving the overall quality of silicon wafers, reducing production costs, and also helping to expand the operating range of the etch process, making the process more stable and reliable.

[0013] In the above-described process method, the silicon wafer cutting force model in step S2 is the instantaneous force analysis of the diamond wire oscillation.

[0014] In the above-described process, the texture width in step S4 is equal to the cutting depth and the number of cycles.

[0015] In the above process, the number of cycles = cycle time * [average line speed / (average wire supply + average return wire)].

[0016] In the above-described process, the cycle time in step S4 is equal to the cutting depth and the average table speed.

[0017] In the above-described process, the texture width in step S6 is equal to the average table speed divided by the cycle.

[0018] In the above-mentioned process method, the linear speed is 2100m / min, the table speed range is 2300um / min-2500um / min, and the cycle range is 1.25n / min-1.38n / min.

[0019] In the above process method, the cycle is 1.28 n / min, the table speed range is 2300um / min-2500um / min, and the linear speed setting range is 2100m / min-2300m / min.

[0020] In the above-described process, the acceleration / deceleration time t is 5.5s-6.5s. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating the process steps of an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the acceleration and deceleration forces acting on the diamond wire of the present invention;

[0023] Figure 3 This is a schematic diagram of the force exerted on the diamond wire during its swing in this invention.

[0024] Figure 4 This is a schematic diagram illustrating the force analysis of the diamond wire during its oscillation in this invention.

[0025] The symbols in the attached diagram are explained as follows: 100 diamond wire, 200 silicon wafer. Detailed Implementation

[0026] The embodiments of the present invention are described in detail below, with reference to... Figures 1 to 4 The present invention provides a process method for improving the cutting of wide grooves on a 200mm monocrystalline silicon wafer, comprising the following steps:

[0027] S1: The maximum linear velocity V1 is obtained based on the cutting period linear velocity model and Newton's second law;

[0028] S2: Based on the stress model of silicon wafer cutting, F is derived. 1y ;

[0029] S3: Measure the acceleration and deceleration time t for the width of the well-cut texture through the above steps S1 and S2;

[0030] S4: Based on the cutting process parameter model, the texture width = cutting depth / (cycle * cycle time);

[0031] S5: Measure the period of the width of the well-cut texture through the above step S4;

[0032] S6: Based on the above steps S4 and the cutting process parameter model, the texture width is calculated as: average table speed * (average wire supply + average wire return) / average wire speed.

[0033] S7: Measure the table speed and linear speed for cutting well-defined patterns using the steps above, S6.

[0034] This invention analyzes the key parameters affecting line marks and proposes optimizations to cutting process parameters such as line speed, table speed, acceleration / deceleration time, and cutting cycle. This effectively reduces line marks generated during the cutting process, thereby improving the overall quality of silicon wafers, reducing production costs, and also helping to expand the operating range of the cutting process, making the process more stable and reliable.

[0035] Furthermore, referring to Figure 1 The cutting cycle of the monocrystalline silicon wafer 200 is shown in the figure. The cutting principle of monocrystalline silicon is as follows: a high-strength fine steel wire or resin wire coated with abrasive (usually diamond powder, hereinafter referred to as diamond wire 100) is used as a cutting tool. The diamond wire 100 moves back and forth in a guide system, while the abrasive is transported to the cutting area by high-pressure water or other liquids. Under the action of mechanical force, the diamond wire 100 drives the abrasive to grind the monocrystalline silicon, thereby achieving cutting. Based on the above cutting principle and the cutting of monocrystalline silicon wafer 200... During the period, when the linear velocity accelerates from 0 to V1, v1 = at and F = ma, thus v1 = (F / m) * t. Since the change in linear velocity within one period consists of uniform acceleration (deceleration), uniform velocity, and pause, under relatively ideal conditions, during the uniform velocity process, the force F on the diamond wire 100 is the same as the dynamic friction resistance f. However, during the uniform acceleration and deceleration process, the diamond wire 100 not only has to overcome the dynamic friction resistance f but also needs to provide an additional force greater than f to achieve uniform acceleration (deceleration). Therefore, the force F on the diamond wire 100 during acceleration and deceleration is much greater than that during the uniform velocity process. Therefore, this application mainly focuses on the analysis of the force F on the diamond wire 100 during acceleration and deceleration, referring to... Figure 2 and Figure 3 During the cutting process of diamond wire 100, due to tension fluctuations and interference from the slurry, the force F applied during acceleration and deceleration will fluctuate. (Combined with...) Figure 2 Force diagram, the force F is always along the direction of the diamond line 100, refer to Figure 3 At the instant of the swing, if the force F decreases, refer to Figure 4If the acceleration / deceleration time t increases, the force F1y acting on the surface of silicon wafer 200 will decrease accordingly, thus reducing the force acting on the surface of silicon wafer 200 and improving the effect on wide groove lines. Of course, this invention is not limited to a specific value of the acceleration / deceleration time t. Preferably, when the acceleration / deceleration time t is 5.5s-6.5s, the improvement effect on groove lines is significant. Furthermore, the force model for cutting silicon wafer 200 in step S2 is a force analysis of the diamond wire 100 during its oscillation. Therefore, when other conditions remain unchanged, increasing the acceleration / deceleration time corresponds to a decrease in the force F, meaning that appropriately increasing the acceleration / deceleration time will correspondingly reduce the force acting on the surface of silicon wafer 200, improving the effect on wide groove lines. Thus, through steps S1 and S2, the acceleration / deceleration time t for achieving a well-cut groove width is measured.

[0036] Furthermore, based on the relationship between linear speed, table speed, texture width, and cycle time, a silicon wafer slicing model 200 is obtained. From this model, we derive: Texture width = Cutting depth / Number of cycles, and Cycle time = Number of cycles / Cycle time. Therefore, Texture width = Cutting depth / (Cycle time * Cycle time). Further, combining these formulas with: Number of cycles = Cycle time * [Average linear speed / (Average wire supply + Average wire return)] and Cycle time = Cutting depth / Average table speed, we obtain: Texture width = Average table speed / The cycle and texture width = average table speed * (average wire supply + average return wire) / average line speed. Therefore, when the above formula is: texture width = average table speed / cycle, under the condition that all other conditions remain unchanged, appropriately reducing the table speed and increasing the cycle can reduce the texture width. That is, appropriate low table speed and high line speed have an improving effect on wide texture lines. Preferably, the line speed is 2100m / min, the table speed range is 2300um / min-2500um / min, and the cycle range is 1.25n / min-1.38n / min, and the improvement effect on texture width is more obvious. Furthermore, when all conditions in the formula: Texture width = Average speed * (Average wire supply + Average return wire) / Average wire speed remain unchanged, appropriately reducing the speed and increasing the wire speed cycle can reduce the texture width. That is, appropriate low speed and high wire speed have an improving effect on wide texture lines. Preferably, when the cycle is 1.28n / min, the speed range is 2300um / min-2500um / min, and the wire speed setting range is 2100m / min-2300m / min, the improvement effect on texture lines is more obvious.

[0037] It should be noted that in the description of this invention, any descriptions of orientation, such as up, down, front, back, left, right, etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the purpose of facilitating the description of this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and should not be construed as a limitation of this invention.

[0038] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number, while "above," "below," "within," etc. are understood to include the stated number. If "first" or "second" is mentioned, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0039] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0040] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A process method for improving wide-line marks during the cutting of monocrystalline silicon wafers, characterized in that, Includes the following steps: S1: The maximum linear velocity V1 is obtained based on the cutting period linear velocity model and Newton's second law; S2: Based on the stress model of silicon wafer cutting, the following is derived: ; S3: Measure the acceleration and deceleration time t for the width of the well-cut texture through the above steps S1 and S2; S4: Based on the cutting process parameter model, the texture width = cutting depth / (cycle * cycle time). S5: Measure the period of the width of the well-cut texture through the above step S4; S6: Based on the above step S4 and the cutting process parameter model, the texture width is calculated as: average table speed * (average wire supply + average wire return) / average wire speed. S7: Measure the table speed and linear speed of the table through the above step S6 to cut a good texture. The silicon wafer cutting force model in step S2 is a stress analysis of the instantaneous oscillation of the diamond wire. The texture width in step S4 is equal to the cutting depth and the number of cycles; the acceleration / deceleration time t is 5.5s-6.5s.

2. The process method according to claim 1, characterized in that, The cycle = number of cycles / cycle time.

3. The process method according to claim 2, characterized in that, The number of cycles = cycle time * [average line speed / (average line supply + average return line quantity)].

4. The process method according to claim 3, characterized in that, In step S4, the cycle time is equal to the cutting depth and the average table speed.

5. The process method according to claim 4, characterized in that, In step S6, the texture width is equal to the average speed of the table / the cycle.

6. The process method according to claim 5, characterized in that, The linear velocity is 2100. The speed range is 2300. -2500 The period range is 1.

25. -1.38 .

7. The process method according to claim 6, characterized in that, The period is 1.

28. The speed range is 2300. -2500 The linear speed setting range is 2100. -2300 .

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