Power Devices

Abstract

The power device provided by the present application has a semiconductor epitaxial wafer comprising, in an active region, a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked in a bottom-to-top direction; the second epitaxial layer comprises a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of a first conductivity type, and the second doped region is of a second conductivity type; thereby, when the device is reverse biased, the first doped region and the second doped region form a depletion region, thereby increasing the withstand voltage of the semiconductor epitaxial wafer when the device is reverse biased, and further arranging that the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap, thereby increasing the current path length, and further increasing the withstand voltage of the semiconductor epitaxial wafer when the device is reverse biased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to power devices. Background Art

[0002] Power devices are electronic devices used to control and regulate electricity. Taking MOSFET (metal oxide semiconductor field effect transistor) as an example, MOSFET is a commonly used power device with the characteristics of high voltage, high electric field and high current, as well as the advantages of high speed, low power consumption and reliability. It is widely used in electronic equipment and integrated circuits.

[0003] Among them, the breakdown voltage (Breakdown Voltage, BV) and on-state resistance (On-State Resistance, R ON ) are important parameters for evaluating the performance of power devices. Among them, the breakdown voltage refers to the maximum voltage that a power device can withstand under reverse bias conditions. The on-resistance refers to the resistance between the two ends of a power device when it is in the on state under forward bias conditions. The smaller the on-resistance, the lower the power consumption of the device in the on state. These two parameters are directly related to the reliability and efficiency of power devices in practical applications. At present, if you want to improve the reverse withstand voltage (breakdown voltage) of the device, the on-resistance of the device will also increase significantly when it is forward biased.

[0004] The prior art provides a solution, in which a sub-epitaxial layer with different conductivity types is arranged in the epitaxial layer, and the sub-epitaxial layer includes doped regions with a first conductivity type and doped regions with a second conductivity type arranged alternately, so that when the device is forward biased, a grid-like current path is formed when the current flows through the sub-epitaxial layer, thereby improving the modulation performance of the device current distribution. Furthermore, other prior arts also disclose that the sub-epitaxial layer with doped regions with different conductivity types can also be multiple layers, and the arrangement of the multiple sub-epitaxial layers is the same.

[0005] However, the solution provided by the above prior art is not effective in improving the reverse withstand voltage of the device and needs to be further improved. Summary of the invention

[0006] The power device provided in the present application can solve the problem that when the reverse withstand voltage of the device is improved, the on-resistance is also greatly increased.

[0007] In order to solve the above technical problems, a technical solution adopted in the present application is to provide a power device, including:

[0008] substrate;

[0009] A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions;

[0010] Among them, one side of the substrate is defined as the bottom, and one side of the semiconductor cell is defined as the top; in the active area, the semiconductor epitaxial wafer also includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap.

[0011] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a power device, comprising:

[0012] substrate;

[0013] A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, the semiconductor cells include connected well regions, well region contact regions and source regions; in the active area, the semiconductor epitaxial wafer includes a drift layer, the drift layer is located between the substrate and the semiconductor cells;

[0014] Wherein, in the active area, the semiconductor epitaxial wafer also includes a plurality of charge depletion layers stacked between the drift layer and the semiconductor cell; each of the charge depletion layers includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located on a side of the second epitaxial layer away from the drift layer; the first epitaxial layer and the drift layer have the same conductivity type; the second epitaxial layer has a plurality of injection regions arranged at intervals, and the area of ​​the second epitaxial layer excluding the injection regions is divided into a plurality of epitaxial regions arranged at intervals; one of the second epitaxial layer and the injection region has the same conductivity type as the first epitaxial layer, and the other has a different conductivity type from the first epitaxial layer; the projections of the plurality of injection regions in two adjacent second epitaxial layers on the substrate do not completely overlap.

[0015] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a power device, comprising:

[0016] substrate;

[0017] A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions;

[0018] Among them, one side of the substrate is defined as the bottom, and one side of the semiconductor cell is defined as the top; in the active area, the semiconductor epitaxial wafer also includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; a plurality of junction field effect regions are formed in the second epitaxial layer with intervals, the first epitaxial layer and the junction field effect region are of the first conductivity type, and the second epitaxial layer is of the second conductivity type; the projections of the plurality of junction field effect regions in two adjacent second epitaxial layers on the substrate do not completely overlap.

[0019] Different from the prior art, the beneficial effect of the present application is that in the power device provided by the present application, in the active area, the semiconductor epitaxial wafer also includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; in this way, when the device is reverse biased, the first doped region and the second doped region form a depletion region, so that the withstand voltage of the semiconductor epitaxial wafer when the device is reverse biased can be increased, and the power device provided by the present application will not increase the on-resistance of the device. Furthermore, the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate are not completely overlapped, which can increase the length of the current path, thereby further increasing the withstand voltage of the semiconductor epitaxial wafer when the device is reverse biased. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0021] Figure 1 It is a schematic diagram of the structure of a power device in the related art;

[0022] Figure 2 A schematic diagram of a portion of the structure of an active region of a power device provided in the first embodiment of the present application;

[0023] Figure 3 A schematic diagram of a portion of the structure of an active region of a power device provided in a second embodiment of the present application;

[0024] Figure 4 A schematic diagram of a portion of the structure of an active region of a power device provided in a third embodiment of the present application;

[0025] Figure 5 A schematic diagram of a portion of the structure of a second epitaxial layer in a power device provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of a portion of the structure of a second epitaxial layer in a power device provided in another embodiment of the present application;

[0027] Figure 7 A schematic diagram of a portion of the structure of an active region of a power device provided in a fourth embodiment of the present application;

[0028] Figure 8 A schematic diagram of a portion of the structure of an active region of a power device provided in a fifth embodiment of the present application;

[0029] Fig. 9 A schematic diagram of a portion of the structure of an active region of a power device provided in a sixth embodiment of the present application;

[0030] Fig.10 A schematic diagram of a portion of the structure of an active region of a power device provided in a seventh embodiment of the present application;

[0031] Fig.11 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in the first embodiment of the present application;

[0032] Fig.12 for Fig.11 A partial structural perspective view of a power device provided at another viewing angle;

[0033] Fig.13 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a second embodiment of the present application;

[0034] Fig.14 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a third embodiment of the present application;

[0035] Fig.15 for Fig.14 A partial structural perspective view of a power device provided at another viewing angle;

[0036] Fig.16 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a fourth embodiment of the present application;

[0037] Fig.17 for Fig.16A partial structural perspective view of a power device provided at another viewing angle;

[0038] Fig.18 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in the fifth embodiment of the present application.

[0039] Description of labels:

[0040] Substrate 10; semiconductor epitaxial wafer 20; semiconductor cell 30; well region 31; well region contact region 32; source region 33; first epitaxial layer 40; second epitaxial layer 50; first doped region 51; second doped region 52; electrode structure 60; gate electrode 61; source electrode 62; drain electrode 63; conductive connection region 70; transition region 80;

[0041] The first gap H1; the second gap H2. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] Take the power device MOSFET (metal oxide semiconductor field effect transistor) as an example, see Figure 1 , Figure 1 is a schematic diagram of the structure of a power device in the related art; wherein, Figure 1 The power device shown includes a substrate and a semiconductor epitaxial wafer. The semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active region and an edge terminal region surrounding the active region; in the active region, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, and the figure takes a semiconductor cell as an example, and the plurality of semiconductor cells extend from the surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and each semiconductor cell includes a connected well region, a well region contact region and a source region, and in the figure, each semiconductor cell includes two well regions, two well region contact regions and two source regions.

[0046] The area between the semiconductor cell and the substrate can be called the drift region of the device, where: Figure 1 When the power device shown is reverse biased, it mainly relies on the depletion region formed by the reverse bias of the drift region to bear the withstand voltage. In order to improve the withstand voltage of the device, it is necessary to reduce the doping concentration of the drift region or increase the thickness of the drift region, which will cause the on-resistance of the drift region to increase significantly when the device is forward biased.

[0047] Therefore, how to increase the withstand voltage of the device when it is reverse biased without increasing the on-resistance of the device is an urgent problem to be solved in the art.

[0048] See also Figure 2 and Figure 3 , Figure 2 A schematic diagram of a portion of the structure of an active region of a power device provided in the first embodiment of the present application; Figure 3 A schematic diagram of a portion of the structure of the active region of a power device provided in the second embodiment of the present application.

[0049] In order to solve the above technical problems, the embodiment of the present application provides a power device, which includes a substrate 10 and a semiconductor epitaxial wafer 20. The semiconductor epitaxial wafer 20 is arranged on the substrate 10; the semiconductor epitaxial wafer 20 includes an active region; in the active region, the semiconductor epitaxial wafer 20 has a plurality of semiconductor cells 30 arranged at intervals, and the plurality of semiconductor cells 30 all extend from the surface of the semiconductor epitaxial wafer 20 away from the substrate 10 toward the substrate 10, and the semiconductor cells 30 include a well region 31, a well region contact region 32 and a source region 33 connected to each other.

[0050] Among them, one side of the substrate 10 is defined as the bottom, and one side of the semiconductor cell 30 is defined as the top; in the active area, the semiconductor epitaxial wafer 20 also includes a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 alternately stacked from the bottom to the top; the second epitaxial layer 50 includes a plurality of first doped regions 51 and a plurality of second doped regions 52; the first epitaxial layer 40 and the first doped regions 51 are of the first conductivity type, and the second doped regions 52 are of the second conductivity type; the projections of the plurality of first doped regions 51 in two adjacent second epitaxial layers 50 on the substrate 10 do not completely overlap.

[0051] The material of the substrate 10 includes, but is not limited to, one of silicon, silicon carbide, and gallium nitride, which is not limited here.

[0052] In the figure, a semiconductor cell 30 is taken as an example, and each semiconductor cell 30 includes two well regions 31 , two well region contact regions 32 and two source regions 33 .

[0053] Among them, the well region 31 and the well region contact region 32 are of the second conductivity type, and the doping concentration of the well region contact region 32 is greater than the doping concentration of the well region 31 ; the source region 33 is of the first conductivity type, and the doping concentration of the source region 33 is greater than the doping concentration of the first epitaxial layer 40 .

[0054] It should be noted that the semiconductor cell 30 shown in the figure is only an example, and its structure and function may be consistent with the semiconductor cell 30 of the power device in the prior art. For example, the semiconductor cell 30 may be a strip cell, a square cell, a hexagonal cell, etc., which will not be elaborated here.

[0055] Among them, one of the first conductivity type and the second conductivity type is N type, and the other is P type. For the convenience of description, in the embodiment of the present application, the first conductivity type is N type, and the second conductivity type is P type.

[0056] Specifically, in the power device provided by the present application, in the active area, the semiconductor epitaxial wafer 20 includes a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 alternately stacked in a bottom-to-top direction; the second epitaxial layer 50 includes a plurality of first doped regions 51 and a plurality of second doped regions 52 of different conductivity types; thereby, when the device is forward biased, conduction is achieved through the first epitaxial layer 40 and the first doped region 51; when the device is reverse biased, the first doped region 51 and the second doped region 52 form a depletion region, so that the P-type second doped region 52 depletes the charge of the N-type first doped region 51, and the entire second epitaxial layer 50 becomes a similar "zero-doped" region, thereby increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased; and compared with the prior art method of increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased by reducing the doping concentration of the drift region and / or increasing the thickness of the drift region, the power device provided by the present application will not increase the on-resistance of the device.

[0057] In the embodiment of the present application, the projections of the plurality of first doped regions 51 in two adjacent second epitaxial layers 50 on the substrate 10 do not completely overlap, thereby increasing the current path length and thus increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased.

[0058] It can be understood that in the embodiment of the present application, the first doped region 51 can be understood as a junction field effect region (JFET region) arranged in the second epitaxial layer 50, and the second doped region 52 is a region of the second epitaxial layer 50 excluding the junction field effect region.

[0059] Alternatively, it can also be understood that the bottom first epitaxial layer 40 can be used as a drift layer of the device; and the first epitaxial layer 40 and the second epitaxial layer 50 excluding the bottom first epitaxial layer 40 form a plurality of charge depletion layers.

[0060] The drift layer is stacked with multiple charge depletion layers, each charge depletion layer includes a first epitaxial layer 40 and a second epitaxial layer 50, the first epitaxial layer 40 is located on the side of the second epitaxial layer 50 away from the drift layer, wherein one of the first doped region 51 and the second doped region 52 in the second epitaxial layer 50 is an injection region, and the other is a region of the second epitaxial layer 50 excluding the injection region as an epitaxial region; wherein the region of the second epitaxial layer 50 excluding the injection region is divided into multiple epitaxial regions arranged at intervals, one of the second epitaxial layer 50 and the injection region has the same conductivity type as the first epitaxial layer 40, and the other has a different conductivity type from the first epitaxial layer 40.

[0061] For example, the implanted region has the same conductivity type as the first epitaxial layer 40, and the second epitaxial layer 50 has a different conductivity type from the first epitaxial layer 40. The first epitaxial layer 40 and the second epitaxial layer 50 are both formed by epitaxial growth, and the implanted region is formed in the second epitaxial layer 50 by ion implantation, and the implanted region can be understood as the first doped region 51.

[0062] For another example, the implanted region has a different conductivity type from the first epitaxial layer 40, and the second epitaxial layer 50 has the same conductivity type as the first epitaxial layer 40. The first epitaxial layer 40 and the second epitaxial layer 50 are both formed by epitaxial growth, and the implanted region is formed in the second epitaxial layer 50 by ion implantation, and the implanted region can be understood as the second doped region 52.

[0063] Specifically, by arranging a plurality of stacked charge depletion layers between the drift layer and the semiconductor cell 30, the withstand voltage of the device during reverse bias can be improved. This structure is suitable for ultra-high voltage devices, such as power devices with a withstand voltage rating greater than 1200 volts, such as 3000 volts, 5000 volts, 8000 volts, etc., which are not limited here.

[0064] For example, see Figure 2 , the projections of the plurality of first doping regions 51 of two adjacent second epitaxial layers 50 on the substrate 10 do not overlap at all. Figure 3 , the projections of the first doping regions 51 of two adjacent second epitaxial layers 50 on the substrate 10 partially overlap, and the other parts do not overlap. In this way, by changing the arrangement of the first doping regions 51 in two adjacent second epitaxial layers 50, the current path length is increased, thereby increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased.

[0065] Since the second doping region 52 depletes the charge of the first doping region 51, the width of the second doping region 52 is greater than the width of the first doping region 51. When the projections of the multiple first doping regions 51 of two adjacent second epitaxial layers 50 on the substrate 10 are misaligned, the projections of the multiple second doping regions 52 of two adjacent second epitaxial layers 50 on the substrate 10 partially overlap and are partially misaligned.

[0066] In some embodiments, the power device may be a planar gate power device or a trench gate power device. For ease of description, the present application embodiment takes the trench gate power device as an example. Figure 2 In the trench gate power device, the power device further includes an electrode structure 60, and the electrode structure 60 includes a gate electrode 61, a source electrode 62, and a drain electrode 63. The gate electrode 61, the source electrode 62, and the drain electrode 63 are used to be electrically connected to an external circuit.

[0067] The gate electrode 61 is disposed in the semiconductor epitaxial wafer 20 and is located on the top of the semiconductor epitaxial wafer 20 , and the gate electrode 61 is located between two adjacent well regions 31 in the same semiconductor cell 30 ;

[0068] The source electrode 62 is disposed on a surface of the semiconductor epitaxial wafer 20 away from the substrate 10 , and the source electrode 62 is electrically connected to the source region 33 and the well contact region 32 , and is insulated from the gate electrode 61 .

[0069] The drain electrode 63 is disposed on a surface of the substrate 10 away from the semiconductor epitaxial wafer 20 .

[0070] Specifically, the power device is designed to be a trench gate power device. Trench gate power devices have significant advantages over planar gate power devices, including lower on-resistance, higher breakdown voltage, better switching performance, lower parasitic capacitance, better heat dissipation performance, smaller chip area, higher reliability and easier high-density integration, making them suitable for application scenarios requiring high performance and high reliability.

[0071] See also Figure 4 , Figure 4 A partial structural schematic diagram of the active area of ​​a power device provided in the third embodiment of the present application. In some embodiments, the semiconductor epitaxial wafer 20 also includes a conductive connection area 70, which extends along the thickness direction of the semiconductor epitaxial wafer 20 and electrically connects the second doping area 52 of at least a portion of the second epitaxial layer 50 to the well contact area 32; the conductive connection area 70 and the well contact area 32 are both of the second conductivity type; the conductive connection area 70 is an ion implantation area.

[0072] The thickness direction of the semiconductor epitaxial wafer 20 is the same as the direction from the top to the bottom of the semiconductor epitaxial wafer 20, and the conductive connection region 70 is formed in the first epitaxial layer 40 by ion implantation. The conductive connection region 70 can be located in different first epitaxial layers 40, and the second doped region 52 in the second epitaxial layer 50 adjacent to the conductive connection region 70 is electrically connected.

[0073] Specifically, the well contact region 32 is electrically connected to the plurality of second doped regions 52 through the conductive connection region 70, and the plurality of second doped regions 52 are then electrically connected to the source electrode 62 of the device, so that when the device is reverse biased, the width of the depletion region is increased, the built-in electric field is increased, and the withstand voltage of the device when reverse biased is increased. It can be understood that if the plurality of second doped regions 52 are not electrically connected to the source electrode 62, the second doped regions 52 are floating, and the withstand voltage effect of the device when reverse biased is relatively poor.

[0074] See also Figure 5 , Figure 5A schematic diagram of a partial structure of a second epitaxial layer in a power device provided in an embodiment of the present application; in some embodiments, in the same second epitaxial layer 50, a plurality of first doping regions 51 and a plurality of second doping regions 52 are alternately arranged along the layout direction of the semiconductor cell 30; a first doping region 51 has a first notch H1, and two adjacent second doping regions 52 are connected via the first notch H1 on the first doping region 51.

[0075] In the embodiment of the present application, the semiconductor cells 30 are arranged in the first direction X.

[0076] Specifically, multiple second doped regions 52 in the same second epitaxial layer 50 are interconnected. As long as one second doped region 52 is electrically connected to the well contact region 32 through the conductive connection region 70 (i.e., electrically connected to the source electrode 62 of the device), multiple second doped regions 52 are electrically connected to the source electrode 62 of the device, thereby reducing the difficulty of manufacturing the conductive connection region 70. At the same time, this structure serves to increase the voltage resistance of the semiconductor epitaxial wafer 20 when the device is reverse biased.

[0077] See also Figure 6 , Figure 6 A partial structural diagram of a second epitaxial layer in a power device provided in another embodiment of the present application; Figure 5 What is different from the figure is that in other embodiments, in the same second epitaxial layer 50 , the first notch H1 is not provided on the first doping region 51 , and two adjacent second doping regions 52 are not connected.

[0078] join Figure 7 , Figure 7 A partial structural schematic diagram of the active area of ​​a power device provided in the fourth embodiment of the present application; in some embodiments, along the direction from top to bottom, the width of the first doped region 51 in the multiple second epitaxial layers 50 tends to increase and the doping concentration tends to decrease.

[0079] It can be understood that, since the second epitaxial layer 50 is composed of the first doping region 51 and the second doping region 52, in this embodiment, along the direction from top to bottom, the width of the second doping region 52 in the plurality of second epitaxial layers 50 tends to decrease. In this embodiment, the doping concentration of the second doping region 52 in the plurality of second epitaxial layers 50 can tend to increase or remain unchanged, as long as the first doping region 51 can be turned on when the device is forward biased; and when the device is reverse biased, the second doping region 52 can deplete the charge of the first doping region 51 and pinch off the first doping region 51.

[0080] Among them, in the embodiment of the present application, the width of the first doping region 51 refers to the width of each first doping region 51; "increasing trend" can be a gradual increase (for example, a linear increase) or a step-by-step increase; "decreasing trend" can be a gradual decrease (for example, a linear decrease) or a step-by-step decrease; no limitation is made here.

[0081] It can be understood that, when the doping concentration remains unchanged, the width of the first doping regions 51 in the plurality of second epitaxial layers 50 is designed to increase along the direction from top to bottom, which is equivalent to the resistance of the plurality of first doping regions 51 decreasing; when the width remains unchanged, the concentration of the first doping regions 51 in the plurality of second epitaxial layers 50 is designed to decrease along the direction from top to bottom, which is equivalent to the resistance of the plurality of first doping regions 51 increasing. Therefore, by reasonably designing the matching relationship between the width of the first doping region 51 and the doping concentration, the resistance of the first doping regions 51 in the plurality of second epitaxial layers 50 remains unchanged or decreases within a preset range along the direction from top to bottom, thereby reducing the on-resistance as much as possible while increasing the breakdown voltage of the device. As the width of the first doped region 51 increases, the width of the second doped region 52 will decrease. By increasing the doping concentration of the second doped region 52, when the device is reverse biased, the P-type second doped region 52 can deplete the charge of the N-type first doped region 51, and the entire second epitaxial layer 50 becomes a "zero-doped" region, thereby ensuring the voltage resistance of the device when reverse biased.

[0082] See also Figure 8 , Figure 8 A partial structural schematic diagram of the active area of ​​a power device provided in the fifth embodiment of the present application; in some embodiments, along the direction from top to bottom, the width of the first doped region 51 in the multiple second epitaxial layers 50 tends to decrease and the doping concentration tends to increase.

[0083] It can be understood that, since the second epitaxial layer 50 is composed of the first doping region 51 and the second doping region 52, in this embodiment, along the direction from top to bottom, the width of the second doping region 52 in the plurality of second epitaxial layers 50 increases. Furthermore, the doping concentration of the second doping region 52 in the plurality of second epitaxial layers 50 decreases.

[0084] It can be understood that, when the doping concentration remains unchanged, the width of the first doping regions 51 in the plurality of second epitaxial layers 50 is designed to decrease along the direction from top to bottom, which is equivalent to the resistance of the plurality of first doping regions 51 increasing; when the width remains unchanged, the concentration of the first doping regions 51 in the plurality of second epitaxial layers 50 is designed to increase along the direction from top to bottom, which is equivalent to the resistance of the plurality of first doping regions 51 decreasing. Therefore, by reasonably designing the matching relationship between the width of the first doping region 51 and the doping concentration, the resistance of the first doping regions 51 in the plurality of second epitaxial layers 50 remains unchanged or decreases within a preset range along the direction from top to bottom, thereby reducing the on-resistance as much as possible while increasing the breakdown voltage of the device.

[0085] See also Figure 2 and Figure 6 In some embodiments, in the same second epitaxial layer 50 , a plurality of first doping regions 51 and a plurality of second doping regions 52 are alternately arranged along the layout direction of the semiconductor cell 30 , and adjacent first doping regions 51 and second doping regions 52 form a period.

[0086] In the embodiment of the present application, the arrangement direction of the plurality of semiconductor cells 30 is spaced apart in the first direction X, and each semiconductor cell 30 is extended along the second direction Y. The first direction X is perpendicular to the second direction Y, and both the first direction X and the second direction Y are perpendicular to the thickness direction of the semiconductor epitaxial wafer 20.

[0087] The extension direction of the first doping region 51 and the second doping region 52 is the same as the extension direction of the semiconductor cell 30. In each second epitaxial layer 50, the number of the cycles formed by the first doping region 51 and the second doping region 52 may be one or more.

[0088] By forming the first doping region 51 and the second doping region 52 into multiple periods, the manufacturing process can be simplified, the current path can be further optimized, and the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased can be increased.

[0089] See also Figure 3 and Fig. 9 , Fig. 9 A partial structural schematic diagram of the active area of ​​a power device provided in the sixth embodiment of the present application; along the direction from top to bottom, the number of periods formed by the first doping regions 51 and the second doping regions 52 in the multiple second epitaxial layers 50 shows an increasing trend or remains unchanged.

[0090] Among them, see Figure 3In the direction from top to bottom, the number of periods in the plurality of second epitaxial layers 50 may remain unchanged. For example, the number of periods in each second epitaxial layer 50 is 2, 5, 7 or other numbers, which are not limited here.

[0091] Alternatively, see Fig. 9 In the direction from top to bottom, the number of periods in the plurality of second epitaxial layers 50 may increase. For example, in the direction from top to bottom, the number of periods in the plurality of second epitaxial layers 50 are 2, 3, 4, and 5, respectively.

[0092] It can be understood that in other embodiments, the number of periods in the multiple second epitaxial layers 50 can increase periodically along the direction from top to bottom. For example, the number of periods in the multiple second epitaxial layers 50 along the direction from top to bottom is 2, 3, 4, 2, 3, 4, 2, 3, 4 respectively.

[0093] Specifically, along the direction from top to bottom, the number of cycles formed by the first doping regions 51 and the second doping regions 52 in the multiple second epitaxial layers 50 tends to increase, thereby optimizing the current path and increasing the current conduction path under the same thickness conditions, thereby increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased.

[0094] In some embodiments, the resistance of the plurality of first epitaxial layers 40 decreases or remains constant along a direction from top to bottom.

[0095] For example, along the direction from top to bottom, the resistance of the plurality of first epitaxial layers 40 gradually decreases. For another example, along the direction from top to bottom, the resistance of the plurality of first epitaxial layers 40 decreases in a step-like manner. For another example, along the direction from top to bottom, the resistance of the plurality of first epitaxial layers 40 remains unchanged. This is not limited here.

[0096] The design method in which the resistance of the multiple first epitaxial layers 40 tends to decrease along the direction from top to bottom includes but is not limited to: the thickness of the multiple first epitaxial layers 40 tends to decrease along the direction from top to bottom; or, the doping concentration of the multiple first epitaxial layers 40 tends to increase along the direction from top to bottom.

[0097] Specifically, by setting the resistance of the plurality of first epitaxial layers 40 to decrease from the top to the bottom, the on-resistance of the device can be reduced when the device is forward biased. And through reasonable design and optimization, the on-resistance can be reduced as much as possible while the breakdown voltage of the device is increased, thereby meeting the needs of different application scenarios. In other words, by designing the resistance of the plurality of first epitaxial layers 40 to decrease or remain unchanged, the purpose is to reduce the R SP (Specific on-resistance).

[0098] In some embodiments, the thicknesses of the plurality of first epitaxial layers 40 may be the same or different, which is not limited herein.

[0099] Among them, see Fig.10 , Fig.10 A partial structural schematic diagram of an active region of a power device provided in the seventh embodiment of the present application; in some embodiments, the thickness of the first epitaxial layer 40 located at the bottom is greater than the thickness of the remaining single first epitaxial layers 40 .

[0100] It can be understood that in this embodiment, the first epitaxial layer 40 located at the bottom serves as a drift layer, and the thickness of the drift layer is greater than the thickness of the remaining single first epitaxial layer 40 .

[0101] For example, the thickness of the first epitaxial layer 40 at the bottom is greater than the thickness of the remaining single first epitaxial layers 40, and the thickness of the remaining single first epitaxial layers 40 gradually decreases from the top to the bottom, so that the resistance tends to decrease. Specifically, the ratio of the thickness of the first epitaxial layer 40 at the bottom to the total thickness of the multiple first epitaxial layers 40 can be adjusted according to the withstand voltage design of the device.

[0102] For another example, the first epitaxial layer 40 at the bottom can be used as the drift region of the device, and the first epitaxial layer 40 and the second epitaxial layer 50 except the first epitaxial layer 40 at the bottom can be used together as the charge depletion region. The thickness of the first epitaxial layer 40 at the bottom can be the same as the thickness of the drift region of the existing device, and the charge depletion region is further provided to improve the withstand voltage of the device when it is reverse biased. This structure is suitable for ultra-high voltage devices, such as power devices with a withstand voltage rating greater than 1200 volts, such as 3000 volts, 5000 volts, 8000 volts, etc., which are not limited here.

[0103] In some embodiments, the doping concentration of the first doping region 51 is greater than the doping concentration of the first epitaxial layer 40 .

[0104] Specifically, when the device is forward biased, the current passes through the first epitaxial layer 40 and the first doping region 51, and the doping concentration of the first doping region 51 is higher, which means that the on-resistance of the first doping region 51 is lower, thereby greatly reducing the on-resistance of the semiconductor epitaxial wafer 20 region between the semiconductor cell 30 and the substrate 10. In addition, under the same on-resistance, the higher the doping concentration of the first doping region 51, the smaller its width can be made, thereby reducing the size of the semiconductor cell 30 and the device. In other words, the doping concentration of the first doping region 51 is increased because the higher the doping concentration of the first doping region 51, the smaller the width of the first doping region 51 can be, which is beneficial to reducing the cell pitch. The smaller the cell pitch, the smaller the on-resistance can be.

[0105] Of course, in other embodiments, the doping concentration of the first doping region 51 may be the same as the doping concentration of the first epitaxial layer 40 , which is not limited here.

[0106] In some embodiments, the power device is a SiC MOSFET; the first epitaxial layer 40 is an N-type epitaxial layer; the second epitaxial layer 50 is a P-type epitaxial layer, the first doped region 51 is an N-type implanted region, and the second doped region 52 is a P-type epitaxial region; Figure 4 , a plurality of semiconductor cells 30 are arranged at intervals along a first direction X, and the semiconductor cells 30 extend from one side of the active region to the other opposite side along a second direction Y; in the same second epitaxial layer 50, a plurality of first doped regions 51 are arranged at intervals along the first direction X, and the first doped regions 51 extend from one side of the active region to the other opposite side along the second direction Y; the second direction Y is perpendicular to the first direction X.

[0107] Specifically, the N-type first doping region 51 is formed in each P-type second epitaxial layer 50 by ion implantation, and the second doping region 52 is a region of the P-type second epitaxial layer 50 that is not implanted with N-type doping ions.

[0108] When the first doping region 51 is formed by ion implantation, the inclination angle of the first doping region 51 may be 45-90 degrees.

[0109] For example, the inclination angle of the first doping region 51 may be 45 degrees, 60 degrees, 70 degrees or 90 degrees, etc., which is not limited here.

[0110] Specifically, the inclination angle of the first doping region 51 can be designed to be 45 to 90 degrees, which can improve the doping uniformity and doping efficiency of the first doping region 51, enhance the controllability of the doping area of ​​the first doping region 51, reduce surface damage of the second epitaxial layer 50, etc., thereby improving device reliability.

[0111] In some other embodiments, the power device is a SiC MOSFET; the first epitaxial layer 40 is an N-type epitaxial layer; the second epitaxial layer 50 is an N-type epitaxial layer, the first doped region 51 is an N-type epitaxial region, and the second doped region 52 is a P-type implanted region; a plurality of semiconductor cells 30 are arranged at intervals along a first direction X, and the semiconductor cells 30 extend from one side of the active region to the other opposite side along a second direction Y; in the same second epitaxial layer 50, a plurality of first doped regions 51 are arranged at intervals along the first direction X, and the first doped regions 51 extend from one side of the active region to the other opposite side along the second direction Y; the second direction Y is perpendicular to the first direction X.

[0112] Specifically, the P-type second doping region 52 is formed in each N-type second epitaxial layer 50 by ion implantation, and the first doping region 51 is a region of the N-type second epitaxial layer 50 that is not implanted with P-type doping ions.

[0113] In other embodiments, the plurality of first doped regions 51 and the plurality of second doped regions 52 may also extend from one side of the active region to another opposite side along a third direction; the third direction has an angle with the first direction X, and the angle is less than 90 degrees.

[0114] Specifically, one of the first doping region 51 or the second doping region 52 is formed in the epitaxial layer by ion implantation, and the other is a region in the epitaxial layer that is not implanted with ions, thereby simplifying the preparation process.

[0115] Specifically, in the power device in the embodiment of the present application, in the active area, the semiconductor epitaxial wafer 20 includes a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 alternately stacked from bottom to top; the second epitaxial layer 50 includes a plurality of first doped regions 51 and a plurality of second doped regions 52 of different conductivity types; and it is further arranged that the projections of the plurality of first doped regions 51 in two adjacent second epitaxial layers 50 on the substrate 10 do not completely overlap, thereby increasing the withstand voltage of the device when reverse biased; and compared with the existing power devices, the present application has a lower on-resistance when the withstand voltage level of the device is the same, thereby being able to reduce the size of the chip.

[0116] Among them, in the power device in the embodiment of the present application, the semiconductor epitaxial wafer also includes an edge terminal area surrounding the active area, wherein the structure and function of the edge terminal area can be the same as the structure and function of the edge terminal area of ​​the existing power device.

[0117] Of course, the structure of the edge termination region may also be different from the structure of the edge termination region of the existing power device.

[0118] See also Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.16 as well as Fig.18 , Fig.11 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in the first embodiment of the present application; Fig.12 for Fig.11 A partial structural perspective view of a power device provided at another viewing angle; Fig.13 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a second embodiment of the present application; Fig.14 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a third embodiment of the present application; Fig.16 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in a fourth embodiment of the present application; Fig.18 A schematic diagram of a portion of the structure of an edge termination region of a power device provided in the fifth embodiment of the present application.

[0119] Specifically, in order to further improve the withstand voltage of the device and reduce the waste of chip area to a certain extent, in the power device provided in the embodiment of the present application, the multiple first epitaxial layers 40 and the multiple second epitaxial layers 50 in the active area also extend to the edge terminal area. And similar to the active area, the second epitaxial layer 50 in the edge terminal area also includes a first doping area 51 and a second doping area 52. The first doping area 51 and the second doping area 52 in the edge terminal area can be prepared and formed simultaneously with the first doping area 51 and the second doping area 52 in the active area.

[0120] For details, see Figure 11-Figure 12 , defining the substrate side as the bottom and the semiconductor cell 30 side as the top; in the edge terminal area, the semiconductor epitaxial wafer includes a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 alternately stacked from bottom to top; the second epitaxial layer 50 includes a first doped region 51 and a second doped region 52; the first doped region 51 surrounds the active region to form a first ring structure; the first epitaxial layer 40 and the first doped region 51 are of the first conductivity type, and the second doped region 52 is of the second conductivity type; the projections of the first doped regions 51 in two adjacent second epitaxial layers 50 on the substrate do not completely overlap.

[0121] The number of the first doped regions 51 (ie, the first ring-shaped structures) in each second epitaxial layer 50 may be one or more, which is specifically designed according to the withstand voltage level of the device.

[0122] Among them, see Fig.12 In the present application, the first doping region 51 may be a continuous integrated structure, and the first ring structure refers to a continuous ring structure in which the first doping region 51 surrounds the active region.

[0123] Alternatively, see Fig.17 , Fig.17 for Fig.16 A partial structural perspective view of a power device at another viewing angle is provided; in the present application, the first doping region 51 may also include a plurality of sub-regions arranged at intervals, the plurality of sub-regions are arranged in an annular pattern and arranged around the active region, and the first annular structure refers to the plurality of sub-regions forming the first doping region 51 arranged in an annular pattern around the active region. It can be understood that in this embodiment, the first annular structure has a plurality of second gaps H2 arranged at intervals, and the plurality of second gaps H2 are gaps between two adjacent sub-regions in the first doping region 51.

[0124] Specifically, in the power device provided by the present application, in the edge terminal region, the semiconductor epitaxial wafer includes a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 alternately stacked from the bottom to the top; the second epitaxial layer 50 includes a first doping region 51 and a second doping region 52; the first doping region 51 surrounds the active region to form a first ring structure; the first epitaxial layer 40 and the first doping region 51 are of the first conductivity type, and the second doping region 52 is of the second conductivity type; in this way, when the device is reverse biased, the first doping region 51 and the second doping region 52 form a depletion region, and a peak electric field is formed in the depletion region, so that a plurality of electric field peaks can be formed in the plurality of second epitaxial layers 50, and the high-intensity electric field in the edge terminal region is evenly distributed in the terminal region, so that the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased can be increased. And further, the projections of the first doping regions 51 in two adjacent second epitaxial layers 50 on the substrate do not completely overlap, which can increase the length of the current path, thereby further increasing the withstand voltage of the device when reverse biased. Therefore, under the condition that the device withstands the same voltage, the power device provided by the present application can reduce the size of the edge terminal area and reduce the waste of chip area.

[0125] In addition, if Fig.17 The power device shown replaces the continuous ring-shaped first doping region 51 with a discontinuous ring-shaped (ring-shaped lattice-shaped) first doping region 51. The purpose is to uniformly distribute the terminal electric field. The ring-shaped lattice-shaped first doping region 51 will form an electric field peak at each "second notch H2". By forming multiple electric field peaks, the electric field peak value is reduced to avoid premature breakdown of the device.

[0126] The bottom first epitaxial layer 40 can be used as a drift layer of the device. Multiple first epitaxial layers 40 and multiple second epitaxial layers 50 are located on a side of the drift layer away from the substrate 10 and are alternately stacked. The drift layer is in contact with a second epitaxial layer 50 .

[0127] Among them, the second epitaxial layer 50 has an injection region, and the area of ​​the second epitaxial layer 50 excluding the injection region is the epitaxial region; one of the epitaxial region and the injection region has the same conductivity type as the first epitaxial layer 40 and surrounds the active region to form a first ring structure, and the other has a different conductivity type from the first epitaxial layer 40.

[0128] For example, the implanted region has the same conductivity type as the first epitaxial layer 40, and the epitaxial region has a different conductivity type from the first epitaxial layer 40. The first epitaxial layer 40 and the second epitaxial layer 50 are both formed by epitaxial growth, and the implanted region is formed in the second epitaxial layer 50 by ion implantation. The implanted region can be understood as the first doped region 51, and the epitaxial region can be understood as the second doped region 52.

[0129] For another example, the conductivity type of the implanted region is different from that of the first epitaxial layer 40, and the conductivity type of the epitaxial region is the same as that of the first epitaxial layer 40. The first epitaxial layer 40 and the second epitaxial layer 50 are both formed by epitaxial growth, and the implanted region is formed in the second epitaxial layer 50 by ion implantation. The implanted region can be understood as the second doped region 52, and the epitaxial region can be understood as the first doped region 51.

[0130] Specifically, a plurality of first epitaxial layers 40 and a plurality of second epitaxial layers 50 are alternately stacked on a side of the drift layer away from the substrate, and the second epitaxial layer 50 includes an injection region and an epitaxial region; the adjacent first epitaxial layers 40 and the second epitaxial layers 50 form a charge depletion layer for uniformly distributing the high-intensity electric field in the edge terminal region in the terminal region, thereby improving the withstand voltage of the device when reverse biased. This structure is suitable for ultra-high voltage devices, such as power devices with a withstand voltage rating greater than 1200 volts, such as 3000 volts, 5000 volts, 8000 volts, etc.

[0131] See also Fig.11 , Fig.13 , Fig.14 , Fig.16 as well as Fig.18 In some embodiments, in the edge termination region, each second epitaxial layer 50 includes only one first ring structure, and the projections of the first ring structures of two adjacent second epitaxial layers 50 on the substrate do not overlap at all.

[0132] Specifically, by changing the arrangement of the first ring structures in two adjacent second epitaxial layers 50 , the length of the current path is changed, thereby increasing the withstand voltage of the device when it is reverse biased.

[0133] Furthermore, combined with Figure 11-13 , Fig.12 for Fig.11 A partial structural perspective view of a power device at another viewing angle is provided; in this embodiment, along the direction from top to bottom, the radial size of the first ring structure of the plurality of second epitaxial layers 50 may first increase and then decrease.

[0134] Or, combined Figure 14-17 , Fig.15 for Fig.14 A partial structural perspective view of a power device at another viewing angle is provided; along the direction from top to bottom, the radial size of the first ring structure of the plurality of second epitaxial layers 50 may also show a decreasing trend.

[0135] The radial dimension of the first annular structure may be understood as the inner diameter of the first annular structure in one direction.

[0136] Specifically, the radial dimensions of the first ring structure of the multiple second epitaxial layers 50 are changed along the direction from top to bottom, so as to change the position of the peak electric field in the multiple second epitaxial layers 50, thereby evenly distributing the high-intensity electric field in the edge terminal area in the terminal area, thereby increasing the withstand voltage of the device when reverse biased.

[0137] Among them, see Fig.11 In the embodiment where the radial dimensions of the first ring-shaped structures of the plurality of second epitaxial layers 50 first increase and then decrease, the number of the plurality of second epitaxial layers 50 may be an even number, and the first ring-shaped structures of the second epitaxial layers 50 located in the top half are symmetrically arranged with the first ring-shaped structures of the second epitaxial layers 50 located in the bottom half. In this embodiment, the symmetry axis is located on the first epitaxial layer 40 between the second epitaxial layers 50 in the top half and the second epitaxial layers 50 in the bottom half.

[0138] Alternatively, see Fig.13 , the number of the plurality of second epitaxial layers 50 may be an odd number, and the first ring structure of the second epitaxial layer 50 located at the top of the middle second epitaxial layer 50 is symmetrically arranged with the first ring structure of the second epitaxial layer 50 located at the bottom of the middle second epitaxial layer 50. In this embodiment, the symmetry axis is located on the middle second epitaxial layer 50.

[0139] The projections of the two symmetrically arranged second epitaxial layers 50 on the substrate completely overlap.

[0140] Specifically, the first ring structures in the plurality of second epitaxial layers 50 are symmetrically arranged, so that the high-intensity electric field in the edge terminal region can be evenly distributed in the terminal region, thereby increasing the withstand voltage of the device when reverse biased.

[0141] It should be emphasized that in the embodiment of the present application, the spacing between two adjacent second epitaxial layers 50 (i.e., the thickness of the first epitaxial layer 40) needs to be greater than 0.5 microns to avoid electric field concentration caused by the two adjacent second epitaxial layers 50 being too close, thereby reducing the occurrence of electric field breakdown.

[0142] Among them, combined Fig.16 and Fig.17 In an embodiment in which the radial dimensions of the first ring structures of the plurality of second epitaxial layers 50 show a decreasing trend, the projections of the first ring structures of the plurality of second epitaxial layers 50 on the substrate are concentrically arranged; along the direction from the outer ring to the inner ring, the width of the first ring structures shows a decreasing trend.

[0143] Specifically, along the direction from the outer ring to the inner ring, the width of the plurality of first ring structures is reduced, which means that the width of the second doping region 52 is increased. Thus, in the direction close to the active region, the second doping region 52 can withstand a higher withstand voltage.

[0144] See also Fig.18 In some embodiments, in the edge termination region, each second epitaxial layer 50 includes only one first ring structure, and the projections of the first ring structures of two adjacent second epitaxial layers 50 on the substrate partially overlap, and the other parts do not overlap.

[0145] Specifically, by changing the arrangement of the first ring structures in two adjacent second epitaxial layers 50 , the length of the current path is changed, thereby increasing the withstand voltage of the semiconductor epitaxial wafer 20 when the device is reverse biased.

[0146] Further, see Fig.18 In this embodiment, along the direction from top to bottom, the width of the first ring structure of the plurality of second epitaxial layers 50 tends to increase, and the inner diameter tends to decrease.

[0147] Specifically, the electric field strength tends to decrease along the direction from top to bottom. Therefore, in this embodiment, the width of multiple first ring structures is set to increase, that is, the width of the second doping region 52 tends to decrease. The width change trend of the second doping region 52 is the same as the change trend of the electric field strength, thereby achieving a voltage resistance effect.

[0148] Further, see Fig.18 In this embodiment, the outer edge of the first ring structure is aligned with the outer edge of the second epitaxial layer 50 .

[0149] That is, the first doped region 51 is arranged at the outer side of the active region or farther away from the active region relative to the second doped region 52, and the closer to the active region, the higher the electric field strength. In this embodiment, all the second doped regions 52 in each second epitaxial layer 50 are arranged close to the active region, which is beneficial to improving the withstand voltage of the device.

[0150] In some embodiments, the edge termination region further includes a transition region 80, and the transition region 80 has the same conductivity type as the second doping region 52. The function and structure of the transition region 80 are the same as those of the transition region 80 in the existing power device, and are not described in detail here.

[0151] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions; The substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; in the active area, the semiconductor epitaxial wafer further includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap; The thickness of the first epitaxial layer located at the bottom is greater than the thickness of the remaining single first epitaxial layers.

2. The power device according to claim 1, characterized in that: Projections of the plurality of first doped regions of two adjacent second epitaxial layers on the substrate do not overlap at all.

3. The power device according to claim 1, characterized in that: The semiconductor epitaxial wafer also includes a conductive connection area, which extends along the thickness direction of the semiconductor epitaxial wafer and electrically connects at least part of the second doped region of the second epitaxial layer with the well region contact area; the conductive connection area and the well region contact area are both of the second conductivity type; the conductive connection area is an ion implantation area.

4. The power device according to claim 3, characterized in that: In the same second epitaxial layer, multiple first doping regions and multiple second doping regions are alternately arranged along the layout direction of the semiconductor cells; the first doping region has a first notch, and two adjacent second doping regions are connected through the first notch on the first doping region.

5. The power device according to claim 1, characterized in that: The resistance of the plurality of first epitaxial layers decreases along a direction from the top to the bottom.

6. The power device according to claim 1, characterized in that: Along the direction from the top to the bottom, the width of the first doped regions in the plurality of second epitaxial layers tends to increase and the doping concentration tends to decrease; or, the width of the first doped regions in the plurality of second epitaxial layers tends to decrease and the doping concentration tends to increase.

7. The power device according to claim 1, characterized in that: In the same second epitaxial layer, a plurality of the first doping regions and a plurality of the second doping regions are alternately arranged along the layout direction of the semiconductor cells, and adjacent first doping regions and second doping regions form a period.

8. The power device according to claim 7, characterized in that: Along the direction from the top to the bottom, the number of periods formed by the first doping regions and the second doping regions in the plurality of second epitaxial layers increases or remains unchanged.

9. The power device according to any one of claims 1 to 8, characterized in that: The doping concentration of the first doping region is greater than the doping concentration of the first epitaxial layer.

10. The power device according to any one of claims 1 to 8, characterized in that: The power device is a SiC MOSFET; the first epitaxial layer is an N-type epitaxial layer; The second epitaxial layer is a P-type epitaxial layer, the first doped region is an N-type implanted region, and the second doped region is a P-type epitaxial region; or, the second epitaxial layer is an N-type epitaxial layer, the first doped region is an N-type epitaxial region, and the second doped region is a P-type implanted region; A plurality of the semiconductor cells are arranged at intervals along a first direction, and the semiconductor cells extend from one side of the active region to another opposite side along a second direction; In the same second epitaxial layer, a plurality of the first doped regions are arranged at intervals along the first direction, and the first doped regions extend from one side of the active region to another opposite side along the second direction; the second direction is perpendicular to the first direction.

11. The power device according to any one of claims 1 to 8, characterized in that: The inclination angle of the first doping region is 45 to 90 degrees.

12. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, the semiconductor cells include connected well regions, well region contact regions and source regions; in the active area, the semiconductor epitaxial wafer includes a drift layer, the drift layer is located between the substrate and the semiconductor cells; Wherein, in the active area, the semiconductor epitaxial wafer also includes a plurality of charge depletion layers stacked between the drift layer and the semiconductor cell; each of the charge depletion layers includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located on a side of the second epitaxial layer away from the drift layer; the first epitaxial layer and the drift layer have the same conductivity type; the second epitaxial layer has a plurality of injection regions arranged at intervals, and the area of ​​the second epitaxial layer excluding the injection regions is divided into a plurality of epitaxial regions arranged at intervals; one of the epitaxial region and the injection region has the same conductivity type as the first epitaxial layer, and the other has a different conductivity type from the first epitaxial layer; the projections of the plurality of injection regions in two adjacent second epitaxial layers on the substrate do not completely overlap.

13. The power device according to claim 12, characterized in that: The first epitaxial layer and the implanted region are of the first conductivity type, and the epitaxial region is of the second conductivity type; and projections of the plurality of epitaxial regions in two adjacent second epitaxial layers on the substrate only partially overlap.

14. The power device according to claim 12, characterized in that: The first epitaxial layer and the injection region are of the first conductivity type, and the epitaxial region is of the second conductivity type; the substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; along the direction from the top to the bottom, the width of the epitaxial region in the plurality of second epitaxial layers tends to decrease and the doping concentration tends to increase; or, the width of the epitaxial region in the plurality of second epitaxial layers tends to increase and the doping concentration tends to decrease.

15. The power device according to claim 12, characterized in that: The thickness of the drift layer is greater than the thickness of a single first epitaxial layer.

16. The power device according to claim 12, characterized in that: The implanted region has the same conductivity type as the first epitaxial layer, and a doping concentration of the implanted region is greater than a doping concentration of the first epitaxial layer.

17. The power device according to claim 12, characterized in that: The power device is a SiC MOSFET; the drift layer is an N-type epitaxial layer, and the first epitaxial layer is an N-type epitaxial layer; The second epitaxial layer is a P-type epitaxial layer, the injection region is an N-type injection region, and the epitaxial region is a P-type epitaxial region; or, the second epitaxial layer is an N-type epitaxial layer, the injection region is a P-type injection region, and the epitaxial region is an N-type epitaxial region.

18. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions; The substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; In the active area, the semiconductor epitaxial wafer also includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; a plurality of junction field effect regions are formed in the second epitaxial layer, and the area of ​​the second epitaxial layer excluding the junction field effect region is divided into a plurality of epitaxial regions arranged at intervals; the first epitaxial layer and the junction field effect region are of the first conductivity type, and the epitaxial region is of the second conductivity type; the projections of the plurality of junction field effect regions in two adjacent second epitaxial layers on the substrate do not completely overlap.

19. The power device according to claim 18, characterized in that: The doping concentration of the junction field effect region is greater than the doping concentration of the first epitaxial layer.

20. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions; The substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; in the active area, the semiconductor epitaxial wafer further includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap; Among them, the semiconductor epitaxial wafer also includes a conductive connection area, which extends along the thickness direction of the semiconductor epitaxial wafer and electrically connects at least part of the second doping area of ​​the second epitaxial layer with the well area contact area; the conductive connection area and the well area contact area are both of the second conductivity type; the conductive connection area is an ion implantation area.

21. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions; The substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; in the active area, the semiconductor epitaxial wafer further includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap; Wherein, along the direction from the top to the bottom, the resistance of the plurality of first epitaxial layers tends to decrease.

22. A power device, characterized in that: include: substrate; A semiconductor epitaxial wafer is arranged on the substrate; the semiconductor epitaxial wafer includes an active area; in the active area, the semiconductor epitaxial wafer has a plurality of semiconductor cells arranged at intervals, the plurality of semiconductor cells all extend from a surface of the semiconductor epitaxial wafer away from the substrate toward the substrate, and the semiconductor cells include connected well regions, well region contact regions, and source regions; The substrate side is defined as the bottom, and the semiconductor cell side is defined as the top; in the active area, the semiconductor epitaxial wafer further includes a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked from the bottom to the top; the second epitaxial layer includes a plurality of first doped regions and a plurality of second doped regions; the first epitaxial layer and the first doped region are of the first conductivity type, and the second doped region is of the second conductivity type; the projections of the plurality of first doped regions in two adjacent second epitaxial layers on the substrate do not completely overlap; Among them, along the direction from the top to the bottom, the width of the first doping region in multiple second epitaxial layers tends to increase and the doping concentration tends to decrease; or, the width of the first doping region in multiple second epitaxial layers tends to decrease and the doping concentration tends to increase.

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