A Capacitor Design Prediction Method for Chip Self-Test

Abstract

This invention relates to the field of chip design technology, and more particularly to a capacitor design prediction method for chip self-testing. The method includes obtaining the supply voltage, setting the maximum supply current of the DUT, the transient current percentage, and the allowable voltage drop during capacitor discharge, and calculating the lower limit of the total capacitance value on the chip board; calculating the ESR value of the parallel capacitors under the estimated maximum ripple of the Bulk capacitors; selecting Buck capacitors; selecting several models and numbers of Buck capacitors, and calculating the total equivalent resistance of the Buck capacitors; calculating the total capacitance value of the Buck capacitors based on their models and numbers; calculating the estimated maximum capacitance value of the ceramic capacitors based on the total equivalent resistance value of the Buck capacitors; selecting several models and numbers of ceramic capacitors, calculating the total capacitance value of the ceramic capacitors, and constraining the total capacitance values ​​of both the ceramic and Buck capacitors. This invention solves the problem of rationally matching Bulk and ceramic capacitors.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method for predicting capacitor design for chip self-testing. Background Technology

[0002] Circuit boards are the physical support and an important component for signal transmission in electronic products; chip test carrier boards are interface circuit boards used for chip testing, connecting the chip under test and the test equipment, and are simply referred to as test carrier boards.

[0003] With the rapid development of chip technology and the increasing complexity of chips, chip testing needs to be given more and more attention. The carrier for chip functional testing is the test board, and the design and manufacturing of the test board is an indispensable part of the entire semiconductor industry.

[0004] In the chip automated testing industry, test equipment manufacturers provide standardized test equipment. Therefore, the test carrier board, which serves as the carrier, must also strictly comply with the specifications of the test equipment. Specifically, the external dimensions, thickness, test channel positions, and the position of the chip under test of the test carrier board must all be designed strictly according to the specifications of the test equipment.

[0005] Power supply design is a crucial aspect of chip testing. As the driving force for chip operation, the performance of the power supply directly affects the chip's operating state. This is especially true for high-performance chips, which may switch arbitrarily between low-power and high-power states, further increasing the requirements for power supply stability.

[0006] Bulk capacitors are used in power supply systems for electronic design. They can serve as energy storage and filtering devices (with energy storage being more important than filtering). They are typically polarized capacitors with large capacitance values.

[0007] Ceramic capacitors are used in power supply systems for electronic design, where they serve as both energy storage and filtering devices (with filtering being more important than energy storage). They are typically non-polarized capacitors with small capacitance values.

[0008] Test substrates are characterized by large board size, high board thickness, high performance requirements, short design cycle, and high design cost. In the design of high-current chip test substrates, in order to better improve the stability of chip power supply, bulk capacitors and ceramic capacitors need to be designed closer to the chip, that is, on the chip test substrate. Therefore, how to achieve a reasonable combination of bulk capacitors and ceramic capacitors is an urgent problem to be solved. Summary of the Invention

[0009] To address the shortcomings of existing methods, this invention solves the problem of rationally combining bulk capacitors and ceramic capacitors.

[0010] The technical solution adopted by the present invention is: a capacitance design prediction method for chip self-test comprises the following steps: Step 1: Obtain the power supply voltage of the test bench, set the maximum power supply current of the DUT, the percentage of transient current and the allowable voltage drop for capacitor discharge, and calculate the lower limit of the total capacitance value of the on-board capacitor of the chip; Step 2: Use the theoretical ESR of Bulk capacitors as an indicator to determine whether the matching of model and quantity of actual Bulk capacitors is reasonable, and calculate the ESR value of parallel capacitors under the estimated maximum ripple of Bulk capacitors; Step 3: Select Bulk capacitor models by using the capacitance resonance frequency and capacitance attenuation factor; As a preferred implementation of the present invention, step 3 specifically comprises: Set the thresholds for capacitance resonance frequency f cap and capacitance attenuation factor D d , when f cap and D d satisfy the threshold conditions, the Bulk capacitor model meets the design requirements.

[0011] As a preferred implementation of the present invention, the thresholds for capacitance resonance frequency f cap and capacitance attenuation factor D d comprise: a first threshold: f cap <f0 and D d >D0; a second threshold: f cap =f1 and D d >D1; a third threshold: f2=<f cap <=f3 and D d >D2.

[0012] As a preferred implementation of the present invention, when the capacitance resonance frequency f cap and the capacitance attenuation factor D d satisfy the first threshold, or the second threshold, or the third threshold, the Bulk capacitor model meets the design requirements.

[0013] Step 4: Select a plurality of Bulk capacitor models and a plurality of Bulk capacitors of each model, and calculate the total equivalent resistance value of the Bulk capacitors; As a preferred implementation of the present invention, the formula for the total equivalent resistance of Bulk capacitors is:

[0014] wherein, i is the serial number of the Bulk capacitor model, k j is the number of Bulk capacitors of a certain model; M is the total number of Bulk capacitor models; N is the total number of a certain Bulk capacitor model, is the equivalent resistance value of a certain Bulk capacitor model.

[0015] In a preferred embodiment of the present invention, the total equivalent resistance of the Bulk capacitor is constrained by the constraint condition ESR. Bulk <ESR max_ripple .

[0016] Step 5: Calculate the total capacitance of the Bulk capacitors based on their model and number. Step 6: According to ESR Bulk Calculate the estimated maximum capacitance of the ceramic capacitor; Step 7: Select several models and several numbers of ceramic capacitors, calculate the total capacitance of the ceramic capacitors, and impose constraints on the total capacitance of the ceramic capacitors and the total capacitance of the Bulk capacitors. In a preferred embodiment of the present invention, the condition for constraining the total capacitance of the ceramic capacitor is as follows: < .

[0017] In a preferred embodiment of the present invention, the conditions for constraining the total capacitance of the ceramic capacitors and the total capacitance of the Bulk capacitors are as follows: + > .

[0018] As a preferred embodiment of the present invention, a capacitor design prediction system for chip self-test includes: a memory for storing instructions executable by a processor; and a processor for executing the instructions to implement a capacitor design prediction method for chip self-test.

[0019] In a preferred embodiment of the present invention, a computer-readable medium storing computer program code implements a capacitor design prediction method for chip self-testing when executed by a processor.

[0020] The beneficial effects of this invention are: 1. The selection and quantity ratio of capacitors can be planned before the chip design begins, which has a strong guiding significance for chip design; 2. The prediction method of this invention can be implemented using an Excel macro, which has the advantages of being easy to use and highly accurate; 3. It greatly shortens the design time of chip test projects and reduces the number of iterations of chip test projects. Attached Figure Description

[0021] Figure 1 This is a flowchart of the capacitor design prediction method for chip self-testing of the present invention; Figure 2 This is a schematic diagram of a chip testing system; Figure 3This is a schematic diagram of a system in which the Bulk capacitor and ceramic capacitor of the present invention are mounted on a chip test carrier. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments. The drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0023] like Figure 1 As shown, a capacitor design prediction method for chip self-testing includes the following steps: like Figure 2 This is a schematic diagram of a chip testing system. The three important structures in chip testing include: the test bench, which is responsible for providing power; the test carrier board, which serves as a medium connecting the test bench and the chip under test; and the chip under test, which is the object being tested.

[0024] like Figure 3 As shown, the power supply of the test instrument is a UHC4 power supply, which features low voltage, high current, and fast transient response. This amplifies the path Z-impedance issue, as illustrated in the formula. If the bulk capacitor is placed on the chip test carrier instead of inside the power supply system of the test equipment, the ripple caused by the voltage drop from the test carrier (ATE) control loop can be significantly reduced.

[0025] The UHC4 power channel of this invention requires the Bulk capacitor of the power supply to be placed on the chip under test board, which is the biggest difference from other DPS power channels. The Bulk capacitor on the test board is part of the test board power supply system. In addition to providing phase stability for the power control circuit of the test board, it also supplies power to the chip under test while waiting for the power response.

[0026] Figure 3 This paper presents the basic theory of the design method of Bulk capacitors in high-current chip testing. The chip under test, which requires high current power supply, may encounter large voltage transient drops during the testing process. For example, when the chip suddenly switches from a low-power standby state to a high-power state with full computing power, the voltage becomes unstable. In severe cases, this may cause the chip to fail or even be damaged.

[0027] The introduction of bulk capacitors can effectively improve voltage stability, and bulk capacitors can be directly designed into the power supply system inside the test equipment.

[0028] In addition, the stability of the power supply system is also related to the ceramic capacitor. Relatively speaking, the ceramic capacitor has a slightly smaller impact on the stability of the power supply system than the bulk capacitor.

[0029] In the design of high-current chip test carrier boards, in order to better improve the stability of chip power supply, bulk capacitors and ceramic capacitors need to be designed closer to the chip, that is, on the chip test carrier board.

[0030] Therefore, it is crucial to achieve a proper combination of bulk capacitors and ceramic capacitors. Simply put, the combination of bulk capacitors and ceramic capacitors can be divided into two aspects: 1. What type of capacitor to use? The differences between different capacitor types include: capacitance value, equivalent resistance, equivalent inductance, manufacturer, etc. 2. How to select the quantity of different types of capacitors, how to predict the selection and quantity ratio of bulk capacitors and ceramic capacitors, and how to quickly and accurately determine whether the prediction results can meet the performance requirements of the current chip are urgent problems to be solved.

[0031] Step 1: Obtain the power supply voltage V of the testing machine. Supply Set the maximum supply current I of the DUT. DUT Transient current percentage PCT Transient and the allowable voltage drop (PCT) during capacitor discharge drop ; Calculate the lower limit of the total capacitance value on the chip board The formula is:

[0032] in, The response time of the power supply is taken as a constant of 0.00004 seconds; PCT drop The extra factor of 1 / 2 is because of the voltage drop caused by the capacitor's own discharge when it is working.

[0033] The power supply system requires capacitors consisting of two parts: bulk capacitors and ceramic capacitors. The sum of the capacitance values ​​of the bulk capacitors and ceramic capacitors must be greater than [a certain value]. The capacitance values ​​of bulk capacitors and ceramic capacitors are not fixed; the ratio of the two types of capacitors needs to be determined, i.e., the matching of their models and quantities.

[0034] Step 2: Use the theoretical ESR (Equivalent Resistance) of the bulk capacitors as an indicator to determine whether the actual bulk capacitor model and quantity are appropriate, and calculate the ESR value of the parallel capacitors under the estimated maximum ripple of the bulk capacitors. max_ripple The formula is:

[0035] Step 3: Utilize the capacitor's resonant frequency f cap Capacitor attenuation factor D d Selecting the appropriate bulk capacitor; setting thresholds for the capacitance resonance frequency and the capacitance attenuation factor, when f cap and D d satisfy the threshold condition, the Bulk capacitance model meets the design requirements; the thresholds for the capacitance resonance frequency and the capacitance attenuation factor include: a first threshold: f cap <f0 and D d >D0; a second threshold: f cap =f1 and D d >D1; a third threshold: f2=<f cap <=f3 and D d >D2; in this embodiment, f0=100kHz; f1=150kHz; f2=200kHz; f3=250kHz; D0=0.5; D1=1; D2=2.5; when f cap and D d satisfy the first threshold, the second threshold or the third threshold, the Bulk capacitance model meets the design requirements.

[0036] Step 4, selecting a plurality of models and a plurality of Bulk capacitors, and calculating the total equivalent resistance ESR of the Bulk capacitors Bulk , the formula is:

[0037] wherein, i is the sequence number of the Bulk capacitance model, k j is the number of Bulk capacitors of a certain model; M is the total number of Bulk capacitance models; N is the total number of a certain Bulk capacitance model, is the equivalent resistance value of a certain Bulk capacitance model.

[0038] using ESR max_ripple to perform a first capacitance capacity constraint on ESR Bulk , and the first capacitance capacity constraint condition is: ESR Bulk <ESR max_ripple .

[0039] on the premise of satisfying the capacitance capacity constraint condition, the smaller the ESR Bulk value, the better the performance.

[0040] Step 5, calculating the total capacitance of the Bulk capacitors according to the model and number of Bulk capacitors obtained in Step 4, the formula is:

[0041] wherein, i is the sequence number of the Bulk capacitance model, k j is the number of Bulk capacitors of a certain model, C Bulk_i is the capacitance value of a certain Bulk capacitance model.

[0042] Step 6: Based on the total equivalent resistance (ESR) of the Bulk capacitor. Bulk Calculate the estimated maximum capacitance of a ceramic capacitor. The formula is:

[0043] Where a is a constant, a = 367.

[0044] Step 7: Select several models and numbers of ceramic capacitors, and calculate the total capacitance value of the ceramic capacitors. The formula is:

[0045] Among them, i ’ This refers to the ceramic capacitor model serial number, l j’ This represents the number of ceramic capacitors of a certain model. This refers to the capacitance value of a specific ceramic capacitor model. use right A second capacitance constraint is applied, and the constraint conditions for the second capacitance are as follows: < ; Set a third capacitor capacity constraint, the condition of which is: + > Specific Implementation Example 1: Input design basic requirements: Supply voltage V Supply 0.8V; Maximum supply current I DUT 40A; Permissible voltage drop during capacitor discharge (PCT) droop 5%; Transient current percentage (PCT) Transient 100%; Calculate the lower limit of the total capacitance of the chip board. : 8000uf; Calculate the ESR value of the parallel capacitor under the estimated maximum ripple. max_ripple 0.5 mohm; Table 1 shows the matching of Bulk capacitors by model and quantity:

[0047] Calculate the total equivalent resistance (ESR) of the Bulk capacitor. Bulk 0.395 mohm; It can be seen that the ESR value of the Bulk capacitor combination is lower than the ESR value of the parallel capacitor under the estimated maximum ripple of all Bulk capacitors calculated in theory: 0.395 < 0.5; The total capacitance of these bulk capacitors is calculated to be 7980uF. The theoretical maximum value of the ceramic capacitor is calculated to be 929.37uF. Table 2. Matching of Ceramic Capacitor Models and Quantities

[0048] The total capacitance of these ceramic capacitors was calculated to be 541.3uF. The total capacitance of the ceramic capacitors is lower than the calculated theoretical maximum value of the ceramic capacitors: 541.3 < 929.37; the total capacitance of the Bulk capacitors and ceramic capacitors is greater than the calculated total capacitance required for system stability (lower limit): 7980 + 541.3 > 8000.

[0049] This indicates that the current design scheme for Bulk capacitors and ceramic capacitors meets the relevant performance requirements of the current project.

[0050] Example 2: Input design basic requirements: Supply voltage V Supply 0.6V; Maximum supply current I DUT 80A; Permissible voltage drop during capacitor discharge (PCT) droop 5%; Transient current percentage (PCT) Transient 100%; Calculate the lower limit of the total capacitance of the chip board. :21333uf; Calculate the ESR value of the parallel capacitor under the estimated maximum ripple. max_ripple 0.188 mohm; Table 3 lists the model and quantity of Bulk capacitors:

[0051] Calculate the total equivalent resistance (ESR) of the Bulk capacitor. Bulk 0.306 mohm; It can be seen that the ESR value of the Bulk capacitor combination is lower than the ESR value of the parallel capacitor under the theoretically calculated maximum ripple of all Bulk capacitors: 0.306 > 0.188, which does not meet the standard; The total capacitance of these bulk capacitors is calculated to be 10470uF. The theoretical maximum value of the ceramic capacitor is calculated to be 1198.87uF. Table 4. Matching of Ceramic Capacitor Models and Quantities

[0052] The total capacitance of these ceramic capacitors was calculated to be 1343uF. The total capacitance of the ceramic capacitors is higher than the calculated theoretical maximum value of the ceramic capacitors: 1343 > 1198.87, which does not meet the standard; the total capacitance of the bulk capacitors and ceramic capacitors is less than the calculated total capacitance value (lower limit) required for system stability: 10470 + 1343 < 21333, which does not meet the standard.

[0053] This indicates that the current design schemes for Bulk capacitors and ceramic capacitors do not meet the relevant performance requirements of the current project.

[0054] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for predicting capacitor design for chip self-testing, characterized in that, Includes the following steps: Step 1: Obtain the power supply voltage of the test equipment, set the maximum power supply current of the DUT, the transient current percentage and the allowable voltage drop of capacitor discharge, and calculate the lower limit of the total capacitance value on the chip board. Step 2: Use the theoretical ESR of the Bulk capacitor as an indicator to determine whether the actual Bulk capacitor model and quantity are reasonable, and calculate the ESR value of the parallel capacitor under the estimated maximum ripple of the Bulk capacitor. Step 3: Select the appropriate Bulk capacitor based on its resonant frequency and attenuation factor. Step 4: Select several models and several numbers of Bulk capacitors, and calculate the total equivalent resistance of the Bulk capacitors; Step 5: Calculate the total capacitance of the Bulk capacitors based on their model and number. Step 6: Calculate the estimated maximum capacitance of the ceramic capacitor based on the total equivalent resistance of the Bulk capacitor; Step 7: Select several models and several numbers of ceramic capacitors, calculate the total capacitance of the ceramic capacitors, and impose constraints on the total capacitance of the ceramic capacitors and the total capacitance of the Bulk capacitors.

2. The capacitance design prediction method for chip self-testing according to claim 1, characterized in that, Step three specifically includes: Set the capacitor resonant frequency f cap and capacitance attenuation factor D d The threshold when f cap D d When the threshold conditions are met, the Bulk capacitor model meets the design requirements.

3. The capacitance design prediction method for chip self-testing according to claim 2, characterized in that, Capacitor resonant frequency f cap and capacitor attenuation factor D d thresholds include: first threshold: f cap <f0 and D d >D0; second threshold: f cap =f1 and D d >D1; third threshold: f2=<f cap <=f3 and D d >D2.

4. The capacitance design prediction method for chip self-testing according to claim 3, characterized in that, When the capacitor resonant frequency f cap and capacitance attenuation factor D d If the first, second, or third threshold is met, the Bulk capacitor model meets the design requirements.

5. The capacitance design prediction method for chip self-testing according to claim 1, characterized in that, Bulk capacitor equivalent total resistance ESR Bulk The formula is: ； Where i is the model number of the Bulk capacitor, and k j M represents the number of a certain type of Bulk capacitor; M represents the total number of Bulk capacitor models; N represents the total number of a certain Bulk capacitor model. This is the equivalent resistance value of a certain Bulk capacitor model.

6. The capacitance design prediction method for chip self-testing according to claim 1, characterized in that, The total equivalent resistance of the Bulk capacitor is constrained, and the constraint condition is the total equivalent resistance ESR of the Bulk capacitor Bulk <ESR value of parallel capacitors under the estimated maximum ripple of Bulk capacitor ESR max_ripple .

7. The capacitance design prediction method for chip self-testing according to claim 1, characterized in that, The condition for constraining the total capacitance of ceramic capacitors is: the total capacitance of ceramic capacitors... Estimated maximum capacitance of ceramic capacitors .

8. The capacitance design prediction method for chip self-testing according to claim 1, characterized in that, The constraint on the total capacitance of the ceramic capacitors and the total capacitance of the bulk capacitors is as follows: the total capacitance of the ceramic capacitors... +Total capacitance of Bulk capacitors Lower limit of total capacitance value on the chip board .

9. A capacitor design prediction system for chip self-testing, characterized in that, include: Memory is used to store instructions that can be executed by the processor; A processor for executing instructions to implement the capacitor design prediction method for chip self-test as described in any one of claims 1-8.

10. A computer-readable medium storing computer program code, characterized in that, The computer program code, when executed by a processor, implements the capacitor design prediction method for chip self-test as described in any one of claims 1-8.

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