Shift register, gate drive circuit, display panel and display device

Abstract

The present disclosure provides a shift register, a gate driving circuit and a driving method thereof, a display panel and a display device. The shift register comprises an input sub-circuit, a first control sub-circuit, an output sub-circuit, an output control sub-circuit and a second control sub-circuit. The input sub-circuit electrically connects an input terminal and a first node based on a signal of a first clock signal terminal. The output sub-circuit outputs a signal of a second clock signal terminal to an output terminal based on a signal of a third node. The output control sub-circuit electrically connects the output terminal and a second power signal terminal based on a signal of a second node. The second control sub-circuit electrically connects the second power signal terminal and the second node based on signals of a third clock signal terminal and the first node. An active level period of the signal of the third clock signal terminal and an active level period of the signal of the second power signal terminal overlap for at least 1H. The present disclosure can control the reset time of the first node through the overlap of the signals of the clock signal lines.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit and its driving method, a display panel and a display device. Background Technology

[0002] Gate driver on array (GOA) circuits are widely used in display products. The GOA circuit is integrated onto the array substrate and fabricated simultaneously with other display components on the substrate, which can reduce the cost of display products.

[0003] The GOA circuit outputs a row scan signal to the transistor in the pixel drive circuit to control the writing of data signals. However, as the refresh rate of display products increases, the writing time of one row is shortened. Therefore, there is a problem that data cannot be fully written in high-frequency cases, making it difficult to implement high-frequency display products. Summary of the Invention

[0004] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a shift register, comprising:

[0005] An input sub-circuit is electrically connected to the input terminal, the first node, and the first clock signal terminal, and is configured to electrically connect the input terminal and the first node based on the signal from the first clock signal terminal.

[0006] The first control sub-circuit is electrically connected to the first power signal terminal, the second node and the first clock signal terminal, and is configured to electrically connect the first power signal terminal and the second node based on the signal of the first clock signal terminal.

[0007] The output sub-circuit is electrically connected to the third node, the second clock signal terminal, and the output terminal, and is configured to output the signal from the second clock signal terminal to the output terminal based on the signal from the third node.

[0008] The output control sub-circuit is electrically connected to the second node, the second power signal terminal and the output terminal, and is configured to electrically connect the second power signal terminal and the output terminal based on the signal of the second node.

[0009] The second control sub-circuit is electrically connected to the third clock signal terminal, the second power supply signal terminal, the second node, and the first node, and is configured to electrically connect the second power supply signal terminal to the second node based on the signals from the third clock signal terminal and the first node.

[0010] Among them, the effective level period of the signal at the third clock signal terminal and the effective level period of the signal at the second power supply signal terminal overlap for at least 1H, where H represents the time required for the shift register to scan one row of pixels.

[0011] Optionally, the shift register further includes: a first voltage regulator circuit, which includes: a first transistor and a first capacitor.

[0012] The first electrode of the first capacitor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the first transistor, the second electrode of the first transistor is electrically connected to the third node, and the control electrode is electrically connected to the second node.

[0013] Optionally, the shift register further includes a third control sub-circuit electrically connected to the first node, the second node, and the first clock signal terminal, configured to electrically connect the first clock signal terminal to the second node based on the signal from the first node.

[0014] Optionally, the shift register further includes a second voltage regulator circuit, electrically connected to the first node, the third node and the first power supply signal terminal, configured to electrically connect the third node to the first node based on the signal from the first power supply signal terminal.

[0015] Optionally, the input sub-circuit includes a second transistor, with its first electrode electrically connected to the input terminal and its second electrode electrically connected to the first node, and its control electrode electrically connected to the first clock signal terminal.

[0016] The first control sub-circuit includes a third transistor, the first electrode of which is electrically connected to a first power supply signal terminal, the second electrode of which is electrically connected to the second node, and the control terminal is electrically connected to a first clock signal terminal.

[0017] The output sub-circuit includes a fourth transistor and a second capacitor. The first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the output terminal. The control electrode is electrically connected to the third node. The first electrode of the second capacitor is electrically connected to the third node, and the second electrode is electrically connected to the output terminal.

[0018] The output control sub-circuit includes a fifth transistor and a third capacitor. The first electrode of the fifth transistor is electrically connected to the output terminal, the second electrode is electrically connected to the second power supply signal terminal, and the control electrode is electrically connected to the second node. The first electrode of the third capacitor is electrically connected to the second node, and the second electrode is electrically connected to the second power supply signal terminal.

[0019] The second control sub-circuit includes a sixth transistor and a seventh transistor.

[0020] The first electrode of the sixth transistor is connected to the first node, the second electrode is connected to the first electrode of the seventh transistor, the control electrode is connected to the third clock signal terminal, the second electrode of the seventh transistor is connected to the second power supply signal terminal, and the control electrode is connected to the second node.

[0021] Optionally, the third control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the first clock signal terminal, the second electrode of which is electrically connected to the second node, and the control electrode of which is electrically connected to the first node.

[0022] A second aspect of this disclosure provides a gate driving circuit including a plurality of cascaded shift registers as described above, wherein the output or carry terminal of the nth stage shift register is electrically connected to the input terminal of another stage shift register, where n is a positive integer greater than or equal to 1.

[0023] The input of the first-stage shift register is electrically connected to the first initial signal line, and the input of the second-stage shift register is electrically connected to the second initial signal line.

[0024] There is an overlap of at least 1 hour between the effective level period of the signal connected to the first initial signal line and the effective level period of the signal connected to the second initial signal line.

[0025] The output of the nth stage shift register is electrically connected to the input of the (n+2)th stage shift register.

[0026] Optionally, the first clock signal terminal of the 4m-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line.

[0027] The first clock signal terminal of the 4m-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line.

[0028] The first clock signal terminal of the 4m-1 stage shift register is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line.

[0029] The first clock signal terminal of the 4m-stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line, where m is a positive integer.

[0030] Optionally, the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register for at least 1 hour, and the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1 stage shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register for at least 1 hour.

[0031] A third aspect of this disclosure provides a display panel including the gate driving circuit described above.

[0032] Optionally, the display panel further includes: at least one pixel circuit, the pixel circuit including: a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a first reset sub-circuit, and a light-emitting unit.

[0033] The driver sub-circuit, electrically connected to the fourth, fifth, and sixth nodes, is configured to generate a drive current based on the data signal input from the fourth node.

[0034] The light-emitting control sub-circuit is electrically connected to the fourth power supply signal terminal, the fifth node, the sixth node, the first and second light-emitting control terminals, and the anode of the light-emitting unit. It is configured to transmit drive current to the anode based on the signals from the first and second light-emitting control terminals.

[0035] The write sub-circuit is electrically connected to the fourth node, the data signal terminal, and the write control terminal, and is configured to transmit the data signal connected to the data signal terminal to the fourth node based on the signal from the write control terminal.

[0036] The first reset sub-circuit is electrically connected to the first reset control terminal, the first reset signal terminal, and the sixth node. It is configured to connect the first reset signal terminal to the sixth node based on the signal from the first reset control terminal.

[0037] The first reset signal terminal is connected to a DC or AC signal with a changing potential.

[0038] Optionally, the image display process of the light-emitting unit includes a refresh frame and a hold frame. The first reset signal terminal receives a signal with a first amplitude during the refresh frame and a signal with a second amplitude during the hold frame.

[0039] The first amplitude is greater than the second amplitude.

[0040] Optionally, the output of the shift register is electrically connected to the write control terminal of the pixel circuit of the corresponding row.

[0041] The fourth aspect of this disclosure provides a driving method for the gate driving circuit described above.

[0042] In the first stage of the nth-stage shift register, based on the fact that the signal connected to the first clock signal terminal is at an effective level and the signal connected to the second clock signal terminal is at an invalid level, the input sub-circuit and output sub-circuit of the nth-stage shift register are turned on, and the first power supply signal terminal and the second node are turned on through the first control sub-circuit of the nth-stage shift register;

[0043] In the second stage of the nth stage shift register, the output sub-circuit of the nth stage shift register is turned on to output an effective level signal. Based on the signal connected to the second clock signal terminal of another stage shift register cascaded with the nth stage shift register becoming effective, the output sub-circuit of the other stage shift register is turned on to output an effective level signal.

[0044] The fifth aspect of this disclosure provides a display device including the display panel described above.

[0045] The beneficial effects of this disclosure are as follows:

[0046] This disclosure addresses existing problems by providing a shift register, a gate driving circuit and its driving method, a display panel and a display device. By providing a shift register with a second control sub-circuit, wherein the effective level period of the signal connected to the third clock signal terminal (which serves as the control terminal) in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1 hour, the reset time of the first node can be controlled, improving the adjustment flexibility of the first node, increasing the output driving capability, and improving the display effect, thus having broad application prospects. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a timing diagram of the clock signal terminal and the output terminal of the shift register according to an embodiment of the present disclosure;

[0049] Figure 2 This is a schematic block diagram of a shift register according to an embodiment of the present disclosure;

[0050] Figure 3 This is a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0051] Figure 4 A schematic timing diagram of the signal lines of a gate drive circuit according to an embodiment of the present disclosure is shown;

[0052] Figure 5 This is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;

[0053] Figure 6 This is a schematic circuit diagram of a shift register according to another embodiment of the present disclosure;

[0054] Figure 7 According to Figure 6 The timing diagram of the key ports of the shift register simulation is shown below;

[0055] Figure 8 According to Figure 5 and Figure 6 The diagram shows a simulation comparison of the shift register outputs.

[0056] Figure 9 This is a simulation diagram of the output of the gate drive circuit according to an embodiment of the present disclosure;

[0057] Figure 10 A circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure is shown;

[0058] Figure 11 Showing according to Figure 10 The timing diagram of the key ports of the pixel circuit shown is as follows. Detailed Implementation

[0059] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0060] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0061] All transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the gate of the transistor is called the control electrode, and one of the source and drain is called the first electrode, and the other is called the second electrode. In the embodiments of this disclosure, the first electrode of the transistor is called the drain and the second electrode is called the source, as an example. In addition, the shift register unit of the embodiments of this disclosure uses an N-type transistor and improves the drive compensation architecture based on NMOS transistors. Therefore, the conduction condition of the transistor is that the control electrode is connected to a high-level signal, which will not be described in detail below. It is conceivable that when a P-type transistor is used, the conduction condition of the transistor is reversed. When the gate input is low, the source and drain are turned on. It is only necessary to adjust the signal level of the corresponding port. Therefore, the implementation of the P-type transistor should also be within the protection scope of the embodiments of this disclosure.

[0062] It should also be noted that the gate driving circuit disclosed herein can be used for line-by-line scanning of the control electrode of the write transistor in an LPTS display panel, or for line-by-line scanning of the control electrode of the write transistor in an LPTO display panel (where both N-type TFTs and P-type TFTs exist in the pixel circuit).

[0063] To solve at least one of the above problems, refer to Figure 1 and Figure 2 As shown, this disclosure provides a shift register, including:

[0064] The input sub-circuit 10 is electrically connected to the input terminal STV, the first node N1 and the first clock signal terminal CK, and is configured to electrically connect the input terminal STV and the first node N1 based on the signal of the first clock signal terminal CK.

[0065] The first control sub-circuit 20 is electrically connected to the first power signal terminal VGH, the second node N2 and the first clock signal terminal CK, and is configured to electrically connect the first power signal terminal VGH and the second node N2 based on the signal of the first clock signal terminal CK.

[0066] The output sub-circuit 30 is electrically connected to the third node N3, the second clock signal terminal CB and the output terminal OUT, and is configured to output the signal of the second clock signal terminal CB to the output terminal OUT based on the signal of the third node N3.

[0067] The output control sub-circuit 40 is electrically connected to the second node N2, the second power signal terminal VGL and the output terminal OUT, and is configured to electrically connect the second power signal terminal VGL and the output terminal OUT based on the signal of the second node N2.

[0068] The second control sub-circuit 50 is electrically connected to the third clock signal terminal CB-2, the second power supply signal terminal VGL, the second node N2, and the first node N1. It is configured to electrically connect the second power supply signal terminal VGL to the second node N2 based on the signals from the third clock signal terminal CB-2 and the first node N1.

[0069] Among them, the effective level period of the signal at the third clock signal terminal CB-2 overlaps with the effective level period of the signal at the second power supply signal terminal VGL by at least 1H, where H represents the time required for the shift register to scan one row of pixels.

[0070] In this embodiment, by providing a shift register with a second control sub-circuit, and the effective level period of the signal connected to the third clock signal terminal, which serves as the control terminal in the control sub-circuit, overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1 hour, the reset time of the first node can be controlled, the adjustment flexibility of the first node can be improved, the output driving capability can be increased, and the display effect can be improved.

[0071] To help understand the function of the shift register in the embodiments of this disclosure, a block diagram of a gate drive circuit formed by cascading shift registers according to the embodiments of this disclosure is first used to illustrate an application scenario and the function of the shift register.

[0072] Reference Figure 3 As shown, Figure 3 An exemplary block diagram of a gate drive circuit consisting of four cascaded shift registers GOA-1, GOA-2, GOA-3, and GOA-4 is shown, wherein the structure of each shift register stage satisfies Figure 2 The block diagram shown.

[0073] It should be understood that Figure 3 This is for illustrative purposes only and is not intended to limit this disclosure; the specific number of cascaded shift registers will depend on the need.

[0074] Reference Figure 3 As shown, the output terminal Out of the first-stage shift register GOA-1 is electrically connected to the input terminal STV of the third-stage shift register GOA-3, the output terminal Out of the second-stage shift register GOA-2 is electrically connected to the input terminal STV of the fourth-stage shift register GOA-4, the input terminal STV of the first-stage shift register GOA-1 is electrically connected to the first initial signal line stv1, the input terminal STV of the second-stage shift register GOA-2 is electrically connected to the second initial signal line stv2, the output terminal Out of the current-stage shift register is electrically connected to the input terminal STV of the next-stage shift register, and the input terminal of the first-stage shift register is electrically connected to the initial signal line stv.

[0075] In other words, the output terminal Out of the current stage shift register is electrically connected to the input terminal STV of the next stage shift register, which is one row away. This is because, in order to achieve an effective output time period by utilizing the overlapping of the effective levels of the signal lines, the start time of the signal output by the adjacent next-stage shift register is delayed relative to the signal required by the input terminal of the adjacent next-stage shift register. Therefore, when the shift registers of this embodiment are cascaded, the input terminals of the first and second stage shift registers require two initial signal lines to provide input signals.

[0076] Continue to refer to Figure 3 As shown, the first clock signal terminal CK of the first-stage shift register GOA-1 is electrically connected to the first clock signal line CK1, the second clock signal terminal CB is electrically connected to the third clock signal line CB1, and the third clock signal line CB-2 is electrically connected to the fourth clock signal line CB2; the first clock signal terminal CK of the second clock signal line GOA-2 is electrically connected to the second clock signal line CK2, the second clock signal terminal CB is electrically connected to the fourth clock signal line CB2, and the third clock signal line CB-2 is electrically connected to the third clock signal line CB1; the first clock signal terminal CK of the third clock signal line GOA-3 is electrically connected to the third clock signal line CB1, the second clock signal terminal CB is electrically connected to the first clock signal line CK1, and the third clock signal line CB-2 is electrically connected to the second clock signal line CK2; the first clock signal terminal CK of the fourth clock signal line GOA-4 is electrically connected to the fourth clock signal line CB2, the second clock signal terminal CB is electrically connected to the second clock signal line CK2, and the third clock signal line CB-2 is electrically connected to the first clock signal line CK1.

[0077] In embodiments of this disclosure, when there are more cascaded shift registers, they are cascaded in groups of four in the manner described above.

[0078] As can be seen, when the shift registers of this embodiment are cascaded, they can use at least 4 signal lines, and use one of the clock signal lines and the other two clock signal lines to provide clock signals with appropriate timing and overlapping relationships during the effective level period for each shift register. Thus, the effective time extension effect of each stage output can be achieved with as few clock signal lines as possible during cascading.

[0079] The following is combined with Figure 2 , Figures 5 to 8 The specific structure and function of the shift registers in the embodiments of this disclosure are described with reference to specific examples.

[0080] Reference Figure 2 and Figure 5As shown, the shift register includes an input sub-circuit 10, a first control sub-circuit 20, an output sub-circuit 30, an output control sub-circuit 40, and a second control sub-circuit 50.

[0081] The input sub-circuit 10 is electrically connected to the input terminal STV, the first node N1 and the first clock signal terminal CK, and is configured to electrically connect the input terminal STV and the first node N1 based on the signal of the first clock signal terminal CK.

[0082] Specifically, the input sub-circuit includes a second transistor T2. The first electrode of the second transistor T2 is electrically connected to the input terminal STV, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal terminal CK. When the first clock signal terminal CK is connected to a high-level signal, the second transistor T2 is turned on, and the signal of the input terminal STV is input to the first node N1.

[0083] The first control sub-circuit 20 is electrically connected to the first power signal terminal VGH, the second node N2 and the first clock signal terminal CK, and is configured to electrically connect the first power signal terminal VGH and the second node N2 based on the signal of the first clock signal terminal CK.

[0084] Specifically, the first control sub-circuit 20 includes a third transistor T3. The first electrode of the third transistor T3 is electrically connected to the first power supply signal terminal VGH, the second electrode is electrically connected to the second node N2, and the control terminal is electrically connected to the first clock signal terminal CK. In response to a high-level signal being applied to the first clock signal terminal CK, the third transistor T3 is turned on, inputting the potential of the first power supply signal terminal VGH to the second node N2.

[0085] The output sub-circuit 30 is electrically connected to the third node N3, the second clock signal terminal CB, and the output terminal Out, and is configured to output the signal of the second clock signal terminal CB to the output terminal Out based on the signal of the third node N3.

[0086] Specifically, the output sub-circuit 30 includes a fourth transistor T4 and a second capacitor C2. The first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, the second electrode is electrically connected to the output terminal Out, and the control electrode is electrically connected to the third node N3. The first electrode of the second capacitor C2 is electrically connected to the third node N3, and the second electrode is electrically connected to the output terminal Out. In response to the high level of the third node N3, the fourth transistor T4 is turned on and transmits the signal connected to the second clock signal terminal CB to the output terminal Out. In addition, the second capacitor C2 is used to maintain the potential of the control electrode of the fourth transistor T4.

[0087] The output control sub-circuit 40 is electrically connected to the second node N2, the second power signal terminal, and the output terminal, and is configured to electrically connect the second power signal terminal VGL to the output terminal Out based on the signal of the second node N2.

[0088] The output control sub-circuit 40 includes a fifth transistor T5 and a third capacitor C3. The first electrode of the fifth transistor T5 is electrically connected to the output terminal Out, the second electrode is electrically connected to the second power supply signal terminal VGL, and the control electrode is electrically connected to the second node N2. The first electrode of the third capacitor C3 is electrically connected to the second node N2, and the second electrode is electrically connected to the second power supply signal terminal VGL. In response to the high level of the second node N2, the fifth transistor T5 is turned on and transmits the signal connected to the second power supply signal terminal VGL to the output terminal Out. In addition, the third capacitor C3 is used to maintain the potential of the control electrode of the fifth transistor T5.

[0089] Specifically, the shift register also includes a second control sub-circuit 50, electrically connected to the third clock signal terminal CB-2, the second power supply signal terminal VGL, the second node N2, and the first node N1, configured to electrically connect the second power supply signal terminal VGL to the second node N2 based on the signals of the third clock signal terminal CB-2 and the first node N1.

[0090] In the embodiments of this disclosure, the effective level period of the signal at the third clock signal terminal CB-2 overlaps with the effective level period of the signal at the second power signal terminal CB for at least 1H, where H represents the time required for the shift register to scan one row of pixels.

[0091] Specifically, the second control sub-circuit 50 includes a sixth transistor T6 and a seventh transistor T7. The first electrode of the sixth transistor T6 is electrically connected to the first node N1, the second electrode is electrically connected to the first electrode of the seventh transistor N7, and the control electrode is electrically connected to the third clock signal terminal CB-2. The second electrode of the seventh transistor T7 is electrically connected to the second power supply signal terminal VGL, and the control electrode is electrically connected to the second node N2. When the signal at the third clock signal terminal CB-2 is high, the sixth transistor T6 is turned on, transferring the potential of the first node N1 to the fourth node N4. When the potential of the second node N2 is high, the seventh transistor T7 is turned on, transferring the potential of the second power supply signal terminal VGL to the fourth node N4. When both the sixth transistor T6 and the seventh transistor T7 are turned on, the potential of the second power supply signal terminal VGL is written to the first node N1.

[0092] This configuration allows for separate control of the third clock signal terminal CB-2 and the second clock signal terminal CB by setting different clock signals. This enables more flexible control of the reset time of the first node N1. The overlap between the effective level of the signal at the third clock signal terminal CB-2 and the effective level of the signal at the second clock signal terminal CB is the reset time of the first node N1. Furthermore, by setting different clock signals for the third clock signal terminal CB-2 and the second clock signal terminal CB, the RC ratio of the current stage shift register can be reduced, increasing the output drive capability of the second clock signal terminal CB.

[0093] Specifically, considering the overlap of effective clock signal periods between stages, when the signal at the second clock signal terminal CB transitions from low to high, this voltage change couples to the third node N3. The voltage transition at the third node N3 causes the fourth transistor T4, which acts as the output transistor, to mis-turn on, thus affecting the potential of the output terminal Out and resulting in erroneous output. In embodiments of this disclosure, the shift register further includes a first voltage regulator circuit 60.

[0094] Reference Figure 5 As shown, the first voltage regulator circuit 60 includes a first transistor T1 and a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the first power supply signal terminal VGH, and the second terminal is electrically connected to the first terminal of the first transistor T1. The second terminal of the first transistor T1 is electrically connected to the third node N3, and the control terminal is electrically connected to the second node N2. Whenever the potential of the second node N2 is high, the first transistor T1 is turned on, transmitting the high-level potential coupled from the first terminal of the first capacitor C1 to the second terminal to the third node N3, thereby stabilizing the third node N3 at a high-level signal.

[0095] Optionally, continue to refer to Figure 5 As shown, the shift register also includes a third control sub-circuit, which is electrically connected to the first node N1, the second node N2, and the first clock signal terminal CK. It is configured to electrically connect the first clock signal terminal CK to the second node N2 based on the signal from the first node N1. The third control sub-circuit includes a transistor T8, whose first electrode is electrically connected to the first clock signal terminal CK, its second electrode is electrically connected to the second node N2, and its control electrode is electrically connected to the first node N1. Transistor T8 is turned on in response to a high level at the first node N1, writing the signal from the first clock signal terminal CK into the second node N2.

[0096] Optionally, refer to Figure 5As shown, the shift register also includes a second voltage regulator circuit. The second voltage regulator circuit is electrically connected to the first node N1, the third node N3, and the first power supply signal terminal VGH, configured to electrically connect the third node N3 to the first node N1 based on the signal from the first power supply signal terminal VGH. The second voltage regulator circuit includes a transistor T9. The first electrode of transistor T9 is electrically connected to the first node N1, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first power supply signal terminal VGH. Under the potential of the first power supply signal terminal VGH, transistor T9 remains continuously turned on, preventing leakage current from the third node N3 through the path of the second transistor T2 and the sixth transistor T6, reducing the stress of the third node N3 on the first node N1, and promoting voltage stability and preventing fluctuations in the third node N3, thus allowing the fourth transistor T4, which serves as the output transistor, to be fully turned on.

[0097] Alternatively, refer to Figure 6 As shown, in another example, the shift register further includes an auxiliary output sub-circuit and an auxiliary output control sub-circuit. The auxiliary output control sub-circuit includes a transistor T10, whose first electrode is electrically connected to the carry terminal CR, its second electrode is electrically connected to the second power supply signal terminal VGL, and its control electrode is electrically connected to the second node N2. In response to a high potential at the second node N2, transistor T10 is turned on, transmitting the potential of the second power supply signal terminal VGL to the carry terminal CR. The auxiliary output sub-circuit includes a transistor T11 and a fourth capacitor C4. The first electrode of transistor T11 is electrically connected to the second clock signal terminal CB, its second electrode is electrically connected to the carry terminal CR, and its control electrode is electrically connected to the third node N3. Transistor T11 is turned on in response to a high potential at the third node N3, transmitting the signal from the second clock signal terminal CB to the carry terminal CR. The fourth capacitor C4 is used to store the potential of the third node N3.

[0098] As can be seen, the signal output from the carry terminal CR is the same as the signal output from the output terminal Out, and can be used to cascade with another stage shift register. Of course, as... Figure 5 As shown, because the auxiliary output sub-circuit includes a fourth capacitor C4, the second capacitor C2 may not be included in the output sub-circuit 30. The function of the fourth capacitor C4 is the same as that of the second capacitor C2. Additionally, the auxiliary control sub-circuit may include a capacitor connected between the second node N2 and the second power supply signal terminal VGL, while the output control sub-circuit may not include a third capacitor C3.

[0099] In addition, although Figure 6 The example does not include a first voltage regulator circuit, but is not limited to it; the shift register may include... Figure 5 The first voltage regulator circuit 60, consisting of the first transistor T1 and the first capacitor C1 shown, is designed to prevent the output terminal Out and the carry terminal CR from being affected by the voltage jump of the second clock signal terminal CB.

[0100] To further understand the structural relationship of each cascaded shift register in the gate drive circuit, the driving process of the gate drive circuit is described below by referring to the timing diagram of the shift register and the driving process of the shift register.

[0101] Figure 7 Show Figure 6 The timing diagram of the shift register is shown. For a single-stage shift register, the driving process includes: stage 1 T1, stage 2 T2, stage 3 T3, and stage 4 T4.

[0102] In the first stage T1, the signal at the first clock signal terminal CK is high, the signal at the second clock signal terminal CB is low, the signal at the third clock signal terminal CB-2 is low, and the signal at the input terminal STV is high. The high-level period of the signal connected to the third clock signal terminal CB-2 overlaps with the high-level period of the signal connected to the second clock signal terminal CB2 for at least 1 hour. The fourth clock signal line CB2 is the synchronized signal.

[0103] Specifically, in response to the high level of the first clock signal terminal CK, the second transistor T2 turns on, inputting the high-level signal from the input terminal STV to the first node N1. Because transistor T9 remains on, the high-level signal is written to the third node N3 via the on-state transistor T9 and maintained by charging the fourth capacitor C4. In response to the high level of the third node N3, the fourth transistor T4 turns on, transmitting the low-level signal from the second clock signal terminal CB to the output terminal Out.

[0104] At the same time, the third transistor T3 is turned on, connecting the first power supply signal terminal VGH with the second node N2. The fifth transistor T5 is also turned on, and the output control sub-circuit also transmits a low-level signal to the output terminal Out.

[0105] In the second stage T2, the signal at the first clock signal terminal CK is low, the signal at the second clock signal terminal CB is high, the signal at the third clock signal terminal CB-2 changes from low to high, and the signal at the input terminal STV is low. The second transistor T2 and the third transistor T3 are turned off. Due to the effect of the fourth capacitor C4, the third node N3 maintains a high potential, and the fourth transistor T4 remains on, outputting the high-level signal from the second clock signal terminal CB to the output terminal Out. Furthermore, due to the bootstrap effect of the fourth capacitor C4, the potential of the third node N3 is higher than in the first stage T1.

[0106] Furthermore, because transistor T9 remains on, the potential change of the first node N1 is approximately the same as that of the third node N3. In the third control sub-circuit, transistor T8 turns on, writing a low-level signal from the first clock signal terminal CK to the second node N2, and the fifth transistor T5 turns off in response to the low-level signal. During this stage, because the third clock signal terminal CB-2 changes from low to high, the fourth node N4 controls the sixth transistor T6 to turn on when the third clock signal terminal CB-2 becomes high, writing a high-level signal to the fourth node N4.

[0107] In the third stage T3, the signal at the first clock signal terminal CK is high, the signal at the second clock signal terminal CB is low, the signal at the third clock signal terminal CB-2 changes from high to low, and the signal at the input terminal STV remains low.

[0108] At this time, the third transistor T3 turns on, writing the high-level signal of the first power supply signal terminal VGH into the second node N2. When the second node N2 and the third clock signal terminal CB-2 are both high, the sixth transistor T6 and the seventh transistor T7 turn on, writing the low-level signal of the second power supply signal terminal VGL into the first node N1. Therefore, the first node N1, the third node N3, and the fourth node N4 are all low. The fourth transistor T4 turns off, and the fifth transistor T5 turns on, outputting the low-level signal of the second power supply signal terminal VGL to the output terminal Out, thereby resetting the shift register of this stage.

[0109] In the fourth stage T4, the first clock signal terminal CK is low, the second clock signal terminal CB becomes high, the third clock signal terminal CB-2 changes from low to high, and the input terminal STV remains a low signal.

[0110] The second transistor T2 is off, the third transistor T3 is on, and the transistor T9 remains on. The second node N2 is at a high level. Under the action of the fourth capacitor C4, the third node N3 and the first node N1 are at a low level. The seventh transistor T7 and the fifth transistor T5 are on, and the fourth node N4 is at a low level. The output terminal Out still outputs a low level.

[0111] In the first stage T1, the second stage T2, and the fourth stage T4, the signal connected to the third clock signal terminal CB-2 overlaps with the high-level period of the second clock signal terminal CB for at least 1 hour. This overlap period can be used to reset the first node N1 and flexibly control the potential of the first node N1. In addition, by setting the signal connected to the third clock signal terminal CB-2 to be different from the clock signal connected to the second clock signal terminal CB, the RC of the current stage shift register can be reduced, and the output drive capability of the second clock signal terminal CB can be increased.

[0112] Furthermore, for any level shift register, in the first stage T1, a high-level signal is written to the first node N1 under the control of the high level period of the first clock signal CK, and in the second stage T2, a high-level signal is output at the output terminal Out segment when the second clock signal terminal CB is high.

[0113] Combination Figure 1 and Figure 7 The timing diagram shown, and further combined with Figure 3 As shown in the gate drive circuit diagram, if n represents the current stage and n+1 represents the next stage cascaded with the current stage, during the period when the first clock signal terminal CK of the nth stage shift register is high (i.e., the signal of the first clock signal line CK1 is high), the nth stage shift register begins to write a valid level signal. During this period, by setting the third clock signal line CK2 connected to the first clock signal terminal CK of the n+1th stage shift register to overlap with the first clock signal line CK1, the n+1th stage shift register enters the input writing stage earlier. Simultaneously, since the period when the second clock signal terminal CB of the nth stage shift register is high (i.e., the signal of the second clock signal line CB1 is high) overlaps with the period when the signal of the third clock signal line CK2 connected to the first clock signal terminal CK of the n+1th stage shift register is high, the n+1th stage shift register ends the input signal writing earlier. Furthermore, in the latter half of the second stage T2 (i.e., the second clock signal line CB) of the nth stage shift register, which is the overlapping period between the high level period of the fourth clock signal line CB2 connected to the second clock signal terminal CB of the (n+1)th stage shift register and the high level period of the second clock signal line CB, the (n+1)th stage shift register outputs a high level signal in advance, so that the scan signals output by each stage shift register have overlapping periods.

[0114] With this setting, during the display process of the high-frequency display panel, while maintaining a high refresh rate, the output duration of the scan signal is extended by utilizing the overlapping period, thereby ensuring that the transistors in the connected pixel circuit can be fully turned on, and ensuring the effective writing of data signals.

[0115] In addition, it is important to note that during the fourth stage T4 when the input signal of the second clock signal terminal CB transitions from low to high, the third node N3 is falsely raised due to the coupling effect of the second clock signal CB.

[0116] Reference Figure 8 As shown, Figure 8 for Figure 5 The diagram shows the output of the shift register, which includes the first voltage regulator circuit. Figure 6The diagram shows a simulation comparison of the shift register output, excluding the first voltage regulator circuit. The periods with significantly higher amplitudes are the effective output periods, during which the output signals overlap. Other ineffective output periods show waveforms with large amplitude fluctuations. Figure 6 The shift register shown has a waveform with almost no fluctuations. Figure 5 The shift register shown is an example. It can be seen that without the first voltage regulator circuit, the overlapping of clock signals causes significant interference from the signal jumps at the second clock signal terminal CB at the output. With the first voltage regulator circuit, the output can be effectively stabilized, reducing the interference of the clock signal coupling of the output transistor on the output signal.

[0117] Based on the same inventive concept, embodiments of this disclosure also provide a gate driving circuit, which includes a plurality of cascaded shift registers as described in the above embodiments, wherein the output or carry terminal of the nth stage shift register is electrically connected to the input terminal of another stage shift register, where n is a positive integer greater than or equal to 1.

[0118] The input of the first-stage shift register is electrically connected to the first initial signal line stv1, and the input of the second-stage shift register is electrically connected to the second initial signal line stv2.

[0119] There is an overlap of at least 1 hour between the effective level period of the signal connected to the first initial signal line and the effective level period of the signal connected to the second initial signal line.

[0120] The output of the nth stage shift register is electrically connected to the input of the (n+2)th stage shift register.

[0121] Optionally, the first clock signal terminal CK of the 4m-3 stage shift register is electrically connected to the first clock signal line CK1, the second clock signal terminal CB is electrically connected to the third clock signal line CB1, and the third clock signal terminal CB-2 is electrically connected to the fourth clock signal line CB2. The first clock signal terminal CK of the 4m-2 stage shift register is electrically connected to the second clock signal line CK2, the second clock signal terminal CB is electrically connected to the fourth clock signal line CB2, and the third clock signal terminal CB-2 is electrically connected to the third clock signal line CB1. The first clock signal terminal CK of the 4m-1 stage shift register is electrically connected to the third clock signal line CB1, the second clock signal terminal CB is electrically connected to the first clock signal line, and the third clock signal terminal CB-2 is electrically connected to the second clock signal line CK2. The first clock signal terminal of the 4m stage shift register is electrically connected to the fourth clock signal line CB2, the second clock signal terminal CB is electrically connected to the second clock signal line CK2, and the third clock signal terminal CB-2 is electrically connected to the first clock signal line CK1, where m is a positive integer.

[0122] It is understandable that when m=1, the structure of the gate drive circuit is as follows: Figure 3 As shown, this implementation is not limited to this, and the specific value of m can be selected as needed.

[0123] Optionally, the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register for at least 1 hour, and the effective level signal period of the signal connected to the second clock signal terminal of the 2m-1 stage shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register for at least 1 hour.

[0124] With this configuration, clock signals are provided using at least the first to fourth clock signal lines, and the effective level periods of the corresponding clock signals provided to adjacent shift registers overlap by at least 1 hour. This results in overlapping effective level periods of the output signals of adjacent shift register circuits, increasing the length of the effective output level time and ensuring that data signals can be fully written at high scan frequencies.

[0125] Reference Figure 9 As shown in the figure, a simulation diagram of the output of the gate drive circuit according to an embodiment of this disclosure is presented. (Refer to...) Figure 9 As shown, the simulation process uses a gate drive circuit composed of cascaded 5-stage shift registers. By designing the effective level periods of the clock signal to overlap sequentially, the output signals of each stage have overlapping periods. Compared with the output signals without overlapping periods, it can ensure that the duration of each stage output is increased within a limited time period, thereby increasing the conduction time of the transistors in the pixel circuit controlled by the output signal, ensuring that the data signal is fully written.

[0126] Based on the same inventive concept, embodiments of this disclosure also provide a driving method applied to the gate driving circuit described above, comprising:

[0127] In the first stage of the nth-stage shift register, based on the fact that the signal connected to the first clock signal terminal is at an effective level and the signal connected to the second clock signal terminal is at an invalid level, the input sub-circuit and output sub-circuit of the nth-stage shift register are turned on, and the first power supply signal terminal and the second node are turned on through the first control sub-circuit of the nth-stage shift register.

[0128] In the second stage of the nth stage shift register, the output sub-circuit of the nth stage shift register is turned on to output an effective level signal. Based on the signal connected to the second clock signal terminal of another stage shift register cascaded with the nth stage shift register becoming effective, the output sub-circuit of the other stage shift register is turned on to output an effective level signal.

[0129] Those skilled in the art should understand that the specific process of the above method has been explained in detail with reference to the timing diagrams when describing the specific circuit principle of the shift register above, and will not be repeated here.

[0130] In this embodiment, by providing a shift register with a second control sub-circuit, and the effective level period of the signal connected to the third clock signal terminal, which serves as the control terminal in the control sub-circuit, overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1 hour, the reset time of the first node can be controlled, the adjustment flexibility of the first node can be improved, the output driving capability can be increased, and the display effect can be improved.

[0131] In addition, clock signals are provided using at least the first to fourth clock signal lines, and the effective level periods of the corresponding clock signals provided to adjacent shift registers overlap by at least 1H. This results in overlapping effective level periods of the output signals of adjacent shift register circuits, increasing the length of the effective output level time and ensuring that data signals can be fully written at high scan frequencies.

[0132] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which includes the gate driving circuit described in the above embodiments.

[0133] This display panel, including the aforementioned gate drive circuit, can effectively achieve high-frequency display.

[0134] Optionally, refer to Figure 10 The example diagram shown illustrates a display panel comprising: at least one pixel driving circuit; the pixel circuit includes: a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a first reset sub-circuit, and a light-emitting unit.

[0135] The driver sub-circuit, electrically connected to the fourth node Q4, the fifth node Q5, and the sixth node Q6, is configured to generate a drive current based on the data signal input to the fourth node Q4.

[0136] The light-emitting control sub-circuit is electrically connected to the fourth power supply signal terminal, the fifth node Q5, the sixth node Q6, the first and second light-emitting control terminals EM1 and EM2, and the anode of the light-emitting unit D. It is configured to transmit drive current to the anode based on the signals from the first and second light-emitting control terminals EM1 and EM2.

[0137] The write sub-circuit is electrically connected to the fourth node Q4, the data signal terminal Vdata, and the write control terminal Gate. It is configured to transmit the data signal connected to the data signal terminal Vdata to the fourth node Q4 based on the signal from the write control terminal Gate.

[0138] The first reset sub-circuit is electrically connected to the first reset control terminal Reset1, the first reset signal terminal Vint2, and the sixth node Q6. It is configured to electrically connect the first reset signal terminal Vint2 and the sixth node Q6 based on the signal from the first reset control terminal Reset1.

[0139] The first reset signal terminal Vint2 is connected to a DC or AC signal with a changing potential.

[0140] In this embodiment, by setting the reset signal terminal for resetting the sixth node of the driving sub-circuit to a DC or AC signal with a changing potential, different reset signals can be output according to the threshold offset in different display stages in the driving sub-circuit. This ensures that the reset effect is consistent in different time periods, maintains consistent display brightness in different time periods, and improves the display effect.

[0141] Specifically, refer to Figure 10 As shown, the driving sub-circuit includes: an eighth transistor M8, the first electrode of the eighth transistor M8 is electrically connected to the fifth node Q5, the second electrode is electrically connected to the sixth node Q6, and the control electrode is electrically connected to the fourth node Q4.

[0142] The light-emitting control sub-circuit includes: a ninth transistor M9 and a tenth transistor M10. The first electrode of the ninth transistor M9 is electrically connected to the fourth power supply signal terminal VDD, the second electrode is electrically connected to the fifth node Q5, and the control electrode is electrically connected to the first light-emitting control terminal EM1. The first electrode of the tenth transistor is electrically connected to the sixth node Q6, the second electrode is electrically connected to the anode, and the control electrode is electrically connected to the second light-emitting control terminal EM2.

[0143] The first reset sub-circuit includes an eleventh transistor M11. The first electrode of the eleventh transistor M11 is electrically connected to the first reset signal terminal Vinit2, the second electrode is electrically connected to the sixth node Q6, and the control electrode is electrically connected to the first reset control terminal Reset1.

[0144] Optionally, refer to Figure 10 As shown, the pixel circuit is a discrete compensation circuit. The pixel circuit also includes a write sub-circuit and a compensation sub-circuit. The write sub-circuit is electrically connected to the fourth node, the data signal terminal, and the write control terminal, and is configured to transmit the data signal input to the data signal terminal to the fourth node based on the signal from the write control terminal.

[0145] The compensation sub-circuit is electrically connected to the set signal terminal, the set control terminal, and the fourth node. It is configured to transmit the signal from the set signal terminal to the fourth node based on the signal from the set control terminal to perform threshold voltage compensation.

[0146] Continue to refer to Figure 10 As shown, the write sub-circuit includes a twelfth transistor M12. The first electrode of the twelfth transistor M12 is electrically connected to the data signal terminal Vdata, the second electrode is electrically connected to the fourth node Q4, and the control electrode is electrically connected to the write control terminal Gate. The compensation sub-circuit includes a thirteenth transistor M13. The first electrode of the thirteenth transistor M13 is electrically connected to the set signal terminal Vinit1, the second electrode is electrically connected to the fourth node Q4, and the control electrode is electrically connected to the set control terminal.

[0147] Figure 11 Show Figure 10 Timing diagram of key ports in the circuit schematic. The pixel driving process includes reset phase t1, compensation phase t2, writing phase t3, and emission phase t4.

[0148] During the reset phase t1, the second light-emitting control terminal EM2, the first reset control terminal Reset2, and the set control terminal Reset1 are at high levels. The tenth transistor M10, the eleventh transistor M11, and the thirteenth transistor M13 are all turned on, inputting the signal from the first reset signal terminal Vinit2 to the sixth node Q6 and the seventh node Q7, and writing the signal from the set signal terminal Vinit1 to the fourth node Q4. At this time, the signal input to the set signal Vinit1 is essentially a reset signal.

[0149] During compensation phase t2, the set control terminal Reset1 is high, turning on the thirteenth transistor M13. This directly writes the compensation signal from the set signal terminal Vinit1 to the fourth node N4, performing threshold compensation on the eighth transistor M8, which acts as the driving transistor. Simultaneously, the first light-emitting control terminal EM1 is also high, turning on the ninth transistor M9 to activate the eighth transistor M8, thus cooperating to achieve threshold compensation.

[0150] During the writing phase t3, the scan signal output by the gate drive circuit is sent to the write control terminal Gate, the twelfth transistor M12 is turned on, and the data signal connected to the data signal terminal Vdata is input to the control terminal of the eighth transistor M8.

[0151] During the light-emitting stage t4, the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 are at a high level. Under the action of capacitor C, the fourth node Q4 remains on, thereby forming a driving current path to output to the anode of the light-emitting unit D.

[0152] The above settings, utilizing separate data signal writing and threshold compensation, achieve the goal of extending the threshold compensation time.

[0153] In particular, considering that the image display process includes refresh frames and hold frames, during the refresh frame stage, the pixel driving circuit writes data signals, while during the hold frame stage, the pixel driving circuit does not write data signals. The brightness of the display unit is different when data signals are written and when data signals are not written, which will produce visible flicker.

[0154] The inventors discovered through research that the reason for the difference in brightness between the two stages is that when the eighth transistor M8 is turned on in one state for a long time during the frame holding stage, it will produce a characteristic shift in a certain direction. In other words, the degree of shift is different between the two stages, resulting in a fast flash at the moment of switching.

[0155] To address this issue, in the embodiments of this disclosure, the signal connected to the first reset signal terminal is configured to be a DC signal or an AC signal with a changing potential. More preferably, the first reset signal terminal Vinit2 receives a signal with a first amplitude during the refresh frame and a signal with a second amplitude during the hold frame. The specific amplitude relationship and values ​​are determined based on the offset direction and amplitude of the driving transistor. The offset direction and amplitude are determined by the detection mechanism in the display panel, and will not be elaborated further here.

[0156] By using the above settings, flickering during frame refresh and frame hold transitions is avoided, thus improving the display quality.

[0157] It should be noted that the above pixel circuit structure is only illustrative and is not intended to be limiting. Pixel driving circuits composed of other numbers of transistors are also applicable to the embodiments of this disclosure, as long as the pixel circuit resets the second pole of the driving transistor through the first reset circuit.

[0158] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including the display panel described in the above embodiments.

[0159] In this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, vehicle display, digital photo frame, or navigator. By using a display panel with the above gate driving circuit, the normal display of the screen can be ensured during the display process of the display device, especially at high refresh rates. It has strong driving capability and broad application prospects.

[0160] This disclosure addresses existing problems by providing a shift register, a gate driving circuit and its driving method, a display panel and a display device. By providing a shift register with a second control sub-circuit, wherein the effective level period of the signal connected to the third clock signal terminal (which serves as the control terminal) in the control sub-circuit overlaps with the effective level period of the signal connected to the second clock signal terminal in the output sub-circuit for at least 1 hour, the reset time of the first node can be controlled, improving the adjustment flexibility of the first node, increasing the output driving capability, and improving the display effect, thus having broad application prospects.

[0161] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A shift register, characterized in that, include: An input sub-circuit is electrically connected to an input terminal, a first node, and a first clock signal terminal, and is configured to electrically connect the input terminal to the first node based on the signal from the first clock signal terminal. A first control sub-circuit is electrically connected to a first power signal terminal, a second node and a first clock signal terminal, and is configured to electrically connect the first power signal terminal and the second node based on the signal of the first clock signal terminal. An output sub-circuit is electrically connected to a third node, a second clock signal terminal, and an output terminal, and is configured to output the signal of the second clock signal terminal to the output terminal based on the signal of the third node. An output control sub-circuit is electrically connected to the second node, the second power signal terminal and the output terminal, and is configured to electrically connect the second power signal terminal and the output terminal based on the signal of the second node. The second control sub-circuit is electrically connected to the third clock signal terminal, the second power signal terminal, the second node, and the first node, and is configured to electrically connect the second power signal terminal to the first node based on the signals from the third clock signal terminal and the second node. Wherein, the effective level period of the signal at the third clock signal terminal overlaps with the effective level period of the signal at the second clock signal terminal by at least 1H, and the signals at the third clock signal terminal and the second clock signal terminal are asynchronous signals, where H represents the time required for the shift register to scan one row of pixels.

2. The shift register according to claim 1, characterized in that, Also includes: The first voltage regulator circuit includes: a first transistor and a first capacitor. Wherein, the first electrode of the first capacitor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the first electrode of the first transistor, the second electrode of the first transistor is electrically connected to the third node, and the control electrode is electrically connected to the second node.

3. The shift register according to claim 1, characterized in that, Also includes: The third control sub-circuit is electrically connected to the first node, the second node, and the first clock signal terminal, and is configured to electrically connect the first clock signal terminal to the second node based on the signal from the first node.

4. The shift register according to claim 1, characterized in that, Also includes: The second voltage regulator circuit is electrically connected to the first node, the third node, and the first power signal terminal, and is configured to electrically connect the third node to the first node based on the signal from the first power signal terminal.

5. The shift register according to claim 1, characterized in that, The input sub-circuit includes a second transistor, with its first electrode electrically connected to the input terminal and its second electrode electrically connected to the first node, and its control electrode electrically connected to the first clock signal terminal. The first control sub-circuit includes a third transistor, wherein the first terminal of the third transistor is electrically connected to the first power supply signal terminal, the second terminal is electrically connected to the second node, and the control terminal is electrically connected to the first clock signal terminal. The output sub-circuit includes a fourth transistor and a second capacitor. The first electrode of the fourth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the third node. The first electrode of the second capacitor is electrically connected to the third node, and the second electrode is electrically connected to the output terminal. The output control sub-circuit includes a fifth transistor and a third capacitor. The first electrode of the fifth transistor is electrically connected to the output terminal, the second electrode is electrically connected to the second power signal terminal, and the control electrode is electrically connected to the second node. The first electrode of the third capacitor is electrically connected to the second node, and the second electrode is electrically connected to the second power signal terminal. The second control sub-circuit includes a sixth transistor and a seventh transistor. The first electrode of the sixth transistor is electrically connected to the first node, the second electrode is electrically connected to the first electrode of the seventh transistor, the control electrode is electrically connected to the third clock signal terminal, the second electrode of the seventh transistor is electrically connected to the second power signal terminal, and the control electrode is electrically connected to the second node.

6. The shift register according to claim 3, characterized in that, The third control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the first clock signal terminal, the second electrode of which is electrically connected to the second node, and the control electrode of which is electrically connected to the first node.

7. A gate driving circuit, characterized in that, The system includes multiple cascaded shift registers as described in any one of claims 1-6, wherein the output or carry of the nth stage shift register is electrically connected to the input of another stage shift register, where n is a positive integer greater than or equal to 1. The input of the first-stage shift register is electrically connected to the first initial signal line, and the input of the second-stage shift register is electrically connected to the second initial signal line. The effective level period of the signal connected to the first initial signal line overlaps with the effective level period of the signal connected to the second initial signal line by at least 1 hour. The output of the nth stage shift register is electrically connected to the input of the (n+2)th stage shift register.

8. The gate driving circuit according to claim 7, characterized in that, The first clock signal terminal of the 4m-3 stage shift register is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line. The first clock signal terminal of the 4m-2 stage shift register is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 4m-1 stage shift register is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. The first clock signal terminal of the 4m-stage shift register is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. Where m is a positive integer.

9. The gate driving circuit according to claim 8, characterized in that, in, The effective level signal period of the signal connected to the first clock signal terminal of the 2m-1 stage shift register overlaps with the effective level signal period of the signal connected to the first clock signal terminal of the 2m stage shift register for at least 1 hour.

10. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 7-9.

11. The display panel according to claim 10, characterized in that, Also includes: At least one pixel circuit, the pixel circuit comprising: a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a first reset sub-circuit, and a light-emitting unit. The driving sub-circuit, electrically connected to the fourth, fifth, and sixth nodes, is configured to generate a driving current based on the data signal input from the fourth node. The light-emitting control sub-circuit is electrically connected to the fourth power supply signal terminal, the fifth node, the sixth node, the first and second light-emitting control terminals, and the anode of the light-emitting unit. It is configured to transmit the driving current to the anode based on the signals from the first and second light-emitting control terminals. The write sub-circuit is electrically connected to the fourth node, the data signal terminal, and the write control terminal, and is configured to transmit the data signal connected to the data signal terminal to the fourth node based on the signal from the write control terminal. The first reset sub-circuit is electrically connected to the first reset control terminal, the first reset signal terminal, and the sixth node, and is configured to electrically connect the first reset signal terminal to the sixth node based on the signal from the first reset control terminal. The first reset signal terminal is connected to a DC or AC signal with a changing potential.

12. The display panel according to claim 11, characterized in that, The image display process of the light-emitting unit includes a refresh frame and a hold frame. The first reset signal terminal receives a signal with a first amplitude in the refresh frame and a signal with a second amplitude in the hold frame. The first amplitude is greater than the second amplitude.

13. The display panel according to claim 11, characterized in that, The output of the shift register is electrically connected to the write control terminal of the pixel circuit of the corresponding row.

14. A driving method for a gate driving circuit as described in any one of claims 7-9, characterized in that, In the first stage of the nth-stage shift register, based on the fact that the signal connected to the first clock signal terminal is at an effective level and the signal connected to the second clock signal terminal is at an invalid level, the input sub-circuit and the output sub-circuit of the nth-stage shift register are turned on, and the first power supply signal terminal and the second node are turned on through the first control sub-circuit of the nth-stage shift register; In the second stage of the nth stage shift register, the output sub-circuit of the nth stage shift register is turned on to output a valid level signal. Based on the signal connected to the second clock signal terminal of another stage shift register cascaded with the nth stage shift register becoming valid, the output sub-circuit of the other stage shift register is turned on to output a valid level signal.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 10-13.

Images