On-chip check circuit, memory and storage device

Abstract

The application provides an on-chip check circuit, a memory and a storage device. The on-chip check circuit comprises an encoder and a first error correction circuit. In a write stage, the encoder generates a first check code according to a bit group represented by write data and an error correction matrix and writes the first check code into a storage array. In a read stage, the encoder generates a second check code according to a bit group represented by read data and the error correction matrix, and generates an error correction code based on the read first check code and the generated second check code. The first error correction circuit receives the read data, performs single-bit error correction on the read data according to the error correction code output by the encoder, and outputs first error correction data. The error correction matrix comprises an error correction code corresponding to each bit in each beat. The error correction matrix satisfies: the exclusive-OR result of error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits. The scheme can realize data checking.

Description

Technical Field

[0001] This application relates to memory technology, and more particularly to an on-chip verification circuit, a memory, and a storage device. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In practical applications, on-chip error checking and correction (On-Die ECC) is introduced to ensure data reliability. Specifically, on-chip error checking and correction can support the correction of single-bit errors, but for multi-bit errors, on-chip error checking and correction may result in false corrections. The data after false correction is transmitted to an external source for further verification, such as memory module-level error checking and correction (Rank-level ECC), which may further aggravate the bit error situation. Summary of the Invention

[0004] Embodiments of this application provide an on-chip verification circuit, a memory, and a storage device.

[0005] According to some embodiments, a first aspect of this application provides an on-chip verification circuit applied to a memory. The on-chip verification circuit includes: an encoder connected to the memory's storage array, configured to generate a first verification code and write it to the storage array based on the written data and bit groups represented by the error correction matrix during a write phase; and to generate a second verification code based on the read data and bit groups represented by the error correction matrix during a read phase, and to generate an error correction code based on the read first verification code and the second verification code; and a first error correction circuit connected to the encoder, configured to receive the read data, and perform single-bit error correction on the read data according to the error correction code output by the encoder, and then output first error correction data; wherein the error correction matrix includes an error correction code corresponding to each bit in each phase, and the error correction matrix satisfies that: the XOR result of the error correction codes corresponding to any plurality of bits is not the same as the error correction code corresponding to any bit in the same phase as one of the plurality of bits.

[0006] In some embodiments, in the error correction matrix, the XOR result of the error correction codes corresponding to any plurality of bits belonging to the same phase is not the same as the error correction code corresponding to any bit in the error correction matrix; the XOR result of the error correction codes corresponding to any plurality of bits belonging to different phases is not the same as the error correction code corresponding to any bit in the same phase as one of the plurality of bits.

[0007] In some embodiments, the on-chip verification circuit further includes: a data selector; a first input terminal of the data selector receives write data, a second input terminal of the data selector receives read data, and an output terminal of the data selector is connected to the input terminal of the encoder and the storage array; the data selector is used to output write data during the write phase and output read data during the read phase.

[0008] In some embodiments, the first error correction circuit includes: a first decoder and a first correction circuit; the input terminal of the first decoder is connected to the encoder, the first decoder is used to receive the error correction code output by the encoder, determine the first target position to be flipped based on the error correction code and the error correction matrix, and output a first error correction instruction pointing to the first target position; the first correction circuit is connected to the output terminal of the first decoder, the first correction circuit is used to receive readout data, and perform data flipping on the bits under the first target position according to the first error correction instruction to obtain first error correction data.

[0009] In some embodiments, the on-chip verification circuit further includes: a plurality of buffer circuits, including: a first buffer circuit, the input of which receives write data, and the output of which is connected to a first input of a data selector, for buffering and outputting the received write data; a second buffer circuit, the input of which is connected to the output of the data selector, and the output of which is connected to a memory array, for buffering and outputting the write data output by the data selector during the write phase; and a third buffer circuit, the input of which is connected to an encoder, and the output of which is connected to the memory array, for buffering and outputting the first data output by the encoder during the write phase. A first checksum buffer output; a fourth buffer circuit, the input of which is connected to the storage array, and the output of which is connected to the encoder, used to buffer the first checksum read from the storage array during the reading phase; a fifth buffer circuit, the input of which is connected to the storage array, and the output of which is connected to the second input of the data selector and the first error correction circuit, used to buffer the read data read from the storage array during the reading phase; a sixth buffer circuit, the input of which is connected to the output of the first error correction circuit, and the output of which is used to buffer the first error correction data output by the first error correction circuit.

[0010] In some embodiments, the buffer circuit includes an even number of inverters connected in series.

[0011] In some embodiments, the XOR result of the error correction codes corresponding to any plurality of bits is not the same as the error correction code corresponding to any bit in the same phase as one of the plurality of bits, including: the XOR result of the error correction codes corresponding to any two bits in the same phase is not the same as the error correction code corresponding to any bit in the same phase as one of the two bits.

[0012] In some embodiments, the XOR results of the error correction codes corresponding to different bits belonging to the same step in the error correction matrix are different.

[0013] In some embodiments, the on-chip verification circuit further includes: a second error correction circuit; the second error correction circuit is connected to the encoder, receives a multi-bit error correction instruction, and reads out data or first error correction data, and is used to respond to the multi-bit error correction instruction pointing to a target frame number, and output the second error correction data after performing multi-bit error correction on the received data according to the error correction code output by the encoder; wherein, the multi-bit error correction instruction pointing to a target frame number indicates that a multi-bit error occurred in the readout data in the same frame, and the multi-bit error occurred in the target frame number.

[0014] In some embodiments, the second error correction circuit includes: a second decoder and a second correction circuit; the input of the second decoder is connected to the encoder, the second decoder receives an error correction code and a multi-bit error correction instruction, and is used to determine the second target position to be flipped based on the target frame number pointed to by the multi-bit error correction instruction, the error correction code, and the error correction matrix in response to the multi-bit error correction instruction pointing to the target frame number, and output a second error correction instruction pointing to the second target position; the second correction circuit is connected to the output of the second decoder, the second correction circuit is used to receive readout data or first error correction data, and perform data error correction on the bits at the second target position according to the second error correction instruction to obtain second error correction data.

[0015] In some embodiments, the second correction circuit is connected to the data input terminal of the first error correction circuit for receiving read data, or the second correction circuit is connected to the output terminal of the first error correction circuit.

[0016] According to some embodiments, a second aspect of this application provides a memory including: a memory array and an on-chip verification circuit as described in any of the preceding embodiments.

[0017] According to some embodiments, a third aspect of this application provides a storage device, including: an off-chip verification circuit and at least one memory as described in any of the preceding embodiments; the off-chip verification circuit is connected to at least one memory and is used to verify each bit of data in first error-corrected data output by at least one memory during a read phase, the verification including single-bit error correction and multi-bit detection.

[0018] In some embodiments, the off-chip verification circuit includes: an indicator circuit; the indicator circuit is configured to send a multi-bit error correction instruction pointing to a target number of times to all memories if a multi-bit error exists in the same data block.

[0019] In some embodiments, the off-chip verification circuit further includes: a processing circuit, configured to perform a first data integration on the first error correction data output from different memories, and perform data verification on the integrated data; if there are no data errors or they can be corrected, then output the off-chip verified data; if the memory needs to perform secondary correction, then after receiving the second error correction data, the integrated data is replaced with erroneous data based on the second error correction data and data verification is performed again; if there are no data errors or they can be corrected, then output the off-chip verified data.

[0020] The on-chip verification circuit, memory, and storage device provided in this application include an encoder and a first error correction circuit. The encoder is responsible for generating verification codes for the write and read stages, and obtaining error correction codes based on the verification codes of the two stages. The first error correction circuit performs single-bit error correction on the data read in the read stage based on the error correction codes. The verification codes in this scheme are generated by the encoder based on bit groups represented by the error correction matrix. The error correction matrix includes the error correction code corresponding to each bit in each frame, and satisfies that the bit corresponding to the XOR result of any number of error correction codes is not located in the same frame as any bit of those multiple bits. Therefore, even if there are multiple bit errors that lead to the generation of miscorrected error correction codes, since the miscorrected error correction codes are not located in the same frame as the bits where the multiple bit errors occurred, it will not lead to new multi-bit errors in the same frame, thereby avoiding further expansion of data errors, realizing data verification, and effectively improving the reliability of verification. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0022] Figure 1 This is an example diagram illustrating the architecture of a memory according to one embodiment;

[0023] Figure 2 This is a structural example diagram of a storage cell shown in one embodiment;

[0024] Figure 3 This is a flowchart illustrating an example of on-chip verification.

[0025] Figure 4 This is a schematic diagram of an example architecture;

[0026] Figure 5 Here is a sample data structure diagram;

[0027] Figure 6 This is a schematic diagram of an example on-chip verification circuit;

[0028] Figure 7 Here is an example of a single-bit error;

[0029] Figure 8 Here is an example of a two-bit error;

[0030] Figure 9 Here is a sample data structure diagram;

[0031] Figure 10 This is a schematic diagram of an example on-chip verification circuit;

[0032] Figure 11 This is a schematic diagram of an example on-chip verification circuit;

[0033] Figure 12 This is a schematic diagram of an example on-chip verification circuit;

[0034] Figure 13 This is a schematic diagram of an example buffer circuit.

[0035] Figure 14 This is a schematic diagram of an example on-chip verification circuit;

[0036] Figure 15 This is a schematic diagram of an example on-chip verification circuit;

[0037] Figure 16 An example diagram of the structure of a memory;

[0038] Figure 17 This is a structural example diagram of a storage device.

[0039] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0041] The terms "comprising" and "having" in this application are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as markings or distinctions and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings.

[0042] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0043] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0044] Figure 1 This is an example diagram of a memory architecture shown in one embodiment, such as... Figure 1 As shown, taking DRAM as an example, it includes a data input / output buffer, row decoder, column decoder, sense amplifier, and memory array. The data input / output buffer belongs to the peripheral circuitry, while the sense amplifier, row decoder, column decoder, and memory array belong to the array circuitry. The memory array mainly consists of word lines, bit lines, and memory cells. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines forms the memory cell of the memory array.

[0045] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to one embodiment. The memory cell mainly consists of a transistor switch M and a capacitor C. The capacitor is used to store data, and the transistor switch is used to turn off or on depending on the selected state.

[0046] Access to a memory cell can be achieved by controlling word lines and bit lines. Taking a read scenario as an example: when data needs to be read from a memory cell, the word line of the row containing that memory cell can be selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and the state of capacitor C can be detected by sensing and amplifying the bit line signal. For example, if the bit data stored in the memory cell is 1, then after transistor M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when writing bit data to a memory cell, such as writing 1, the word line of the row containing that memory cell can be selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and by setting the logic level of the bit line to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0047] In practical applications, considering the influence of various factors such as process deviations, ionizing radiation, temperature, and data loss, discrepancies may occur between the data actually read and the data written, resulting in data errors. Therefore, to ensure data accuracy, on-chip error checking and correction (On-Die ECC) is introduced. Based on on-chip error checking and correction, the memory can verify its own data, achieving single-bit error correction. Taking DDR5 of Double Data Rate Synchronous Dynamic Random Access Memory (DDR) as an example, it generates 8 parity bits for every 128 bits of data. As an example, Figure 3 Here is a schematic diagram of an example on-chip verification process, such as... Figure 3 As shown, the on-chip verification process roughly includes the following steps: When data is written, the bit verifier writes 128 bits of data (write data) to the memory as needed, generates 8 bits of first check data, and stores the write data and check data together in the memory; when data is read, 128 bits of data (read data) and 8 bits of the first check data are read from the memory. The error correction code generator generates 8 bits of second check data based on the read 128 bits of data, and compares the generated second check data with the first check data read from the memory to generate an error correction code. The error correction code determines whether the read data contains errors. For example, if the error correction code is all 0s, it indicates no error; if it is not 0, it indicates a data error. Correspondingly, the error correction code decoder decodes the error code to locate the data error position. The error corrector performs a bit flipping correction on the bits at the data error position, for example, flipping 0 to 1 or 1 to 0, and outputs the corrected 128 bits of data.

[0048] In the example technology, data verification is configured with on-chip and off-chip verification, such as Rank-level Error Checking and Correction (ROC). In practical applications, the entire DRAM system can be divided into the following layers from top to bottom: channel, dual in-line memory modules (DIMMs), RANK, chip, bank, sub-array, local sub-array (MAT), row, and cell. A bank refers to chips that receive the same Chip Select (CS) signal and can be accessed through the same memory channel. All chips in a bank share the address, control, and data lines provided by the same memory channel. The memory controller can perform read and write operations on all chips within the same bank. Specifically, on-chip verification targets the data in the memory array of each chip, outputting data step-by-step in units of one clock cycle; off-chip verification targets each clock cycle of data output by all chips within a bank. As an example, Figure 4 This is a schematic diagram of an example architecture. Figure 5 Here is an example data structure diagram, such as Figure 4 As shown, a dual in-line memory module has a library and a chip for storing verification data (the chip not shaded in the figure). The library contains eight memory chips. Figure 4 (The chip is filled with shaded areas). Assuming each memory chip outputs 8 bits per cycle, for a total of 16 cycles, then... Figure 5 As shown, the aforementioned library contains DRAM0 to DRAM7. Each memory chip stores 128 bits of data, d0 to d127. Each memory chip has eight data ports, DQ0 to DQ7. This 128 bits of data is output in 16 cycles. In each cycle, 8 bits of data are output through data ports DQ0 to DQ7. For example, for any memory chip, in the first cycle, it outputs 8 bits (d0 to d7) through data ports DQ0 to DQ7; in the second cycle, it outputs 8 bits (d8 to d15), and so on, until the 16th cycle, when it outputs d120 to d127. To explain using the above example, on-chip verification is performed by each memory chip on its own 128 bits of data. Off-chip verification, on the other hand, is performed at the RANK level on the data output by these eight memory chips in each cycle. For instance, if each memory chip outputs 8 bits per cycle, then the eight memory chips output 64 bits per cycle. Off-chip verification then verifies these 64 bits per cycle. Current on-chip verification technology can correct single-bit errors, while off-chip verification technology can correct single-bit errors and detect multi-bit (e.g., double-bit) errors.

[0049] In practical applications, multi-bit errors may occur in a certain memory chip. On-chip verification for multi-bit errors may result in false corrections. The corrected data is then transmitted externally for off-chip verification. During off-chip verification, newly generated false correction bits may further generate more false corrections, exacerbating the error situation. To avoid the amplification of data errors, some aspects of the embodiments of this application involve the above considerations. The following examples illustrate the solution.

[0050] Example 1

[0051] Figure 6 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 6 As shown, the on-chip verification circuit 31 includes: an encoder 11 and a first error correction circuit 12;

[0052] The encoder 11, connected to the storage array 13 of the memory, is used to generate a first check code and write it to the storage array 13 based on the written data Data1 and the bit group represented by the error correction matrix during the write phase; and to generate a second check code based on the read data Data2 and the bit group represented by the error correction matrix during the read phase, and to generate an error correction code Syn based on the read first check code and the second check code.

[0053] The first error correction circuit 12 is connected to the encoder 11 and is used to receive the read data Data2, and perform single-bit error correction on the read data Data2 according to the error correction code output by the encoder 11, and then output the first error correction data Correct Data1.

[0054] The error correction matrix includes the error correction code corresponding to each bit in each cycle. The error correction matrix satisfies the following condition: the XOR result of the error correction codes corresponding to any plurality of bits is not the same as the error correction code corresponding to any bit in the same cycle as one of the plurality of bits. In practical applications, the circuit provided in this embodiment can be applied to various memories. As an example, it can be applied to, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0055] It should be noted that the description of writing the first parity bit into the memory array in this application needs to be understood based on the actual chip design. In some embodiments, the target storage areas for the written data and the parity bit are the same, meaning that every area of ​​a single DRAM can be used to store the written data and the parity bit. In other embodiments, the target storage areas for the written data and the parity bit are different, and they are stored in different locations within the DRAM. This document does not impose any limitations on the writing area of ​​the parity bit, and the final storage locations of the written data and the parity bit are collectively referred to as the memory array.

[0056] Specifically, a single-bit error refers to a situation where a single bit in the data to be verified is incorrect. This error occurs when the data written and read are inconsistent. For example, a bit originally written to the storage array might be 1 or 0, but due to various factors, that bit is flipped to 0 or 1 in the memory array, resulting in an error when that bit is subsequently read. Figure 7 As an example of a single-bit error, such as Figure 7 As shown, taking the data to be verified as the verification object of on-chip verification, for example, a memory storing 128 bits, assuming the shaded bits are the erroneous bits, as shown in the figure, one bit d0 in the 128 bits stored in the illustrated memory is erroneous, i.e., a single-bit error has occurred. In practical applications, both on-chip and off-chip verification can achieve single-bit error correction. That is, for the case of a single-bit error, the erroneous bit can be accurately located and its data can be flipped, thereby achieving accurate error correction. For... Figure 7 As shown, on-chip verification can correct errors in bit d0, thus obtaining accurate 128 bits.

[0057] In practical applications, in addition to the single-bit error scenario described above, multi-bit errors may also occur. Specifically, a multi-bit error occurs when at least two bits of data are corrupted. An example is provided with reference to the accompanying diagram. Figure 8 As an example of a two-bit error, such as Figure 8 As shown, taking on-chip verification as an example, two bits out of the 128 bits shown in the figure, namely bits d0 and d17, are erroneous, i.e., a double-bit error occurs. For multi-bit errors, current on-chip and off-chip verification can detect multi-bit errors, but cannot correct them. This is because, although verification can detect whether multiple bits in the data to be verified are erroneous, current verification methods cannot determine the specific positions of the erroneous bits, thus preventing effective error correction. Conversely, taking on-chip verification as an example, still combining... Figure 8 For example, assuming data error correction is based on on-chip parity, if the error correction code generated based on multi-bit errors is the same as the error correction code corresponding to a single bit, it may actually cause a new bit to be incorrect. Figure 8 As shown, the error correction code generated due to the multi-bit error is the same as the error correction code corresponding to d6. After performing on-chip verification, a new bit error is generated, meaning d6 is incorrectly corrected. It can be observed that the new erroneous bit d6 caused by the incorrect correction is located in the same clock cycle as the original erroneous bit d0. Combining this with the aforementioned verification process regarding on-chip and off-chip verification, it can be seen that every clock cycle of data in all memories under a library will undergo off-chip verification. Referring to this example, Figure 8The first data output from the shown memory will contain multiple bit errors (d6 and d0). These, along with the first data output from other memories in the same memory bank (not shown in the figure), are transmitted to an off-chip verification circuit for off-chip verification. It can be seen that the objects of this off-chip verification, i.e., the first data output from each memory, contain at least... Figure 8 The two bits shown are incorrect, indicating a multi-bit error. As mentioned above, current off-chip verification techniques cannot effectively correct multi-bit errors. On the contrary, due to the presence of multi-bit errors, new bit errors may be generated in the data obtained after off-chip verification, causing data errors to be amplified layer by layer in the on-chip and off-chip verification processes.

[0058] To avoid the aforementioned situation, this embodiment designs a bit grouping method. This grouping method is defined by an error correction matrix. Furthermore, by adding constraints to the error correction matrix, the positions of potential miscorrections during data verification are constrained and adjusted to avoid situations that could lead to further amplification of errors. Taking the data verification principle as an example, the principle of data verification is to group the data to be verified. Each piece of data to be verified is assigned to one or more groups, and each group contains one and only one check bit. Different pieces of data to be verified have different grouping rules, thus obtaining error correction codes that are different from each other according to the grouping rules. That is, each bit of the error correction code represents whether it has been assigned to the corresponding group. In essence, each error correction bit of the error correction code corresponds to each check bit of the check code; that is, each error correction bit is obtained by XORing the corresponding check bits in the written and read check codes. Therefore, for the check code, it is equivalent to completing bit grouping as well. Specifically, after a bit of data is assigned to a group corresponding to a parity bit, whether that bit is erroneous will affect the value of that parity bit, and consequently, the value of the error correction code generated based on the parity code. For example, if the generated parity bit is erroneous, its value will change compared to its value during writing. Subsequently, based on this parity code and the parity code generated during writing, the corresponding bit of the error correction code will also be 1. This is because the error correction code is usually obtained by XORing the parity code generated during writing and the parity code generated during reading. Based on the defined grouping method, parity codes are generated for the data during writing and reading respectively, resulting in the parity code for writing and the parity code for reading. Subsequently, the XOR result of these two parity codes, i.e., the error correction code, is used to determine which bit has erroneous, thus achieving single-bit error correction.

[0059] In this embodiment, the error correction matrix defines the error correction code corresponding to each bit in each cycle, essentially completing the bit grouping design. For example, Table 1 shows an example error correction matrix. As shown in Table 1, DQ0 to DQ7 represent the eight data ports of a memory, 0 to 15 in the second row represent 16 cycles, and pc0 to pc7 represent the 8 bits of the error correction code. It should be noted that this example uses a memory with eight data ports, outputting 8 bits of data per cycle for a total of 16 cycles, and the error correction code having a data length of 8 bits. It is understood that practical applications are not limited to the scenarios shown in the table.

[0060] Table 1

[0061]

[0062] Referring to the data structure illustrated above, for example, column 0 under DQ0 represents the bit output by a memory through data port DQ0 in the first clock cycle, i.e., d0 out of the entire 128 bits. Correspondingly, the error correction code for d0 is pc0 to pc7 in this column, i.e., 00000101. Similarly, referring to column 1 under DQ0, the error correction code for d8 is 11110101; referring to column 0 under DQ3, the error correction code for d3 is 01100101. Specifically, the error correction matrix in this embodiment includes the error correction code corresponding to each bit in each clock cycle, reflecting the check code affected when a single-bit error occurs in a bit. For example, referring to Table 1, we can see that the error correction code corresponding to d0 is 00000101, meaning that d0 is grouped into the group corresponding to check codes p5 and p7. In other words, the error correction matrix actually defines the bit grouping situation in data verification. It should be noted that PB (the cell to the right of DQ7) in the table above is the error correction code of the check code. In practical applications, in order to ensure accurate data verification based on the check code, in addition to verifying the data to be verified, the check code is also verified to obtain the error correction code of the check code. This is to avoid inaccurate data verification based on the check code due to errors in the check code itself. In other words, Table 1 shows at least 128 bits of data + 8 bits of check code, a total of 136 bits of error correction code.

[0063] Taking a single-bit error as an example, suppose encoder 11 generates a first check code based on the written data and the bit group represented by the above error correction matrix, and obtains a second check code based on the read data and the above error correction matrix. When a single-bit error occurs, such as when d0 is an erroneous bit, the error correction code Syn generated by encoder 11 based on the first and second check codes will be 00000101. Correspondingly, the first error correction circuit 12 can determine the position d0 based on the error correction matrix according to the error correction code output by encoder 11, and thus perform data flipping on the data under d0.

[0064] The above example illustrates the principle of the error correction matrix using a single-bit error scenario. In conjunction with the above, to avoid the potential amplification of errors due to multi-bit errors, the error correction matrix in this scheme satisfies the following condition: the XOR result of the error correction codes corresponding to any plurality of bits is not the same as the error correction code corresponding to any bit in the same phase as one of those plurality of bits. In practical applications, miscorrection occurs because the error correction bits of the error correction code are affected multiple times by multiple erroneous bits, resulting in an incorrect error correction code corresponding to a specific bit. For example, referring to Table 1 above, when the bits corresponding to the second column of DQ0 (data output by the memory through DQ0 in the third phase, i.e., d16) and the bits corresponding to the third column of DQ0 (data output by the memory through DQ0 in the fourth phase, i.e., d24) both have errors, the error correction bits pc3 and pc7 will be affected twice, resulting in an incorrect error correction code. Specifically, the check code mentioned in this embodiment refers to data of type check code generated based on the data to be checked, and the accuracy of the check code itself varies. For example, when a multi-bit error occurs, the generated check code may be incorrect, and therefore the subsequently generated error correction code may also be incorrect. That is, the error correction code does not point to the actual bit that had the error, which will lead to false correction.

[0065] In this embodiment, the error correction matrix satisfies that the XOR result of the error correction codes corresponding to any number of bits is not the same as the error correction code corresponding to any bit in the same phase as one of those bits. This design ensures that when a multi-bit error occurs, the generated error correction code does not point to a bit in the same phase as the erroneous multi-bit bit, thus preventing the error from being amplified. For ease of understanding, Figure 9 Here is an example data structure diagram, such as Figure 9 As shown, taking the aforementioned case of a single memory outputting 128 bits in 16 cycles as an example, assuming a multi-bit error occurs, as shown in the figure, and again taking errors in bits d0 and d17 as an example, based on the error correction matrix that meets the conditions set in this embodiment, the bits corresponding to the obtained error correction code will not be the same-cycle data of d0 and d17. Therefore, as long as the generated error correction code does not point to any bit in the 128 bits, i.e., no miscorrected bits are generated, or, as... Figure 9As shown, based on the bit grouping represented by the error correction matrix, the XOR result of the error correction codes corresponding to d0 and d17 is designed to be the error correction code corresponding to d15, which is not in the same batch as d0 or d17. That is, even if the generated error correction code points to one bit out of 128 bits, as long as the miscorrected bit and the originally erroneous bits are not in the same batch, the error in the batch containing the miscorrected bit can be corrected through off-chip verification since it is a single-bit error. The number of "multiple bits" can be varied, such as two-bit errors, three-bit errors, four-bit errors, or even all eight bits being erroneous. Correspondingly, in one example, the XOR result of the error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same batch as one of those multiple bits. This includes the XOR result of the error correction codes corresponding to any two bits in the same batch being not the same as the error correction code corresponding to any bit in the same batch as one of those two bits.

[0066] In practical applications, there are various ways to ensure that the error correction matrix satisfies the above conditions. In one example, the XOR result of the error correction codes corresponding to any number of bits belonging to the same phase in the error correction matrix is ​​not the same as the error correction code corresponding to any bit in the error correction matrix; similarly, the XOR result of the error correction codes corresponding to any number of bits belonging to different phases is not the same as the error correction code corresponding to any bit in the same phase as one of those bits. For example, it can be understood that each error correction bit of an 8-bit error correction code can take the value of 0 or 1, so there are 2 to the power of 8 possible values ​​for an 8-bit error correction code, or 256 cases. Combining the previous example, assuming the amount of data to be verified in the memory is 128 bits, then only 128 cases need to be selected from the 256 cases to design the error correction code corresponding to each bit in each phase of the error correction matrix. In practical applications, the error correction code for the check code can also be considered, so another 8 cases need to be selected to design the error correction code for the check code, meaning a total of 136 cases out of 256 are needed to design the error correction matrix. Based on this example, it can be seen that 120 cases remain unused. Therefore, as an example, it can be designed that the XOR result of the error correction codes corresponding to any number of bits in the error correction matrix is ​​one of the values ​​among these 120 cases. Accordingly, when a multi-bit error occurs, the error correction code generated by encoder 11 will not be the error correction code corresponding to any single bit in the error correction matrix. Based on this error correction code, the first error correction circuit 12 will not perform data flipping on the 128 bits of data, thereby avoiding the generation of miscorrected bits. Through the above scheme, it is not necessary to add new check bits, and the data error is not amplified when a multi-bit error occurs.

[0067] Specifically, encoder 11 receives data to be written during writing and data to be read during reading. By combining the grouping method represented by the error correction matrix, it obtains the checksum for the writing phase and the checksum for the reading phase, and then derives the error correction code from these two. Therefore, the data received by encoder 11 differs at different stages. Thus, to ensure reliable encoder operation, in one example... Figure 10 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 10 As shown, the on-chip verification circuit 31 also includes a data selector 14;

[0068] The first input terminal of the data selector 14 receives the written data Data1, the second input terminal of the data selector 14 receives the read data Data2, and the output terminal of the data selector 14 is connected to the input terminal of the encoder 11 and the storage array 13.

[0069] Data selector 14 is used to output written data Data1 during the write phase and read data Data2 during the read phase.

[0070] Specifically, the data selector 14 provides the corresponding data to the encoder according to the current stage. For example, during the write stage, the data selector 14 can respond to a selection signal to select and output the data received at the first input terminal; during the read stage, the data selector 14 responds to a selection signal to select and output the data received at the second input terminal. The selection signal can be generated by relevant circuits or components in the memory, and can be designed to be in different level states to instruct the data selector to output data from the first or second input terminal. In practical applications, the specific implementation of the data selector 14 is not limited. For example, it can include a multiplexer (MUX), or it can be implemented based on some transmission circuits (such as transmission gates, controllable switches, etc.). No specific implementation method of the data selector is limited here.

[0071] The data selector in this example provides the encoder with the write data required to generate the first checksum during the write phase and the read data required to generate the second checksum during the read phase. This ensures the normal operation of the encoder, avoids data verification errors caused by data reception errors, and improves the accuracy and reliability of data verification. Furthermore, by using the data selector for data selection and output, there is no need to design a dedicated data transmission circuit for the encoder, which effectively simplifies the circuit structure and reduces costs.

[0072] Based on the error correction code Syn output by encoder 11, the first error correction circuit 12 performs single-bit error correction on the read data Data2 according to the error correction code Syn, to obtain the first error-corrected data Correct Data1. The specific structure of the first error correction circuit 12 is not limited. In an example diagram, Figure 11 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 11 As shown, the first error correction circuit 12 includes: a first decoder 121 and a first correction circuit 122;

[0073] The input terminal of the first decoder 121 is connected to the encoder 11. The first decoder 121 is used to receive the error correction code Syn output by the encoder 11, determine the first target position to be flipped based on the error correction code Syn and the error correction matrix, and output the first error correction instruction SBC pointing to the first target position.

[0074] The first correction circuit 122 is connected to the output of the first decoder 121. The first correction circuit 122 is used to receive the read data Data2 and, according to the first error correction instruction SBC, perform data flipping on the bits at the first target position to obtain the first error correction data Correct Data1.

[0075] Specifically, encoder 11 generates an error correction code Syn based on the first checksum generated during writing and the second checksum generated during reading. As mentioned earlier, the first and second checksums are generated by encoder 11 based on the grouping method represented by the error correction matrix, respectively, according to the written and read data. Therefore, the error correction code generated by encoder 11 based on the first and second checksums matches the conditions satisfied by the aforementioned error correction matrix. It can be seen that the error correction matrix satisfies the condition that the bits corresponding to the XOR result of any number of error correction codes are not located in the same bit position as any of those bits. By limiting the above conditions, single-bit errors can be accurately determined based on the error correction matrix, thereby performing single-bit error correction, and preventing error amplification when multiple bit errors occur. Specifically, for a single-bit error, the error correction code Syn generated by encoder 11 accurately points to the location of the erroneous bit. Correspondingly, the first decoder 121, based on the error correction code Syn output by encoder 11 and the error correction matrix, can accurately determine the location of the erroneous bit corresponding to Syn. That is, the first target position obtained by the first decoder 121 is accurate, pointing to the actual erroneous bit. Accordingly, the first decoder 121 outputs a first error correction instruction SBC pointing to the first target position. The first correction circuit 122 receives the read data Data2 and the first error correction instruction SBC output by the first decoder 121 pointing to the first target position. Based on the first error correction instruction SBC, it performs data flipping on the bits at the first target position in the read data Data2. For example, if the bit at the first target position in the read data is 1, it is changed to 0; if it is 0, it is changed to 1. It can be understood that since the error correction code Syn provided by encoder 11 is accurate in the case of a single-bit error, the first error correction instruction SBC output by the first decoder based on Syn is also accurate. Therefore, the data flipping performed by the first correction circuit 122 can achieve accurate error correction.

[0076] In the case of multi-bit errors, the error correction code Syn generated by encoder 11 is inaccurate based on the conditions satisfied by the error correction matrix; that is, it does not accurately point to the actual erroneous bit. Specifically, the error correction code Syn at this time may not be the error correction code corresponding to any single bit in the error correction matrix, or it may be the error correction code corresponding to a single bit in the error correction matrix, but that single bit is not in the same phase as the actual erroneous bit. Correspondingly, based on the error correction code Syn output by encoder 11 at this time, first decoder 121 may not be able to identify the first target position based on the error correction matrix and cannot output a recognizable first error correction instruction SBC. For example, first decoder 121 may not output the first error correction instruction, or output a pre-default invalid instruction, such as an all-zero instruction, indicating that no data flipping is performed on any bit of the read data. Correspondingly, first correction circuit 122 does not perform data flipping on any bit of the read data, thereby ensuring that the data error is limited to the original erroneous bit range and does not lead to the generation of new bit errors. Alternatively, the first decoder 121 can obtain the first target position based on the error correction code Syn output by the encoder 11. However, the first target position does not accurately point to the actual erroneous bit, but rather to a bit in another frame. Correspondingly, the first error correction instruction SBC output by the first decoder 121 is also inaccurate. The first correction circuit 122 performs data flipping on the bit at the first target position pointed to by the first error correction instruction SBC. However, this data flipping does not achieve effective data error correction, but instead produces a false correction. Since this falsely corrected bit is not located in the same frame as any bit that actually caused the error, it can be corrected through off-chip verification. This ensures that the final data error is limited to the original range of erroneous bits, without causing new uncorrectable bit errors, thus preventing the data error from being amplified.

[0077] In practical applications, the error correction matrix can be pre-stored in the encoder 11 and the first decoder 121, so that the first decoder 121 can determine the first target position based on the error correction matrix and output the first error correction instruction SBC. In this example, the first error correction circuit includes a first decoder and a first correction circuit. The first decoder can determine the position to be flipped based on the error correction matrix according to the error correction code output by the encoder, and output the first error correction instruction pointing to the position to be flipped. The corresponding first correction circuit performs data flipping on the bits at the position to be flipped to obtain the first error-corrected data. In this example, since the signals generated by the above circuits are all based on the error correction matrix that meets specific conditions, false corrections can be avoided or the false corrections that occur can be corrected through off-chip verification. This achieves accurate and effective single-bit error correction, and also effectively prevents data errors from being amplified in the case of multi-bit errors.

[0078] In practical applications, circuits are often included to improve data transmission accuracy in order to ensure accurate and reliable data transmission. In one example, Figure 12 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 12 As shown, the on-chip verification circuit 31 also includes: multiple buffer circuits, including:

[0079] The first buffer circuit 21 receives the written data Data1 at its input terminal and its output terminal is connected to the first input terminal of the data selector 14 to buffer and output the received written data Data1.

[0080] The second buffer circuit 22 has its input terminal connected to the output terminal of the data selector 14 and its output terminal connected to the storage array 13. It is used to buffer the write data Data1 output by the data selector 14 during the write phase.

[0081] The third buffer circuit 23 has its input terminal connected to the encoder 11 and its output terminal connected to the storage array 13. It is used to buffer the first check code output by the encoder 11 during the writing stage.

[0082] The fourth buffer circuit 24 has its input connected to the storage array 13 and its output connected to the encoder 11. It is used to buffer the output of the first check code read from the storage array 13 during the reading stage.

[0083] The fifth buffer circuit 25 has its input terminal connected to the storage array 13 and its output terminal connected to the second input terminal of the data selector 14 and the first error correction circuit 12. It is used to buffer and output the read data Data2 read from the storage array 13 during the reading stage.

[0084] The sixth buffer circuit 26 has its input terminal connected to the output terminal of the first error correction circuit 12. The output terminal of the sixth buffer circuit 26 is used to buffer and output the first error correction data Correct Data1 output by the first error correction circuit 12.

[0085] The specific structure of the aforementioned buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters connected in series. For instance, taking the first buffer circuit 21 as an example... Figure 13 Here is a schematic diagram of an example buffer circuit, such as... Figure 13As shown, the first buffer circuit 21 may include an even number of inverters 211 connected in series. It should be noted that other buffer circuits may also adopt the structure shown. In practical applications, when designing the number of inverters in the buffer circuit, the delay on each path can also be considered to optimize signal synchronization and match signal timing.

[0086] The signal transmission at each stage is illustrated in the diagram: During the write stage, the incoming write data Data1 is transmitted to the first input terminal of the data selector 14. Since it is in the write stage, the data selector 14 selects and outputs the write data received at the first input terminal. Correspondingly, the write data output by the data selector 14 is transmitted to the storage array 13 for storage, and also to the encoder 11. In this stage, the encoder 11 generates a first check code (ECC code) based on the received write data and the grouping method represented by the error correction matrix, and outputs it to the storage array 13 to store the check code used during the write process. The above describes the relevant signal transmission during the write stage.

[0087] Next, when data stored in storage array 13 needs to be read, the read data Data2 from storage array 13 is transmitted to the second input terminal of data selector 14 and the data input terminal of the first error correction circuit 12. Simultaneously, the first checksum ECC code read from storage array 13 is transmitted to encoder 11. Since it is in the reading phase, data selector 14 selects and outputs the read data received at its second input terminal to encoder 11. Correspondingly, encoder 11 generates a second checksum based on the read data provided by data selector 14 and the grouping method represented by the error correction matrix. Based on this second checksum and the first checksum read from storage array, error correction code Syn is obtained and output to the first error correction circuit 12. The second error correction circuit 12 performs single-bit error correction on the read data based on the error correction code provided by encoder 11, obtaining first error-corrected data Correct Data1, which is then output off-chip.

[0088] This example demonstrates how to achieve buffered signal transmission by setting up a buffer circuit, thereby ensuring the accuracy and reliability of signal transmission. Furthermore, by adjusting the delay characteristics of the buffer circuit, signal synchronization can be further optimized and signal timing can be matched.

[0089] Furthermore, while avoiding the amplification of data errors, it is also desirable to achieve effective error correction for multi-bit errors. In one example, in conjunction with the aforementioned error correction matrix, it is also considered to set error correction codes corresponding to multi-bit errors to achieve effective multi-bit error correction. To achieve the above multi-bit error correction, as an example, the XOR result of the error correction codes corresponding to different bits belonging to the same cycle in the error correction matrix is ​​different. It can be understood that, based on the verification principle, the XOR result of the error correction codes corresponding to multiple bits can reflect the error correction codes generated when these multiple bits have errors. At the same time, considering that single-bit errors in each cycle can also be corrected through off-chip verification, in order to improve verification efficiency and achieve multi-bit error correction, this example specifically targets the data in the same cycle, further limiting the XOR result of the error correction codes corresponding to different bits belonging to the same cycle in the error correction matrix to be different. The "different multiple bits" mentioned here refers to different combinations of content. Combining this with the data structure of the previous example, taking an eight-port memory (DQ0-DQ7) as an example, the memory outputs 8 bits per cycle. For instance, in the first cycle, the outputs from DQ0-DQ7 are d0-d7, and in the second cycle, they are d8-d15. Correspondingly, there are multiple combinations of these 8 bits per cycle to form multiple-bit combinations. For example, taking a two-bit combination in a certain cycle as an example, the bits output from DQ0 and DQ1 form one combination, the data output from DQ2 and DQ3 form another, and the data output from DQ0 and DQ2 also form yet another. In short, as long as the bits in the combination are not completely identical, it is considered a different multiple bit combination. Furthermore, this example only uses two bits; it can be understood that the multiple bits are not limited to two-bit cases, but can also be three-bit, four-bit, etc. Based on the error correction matrix satisfying the above characteristics, an error correction matrix for the multiple-bit case can be established, that is, this error correction matrix includes the error correction code corresponding to each group of multiple bits in the same cycle. The error-correcting code can be obtained by XORing the error-correcting codes corresponding to each bit in the group of multiple bits. Subsequently, based on the error correction matrix for the multi-bit case, when a multi-bit error is determined to have occurred in the same time frame, the multiple bits that have erred can be identified by combining the current error-correcting code with the error correction matrix containing the error-correcting codes corresponding to each group of multiple bits in the same time frame, thus achieving multi-bit error correction.

[0090] In conjunction with the above, as an example, Figure 14 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 14 As shown, the on-chip verification circuit 31 also includes a second error correction circuit 15;

[0091] The second error correction circuit 15 is connected to the encoder 11, receives the multi-bit error correction instruction DUE, and reads data Data2 or the first error correction data Correct Data1. In response to the multi-bit error correction instruction DUE pointing to the target number of beats, it performs multi-bit error correction on the received data according to the error correction code Syn output by the encoder 11 and outputs the second error correction data CorrectData2.

[0092] The multi-bit error correction instruction DUE, pointing to the target clock cycle number, indicates that a multi-bit error occurred in the read data Data2 within the same clock cycle, and that the multi-bit error occurred at the target clock cycle number. As an example, the multi-bit error correction instruction can be generated by off-chip verification. Specifically, in conjunction with the aforementioned content, off-chip verification is used to verify the data output of each clock cycle from all memories under the same library, and off-chip verification can achieve both single-bit error correction and multi-bit detection. Therefore, for single-bit errors in each clock cycle, off-chip verification can effectively correct them. For multi-bit errors in each clock cycle, when off-chip verification detects a multi-bit error in the currently verified clock cycle, it can issue a multi-bit error correction instruction DUE to the on-chip verification circuit, and this multi-bit error correction instruction points to the currently verified clock cycle, i.e., the target clock cycle number. In one example, if the second error correction circuit 15 of the on-chip verification circuit receives the multi-bit error correction instruction returned by the off-chip verification circuit, it can perform subsequent operations based on the error correction code. It should be noted that the second error correction circuit 15 receiving the multi-bit error correction instruction DUE mentioned here is only used to indicate the signal connection relationship of the second error correction circuit. In practical terms, "receiving" here also includes receiving but not actually accepting. For example, the multi-bit error correction instruction is only received when the current error correction code determines that the memory itself needs to respond to it, in order to reduce power consumption. This is because, although off-chip verification can achieve multi-bit detection, it cannot pinpoint which specific multi-bit errors occurred, and therefore cannot determine which memory output the erroneous multi-bit in this cycle. Therefore, after detecting a multi-bit error in this cycle, off-chip verification sends multi-bit error correction instructions to all memories in the library. Correspondingly, the second error correction circuit of each memory's on-chip verification circuit only performs subsequent multi-bit error correction processing after determining that the currently received multi-bit error correction instruction is valid.

[0093] As an example, whether a multi-bit error correction instruction needs to be responded to by the memory where the on-chip verification circuit resides can be determined based on the error correction code currently output by the encoder 11. For instance, if the encoder 11 in the on-chip verification circuit of a certain memory does not output an error correction code or outputs a default invalid code, indicating that the on-chip verification result is that no data error has occurred, then the multi-bit error detected by the on-chip verification circuit may be in the data output by other memories. Therefore, even if the second error correction circuit of the on-chip verification circuit receives a multi-bit error correction instruction sent by the external verification circuit, no data error correction is required, and the multi-bit error correction instruction sent to this memory is considered not to need to be responded to. As another example, if the error correction code currently output by the encoder 11 in the on-chip verification circuit of a certain memory is neither empty nor a default invalid code, but the error correction code is not the error correction code corresponding to any multi-bit combination in the error correction matrix, meaning the error correction code cannot be recognized, then the multi-bit error correction instruction is considered not to need to be responded to, and data error correction is also not performed. If a multi-bit error correction instruction needs to be responded to, for example, if the error correction code output by the current encoder 11 falls into any of the error correction codes corresponding to different multi-bit values ​​defined in the error correction instruction, it indicates that a multi-bit error occurred in this memory. Accordingly, the second error correction circuit 15 can determine the erroneous multi-bit based on the multi-bit combination corresponding to the error correction code, and then perform data error correction. Specifically, the object of error correction can be read data, and the corresponding corrected second error-corrected data can be transmitted to an off-chip verification circuit for further off-chip verification. Alternatively, the object of error correction can be the first error-corrected data, and the corrected second error-corrected data can be transmitted to an off-chip verification circuit. The off-chip verification circuit integrates the first and second error-corrected data and performs off-chip verification again. In other words, in some embodiments, the second error correction circuit 15 determines whether to respond to the multi-bit error correction instruction DUE based on the error correction code Syn.

[0094] In practical applications, the specific structure of the second error correction circuit is not limited. In one example, Figure 15 Here is a schematic diagram of an example on-chip verification circuit, such as... Figure 15 As shown, the second error correction circuit 15 includes: a second decoder 151 and a second correction circuit 152;

[0095] The input of the second decoder 151 is connected to the encoder 11. The second decoder 151 receives the error correction code Syn and the multi-bit error correction instruction DUE. In response to the multi-bit error correction instruction DUE pointing to the target number of beats, based on the target number of beats pointed to by the multi-bit error correction instruction DUE, the error correction code Syn, and the error correction matrix, the second target position to be flipped is determined, and the second error correction instruction DBC pointing to the second target position is output.

[0096] The second correction circuit 152 is connected to the output of the second decoder 151. The second correction circuit 152 is used to receive the read data Data2 or the first error correction data Correct Data1, and to perform data error correction on the bits at the second target position according to the second error correction instruction to obtain the second error correction data Correct Data2.

[0097] Specifically, encoder 11 generates an error correction code Syn based on the first checksum generated during writing and the second checksum generated during reading. As mentioned earlier, the first and second checksums are generated by encoder 11 based on the grouping method represented by the error correction matrix, respectively, according to the written and read data. Therefore, the error correction code generated by encoder 11 based on the first and second checksums matches the conditions satisfied by the aforementioned error correction matrix. It can be seen that the error correction matrix also satisfies the condition that the XOR result of the error correction codes corresponding to different bits belonging to the same pulse is different. As an example, another error correction matrix can be established, hereinafter also called a multi-bit error correction matrix, including error correction codes corresponding to different combinations of bits in the same pulse. The error correction code corresponding to each combination is obtained based on the XOR result of the error correction code corresponding to each bit in that combination.

[0098] In the case of multi-bit errors, the off-chip verification circuit sends a multi-bit error correction instruction (DUE) to the on-chip verification circuits of all memories in the library. Taking the on-chip verification circuit of a certain memory as an example, the second decoder 151 of the on-chip verification circuit checks whether the error correction code Syn output by the current encoder 11 is any of the error correction codes defined in the multi-bit error correction matrix. If not, no error correction is performed. Conversely, if the error correction code is a certain error correction code defined in the multi-bit error correction matrix, the individual bits under the multi-bit combination corresponding to the error correction code in the multi-bit error correction matrix are determined. For example, it is determined that the bit combination corresponding to the error correction code includes the bits output by data ports DQ0 and DQ1. Furthermore, combined with the target clock number pointed to by the multi-bit error correction instruction DUE, for example, pointing to the second clock, it can be determined that the multi-bits that have erroneous are the data output by DQ0 and DQ1 of the memory in the second clock, combined with the data structure of the aforementioned example, namely d8 and d9. After determining the second target location where a multi-bit error occurs, the second decoder 151 outputs a second error correction instruction pointing to that second target location to the second correction circuit 152. Correspondingly, the second correction circuit 152 performs data flipping on the bits at the second target location in the read data, such as d8 and d9 in the example above; or, the second correction circuit 152 can also perform data flipping on the bits at the second target location in the first error correction data Correct Data1 output by the first error correction circuit 12, thus achieving multi-bit error correction. The second correction circuit can correct various types of data. Performing multi-bit error correction on read data eliminates the need for additional processing by the off-chip verification circuit, improving the efficiency of off-chip verification. Performing multi-bit error correction on the first error correction data eliminates the need for a buffer structure for the second error correction circuit to buffer the read data, simplifying the structure of the on-chip verification circuit. Accordingly, in one example, the second correction circuit 152 is connected to the data input terminal of the first error correction circuit 12 for receiving read data Data2, or the second correction circuit 152 is connected to the output terminal of the first error correction circuit 12. Specifically, Figure 15 The example provided is multi-bit error correction performed on the first error-correcting data.

[0099] In this example, the second error correction circuit includes a second decoder and a second correction circuit. The second decoder determines the multi-bit error location based on the error correction code corresponding to the multi-bit combination in the error correction matrix according to the error correction code and the target number of the multi-bit instruction. The second correction circuit corrects the corresponding bit according to the second error correction instruction pointing to the multi-bit error location, thereby avoiding data error amplification and realizing multi-bit error correction, improving the accuracy and reliability of data verification.

[0100] In practical applications, circuits are also included to improve data transmission accuracy in order to ensure accurate and reliable data transmission. In one example, as... Figure 15As shown, the on-chip verification circuit 31 also includes:

[0101] The seventh buffer circuit 27 receives the multi-bit error correction instruction DUE at its input terminal and is connected to the second decoder 151 at its output terminal to buffer and output the multi-bit error correction instruction DUE.

[0102] The eighth buffer circuit 28 has its input terminal connected to the output terminal of the second error correction circuit 15. The output terminal of the eighth buffer circuit 28 is used to buffer and output the second error correction data Correct Data2 output by the second error correction circuit 15.

[0103] The specific structure of the aforementioned buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters connected in series. The signal transmission at each stage is illustrated in the diagram: When the off-chip verification circuit detects a multi-bit error in the current frame, it sends a multi-bit error correction instruction DUE to the seventh buffer circuit 27 of the on-chip verification circuit of all memories. Taking a memory as an example, the seventh buffer circuit 27 of the on-chip verification circuit of the memory buffers and outputs the received multi-bit error correction instruction DUE to the second decoder 151. The second decoder 151, based on the target frame number pointed to by the multi-bit error correction instruction provided by the seventh buffer circuit 27, the error correction code Syn currently output by the encoder 11, and the error correction matrix, outputs a second error correction instruction DBC pointing to the location where the multi-bit error occurred. The second correction circuit 152, based on the second error correction instruction DBC, performs data error correction on the corresponding bits in the read data or the first error correction instruction to obtain the second error correction data Correct Data2. The output of the second correction circuit 152 is used as the output of the second error correction circuit 15, and the second error correction data Correct Data2 is output to the eighth buffer circuit 28. The eighth buffer circuit 28 buffers and outputs the second error correction data Correct Data2 to the off-chip.

[0104] This example demonstrates how to achieve buffered signal transmission by setting up a buffer circuit, thereby ensuring the accuracy and reliability of signal transmission. Furthermore, by adjusting the delay characteristics of the buffer circuit, signal synchronization can be further optimized and signal timing can be matched.

[0105] The on-chip verification circuit provided in this application includes an encoder and a first error correction circuit. The encoder is responsible for generating verification codes for the write and read stages, and obtaining error correction codes based on the verification codes of the two stages. The first error correction circuit further performs single-bit error correction on the data read in the read stage based on the error correction codes. The verification codes in this scheme are generated by the encoder based on bit groups represented by the error correction matrix. The error correction matrix includes the error correction codes corresponding to each bit in each frame, and satisfies the condition that the bit corresponding to the XOR result of any number of error correction codes is not located in the same frame as any bit of those multiple bits. Therefore, even if there are multiple bit errors that lead to the generation of miscorrected error correction codes, since the miscorrected error correction codes are not located in the same frame as the bits where the multiple bit errors occurred, it will not lead to new multi-bit errors in the same frame, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0106] Example 2

[0107] Figure 16 Here is an example diagram of the structure of a memory, such as Figure 16 As shown, the memory includes: a storage array 13, and an on-chip verification circuit 31 as in any of the preceding examples.

[0108] Based on the aforementioned embodiments, taking DRAM as an example: During the write phase, the on-chip verification circuit 31 transmits the write data Data1 to the storage array 13, and simultaneously generates a first check code (ECC code) based on the write data Data1 and the bit groups represented by the error correction matrix, and stores it in the storage array 13; During the read phase, the on-chip verification circuit 31 reads the first check code (ECC code) and read data Data2 from the storage array, generates a second check code based on the read data Data2 and the bit groups represented by the error correction matrix, obtains an error correction code based on the first and second check codes, and performs single-bit error correction on the read data Data2 based on the error correction code, outputting the first error-corrected data Correct Data1. The error correction matrix includes the error correction code corresponding to each bit in each cycle, and the error correction matrix satisfies the following condition: the bit corresponding to the XOR result of any plurality of error correction codes is not located in the same cycle as any bit of those plurality of bits, thereby preventing data errors from being amplified when multi-bit errors occur.

[0109] In the memory provided in this embodiment, the on-chip verification circuit includes an encoder and a first error correction circuit. The encoder is responsible for generating verification codes for the write and read stages, and obtaining error correction codes based on the verification codes of the two stages. The first error correction circuit further performs single-bit error correction on the data read in the read stage based on the error correction codes. The verification codes in this scheme are generated by the encoder based on bit groups represented by the error correction matrix. The error correction matrix includes the error correction code corresponding to each bit in each frame, and satisfies the condition that the bit corresponding to the XOR result of any number of error correction codes is not located in the same frame as any bit of those multiple bits. Therefore, even if there are multiple bit errors that lead to the generation of miscorrected error correction codes, since the miscorrected error correction codes are not located in the same frame as the bits where the multiple bit errors occurred, it will not lead to new multi-bit errors in the same frame, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0110] Example 3

[0111] Figure 17 Here is a structural example diagram of an example storage device, such as... Figure 17 As shown, the storage device includes: an off-chip verification circuit 41 and at least one memory 42 as exemplified in Embodiment 2;

[0112] An off-chip verification circuit 41 is connected to at least one memory 42 and is used to verify each bit of data in the first error correction data Correct Data1 output by at least one memory 42 during the read phase. The verification includes single-bit error correction and multi-bit detection.

[0113] In the example of the scheme described in the foregoing embodiments: During the reading phase, each memory 42 obtains first error-corrected data (Correct Data1) based on the aforementioned verification process, and outputs each frame of the first error-corrected data (Correct Data1) frame by frame. The off-chip verification circuit 41 receives the first error-corrected data (Correct Data1) output by all memories 42 in the current frame and performs off-chip data verification. Based on the foregoing, since the error correction matrix used in on-chip verification meets specific conditions, on-chip verification will not produce false corrections for multi-bit errors, or even if false corrections occur, the position of the falsely corrected bit will not cause off-chip verification to generate new multi-bit errors in the same frame, thereby preventing data errors from being amplified.

[0114] Furthermore, if a single-bit error exists in the data of the current frame, the off-chip verification circuit 41 performs single-bit error correction on the data of this frame. If a multi-bit error exists in the data of the current frame, the off-chip verification circuit 41 sends a multi-bit error correction instruction to all memories 42. In one example, the off-chip verification circuit 41 includes: an indicator circuit 411; the indicator circuit 411 is used to send a multi-bit error correction instruction DUE pointing to a target frame number to all memories 42 if a multi-bit error exists in the same frame of data. Specifically, each memory 42 confirms whether the multi-bit error correction instruction is valid for itself. If valid, it performs multi-bit error correction and outputs the second error-corrected data, Correct Data2. The memory can perform multi-bit error correction based on the read data or based on the first error-corrected data.

[0115] Accordingly, to obtain the final accurate data, the off-chip verification circuit 41 also includes a processing circuit 412, used to perform a first data integration of the first error-correcting data output from different memories, and to perform data verification on the integrated data; if there are no data errors or they can be corrected, the off-chip verified data is output; if the memory needs to perform secondary correction, after receiving the second error-correcting data, the erroneous data in the integrated data is replaced based on the second error-correcting data and data verification is performed again. If there are no data errors or they can be corrected, the off-chip verified data is output. Specifically, the processing circuit 412 performs a first integration based on the first error-correcting results obtained by each memory according to single-bit error correction to obtain the verification object for off-chip verification, that is, the data belonging to the current capture in the first error-correcting results of each memory. Data verification is performed on this data. If the data captured in the current capture has no data errors or only has single-bit errors (i.e., it can be corrected), the off-chip verified data is output. In another scenario, if the integrated data, i.e. the data captured by each memory, is found to have multi-bit errors, it is necessary to return to the memory for secondary correction. Accordingly, the instruction circuit 411 sends a multi-bit error correction instruction to all memories. In conjunction with the aforementioned scheme, the memory that needs to respond to the instruction will perform multi-bit error correction on its own data and output the second error correction result. After receiving the second error correction result after secondary correction, the processing circuit 412 replaces the erroneous bits in the data obtained from the first integration and performs data verification again. If the verification passes, the final accurate data is output.

[0116] In the storage device provided in this embodiment, the on-chip verification circuit of the memory includes an encoder and a first error correction circuit. The encoder is responsible for generating verification codes for the write and read stages, and obtaining error correction codes based on the verification codes of the two stages. The first error correction circuit further performs single-bit error correction on the data read in the read stage based on the error correction codes. In this scheme, the verification code is generated by the encoder based on the bit grouping represented by the error correction matrix. The error correction matrix includes the error correction code corresponding to each bit in each frame, and satisfies that the bit corresponding to the XOR result of any number of error correction codes is not located in the same frame as any bit of those multiple bits. Therefore, even if there is a multi-bit error that leads to the generation of a miscorrected error correction code, since the miscorrected error correction code is not located in the same frame as the bit where the multi-bit error occurred, it will not lead to a new multi-bit error in the same frame, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0117] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0118] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. An on-chip verification circuit, characterized in that, The on-chip verification circuit, applied to a memory, includes: An encoder, connected to the storage array of the memory, is used to generate a first check code and write it to the storage array based on the written data and the bit group represented by the error correction matrix during the write phase; and to generate a second check code based on the read data and the bit group represented by the error correction matrix during the read phase, and to generate an error correction code based on the read first check code and the second check code. A first error correction circuit, connected to the encoder, is used to receive the readout data, and perform single-bit error correction on the readout data according to the error correction code output by the encoder, and then output the first error correction data. The error correction matrix includes an error correction code corresponding to each bit in each cycle. The error correction matrix satisfies the following conditions: the XOR result of the error correction codes corresponding to any plurality of bits is not the same as the error correction code corresponding to any bit in the same cycle as one of the plurality of bits; wherein, in the error correction matrix, the XOR result of the error correction codes corresponding to any plurality of bits belonging to the same cycle is not the same as the error correction code corresponding to any bit in the error correction matrix, and the XOR result of the error correction codes corresponding to different plurality of bits belonging to the same cycle is different; wherein, each cycle contains 8 bits of data, and the error correction code is 8 bits. The second error correction circuit is connected to the encoder and receives a multi-bit error correction instruction and the readout data or the first error correction data. In response to the multi-bit error correction instruction pointing to the target number of beats, the circuit performs multi-bit error correction on the received data according to the error correction code output by the encoder and outputs the second error correction data. The multi-bit error correction instruction pointing to the target time step indicates that the read data has a multi-bit error in the same time step, and the multi-bit error occurs in the target time step.

2. The on-chip verification circuit according to claim 1, characterized in that, The XOR result of the error correction codes corresponding to any number of bits belonging to different phases is not the same as the error correction code corresponding to any bit in the same phase as one of those bits.

3. The on-chip verification circuit according to claim 1, characterized in that, The on-chip verification circuit also includes: a data selector; The first input terminal of the data selector receives the written data, the second input terminal of the data selector receives the read data, and the output terminal of the data selector is connected to the input terminal of the encoder and the storage array. The data selector is used to output the written data during the write phase and the read data during the read phase.

4. The on-chip verification circuit according to claim 3, characterized in that, The first error correction circuit includes: a first decoder and a first correction circuit; The input terminal of the first decoder is connected to the encoder. The first decoder is used to receive the error correction code output by the encoder, determine the first target position to be flipped based on the error correction code and the error correction matrix, and output a first error correction instruction pointing to the first target position. The first correction circuit is connected to the output of the first decoder. The first correction circuit is used to receive the read data and, according to the first error correction instruction, to perform data flipping on the bits at the first target position to obtain the first error correction data.

5. The on-chip verification circuit according to claim 4, characterized in that, The on-chip verification circuit also includes: multiple buffer circuits, including: A first buffer circuit is provided, wherein the input terminal of the first buffer circuit receives the written data and the output terminal of the first buffer circuit is connected to the first input terminal of the data selector, and is used to buffer and output the received written data. A second buffer circuit, the input of which is connected to the output of the data selector and the output of which is connected to the storage array, is used to buffer the write data output by the data selector during the write phase. A third buffer circuit, the input of which is connected to the encoder and the output of which is connected to the storage array, is used to buffer the first check code output by the encoder during the writing phase. A fourth buffer circuit, the input of which is connected to the storage array and the output of which is connected to the encoder, is used to buffer and output the first check code read from the storage array during the reading phase. A fifth buffer circuit, the input of which is connected to the storage array, and the output of which is connected to the second input of the data selector and the first error correction circuit, is used to buffer and output the read data read from the storage array during the reading phase. A sixth buffer circuit, the input of which is connected to the output of the first error correction circuit, and the output of which is used to buffer the first error correction data output by the first error correction circuit.

6. The on-chip verification circuit according to claim 5, characterized in that, The buffer circuit includes an even number of inverters connected in series.

7. The on-chip verification circuit according to claim 1, characterized in that, The second error correction circuit includes: a second decoder and a second correction circuit; The input of the second decoder is connected to the encoder. The second decoder receives the error correction code and the multi-bit error correction instruction. In response to the multi-bit error correction instruction pointing to the target number of beats, the second target position to be flipped is determined based on the target number of beats pointed to by the multi-bit error correction instruction, the error correction code and the error correction matrix. The second decoder outputs a second error correction instruction pointing to the second target position. The second correction circuit is connected to the output of the second decoder. The second correction circuit is used to receive the readout data or the first error correction data, and to perform data error correction on the bits at the second target position according to the second error correction instruction to obtain the second error correction data.

8. The on-chip verification circuit according to claim 7, characterized in that, The second correction circuit is connected to the data input terminal of the first error correction circuit for receiving the read data, or the second correction circuit is connected to the output terminal of the first error correction circuit.

9. A memory, characterized in that, Includes: a memory array, and an on-chip verification circuit as described in any one of claims 1-8.

10. A storage device, characterized in that, include: An off-chip verification circuit and at least one memory as described in claim 9; The off-chip verification circuit is connected to the at least one memory and is used to verify each bit of data in the first error correction data output by the at least one memory during the reading phase. The verification includes single-bit error correction and multi-bit detection.

11. The storage device according to claim 10, characterized in that, The off-chip verification circuit includes: an indicator circuit; The indicator circuit is used to send a multi-bit error correction instruction pointing to the target number of times to all the memories if there are multi-bit errors in the same data.

12. The storage device according to claim 11, characterized in that, The off-chip verification circuit also includes: The processing circuit is used to perform a first data integration on the first error correction data output from different memories, and to perform data verification on the integrated data; if there are no data errors or they can be corrected, the off-chip verified data is output; if the memory needs to perform a second correction, after receiving the second error correction data, the integrated data is replaced with erroneous data based on the second error correction data and the data is verified again; if there are no data errors or they can be corrected, the off-chip verified data is output.

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