A fully copper interconnected packaging integrated device and manufacturing method

Abstract

The present invention discloses an all-copper interconnected package integrated device and manufacturing method, comprising: a substrate, comprising an upper copper layer, a ceramic layer, and a lower copper layer in contact with each other in sequence, the upper copper layer comprising a power circuit region, a control circuit region, and an electrode assembly region, with each portion electrically insulated; an upper bridge power MOS transistor, wherein the drain surface is bonded to and electrically connected to the outer surface of the upper bridge power circuit region; a lower bridge power MOS transistor, wherein the drain surface is bonded to and electrically connected to the outer surface of the lower bridge power circuit region, and is electrically connected to the source surface of the upper bridge power MOS transistor via a first copper clip; a heat sink, disposed on the outer surface of the lower copper layer; the drain and source surfaces of the upper and lower bridge power MOS transistors are located on opposite sides. The present invention uses copper clip interconnection to reduce stray inductance, which is beneficial for heat dissipation and temperature uniformity; the MOS transistor uses a double-sided sintered copper layer, which greatly reduces electromigration; and the substrate and the heat sink use a large-area copper sintering connection, which improves reliability and simplifies the process.

Description

Technical Field

[0001] The present invention relates to the technical field of interconnect packaging, and in particular to an all-copper interconnect packaging integrated device and a manufacturing method thereof. Background Art

[0002] With the development of third-generation semiconductors, silicon carbide (SiC) power devices are gradually replacing silicon (Si) power devices and have been widely used in power grids, new energy vehicles, photovoltaics, and other fields. Currently, SiC power device packaging formats include: 1. Single-sided heat dissipation packages that follow the same principles as Si power devices, such as Infineon's Econo flat-pack package and 34mm and 62mm packages; 2. Single-sided direct cooling packages, such as Infineon's HybridPACK Drive, Danfoss's DCM1000X, and ABB's RoadPak; and 3. Double-sided water-cooling packages, such as Hitachi's card-like module and Delphi's Viper.

[0003] The traditional Si power device packaging can be specifically described as follows: the chip is soldered to the substrate, which is then soldered to the copper baseplate. The source electrode on the chip's top surface is connected to the substrate via aluminum wire. The module dissipates heat by attaching the copper baseplate to a heat sink, with thermal grease applied between the copper baseplate and the heat sink. Due to the high power density, high frequency, and high operating temperature characteristics of SiC power devices, the traditional Si power device packaging is not suitable for SiC, and SiC's advantages cannot be fully utilized.

[0004] For SiC power devices, one of the more advanced packaging solutions in the new energy vehicle field is specifically described as follows: the chip is sintered on the substrate through sintered silver, the substrate and the radiator are brazed, and single-sided direct water cooling is used for heat dissipation. The source electrode on the upper surface of the chip is also connected to a layer of copper foil through sintered silver, and copper wire is punched on the copper foil to connect the source electrode to the substrate. The current problems in this type of package are: 1. The stray inductance caused by copper wire bonding is large, which slows down the module switching speed and prevents the SiC chip from fully exerting its high-speed switching performance; 2. The large-area brazing between the substrate and the heat sink has a thick solder layer, poor connection quality, and large interface thermal resistance, which affects the reliability of the module; 3. The double-sided silver sintered layer of the chip is prone to electromigration under high current and high temperature working environments, affecting reliability; 4. Large-area brazing connection between the substrate and the heat sink: Large-area connection will produce large warping. To compensate for the warping problem, the solder thickness exceeds 100 microns. Excessively thick solder will reduce the connection strength of the solder layer, increase the thermal resistance, and affect heat dissipation. There is a solution to use sintered silver instead of brazing solder, but this connection layer needs to be at least 100 microns thick, and the use of sintered silver will greatly increase the cost.

[0005] The double-sided cooling packaging solution replaces traditional wire bonding with plate / column structures, which can effectively reduce the module's stray inductance and also add a heat dissipation path for the module. Compared with single-sided heat dissipation, it can improve the heat dissipation capacity by 30% to 50%.

[0006] Based on this technical background, the present invention studies an all-copper interconnected packaging integrated device and a manufacturing method. Summary of the Invention

[0007] In response to the shortcomings of the existing technology, the present invention proposes an all-copper interconnected packaging integrated device and manufacturing method. The device adopts a copper clip interconnection structure, which reduces stray inductance and facilitates heat dissipation and temperature uniformity. The sintered silver layer on the upper and lower surfaces of the MOS tube is replaced with a sintered copper layer, which greatly reduces the possibility of electromigration, improves packaging reliability, and reduces raw material costs. The substrate and the heat sink are connected by a large-area copper sintering, which can reduce warpage and reduce interface thermal resistance, improve connection quality and reliability, reduce raw material costs, and simplify the process.

[0008] In order to achieve the above-mentioned object, the first aspect of the present invention provides an all-copper interconnected package integrated device, comprising:

[0009] A substrate comprising an upper copper layer, a ceramic layer, and a lower copper layer in contact with each other in sequence, wherein the upper copper layer comprises a power circuit region, a control circuit region, and an electrode assembly region, and each portion is electrically insulated from the other portion; the power circuit region comprises an upper bridge power circuit region and a lower bridge power circuit region; the control circuit region comprises an upper bridge control circuit region and a lower bridge control circuit region; each control circuit region comprises a gate resistor assembly region and a Kelvin source bonding region;

[0010] The upper bridge power MOS tube has a drain surface that is mechanically and electrically connected to the outer surface of the upper bridge power loop region by sintering copper paste, and a source surface that is mechanically and electrically connected to the first copper clip by sintering copper paste;

[0011] The drain surface of the lower bridge power MOS transistor is mechanically and electrically connected to the outer surface of the lower bridge power loop region via sintered copper paste, and is electrically connected to the source surface of the upper bridge power MOS transistor via a first copper clip, and the source surface is mechanically and electrically connected to the second copper clip via sintered copper paste;

[0012] a heat sink, disposed on the outer surface of the lower copper layer;

[0013] The drain surfaces and source surfaces of the upper bridge power MOS tube and the lower bridge power MOS tube are located on opposite surfaces.

[0014] A second aspect of the present invention provides a method for manufacturing the above-mentioned device, comprising:

[0015] Interconnection between the power MOS tube and the substrate: Print copper paste on the surface of the power loop area, place the drain surface of the power MOS tube on the copper paste, and preheat and sinter in sequence to form a sintered copper layer connecting the power MOS tube and the substrate;

[0016] Interconnection between substrate and radiator: Copper paste is printed on the surface of the radiator, the lower copper layer of the substrate is placed on the copper paste, and preheating and sintering are performed in sequence to form a large-area sintered copper layer connecting the substrate and the radiator;

[0017] Interconnection between power MOS tubes and copper clips: Print copper paste on all bottom surfaces of the first and second copper clips, align the rectangular protruding end of the first copper clip with the source surface of each upper bridge power MOS tube, align the outer edge of the other bottom surface with the bottom edge of the lower bridge power loop area, and align the rectangular protruding end of the second copper clip with the source surface of the lower bridge power MOS tube. Preheat and sinter in sequence to form a sintered copper layer that interconnects the upper and lower bridge power MOS tubes.

[0018] The technical effects of the present invention include:

[0019] (1) The all-copper interconnected package integrated device proposed in the present invention adopts a copper clip interconnection structure, which reduces stray inductance and is conducive to heat dissipation and temperature uniformity; the double-sided silver sintering layer of the MOS tube is replaced by a double-sided copper sintering layer, which greatly reduces the possibility of electromigration, improves packaging reliability, and reduces raw material costs; the substrate and the heat sink adopt a large-area copper sintering connection, which can reduce warpage, reduce interface thermal resistance, improve connection quality and reliability, reduce raw material costs, and simplify the process.

[0020] (2) The all-copper interconnected package integrated device proposed in the present invention utilizes copper clip technology to replace copper wire bonding technology, thereby solving the problem of high stray inductance in the copper wire bonding technology solution and effectively reducing the stray inductance of the commutation circuit to 3-4 nH, which helps to improve the switching performance. At the same time, it can also conduct heat away from the power MOS tube, adding a heat dissipation path for the power MOS tube, effectively improving the heat dissipation capacity of the module and having a temperature equalization effect. The uniform temperature of each power MOS tube also has a certain promoting effect on the current sharing of the power MOS tube.

[0021] (3) In the all-copper interconnected package integrated device proposed by the present invention, the interconnected copper clips can also be integrated with the power terminals, which reduces the number of integrated components, the number of components and process steps, and the process cost.

[0022] (4) The present invention proposes a fully copper interconnected package integrated device, in which double-sided copper sintering replaces double-sided silver sintering technology, which solves the problem that the silver material in the double-sided silver sintering technology is prone to electromigration, affecting reliability. Under high current and high temperature working conditions, copper material is less likely to electromigrate, thereby improving reliability, and at the same time, the cost is lower than that of silver material.

[0023] (5) The all-copper interconnected packaging integrated device proposed in the present invention utilizes large-area copper sintering to replace the large-area brazing welding technology solution, which solves the problems of weak connection strength, large thermal resistance, and poor reliability of excessively thick large-area brazing layers. The shear strength of pressureless sintered copper can reach above 40 MPa, and the shear strength of pressurized sintered copper can reach above 100 MPa, with lower thermal resistance. Compared with sintered silver, the performance is similar or better, the raw material cost is lower, and combined with double-sided copper sintering technology, the process cost can also be reduced.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0026] Figure 1 This is a circuit topology diagram of the all-copper interconnected package integrated device proposed by the present invention.

[0027] Figure 2 This is a schematic diagram of an all-copper interconnected power module in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0028] Figure 3A This is a schematic top view of the interior of an all-copper interconnected power module in a specific embodiment of the all-copper interconnected package integration device proposed by the present invention.

[0029] Figure 3B This is a three-dimensional schematic diagram of the interior of an all-copper interconnected power module in a specific embodiment of the all-copper interconnected package integration device proposed by the present invention.

[0030] Figure 4A , B are schematic diagrams of the copper layer circuit on the substrate in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0031] Figure 5 This is a schematic diagram of a power MOS tube in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0032] Figure 6 This is a schematic diagram of double-sided copper sintering in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0033] Figure 7 This is a schematic diagram of large-area copper sintering in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0034] Figure 8A This is a schematic top view of the second copper clip in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0035] Figure 8B This is a three-dimensional schematic diagram of the second copper clip in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0036] Figure 9A This is a schematic top view of a first copper clip in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0037] Figure 9B A three-dimensional schematic diagram of the first copper clip in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention

[0038] Figure 10 This is a schematic diagram of a heat sink in a specific embodiment of the all-copper interconnected package integrated device proposed by the present invention.

[0039] Description of reference numerals:

[0040] 1-1, 1-2 – DC+ terminal, 2-1 – DC- terminal, 2-2 – second copper clip, 3 – AC terminal, 4 – heat sink, 5-1, 5-2 – first copper clip, 6 – power MOS transistor, 6-1 – power MOS transistor source pad, 7 – substrate, 8 – sintered copper layer of power MOS transistor, 9 – sintered copper layer between power MOS transistor and substrate, 10 – large-area sintered copper layer between substrate and heat sink, 11 – control terminal;

[0041] 11-1, 11-2 - NTC thermistor control terminals, 11-3 - lower bridge MOS transistor gate control terminal, 11-4 - lower bridge MOS transistor source control terminal, 11-5 - upper bridge MOS transistor source control terminal, 11-6 - upper bridge MOS transistor gate control terminal, 11-7 - upper bridge MOS transistor drain sensing terminal;

[0042] T1 - upper bridge power MOS tube, T2 - lower bridge power MOS tube, L1 - upper bridge power circuit area, L2 - lower bridge power circuit area, L3 - upper bridge control circuit area, L4 - lower bridge control circuit area, L5 - electrode assembly area. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0044] In the present invention, unless otherwise specified, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of a device in normal use, and "inner" and "outer" refer to positions relative to the device's outline. Furthermore, the terms "first, second, and third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, features defined as "first, second, and third" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise explicitly and specifically defined.

[0045] The present invention provides a package integrated device with full copper interconnection, such as Figure 1 As shown, including:

[0046] Substrate 7, including an upper copper layer, a ceramic layer, and a lower copper layer in contact with each other in sequence. The upper copper layer includes a power circuit area, a control circuit area, and an electrode assembly area L5. Each part is electrically insulated. The power circuit area includes an upper bridge power circuit area L1 and a lower bridge power circuit area L2. The control circuit area includes an upper bridge control circuit area L3 and a lower bridge control circuit area L4. Each control circuit area includes a gate resistor assembly area and a Kelvin source bonding area.

[0047] The drain surface of the upper bridge power MOS transistor T1 is mechanically and electrically connected to the outer surface of the upper bridge power loop area L1 through sintered copper paste, and the source surface is mechanically and electrically connected to the first copper clips 5-1 and 5-2 through sintered copper paste;

[0048] The drain surface of the lower-bridge power MOS transistor T2 is mechanically and electrically connected to the outer surface of the lower-bridge power loop region L2 via sintered copper paste, and is electrically connected to the source surface of the upper-bridge power MOS transistor T1 via first copper clips 5-1 and 5-2. The source surface is mechanically and electrically connected to the second copper clip 2-2 via sintered copper paste.

[0049] a heat sink 4, arranged on the outer surface of the lower copper layer;

[0050] The drain surfaces and source surfaces of the upper bridge power MOS transistor T1 and the lower bridge power MOS transistor T2 are located on opposite sides.

[0051] In the present invention, the power MOS transistor 6 includes an upper bridge power MOS transistor T1 and a lower bridge power MOS transistor T2.

[0052] In the present invention, a copper clip interconnection structure is adopted to reduce stray inductance and facilitate heat dissipation and temperature uniformity; the sintered silver layer on the upper and lower surfaces of the MOS tube is replaced with a sintered copper layer, which greatly reduces electromigration, improves packaging reliability, and reduces raw material costs; the substrate 7 and the heat sink 4 are connected by a large-area copper sintering, which can reduce warpage, reduce interface thermal resistance, improve connection quality and reliability, reduce raw material costs, and simplify the process.

[0053] According to the present invention, the upper copper layer is in the shape of a rectangle;

[0054] The upper bridge power loop area L1 is in the shape of a letter "Π" or "π", with the horizontal side of the letter "Π" close to and parallel to one wide side of the rectangle;

[0055] The lower bridge power loop region L2 is U-shaped, with the bottom edge of the U close to and parallel to the other wide side of the rectangle, and a pair of side edges close to and parallel to the pair of long sides of the rectangle. The bottom edge and the pair of side edges of the U-shape surround the periphery of the vertical edge of the π / π shape.

[0056] The upper bridge control loop area L3 is in the shape of a straight line. The straight line area is located in the middle of the vertical side of the Π / π shape of the upper bridge power loop area L1, and the gate resistor assembly area and the Kelvin source bonding area are staggered in a zipper-like arrangement.

[0057] The lower bridge control loop region L4 is U-shaped, and the U-shape is located in the empty area of ​​the upper bridge power loop region L1Π / π-shaped vertical side surrounded by the lower bridge power loop U-shape, and the gate resistor assembly area and the Kelvin source bonding area are staggered in a zipper-like arrangement;

[0058] The electrode assembly area L5 is in the shape of a pair of triangles, and the pair of triangles are respectively located on the outer sides of the bottom edge of the U shape.

[0059] According to the present invention, the upper bridge power MOS transistor T1 includes two groups of upper bridge MOS transistors, each group of upper bridge MOS transistors includes four upper bridge MOS transistors, and the four upper bridge MOS transistors are arranged in a straight line and parallel to the long side of the rectangle;

[0060] Two groups of upper bridge MOS transistors are arranged parallel and symmetrically on the vertical sides of the π / π shape. The drain surface of each upper bridge MOS transistor is mechanically and electrically connected to the outer surface of the upper bridge power loop area L1 through sintered copper paste;

[0061] The lower bridge power MOS transistor T2 includes two groups of lower bridge MOS transistors, each group of lower bridge MOS transistors includes four lower bridge MOS transistors, and the four lower bridge MOS transistors are arranged in a straight line and parallel to the long side of the rectangle;

[0062] Two groups of lower-bridge MOS transistors are arranged parallel and symmetrically on a pair of side edges of the font. The drain surface of each lower-bridge MOS transistor is mechanically and electrically connected to the outer surface of the lower-bridge power circuit area L2 through sintered copper paste.

[0063] All upper bridge MOS tubes and all lower bridge MOS tubes are electrically connected in parallel.

[0064] According to the present invention, the side end surfaces of the first copper clips 5-1 and 5-2 are in the shape of the upper half of a convex character;

[0065] Four square through holes arranged in a straight line are provided on the rectangular plane where the upper horizontal sides of the first copper clips 5 - 1 and 5 - 2 are located. The four square through holes are used to expose a group of lower bridge MOS transistors on the corresponding side.

[0066] The rectangular plane on one side of the lower horizontal edge of the first copper clips 5-1 and 5-2 is provided with four evenly arranged rectangular protrusions. The size of the lower surface of the protrusions is consistent with the size of the source surface of the MOS tube. The lower surfaces of the four protrusions are respectively mechanically and electrically connected to the source surfaces of the four upper bridge MOS tubes on the corresponding side through sintered copper paste. The lower surface of the rectangular plane on the other side of the horizontal edge is mechanically and electrically connected to the outer surface of the lower bridge power circuit area L2 through sintered copper paste.

[0067] Preferably, it further includes a second copper clip 2-2;

[0068] The side end surface of the second copper clip 2-2 is in the shape of the upper half of a convex character;

[0069] The upper horizontal side of the second copper clip 2-2 is in a rectangular shape;

[0070] The rectangular planes on both sides of the lower side of the second copper clip 2-2 are each provided with four evenly spaced rectangular protrusions. The dimensions of the lower surfaces of the protrusions are consistent with the dimensions of the source surfaces of the MOS tubes. The four evenly spaced rectangular protrusions on each side pass through the four square through-holes on the upper portions of the first copper clips 5-1 and 5-2 on each side. The lower surfaces of the rectangular protrusions are respectively mechanically and electrically connected to the source surfaces of the four lower-bridge MOS tubes on the corresponding side through sintered copper paste.

[0071] A pair of vertical sides of the second copper clip 2-2 are perpendicular to the horizontal sides of its lower portion.

[0072] In the present invention, copper clip technology is used to replace copper wire bonding technology, which solves the problem of high stray inductance in the copper wire bonding technology solution and can effectively reduce the stray inductance of the commutation circuit to 3-4nH, which helps to improve the switching performance. At the same time, it can also conduct heat away from the power MOS tube 6, adding a heat dissipation path for the power MOS tube 6, effectively improving the heat dissipation capacity of the module and having a temperature equalization effect. The uniform temperature of each power MOS tube 6 also has a certain promoting effect on the current equalization of the power MOS tube 6.

[0073] In the present invention, the interconnecting copper clips can also be integrated with the power terminals, thereby reducing the number of integrated components, the number of components and process steps, and lowering the process cost.

[0074] According to the present invention, a pair of DC+ terminals 1-1 and 1-2 are symmetrically arranged at both ends of the horizontal side of the Π / π shape;

[0075] The wide side of the rectangle where the upper horizontal side of the second copper clip 2-2 is located is the DC-terminal 2-1;

[0076] The DC-terminal 2-1 and the pair of DC+ terminals 1-1 and 1-2 are located on one wide side of the upper copper layer and at the same level. The DC-terminal 2-1 is located between the upper and lower parts of the second copper clip 2-2 in terms of level.

[0077] The AC terminal 3 is set at the bottom edge of the U-shaped lower bridge power circuit area L2, and the AC terminal 3 is located on the other wide side of the upper copper layer.

[0078] Preferably, the electrode assembly area L5 is provided with a total of control terminals 11, including thermistor NTC control terminals 11-1 and 11-2, a lower bridge MOS transistor gate control terminal 11-3, a lower bridge MOS transistor control source terminal 11-4, an upper bridge MOS transistor control source terminal 11-5, an upper bridge MOS transistor gate control terminal 11-6, and an upper bridge MOS transistor drain sensing terminal 11-7;

[0079] Thermistor NTC control terminals 11-1 and 11-2 are used to lead out the electrodes at both ends of the thermistor built into the power module to monitor the chip junction temperature of the power module;

[0080] The lower bridge MOS transistor gate control terminal 11 - 3 is electrically connected to the gate of the lower bridge MOS transistor through the lower bridge control loop region L4 ;

[0081] The lower bridge MOS transistor control source terminal 11 - 4 is electrically connected to the source of the lower bridge MOS transistor through the lower bridge control loop region L4 ;

[0082] The upper bridge MOS transistor control source terminal 11 - 5 is electrically connected to the source of the upper bridge MOS transistor through the upper bridge control loop region L3 ;

[0083] The upper bridge MOS transistor gate control terminal 11-6 is electrically connected to the gate of the upper bridge MOS transistor through the upper bridge control loop region L3;

[0084] The upper bridge MOS transistor drain sensing terminal 11-7 is electrically connected to the drain of the upper bridge MOS transistor through the upper bridge control loop region L3;

[0085] The radiator 4 is a microchannel jet radiator, which includes two layers, the upper layer's flow channel is formed by a combination of multiple densely arranged strip fins, and the lower layer's flow channel is formed by a combination of multiple staggered rectangular fins.

[0086] In the present invention, each control terminal 11 is electrically connected to the gates of all upper-bridge MOS transistors and lower-bridge MOS transistors; thermistor NTC control terminals 11-1 and 11-2 are electrically connected to the thermistor NTC; the lower-bridge MOS transistor gate control terminal 11-3 is electrically connected to the gates of all lower-bridge MOS transistors; the lower-bridge MOS transistor control source terminal 11-4 is electrically connected to the control sources of all lower-bridge MOS transistors; the upper-bridge MOS transistor control source terminal 11-5 is electrically connected to the control sources of all upper-bridge MOS transistors; the upper-bridge MOS transistor gate control terminal 11-6 is electrically connected to the gates of all upper-bridge MOS transistors; and the upper-bridge MOS transistor drain sensing terminal 11-7 is electrically connected to the drain of the upper-bridge MOS transistor.

[0087] The heat sink 4 of the present invention is divided into multiple zones for directing fluid flow, referred to as fluid guiding zones. Upon entering the heat sink, the fluid first enters the upper flow channel, then diffuses laterally through the fins to the five adjacent fluid guiding zones. In these zones, the fluid changes direction and diffuses to new fins, repeating this cycle.

[0088] The heat sink 4 can be formed by additive manufacturing of metal powder. The upper flow channel is directly sintered with the lower copper layer of the power module substrate. The fluid can directly contact the lower copper layer of the substrate, minimizing the physical distance between the fluid and the internal heat source of the power module. The densely arranged fins in the upper flow channel will give the fluid an extremely high flow rate, thereby continuously jetting to impact the lower copper layer of the substrate and taking away a large amount of heat.

[0089] In the present invention, the upper bridge power MOS transistor T1 and the lower bridge power MOS transistor T2 are each independently selected from any one of a SiC power device, a silicon-based IGBT and a silicon-based MOSFET.

[0090] In the present invention, double-sided copper sintering replaces the double-sided silver sintering technology solution, which solves the problem that the silver material in the double-sided silver sintering technology solution is prone to electromigration, affecting reliability. Under high current and high temperature working conditions, copper material is less likely to undergo electromigration, which improves reliability. At the same time, the cost is lower than that of silver material.

[0091] In the present invention, large-area copper sintering is used to replace the large-area brazing welding technology solution, which solves the problems of weak connection strength, large thermal resistance and poor reliability of excessively thick large-area brazing layers. The shear strength of pressureless sintered copper can reach more than 40MPa, and the shear strength of pressurized sintered copper can reach more than 100MPa, and the thermal resistance is smaller. Compared with sintered silver, the performance is similar or better, the raw material cost is lower, and combined with double-sided copper sintering technology, the process cost can also be reduced.

[0092] In the present invention, current flows in from the DC+ terminals 1-1 and 1-2, passes through the upper bridge power circuit region L1 of the substrate 7, the drain of the upper bridge power MOS transistor T1, the source of the upper bridge power MOS transistor T1, the first copper clips 5-1 and 5-2, and the lower bridge power circuit region L2 of the substrate 7, and flows out from the AC terminal 3; current flows in from the AC terminal 3, passes through the lower bridge power circuit region L2 of the substrate 7, the drain of the lower bridge power MOS transistor T2, the source of the lower bridge power MOS transistor T2, and finally flows out along the second copper clip 2-2 and the DC-terminal 2-1.

[0093] The present invention also provides a method for manufacturing the above-mentioned device, comprising:

[0094] The power MOS transistor 6 is interconnected with the substrate 7 by printing copper paste on the surface of the power loop area, placing the drain surface of the power MOS transistor 6 on the copper paste, and then preheating and sintering are performed in sequence to form a sintered copper layer 9 connecting the power MOS transistor and the substrate;

[0095] Interconnection between substrate 7 and heat sink 4: Copper paste is printed on the surface of heat sink 4, the lower copper layer of substrate 7 is placed on the copper paste, and preheating and sintering are performed in sequence to form a large area sintered copper layer connecting substrate 7 and heat sink 4;

[0096] Interconnection between the power MOS transistor 6 and the copper clip: Copper paste is printed on all bottom surfaces of the first copper clips 5-1, 5-2, and the second copper clip 2-2. The rectangular protruding ends of the first copper clips 5-1 and 5-2 are aligned with the source surfaces of each upper bridge power MOS transistor T1, and the outer edges of the other bottom surfaces are aligned with the bottom edge of the lower bridge power loop area. The rectangular protruding end of the second copper clip 2-2 is aligned with the source surface of the lower bridge power MOS transistor. Preheating and sintering are performed in sequence to form a sintered copper layer that interconnects the upper and lower bridge power MOS transistors.

[0097] According to the present invention, it also includes:

[0098] Terminal ultrasonic welding: symmetrically weld a pair of DC+ terminals 1-1 and 1-2 at both ends of the horizontal side of the π / π shape, and weld the AC terminal 3 at the bottom side of the U shape.

[0099] Preferably, the thickness of the copper paste used to connect the first copper clips 5-1, 5-2 and the second copper clip 2-2 is 10-100 microns, and the thickness of the copper paste used in the remaining steps is 100-200 microns;

[0100] The preheating temperature of each step is 60-150°C and the time is 3-10 minutes;

[0101] The pressure conditions of sintering in each step are pressure or no pressure, the temperature is 200-280°C, and the time is 3-15 minutes. If pressure sintering is performed, the sintering equipment can use a movable pressure head to accurately match the rectangular protruding ends of the first copper clips 5-1, 5-2 and the second copper clip 2-2.

[0102] The present invention will be described in more detail below through specific examples.

[0103] Example 1

[0104] like Figure 1 As shown, this embodiment provides a packaged integrated device with full copper interconnection, a 2-in-1 half-bridge structure consisting of an upper bridge power MOS tube T1 and a lower bridge power MOS tube T2, and the topology is as follows Figure 1 As shown, the upper bridge power MOS tube T1 and the upper bridge power MOS tube T2 each include 8 SiC chips connected in parallel. Figure 5 As shown, the largest pad on the upper surface of each SiC chip is the power MOS tube source pad 6-1, and the lower surface is the SiC chip drain. The upper bridge power MOS tube T1 represents Figure 4A The substrate 7 shown has 8 chips connected in parallel in the 2nd and 3rd rows from the top to the bottom, and the lower bridge power MOS tube T2 represents 8 chips connected in parallel in the 1st and 4th rows;

[0105] The substrate 7 is composed of three layers, namely, an upper copper layer, a ceramic layer, and a lower copper layer from top to bottom. The upper copper layer is designed with a circuit, and the ceramic layer separates the upper copper layer circuit from the lower copper layer and the heat sink 4 to act as an insulator. Figure 4A As shown, the copper layer where the eight chips of the upper bridge power MOS transistor T1 are located is the upper bridge power circuit area L1 of the copper layer on the substrate 7, that is, the upper bridge circuit part, and the copper layer where the eight chips of the lower bridge power MOS transistor T2 are located is the lower bridge power circuit area L2, that is, the lower bridge circuit part of the copper layer on the substrate 7; Figure 4B As shown, the portion in the middle of the π-shaped vertical side of the upper bridge power circuit area L1 is the upper bridge control circuit area L3, and the portion in the U-shaped portion of the empty area between the π-shaped vertical side of the upper bridge power circuit area and the U-shaped portion is the lower bridge control circuit area L4. The gate resistor assembly areas and the Kelvin source bonding areas of all control circuit areas are staggered in a zipper-like arrangement; Figure 2 、 3A3B is a schematic diagram of the internal structure of the device. Each chip of the upper bridge power MOS transistor T1 and the lower bridge power MOS transistor T2 is sintered on the substrate 7 through sintered copper. The drain electrodes on the lower surface of the eight chips of the upper bridge power MOS transistor T1 are connected to the upper bridge power circuit area L1 of the copper layer on the substrate 7 through sintered copper. The drain electrodes on the lower surface of the eight chips of the lower bridge power MOS transistor T2 are connected to the lower bridge power circuit area L2 of the copper layer on the substrate 7 through sintered copper.

[0106] The power MOS transistor source pads 6-1 on the upper surface of the eight chips of the upper bridge power MOS transistor T1 are connected to the first copper clips 5-1 and 5-2 through copper sintering. The other ends of the first copper clips 5-1 and 5-2 are connected to the lower bridge circuit part of the copper layer on the substrate 7; the power MOS transistor source pads 6-1 on the upper surface of the eight chips of T2 are connected to the second copper clip 2-2 through copper sintering. Figure 6 The schematic diagram of double-sided copper sintering is shown;

[0107] The substrate 77 is connected to the heat sink 4 through a large area of ​​sintered copper, such as Figure 7 As shown;

[0108] The DC+ terminals 1-1, 1-2 and AC terminal 3 are ultrasonically welded to the corresponding positions of the copper layer on the substrate 7. Figure 3A and 3B As shown;

[0109] The DC-terminal 2-1 is made of copper clip materials and processes. The DC-terminal 2-1 is integrated with the second copper clip 2-2 to reduce the number of components. It is directly connected to the source electrode on the upper surface of the lower bridge power MOS tube T2 chip through sintered copper. Figure 2 As shown;

[0110] In this embodiment, current flows in from the DC+ terminals 1-1 and 1-2, passes through the substrate 7 and the upper bridge power circuit region L1, the drain of the upper bridge power MOS transistor T1, the source of the upper bridge power MOS transistor T1, the first copper clips 5-1 and 5-2 in sequence, and flows out from the AC terminal 3. Current flows in from the AC terminal 3, passes through the substrate 7 and the lower bridge power circuit region L2, the drain of the lower bridge power MOS transistor T2, the source of the lower bridge power MOS transistor T2 in sequence, and finally flows out along the second copper clip 2-2 and the DC- terminal 2-1.

[0111] This embodiment provides a method for manufacturing an all-copper interconnected package integrated device, the specific steps of which include:

[0112] (1) Interconnection between the chip and the substrate 7: Copper paste is printed on the substrate 7, and the power MOS transistor 6 chip is placed on the copper paste. It is preheated at 100°C for 8 minutes and sintered at 250°C for 10 minutes under pressure. The copper paste is sintered to form a porous copper layer, i.e., the sintered copper layer 9 of the upper bridge power MOS transistor and the substrate;

[0113] (2) Interconnection between substrate 7 and radiator: Copper paste is printed on radiator 4 with a thickness of 150 μm. The paste is preheated at 100°C for 8 minutes and sintered at 250°C for 10 minutes without pressure. The copper paste is sintered to form a porous copper layer, i.e., a large-area sintered copper layer 10 between substrate and radiator.

[0114] (3) Interconnection between copper clip and chip: Print copper paste on the source pad 6-1 of the power MOS tube. The copper paste has a thickness of 80 μm. Preheat at 100°C for 8 minutes and sinter at 250°C for 10 minutes without pressure. The copper paste is sintered to form a porous copper layer, i.e., the sintered copper layer 8 between the second copper clip 2-2 and the power MOS tube.

[0115] (4) Terminal ultrasonic welding: DC+ terminals 1-1, 1-2, AC terminal 3, and control terminal 11 are welded at corresponding positions on the upper copper layer of substrate 7 to obtain interconnection between the internal and external application components of the module.

[0116] The all-copper interconnected package integrated device in this embodiment adopts a copper clip interconnect structure, which reduces stray inductance and facilitates heat dissipation and temperature uniformity. The sintered silver layers on the upper and lower surfaces of the MOS tube are replaced with sintered copper layers, which greatly reduces electromigration, improves package reliability, and reduces raw material costs. The substrate and the heat sink are connected using a large-area copper sintering connection, which can reduce warpage, reduce interface thermal resistance, improve connection quality and reliability, reduce raw material costs, and simplify the process.

[0117] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A fully copper interconnected package integrated device, characterized in that: include: A substrate comprising an upper copper layer, a ceramic layer, and a lower copper layer in contact with each other in sequence, wherein the upper copper layer comprises a power circuit region, a control circuit region, and an electrode assembly region, and each portion is electrically insulated from the other portion; the power circuit region comprises an upper bridge power circuit region and a lower bridge power circuit region; the control circuit region comprises an upper bridge control circuit region and a lower bridge control circuit region; each control circuit region comprises a gate resistor assembly region and a Kelvin source bonding region; The upper bridge power MOS tube has a drain surface that is mechanically and electrically connected to the outer surface of the upper bridge power loop region by sintering copper paste, and a source surface that is mechanically and electrically connected to the first copper clip by sintering copper paste; The drain surface of the lower bridge power MOS transistor is mechanically and electrically connected to the outer surface of the lower bridge power loop region via sintered copper paste, and is electrically connected to the source surface of the upper bridge power MOS transistor via a first copper clip, and the source surface is mechanically and electrically connected to the second copper clip via sintered copper paste; a heat sink, disposed on the outer surface of the lower copper layer; The drain surfaces and source surfaces of the upper bridge power MOS tube and the lower bridge power MOS tube are located on opposite surfaces.

2. The device according to claim 1, characterized in that The upper copper layer is in a rectangular shape; The upper bridge power loop area is in a Π / π shape, and the horizontal side of the Π / π shape is close to and parallel to a wide side of the rectangle; The lower bridge power circuit area is U-shaped, with the bottom side of the U close to and parallel to the other wide side of the rectangle, and a pair of side sides close to and parallel to a pair of long sides of the rectangle, and the bottom side and the pair of side sides of the U-shape surround the periphery of the vertical side of the π / π shape; The upper bridge control loop area is in a straight line shape, the straight line area is located in the middle of the vertical side of the π / π shape of the upper bridge power loop area, and the gate resistor assembly area and the Kelvin source bonding area are staggered in a zipper shape; The lower bridge control loop area is U-shaped, and the U-shape is located in the empty area of ​​the upper bridge power loop area where the vertical sides of the π / π shape are surrounded by the lower bridge power loop U-shape, and the gate resistor assembly area and the Kelvin source bonding area are staggered in a zipper shape; The electrode assembly area is in the shape of a pair of triangles, and the pair of triangles are respectively located on two outer sides of the bottom edge of the U shape.

3. The device according to claim 2, characterized in that The upper bridge power MOS transistors include two groups of upper bridge MOS transistors, each group of upper bridge MOS transistors includes four upper bridge MOS transistors, and the four upper bridge MOS transistors are arranged in a straight line and parallel to the long side of the rectangle; The two groups of upper bridge MOS transistors are arranged parallel and symmetrically on the vertical sides of the Π / π shape, and the drain surface of each upper bridge MOS transistor is mechanically and electrically connected to the outer surface of the upper bridge power circuit area through sintered copper paste; The lower bridge power MOS transistors include two groups of lower bridge MOS transistors, each group of lower bridge MOS transistors includes four lower bridge MOS transistors, and the four lower bridge MOS transistors are arranged in a straight line and parallel to the long side of the rectangle; The two groups of lower bridge MOS transistors are arranged parallel and symmetrically on a pair of side edges of the U-shape, and the drain surface of each lower bridge MOS transistor is mechanically and electrically connected to the outer surface of the lower bridge power circuit area by sintering copper paste; All upper bridge MOS tubes and all lower bridge MOS tubes are electrically connected in parallel.

4. The device according to claim 3, characterized in that The side end surface of the first copper clip is in the shape of the upper half of a convex character; Four square through holes arranged in a straight line are provided on the rectangular plane where the upper horizontal side of the first copper clip is located, and the four square through holes are used to expose a group of lower bridge MOS transistors on the corresponding side; The rectangular plane on one horizontal side of the lower portion of the first copper clip is provided with four evenly arranged rectangular protruding ends. The size of the lower surface of the protruding ends is consistent with the size of the source surface of the MOS tube. The lower surfaces of the four protruding ends are respectively mechanically and electrically connected to the source surfaces of the four upper bridge MOS tubes on the corresponding side through sintered copper paste. The lower surface of the rectangular plane on the other horizontal side is mechanically and electrically connected to the outer surface of the lower bridge power circuit area through sintered copper paste.

5. The device according to claim 4, characterized in that Also included is a second copper clamp; The side end surface of the second copper clip is in the shape of the upper half of a convex character; The upper horizontal side of the second copper clip is in a rectangular shape; The rectangular planes on both sides of the lower portion of the second copper clip are each provided with four evenly spaced rectangular protrusions. The dimensions of the lower surfaces of the protrusions are consistent with the dimensions of the source surfaces of the MOS tubes. The four evenly spaced rectangular protrusions on each side pass through the four square through-holes on the upper portion of the first copper clip on each side. The lower surfaces of the rectangular protrusions are respectively mechanically and electrically connected to the source surfaces of the four lower-bridge MOS tubes on the corresponding side through sintered copper paste. A pair of vertical sides of the second copper clip are perpendicular to the horizontal sides of the lower portion thereof.

6. The device according to claim 5, characterized in that A pair of DC+ terminals are symmetrically arranged at both ends of the horizontal side of the Π / π shape; The wide side of the rectangle where the upper horizontal side of the second copper clip is located is the DC-terminal; The DC-terminal and the pair of DC+ terminals are located on one wide side of the upper copper layer and at the same horizontal height, and the DC-terminal is located between the upper and lower parts of the second copper clip in terms of horizontal height; An AC terminal is provided at the bottom edge of the U-shape of the lower bridge power loop region, and the AC terminal is located at the other wide side of the upper copper layer.

7. The device according to claim 6, characterized in that The electrode assembly area is provided with control terminals, including a thermistor NTC control terminal, a lower bridge MOS transistor gate control terminal, a lower bridge MOS transistor control source terminal, an upper bridge MOS transistor control source terminal, an upper bridge MOS transistor gate control terminal, and an upper bridge MOS transistor drain sensing terminal; The thermistor NTC control terminal is used to lead out the electrodes at both ends of the thermistor built into the power module to monitor the chip junction temperature of the power module; The gate control terminal of the lower bridge MOS transistor is electrically connected to the gate of the lower bridge MOS transistor through the lower bridge control loop area; The control source terminal of the lower bridge MOS transistor is electrically connected to the source of the lower bridge MOS transistor through the lower bridge control loop region; The upper bridge MOS transistor control source terminal is electrically connected to the source of the upper bridge MOS transistor through the upper bridge control loop region; The gate control terminal of the upper bridge MOS transistor is electrically connected to the gate of the upper bridge MOS transistor through the upper bridge control loop area; The upper bridge MOS transistor drain sensing terminal is electrically connected to the drain of the upper bridge MOS transistor through the upper bridge control loop region; The radiator is a microchannel jet radiator, which includes two layers, the upper layer's flow channel is formed by a combination of multiple densely arranged strip fins, and the lower layer's flow channel is formed by a combination of multiple staggered rectangular fins.

8. A method for manufacturing the device according to any one of claims 1 to 7, characterized in that: include: Interconnection between the power MOS tube and the substrate: Print copper paste on the surface of the power loop area, place the drain surface of the power MOS tube on the copper paste, and preheat and sinter in sequence to form a sintered copper layer connecting the power MOS tube and the substrate; Interconnection between substrate and radiator: Copper paste is printed on the surface of the radiator, the lower copper layer of the substrate is placed on the copper paste, and preheating and sintering are performed in sequence to form a large-area sintered copper layer connecting the substrate and the radiator; Interconnection between power MOS tubes and copper clips: Copper paste is printed on all bottom surfaces of the first and second copper clips. The rectangular protruding end of the first copper clip is aligned with the source surface of each upper bridge power MOS tube, and the outer edge of the other bottom surface is aligned with the bottom edge of the lower bridge power loop area. The rectangular protruding end of the second copper clip is aligned with the source surface of the lower bridge power MOS tube. Preheating and sintering are performed in sequence to form a sintered copper layer that interconnects the upper and lower bridge power MOS tubes.

9. The method according to claim 8, characterized in that Also includes: Terminal ultrasonic welding: symmetrically weld a pair of DC+ terminals at both ends of the horizontal side of the π / π shape, and weld the AC terminal at the bottom side of the U shape.

10. The method according to claim 9, characterized in that The thickness of the copper paste used to connect the first copper clip and the second copper clip is 10 to 100 microns, and the thickness of the copper paste used in the remaining steps is 100 to 200 microns; The preheating temperature of each step is 60-150°C and the time is 3-10 minutes; The pressure conditions of sintering in each step are pressure or no pressure, the temperature is 200-280°C, and the time is 3-15 minutes. If pressure sintering is performed, the sintering equipment can use a movable pressure head to accurately match the rectangular protruding ends of the first copper clip and the second copper clip.

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