Three-dimensional vertical power supply structure of integrated micro-channel and manufacturing method of three-dimensional vertical power supply structure

Abstract

The invention relates to a three-dimensional vertical power supply structure of an integrated micro-channel and a manufacturing method of the three-dimensional vertical power supply structure. The structure comprises a first silicon wafer; a gate driving layer; a first redistribution layer; a first bonding protection layer; a second silicon wafer; a power transistor layer; a second redistribution layer; a second bonding protection layer; a first micro-channel; a second micro-channel; the first micro-channel and the second micro-channel are connected with each other, and inflow and outflow of cooling liquid are realized through the micro-channel inlet and the micro-channel outlet; a first through silicon via; a second through silicon via; and the gate driving layer and the power transistor layer are electrically connected through the first through silicon via and the second through silicon via. According to the three-dimensional vertical power supply structure of the integrated micro-channel, the grid driving layer and the power transistor layer are vertically interconnected and supplied with power through the silicon through hole, the power supply efficiency can be remarkably improved, the micro-channel is integrated in the power supply structure, and the power supply structure can be rapidly cooled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional vertical power supply structure with integrated microchannel and a manufacturing method thereof. Background Art

[0002] As advanced process nodes continue to evolve and the demand for greater computing power in artificial intelligence, data centers, and high-performance computing applications grows rapidly, the power of high-performance processors (such as graphics processing units (GPUs), central processing units (CPUs), and application-specific integrated circuits (ASICs)) continues to rise, while the core voltage continues to fall. These developments pose great challenges to power supply, such as a strong demand for power integrity in the package, including the need to manage voltage gradients between power pins of high-current low-voltage processors caused by the increasing impedance drop of the power distribution network (PDN), transient performance specifications, and power consumption.

[0003] The prior art usually adopts the arrangement of voltage regulator modules (VRM) on printed circuit boards (PCBs) and the power supply to the chip through multi-level PDNs. However, the current flowing out of the VRM needs to pass through a long interconnection path to reach the chip, and the PDN impedance is high and the loss is large. When the high-performance processor has a large load current demand, the PDN impedance will cause a sharp drop in voltage and unacceptable conduction loss, which will seriously limit the processor performance and reduce the system energy efficiency. In addition, the resulting low power efficiency requires a larger thermal management solution, resulting in a larger heat dissipation problem, which will have a bad impact on the normal operation of the high-performance processor.

[0004] Therefore, as the power and thermal consumption of high-performance processors rise sharply, the demand for power supply and heat dissipation increases sharply, and the existing method of arranging VRM plus multi-level PDN on PCB is gradually unable to meet the demand. Summary of the invention

[0005] In view of some or all of the problems in the prior art, the present invention provides a three-dimensional vertical power supply structure with integrated microfluidic channel, the structure comprising:

[0006] The first silicon wafer;

[0007] A gate driving layer, wherein the gate driving layer is arranged on the first surface of the first silicon wafer;

[0008] A first redistribution layer, wherein the first redistribution layer is arranged on a first surface of the gate driving layer;

[0009] A first bonding protection layer, wherein the first bonding protection layer is arranged on the second surface of the first silicon wafer;

[0010] a second silicon wafer;

[0011] A power transistor layer, wherein the power transistor layer is arranged on the first surface of the second silicon wafer;

[0012] a second redistribution layer, the second redistribution layer being arranged on a first surface of the power transistor layer;

[0013] A second bonding protection layer, wherein the second bonding protection layer is arranged on the second surface of the second silicon wafer;

[0014] a first microfluidic channel, wherein the first microfluidic channel is arranged in the first silicon wafer;

[0015] a second microfluidic channel, wherein the second microfluidic channel is arranged in the second silicon wafer;

[0016] The first microfluidic channel and the second microfluidic channel are interconnected, and the coolant flows in and out through the microfluidic channel inlet and the microfluidic channel outlet;

[0017] A first through silicon via, wherein the first through silicon via passes through the first silicon wafer and the first bonding protection layer;

[0018] A second through silicon via, wherein the second through silicon via passes through the second silicon wafer and the second bonding protection layer;

[0019] The gate driving layer and the power transistor layer are electrically connected through the first through silicon via and the second through silicon via.

[0020] Further, the first redistribution layer includes a first interconnect pad, and the first interconnect pad is electrically connected to the gate drive layer; and / or

[0021] The second redistribution layer includes a second interconnection pad electrically connected to the power transistor layer.

[0022] Furthermore, the power supply path of the three-dimensional vertical power supply structure of the integrated microfluidic channel is:

[0023] The gate driving layer drives the power transistor layer, and the power transistor layer supplies power to the chip.

[0024] The present invention also provides a method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels, the method comprising the following steps:

[0025] Manufacturing a gate driving layer on a first surface of a first silicon wafer;

[0026] On the first surface of the gate driving layer, a first redistribution layer is formed;

[0027] On the first surface of the first redistribution layer, a first temporary bonding layer is manufactured, and a first carrier is bonded to the first surface of the first temporary bonding layer to form a first carrier structure;

[0028] Turning over the first carrier structure to thin the second surface of the first silicon wafer;

[0029] Forming a first bonding protection layer on the second surface of the first silicon wafer, and etching the first bonding protection layer and the first silicon wafer to form a first through silicon via groove;

[0030] Depositing a first through silicon via filler in the first through silicon via groove to form a first through silicon via;

[0031] Etching the first bonding protection layer and the first silicon wafer to form a first microchannel and form a wafer structure including a gate driving layer;

[0032] Forming a wafer structure including a power transistor layer, wherein the wafer structure including the power transistor layer includes a second silicon wafer, a power transistor layer, a second redistribution layer, a second temporary bonding layer, a second carrier, a second bonding protection layer, a second through silicon via, and a second microchannel;

[0033] Bonding the wafer structure including the gate drive layer and the wafer structure including the power transistor layer face to face;

[0034] Removing the first carrier sheet, and punching holes at corresponding positions of the inlet and outlet of the first microfluidic channel to form a microfluidic channel inlet and a microfluidic channel outlet;

[0035] The second carrier sheet is removed and cut to form a three-dimensional vertical power supply structure with integrated microfluidic channels.

[0036] Further, the first redistribution layer is manufactured using a Damascus process, and the first redistribution layer includes a first interconnection pad; and / or

[0037] The second redistribution layer is manufactured by using a damascene process, and the second redistribution layer includes a second interconnection pad.

[0038] Further, the first temporary bonding layer is silicon oxide or silicon nitride or silicon oxynitride or organic bonding glue; and / or

[0039] The second temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride or organic bonding glue.

[0040] Further, the first bonding protection layer is silicon oxide or silicon nitride or silicon oxynitride; and / or

[0041] The second bonding protection layer is silicon oxide, silicon nitride, or silicon oxynitride.

[0042] Further, the first through silicon via comprises a first bonding pad; and / or

[0043] The second through silicon via includes a second bonding pad.

[0044] Furthermore, the face-to-face bonding is hybrid bonding, wherein the first bonding pad is bonded to the second bonding pad, and the first bonding protection layer is bonded to the second bonding protection layer.

[0045] Further, the first carrier is removed by mechanical separation or thermal sliding or laser separation; and / or

[0046] The second carrier is removed using mechanical separation or thermal sliding or laser separation.

[0047] The technical solution provided by the present invention has the following beneficial effects:

[0048] 1. The three-dimensional vertical power supply structure with integrated microfluidic channels provided by the present invention separately manufactures a wafer structure including a gate drive layer and a wafer structure including a power transistor layer, which significantly reduces interconnection resistance and parasitic parameters and improves power supply efficiency.

[0049] 2. The three-dimensional vertical power supply structure with integrated microfluidic channels provided by the present invention vertically interconnects and supplies power to the gate drive layer and the power transistor layer through silicon vias, which can significantly improve the transient response of the power supply and reduce the loss of the power distribution network.

[0050] 3. The three-dimensional vertical power supply structure with integrated microfluidic channels provided by the present invention integrates microfluidic channels in the power supply structure, which can quickly dissipate heat for the power supply structure and high-performance processors, and has excellent heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0052] Figure 1 A schematic diagram showing a three-dimensional vertical power supply structure of an integrated microfluidic channel according to an embodiment of the present invention;

[0053] Figure 2 A schematic diagram showing a power supply path of a three-dimensional vertical power supply structure with integrated microfluidic channels according to an embodiment of the present invention is shown;

[0054] Figure 3A schematic diagram showing a process flow of a method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to an embodiment of the present invention; and

[0055] Figure 4a-4k A schematic cross-sectional diagram of a process for forming a three-dimensional vertical power supply structure with integrated microfluidic channels according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0056] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0057] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0058] In this specification, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." only indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0059] In this specification, unless otherwise specified, "first surface" and "second surface" are only used to describe the surfaces of the same component. In addition, "first", "second" and "third" are only used to distinguish and do not include size differences.

[0060] In this specification, unless otherwise specified, the quantifiers "a", "an" do not exclude the presence of a plurality of elements, and the quantifiers "plurality" and "multiple" refer to one or more than one elements.

[0061] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0062] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0063] As the power and thermal power consumption of high-performance chips rise sharply, the demand for power supply and heat dissipation increases sharply. The existing method of arranging VRM plus multi-level PDN on PCB gradually cannot meet the power supply and heat dissipation needs of high-performance chips. The present invention provides a three-dimensional vertical power supply structure with integrated microfluidics, and separately manufactures a wafer structure including a gate drive layer and a wafer structure including a power transistor layer. The gate drive layer and the power transistor layer are vertically interconnected and powered by through silicon vias, which can significantly improve power supply efficiency, improve power supply transient response, and reduce PDN losses. The three-dimensional vertical power supply structure with integrated microfluidics provided by the present invention integrates microfluidics in the power supply structure, can quickly dissipate heat for the power supply structure and high-performance processors, and has excellent heat dissipation performance.

[0064] Figure 1 A schematic diagram of a three-dimensional vertical power supply structure of an integrated microfluidic channel according to an embodiment of the present invention is shown. The three-dimensional vertical power supply structure of the integrated microfluidic channel includes two parts, namely, a wafer structure including a gate drive layer and a wafer structure including a power transistor layer. Figure 1 As shown, the wafer structure including the gate drive layer includes a first silicon wafer 101, a gate drive layer 102, a first redistribution layer 103, a first bonding protection layer 106, a first through silicon via 108, a first microchannel 109, a microchannel inlet 111, and a microchannel outlet 112. The wafer structure including the power transistor layer includes a second silicon wafer 201, a power transistor layer 202, a second redistribution layer 203, a second bonding protection layer 206, a second through silicon via 208, and a second microchannel 209.

[0065] The gate drive layer 102 is arranged on the first surface of the first silicon wafer 101. The gate drive layer is the Gate Drivers layer, which is mainly used to drive the transistor. The first redistribution layer 103 is arranged on the first surface of the gate drive layer 102. In one embodiment of the present invention, the first redistribution layer 103 can be made by the chip back-end process (BEOL), and the first redistribution layer 103 can include multiple dielectric layers and metal layers. In one embodiment of the present invention, the first redistribution layer 103 includes a first interconnect pad (PAD), the first interconnect pad is electrically connected to the gate drive layer 102, the first interconnect pad is made of a metal layer, and the first interconnect pad can be made of pure metals such as Au, Cu, Al, or alloys thereof. The first bonding protection layer 106 is arranged on the second surface of the first silicon wafer 101, and the first bonding protection layer 106 is an inorganic film layer, preferably silicon oxide or silicon nitride or silicon oxynitride. The first through silicon via 108 penetrates the first silicon wafer 101 and the first bonding protection layer 106, and the first through silicon via 108 is filled with a first through silicon via filler. In one embodiment of the present invention, the first through silicon via filler can be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The first microchannel 109 is arranged in the first silicon wafer 101.

[0066] The power transistor layer 202 is arranged on the first surface of the second silicon wafer 201. The power transistor is PowerTransistors, which are interconnected with the gate drive layer 102 through the first silicon via 108 and the second silicon via 208 to form a power supply structure. The second redistribution layer 203 is arranged on the first surface of the power transistor layer 202. In one embodiment of the present invention, the second redistribution layer 203 can be made by a chip back-end process (BEOL), and the second redistribution layer 203 can include multiple dielectric layers and metal layers. In one embodiment of the present invention, the second redistribution layer 203 includes a second interconnect pad, which is electrically connected to the power transistor layer 202. The second interconnect pad is made of a metal layer, and the second interconnect pad can be made of pure metals such as Au, Cu, Al, or alloys thereof. The second bonding protection layer 206 is arranged on the second surface of the second silicon wafer 201. The second bonding protection layer 206 is an inorganic film layer, preferably silicon oxide or silicon nitride or silicon oxynitride. The second through silicon via 208 penetrates the second silicon wafer 201 and the second bonding protection layer 206, and the second through silicon via 208 is filled with a second through silicon via filler. In one embodiment of the present invention, the second through silicon via filler can be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The second microchannel 209 is arranged in the second silicon wafer 201.

[0067] The first microfluidic channel 109 and the second microfluidic channel 209 are interconnected, and the inflow and outflow of the coolant are realized through the microfluidic channel inlet 111 and the microfluidic channel outlet 112. The coolant flows in the first microfluidic channel 109 and the second microfluidic channel 209 to quickly dissipate heat for the power supply structure. The microfluidic channel inlet 111 and the microfluidic channel outlet 112 are made at positions corresponding to the inlet and outlet of the first microfluidic channel 109. The microfluidic channel inlet 111 and the microfluidic channel outlet 112 can also be made at positions corresponding to the inlet and outlet of the second microfluidic channel 209 as needed.

[0068] In one embodiment of the present invention, the first TSV 108 includes a first bonding pad, and the second TSV 208 includes a second bonding pad. The gate driving layer 102 and the power transistor layer 202 are electrically connected through the first TSV 108 and the second TSV 208 .

[0069] Figure 2 FIG. 1 is a schematic diagram showing a power supply path of a three-dimensional vertical power supply structure of an integrated microfluidic channel according to an embodiment of the present invention. Figure 2 As shown, the SoC (System on Chips) includes a Driver Logic and Delay structure, where the Driver Logic structure is used to generate PWM / PFM drive waveforms, and the Delay structure is used to implement delay compensation to reduce output duty cycle distortion. Gate Drivers are composed of HSDriver and LS Driver. HS Driver stands for HighSide Driver, and LS Driver stands for Low Side Driver. The functions of HS Driver and LS Driver are to amplify the control signal generated by the Driver Logic and Delay structure in the SoC to drive the opening and closing of HSMOSFET and LSMOSFET and adjust the output. Power Transistors include multiple power transistors. HS MOSFET and LS MOSFET represent high-side and low-side power transistors, respectively. In most application scenarios, both are N-channel MOS tubes, and can also be GaN, P-channel MOS tubes, etc. During use, HS MOSFET requires a voltage boost circuit due to the floating driving signal, and the source is connected to VIN, where VIN represents the power input from the PCB to the package. The driving signal of LS MOSFET is a ground signal, so no voltage boost circuit is required in the driving circuit. Therefore, the drain of the MOSFET is grounded, L represents inductance, C represents capacitance, and Vout represents the power output of the three-dimensional vertical power supply structure.

[0070] The power required by SoC is divided into two parts. The first part is the power required by the Driver Logic and Delay structure in SoC, and the second part is the power required by the working condition of SOC. The power supply path of the three-dimensional vertical power supply structure with integrated microfluidic channel is: an external power supply such as PCB power supply directly supplies power to the Driver Logic and Delay structure in SoC to drive the Driver Logic and Delay structure; the Driver Logic and Delay structure drives the gate drive layer; the gate drive layer drives the power transistor layer; the power transistor layer outputs Vout, and Vout directly provides the power required for the working condition to SoC through the silicon via near the inductor.

[0071] It should be pointed out that Figure 2 The structure shown is a simplified form. In practical applications, related bootstrap capacitors, feedback resistors and other devices can be added according to actual needs. These devices can be integrated into the structure described in the present invention or provided in other ways such as external connection.

[0072] Figure 3 A schematic flow chart of a method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to an embodiment of the present invention is shown. Figure 4a-4k A schematic cross-sectional diagram of a process for forming a three-dimensional vertical power supply structure with integrated microfluidic channels according to an embodiment of the present invention is shown.

[0073] Combine the following Figure 3 and Figure 4a-4k The invention describes a method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels.

[0074] First, a gate driving layer 102 is fabricated on a first surface of a first silicon wafer 101. Figure 4a In one embodiment of the present invention, the gate driving layer 102 is manufactured through a front end of line (FEOL) process, which includes wafer cleaning, oxidation, doping, deposition, exposure, etching and other processes.

[0075] Next, a first redistribution layer 103 is formed on the first surface of the gate drive layer 102. Figure 4b As shown. The first redistribution layer 103 is manufactured using a Damascus process, and the first redistribution layer 103 includes a first interconnect pad. The first redistribution layer 103 may include a plurality of dielectric layers and a metal layer. In one embodiment of the present invention, the first redistribution layer 103 includes a first interconnect pad, and the first interconnect pad is electrically connected to the gate drive layer 102. The first interconnect pad is made of a metal layer, and the first interconnect pad may be made of a pure metal such as Au, Cu, Al, or an alloy thereof.

[0076] Next, a first temporary bonding layer 104 is formed on the first surface of the first redistribution layer 103, and a first carrier 105 is bonded to the first surface of the first temporary bonding layer 104 to form a first carrier structure, such as Figure 4c In one embodiment of the present invention, the first temporary bonding layer 104 may be silicon oxide or silicon nitride or silicon oxynitride or an organic bonding adhesive, and the organic bonding adhesive may be a bonding adhesive of TMAT, BSI, 3M and DuPont. In one embodiment of the present invention, the first carrier 105 may be glass or a silicon wafer or a metal plate.

[0077] Next, the first carrier structure is turned over to thin the second surface of the first silicon wafer 101. Figure 4d In one embodiment of the present invention, the thinning includes mechanical thinning and etching.

[0078] Next, a first bonding protection layer 106 is formed on the second surface of the first silicon wafer 101, and the first bonding protection layer 106 and the first silicon wafer 101 are etched to form a first through silicon via groove 107. Figure 4e In one embodiment of the present invention, the first bonding protection layer 106 may be an inorganic film layer, preferably silicon oxide or silicon nitride or silicon oxynitride.

[0079] Next, a first TSV filler is deposited in the first TSV recess 107 to form a first TSV 108. Figure 4f In one embodiment of the present invention, the first through silicon via filler may be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. In one embodiment of the present invention, the first through silicon via 108 includes a first bonding pad.

[0080] Next, the first bonding protection layer 106 and the first silicon wafer 101 are etched to form a first microchannel 109, thereby forming a wafer structure including a gate drive layer. Figure 4g shown.

[0081] Next, a wafer structure including a power transistor layer is formed, such as Figure 4hAs shown. The wafer structure including the power transistor layer includes a second silicon wafer 201, a power transistor layer 202, a second redistribution layer 203, a second temporary bonding layer 204, a second carrier 205, a second bonding protection layer 206, a second silicon through hole 208, and a second microchannel 209. The second redistribution layer 203 may include a plurality of dielectric layers and a metal layer. In one embodiment of the present invention, the second redistribution layer 203 includes a second interconnect pad, the second interconnect pad is electrically connected to the power transistor layer, the second interconnect pad is made of a metal layer, and the second interconnect pad may be made of pure metals such as Au, Cu, Al, or alloys thereof. In one embodiment of the present invention, the second temporary bonding layer 204 may be silicon oxide, silicon nitride, silicon oxynitride, or an organic bonding adhesive, and the organic bonding adhesive may be a bonding adhesive of TMAT, BSI, 3M, and DuPont. In one embodiment of the present invention, the second carrier 205 may be glass, a silicon wafer, or a metal plate. In one embodiment of the present invention, the second bonding protection layer 206 may be an inorganic film layer, preferably silicon oxide or silicon nitride or silicon oxynitride. In one embodiment of the present invention, a second through silicon via filler is deposited in the second through silicon via 208, and the second through silicon via filler may be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu. In one embodiment of the present invention, the second through silicon via 208 includes a second bonding pad.

[0082] Next, the wafer structure including the gate drive layer is bonded face-to-face with the wafer structure including the power transistor layer. Figure 4i The face-to-face bonding may be hybrid bonding, wherein the first bonding pad is bonded to the second bonding pad, and the first bonding protection layer is bonded to the second bonding protection layer. The first bonding pad is bonded to the second bonding pad to form an electrical connection, so that the first through silicon via is electrically connected to the second through silicon via.

[0083] Next, the first carrier sheet is removed, and holes are punched at the corresponding positions of the inlet and outlet of the first microfluidic channel to form a microfluidic channel inlet 111 and a microfluidic channel outlet 112, as shown in FIG. Figure 4j In one embodiment of the present invention, mechanical separation or thermal sliding or laser separation is used to remove the first carrier.

[0084] Finally, the second carrier is removed and cut to form a three-dimensional vertical power supply structure with integrated microfluidic channels, such as Figure 4k In one embodiment of the present invention, mechanical separation or thermal sliding or laser separation is used to remove the second carrier.

[0085] The three-dimensional vertical power supply structure with integrated microfluidics provided by the present invention separately manufactures a wafer structure including a gate drive layer and a wafer structure including a power transistor layer, and vertically interconnects and supplies power to the gate drive layer and the power transistor layer through silicon vias, which can significantly improve power supply efficiency, improve power supply transient response, and reduce losses in the power distribution network. Microfluidics are integrated in the power supply structure to quickly dissipate heat for the power supply structure and high-performance processors, and the heat dissipation performance is excellent.

[0086] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A three-dimensional vertical power supply structure with integrated microfluidic channel, characterized in that: include: The first silicon wafer; A gate driving layer, wherein the gate driving layer is arranged on the first surface of the first silicon wafer; A first redistribution layer, wherein the first redistribution layer is arranged on a first surface of the gate driving layer; A first bonding protection layer, wherein the first bonding protection layer is arranged on the second surface of the first silicon wafer; a second silicon wafer; A power transistor layer, wherein the power transistor layer is arranged on the first surface of the second silicon wafer; a second redistribution layer, the second redistribution layer being arranged on a first surface of the power transistor layer; A second bonding protection layer, wherein the second bonding protection layer is arranged on the second surface of the second silicon wafer; a first microfluidic channel, wherein the first microfluidic channel is arranged in the first silicon wafer; a second microfluidic channel, wherein the second microfluidic channel is arranged in the second silicon wafer; The first microfluidic channel and the second microfluidic channel are interconnected, and the coolant flows in and out through the microfluidic channel inlet and the microfluidic channel outlet; A first through silicon via, wherein the first through silicon via passes through the first silicon wafer and the first bonding protection layer; A second through silicon via, wherein the second through silicon via passes through the second silicon wafer and the second bonding protection layer; The gate driving layer and the power transistor layer are electrically connected through the first through silicon via and the second through silicon via.

2. The three-dimensional vertical power supply structure with integrated microfluidic channel according to claim 1, characterized in that: The first redistribution layer comprises a first interconnect pad, and the first interconnect pad is electrically connected to the gate drive layer; and / or The second redistribution layer includes a second interconnection pad electrically connected to the power transistor layer.

3. The three-dimensional vertical power supply structure with integrated microfluidic channel according to claim 1, characterized in that: The power supply path of the three-dimensional vertical power supply structure with integrated microfluidic channel is: The gate driving layer drives the power transistor layer, and the power transistor layer supplies power to the chip.

4. A method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels, characterized in that: The steps include: Manufacturing a gate driving layer on a first surface of a first silicon wafer; On the first surface of the gate driving layer, a first redistribution layer is formed; On the first surface of the first redistribution layer, a first temporary bonding layer is manufactured, and a first carrier is bonded to the first surface of the first temporary bonding layer to form a first carrier structure; Turning over the first carrier structure to thin the second surface of the first silicon wafer; Forming a first bonding protection layer on the second surface of the first silicon wafer, and etching the first bonding protection layer and the first silicon wafer to form a first through silicon via groove; Depositing a first through silicon via filler in the first through silicon via groove to form a first through silicon via; Etching the first bonding protection layer and the first silicon wafer to form a first microchannel and form a wafer structure including a gate driving layer; Forming a wafer structure including a power transistor layer, wherein the wafer structure including the power transistor layer includes a second silicon wafer, a power transistor layer, a second redistribution layer, a second temporary bonding layer, a second carrier, a second bonding protection layer, a second through silicon via, and a second microchannel; Bonding the wafer structure including the gate drive layer and the wafer structure including the power transistor layer face to face; Removing the first carrier sheet, and punching holes at corresponding positions of the inlet and outlet of the first microfluidic channel to form a microfluidic channel inlet and a microfluidic channel outlet; The second carrier sheet is removed and cut to form a three-dimensional vertical power supply structure with integrated microfluidic channels.

5. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4, characterized in that: The first redistribution layer is manufactured using a Damascene process, wherein the first redistribution layer includes a first interconnection pad; and / or The second redistribution layer is manufactured by using a damascene process, and the second redistribution layer includes a second interconnection pad.

6. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4, characterized in that: The first temporary bonding layer is silicon oxide or silicon nitride or silicon oxynitride or organic bonding glue; and / or The second temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride or organic bonding glue.

7. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4, characterized in that: The first bonding protection layer is silicon oxide or silicon nitride or silicon oxynitride; and / or The second bonding protection layer is silicon oxide, silicon nitride, or silicon oxynitride.

8. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4, characterized in that: The first through silicon via comprises a first bonding pad; and / or The second through silicon via includes a second bonding pad.

9. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4 or 8, characterized in that: The face-to-face bonding is a hybrid bonding, wherein the first bonding pad is bonded to the second bonding pad, and the first bonding protection layer is bonded to the second bonding protection layer.

10. The method for manufacturing a three-dimensional vertical power supply structure with integrated microfluidic channels according to claim 4, characterized in that: Removing the first carrier using mechanical separation or thermal sliding or laser separation; and / or The second carrier is removed using mechanical separation or thermal sliding or laser separation.

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