Silicon carbide power semiconductor device and method for forming the same

Abstract

The present invention provides a silicon carbide power semiconductor device and a method for forming the same. The silicon carbide power semiconductor device comprises at least two source and drain regions formed in a device layer, a contact region is formed in the device layer between two adjacent source and drain regions, and a side wall of the source and drain region close to the contact region is in a step shape, a dielectric layer is formed on the device layer, and the dielectric layer has an opening; a first ohmic contact layer, the first ohmic contact layer covers a part of the contact region at the bottom of the opening; a second ohmic contact layer, the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the side wall of the source and drain region close to the contact region and a part of the top surface. Since a side wall of the source and drain region close to the contact region is in a step shape, and a contact hole is provided between the bottom of the second sidewall layer in the opening and the top surface of the source and drain region, the contact area between the second ohmic contact layer and the source and drain region is increased, thereby reducing the contact resistance between the second ohmic contact layer and the source and drain region.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a silicon carbide power semiconductor device and a method for forming the same. Background Art

[0002] In silicon carbide power semiconductor devices, since SiC (silicon carbide) has a high critical electric field, high thermal conductivity and high saturation drift rate, silicon carbide power devices are mainly used in high-power electronic devices in power equipment power conversion and control circuits. As the design size of silicon carbide devices gradually decreases, the manufacturing cost continues to rise. In the formation process of traditional silicon carbide devices, the size of the opening on the source and drain contact area is also constantly decreasing. The current opening etching process and the reduction of the contact resistance of the contact layer in the opening are both very difficult. If the contact resistance between the contact layer and the source and drain area is reduced by increasing the size of the opening, although the purpose of reducing the contact resistance can be achieved, it will inevitably increase the input capacitance, which will have an adverse effect on the switching speed. If the method of increasing the injection concentration is adopted, the effect is difficult to achieve the expected effect. Summary of the invention

[0003] The object of the present invention is to provide a silicon carbide power semiconductor device and a method for forming the same, so as to reduce the contact resistance between the contact layer and the source and drain regions.

[0004] To achieve the above-mentioned object, the present invention provides a silicon carbide power semiconductor device, comprising: a semiconductor substrate, a device layer formed on the semiconductor substrate, at least two source and drain regions formed in the device layer, a contact region formed in the device layer between two adjacent source and drain regions, the top surface of the contact region is lower than the top surface of the source and drain region, and a side wall of the source and drain region close to the contact region is in a step shape, a dielectric layer is formed on the device layer, the dielectric layer has an opening, the opening exposes the contact region and a portion of the side wall and a portion of the top surface of the source and drain region close to the contact region; a first A sidewall layer, wherein the first sidewall layer covers the sidewall of the opening; a second sidewall layer, wherein the second sidewall layer covers a portion of the first sidewall layer, and a contact hole is provided between the bottom of the second sidewall layer and the top surface of the source / drain region, wherein the contact hole is connected to the opening and exposes a portion of the top surface of the source / drain region; a first ohmic contact layer, wherein the first ohmic contact layer covers a portion of the contact region at the bottom of the opening; and a second ohmic contact layer, wherein the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the sidewall of the source / drain region close to the contact region, and the exposed top surface.

[0005] Optionally, the source / drain region includes a first part and a second part, the second part is located on the first part, the width of the second part is smaller than the width of the first part, and a side wall of the first part away from the contact region is aligned with a side wall of the second part away from the contact region, and a side of the second part close to the contact region exposes a portion of the top surface of the first part.

[0006] Optionally, the conductivity type of the source and drain regions is N-type; and the conductivity type of the contact region is P-type.

[0007] Optionally, a material of the first ohmic contact layer is different from a material of the second ohmic contact layer, wherein the material of the first ohmic contact layer is aluminum silicide, platinum silicide or cobalt silicide, and the material of the second ohmic contact layer is nickel silicide or titanium silicide.

[0008] Based on the same inventive concept, the present invention also provides a method for forming a silicon carbide power semiconductor device, comprising: providing a semiconductor substrate, a device layer formed on the semiconductor substrate, at least two source and drain regions formed in the device layer, a contact region formed in the device layer between two adjacent source and drain regions, the top surface of the contact region being lower than the top surface of the source and drain region, a dielectric layer formed on the device layer, the dielectric layer having an opening, the opening exposing the contact region and a portion of the sidewalls and top surface of the source and drain region close to the contact region; sequentially forming a second spacer layer and a first spacer material layer, the first spacer material layer covering the exposed sidewalls and top surface of the source and drain region, the second spacer layer covering the top surface of the source and drain region The sidewall of the sidewall material layer is formed; a first ohmic contact layer is formed, wherein the first ohmic contact layer covers a portion of the contact area at the bottom of the opening; the first sidewall material layer is etched to form a first sidewall layer, and a contact hole is formed between the bottom of the second sidewall layer and the top surface of the source and drain area, wherein the contact hole is connected to the opening and exposes a portion of the top surface of the source and drain area, wherein the first sidewall layer covers a portion of the dielectric layer on the sidewall of the opening; the exposed source and drain area is etched to make the sidewall of the source and drain area close to the contact area in a step shape; a second ohmic contact layer is formed, wherein the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the sidewall of the source and drain area close to the contact area, and the exposed top surface.

[0009] Optionally, the source / drain region includes a first part and a second part, the second part is located on the first part, the width of the second part is smaller than the width of the first part, and a side wall of the first part away from the contact region is aligned with a side wall of the second part away from the contact region, and a side of the second part close to the contact region exposes a portion of the top surface of the first part.

[0010] Optionally, a wet etching process is used to etch the exposed top surface and sidewalls of the source and drain regions to form the contact holes.

[0011] Optionally, the conductivity type of the source and drain regions is N-type; and the conductivity type of the contact region is P-type.

[0012] Optionally, the method for forming the first ohmic contact layer includes: forming a first metal layer, the first metal layer covering the side walls of the opening, the contact area and the top surface of the dielectric layer; performing a first annealing process to allow the first metal layer to react with silicon in the contact area to form the first ohmic contact layer; and, using a wet etching process to remove the top surface of the dielectric layer and the first metal layer on the side walls of the opening.

[0013] Optionally, the method for forming the second ohmic contact layer includes: forming a second metal layer, the second metal layer filling the contact hole and covering the first ohmic contact layer and the exposed side walls of the source and drain regions, and the second metal layer extending to cover the second sidewall layer and the top surface of the dielectric layer; performing an annealing process to allow the second metal layer to react with silicon in the contact hole to form the second ohmic contact layer; and using a wet etching process to remove the second metal layer from the top surface of the dielectric layer and the sidewalls of the second sidewall layer.

[0014] In the silicon carbide power semiconductor device and the method for forming the same provided by the present invention, the silicon carbide power semiconductor device comprises at least two source and drain regions formed in a device layer, a contact region is formed in the device layer between two adjacent source and drain regions, and a side wall of the source and drain region close to the contact region is in a step shape, a dielectric layer is formed on the device layer, and an opening is provided in the dielectric layer, and the opening exposes the contact region and part of the side wall and part of the top surface of the source and drain region close to the contact region; a first ohmic contact layer, the first ohmic contact layer covers part of the contact region at the bottom of the opening; a second ohmic contact layer, the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the side wall of the source and drain region close to the contact region and the exposed top surface. Since the side wall of the source and drain region close to the contact region is in a step shape, and at the same time, there is a contact hole between the bottom of the second sidewall layer in the opening and the top surface of the source and drain region, the second ohmic contact layer fills the contact hole and covers the side wall of the source and drain region close to the contact region, thereby increasing the contact area between the second ohmic contact layer and the source and drain region, thereby reducing the contact resistance between the second ohmic contact layer and the source and drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of a silicon carbide power semiconductor device provided by an embodiment of the present invention.

[0016] Figure 2It is a schematic flow chart of a method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0017] Figure 3 It is a schematic diagram of the structure after an opening is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0018] Figure 4 It is a schematic diagram of the structure after the second spacer material layer is formed in the method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention.

[0019] Figure 5 It is a schematic diagram of the structure after the second sidewall layer is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0020] Figure 6 It is a schematic diagram of the structure after the first metal layer is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0021] Figure 7 It is a schematic diagram of the structure after the first ohmic contact layer is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0022] Figure 8 It is a schematic diagram of the structure after forming contact holes in the method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention.

[0023] Fig. 9 It is a schematic diagram of the structure after the second metal layer is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0024] Fig.10 It is a schematic diagram of the structure after the second ohmic contact layer is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention.

[0025] Among them, the figure marks are explained as follows: 101-semiconductor substrate; 102-device layer; 103-body region; 104-source and drain region; 104a-first part; 104b-second part; 105-contact region; 106-gate oxide layer; 107-gate; 110-dielectric layer; 120-opening; 121-contact hole; 130-initial first sidewall material layer; 131-first sidewall material layer; 131a-first sidewall layer; 140-second sidewall material layer; 140a-second sidewall layer; 150-first metal layer; 151-first ohmic contact layer; 160-second metal layer; 161-second ohmic contact layer; 170-conductive layer. DETAILED DESCRIPTION

[0026] The silicon carbide power semiconductor device and its formation method proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] Figure 1 Schematic diagram of the structure of a silicon carbide power semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the silicon carbide power semiconductor device includes a semiconductor substrate 101, a device layer 102, a dielectric layer 110, a first spacer layer 131a, a second spacer layer 140a, a first ohmic contact layer 151, and a second ohmic contact layer 161. Specifically, the material of the semiconductor substrate 101 is silicon carbide, and the device layer 102 is located on the semiconductor substrate 101, that is, the device layer 102 is formed on the semiconductor substrate 101. The material of the device layer 102 can be silicon carbide, that is, the material of the device layer 102 can be the same as that of the semiconductor substrate 101.

[0028] like Figure 1 As shown, at least two source and drain regions 104 are formed in the device layer 102, and a contact region 105 is formed in the device layer 102 between two adjacent source and drain regions 104. The top surface of the contact region 105 is lower than the top surface of the source and drain regions 104. The conductivity type of the source and drain regions 104 can be N-type, and the conductivity type of the contact region 105 can be P-type.

[0029] In this embodiment, a side wall of the source / drain region 104 close to the contact region 105 is in a step shape. Specifically, the source / drain region 104 includes a first portion 104a and a second portion 104b. The second portion 104b is located on the first portion 104a. The width of the second portion 104b is smaller than the width of the first portion 104a. A side wall (or one side edge) of the first portion 104a away from the contact region 105 is aligned with a side wall (or one side edge) of the second portion 104b away from the contact region 105. A side of the second portion 104b close to the contact region 105 (i.e., the other side wall or the other side edge of the second portion 104b) exposes a portion of the top surface of the first portion 104a, so that a side wall of the source / drain region 104 close to the contact region 105 is in a step shape. In this way, the contact area between the second ohmic contact layer 161 and the source / drain region 104 can be increased.

[0030] Furthermore, a body region 103 is formed in the device layer 102, and the conductivity type of the body region 103 may be P type. The source and drain regions 104 are formed in the body region 103, and each body region 103 has two source and drain regions 104 arranged at intervals, and two adjacent source and drain regions 104 refer to two source and drain regions 104 located in the same body region 103. The top surface of the body region 103 is flush with the top surface of the source and drain regions 104, and the injection depth of the source and drain regions 104 is less than the injection depth of the body region 103, and the injection depth of the contact region 105 is greater than the depth of the body region 103, that is, the contact region 105 penetrates the region between the two adjacent source and drain regions 104 in the body region 103 in the depth direction, and extends to the device layer 102 at the bottom of the body region 103. That is to say, the contact region 105 extends from the top surface of the body region 103 to the device layer 102 at the bottom of the body region 103 . In other words, the contact region 105 partially overlaps with the body region 103 between two adjacent source and drain regions 104 , and the injection depth of the contact region 105 is greater than the injection depth of the body region 103 .

[0031] Preferably, the doping concentration of the contact region 105 is greater than the doping concentration of the body region 103, and the doping concentration in the contact region 105 is greater than the ion doping concentration in the device. The ions in the contact region 105 may be aluminum ions, for example.

[0032] In a further embodiment, a gate oxide layer 106 and a gate 107 located on the gate oxide layer 106 are also formed on the semiconductor substrate 101. The material of the gate oxide layer 106 may be, for example, silicon oxide, and the material of the gate 107 may be polysilicon. The body region 103 is located in the semiconductor substrate 101 on both sides of the gate 107.

[0033] Continue to refer Figure 1 As shown, a dielectric layer 110 is formed on the device layer 102 , and an opening 120 is formed in the dielectric layer 110 on the source and drain region 104 , and the opening 120 exposes the contact region 105 and part of the sidewall and part of the top surface of the source and drain region 104 . The dielectric layer 110 covers the gate 107 .

[0034] The first spacer layer 131a covers a portion of the dielectric layer 110 on the sidewall of the opening 120, and the material of the first spacer layer 131a may be silicon oxide. The second spacer layer 140a covers a portion of the first spacer layer 131a, and a contact hole 121 is provided between the bottom of the second spacer layer 140a and the top surface of the source and drain region 104, that is, the contact hole 121 exposes a portion of the top surface of the source and drain region 104, and the contact hole 121 is connected to the opening 120. The material of the second spacer layer 140a may be silicon nitride.

[0035] In this embodiment, the first ohmic contact layer 151 covers a portion of the contact area 105 at the bottom of the opening 120, that is, the first ohmic contact layer 151 is formed in the opening 120, and the first ohmic contact layer 151 can cover the middle area of ​​the contact area 105, thereby exposing the edge area of ​​the contact area 105, that is, both sides of the first ohmic contact layer 151 expose a portion of the top surface of the contact area 105, which is beneficial to increase the contact area between the second ohmic contact layer 161 and the contact area 105.

[0036] In this embodiment, the material of the first ohmic contact layer 151 is aluminum silicide, platinum silicide or cobalt silicide. In this way, the first ohmic contact layer 151 can form a better ohmic contact interface when contacting the P-type contact area 105, thereby making the first ohmic contact layer 151 and the contact area 105 have better ohmic contact performance, thereby reducing the contact resistance between the first ohmic contact layer 151 and the contact area 105.

[0037] like Figure 1 As shown, the second ohmic contact layer 161 fills the contact hole 121 and covers the first ohmic contact layer 151, the side wall of the source and drain region 104 close to the contact region 105 and the exposed top surface, that is, the second ohmic contact layer 161 covers the side wall of the source and drain region 104 in a stepped shape, and the second ohmic contact layer 161 also covers a part of the top surface of the source and drain region 104 (the part located at the bottom of the second sidewall). Since the side wall of the source and drain region 104 close to the contact region 105 is in a stepped shape, and there is a contact hole 121 between the bottom of the second sidewall layer 140a in the opening and the top surface of the source and drain region 104, the second ohmic contact layer 161 fills the contact hole 121 and covers the side wall of the source and drain region 104 close to the contact region 105, thereby increasing the contact area between the second ohmic contact layer 161 and the source and drain region 104, so that the contact resistance between the second ohmic contact layer 161 and the source and drain region 104 can be reduced.

[0038] Preferably, the material of the second ohmic contact layer 161 is nickel silicide or titanium silicide. Thus, when the second ohmic contact layer 161 contacts the N-type source and drain regions 104, a good ohmic contact interface can be formed, thereby making the second ohmic contact layer 161 and the source and drain regions 104 have good ohmic contact performance, thereby reducing the contact resistance between the second ohmic contact layer 161 and the source and drain regions 104.

[0039] In this embodiment, the silicon carbide power semiconductor device may be a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET).

[0040] Figure 2 FIG. 1 is a flow chart of a method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention. Figure 2 As shown, the present embodiment further provides a method for forming a silicon carbide power semiconductor device, comprising: step S1: providing a semiconductor substrate, a device layer is formed on the semiconductor substrate, at least two source and drain regions are formed in the device layer, a contact region is formed in the device layer between two adjacent source and drain regions, the top surface of the contact region is lower than the top surface of the source and drain region, a dielectric layer is formed on the device layer, the dielectric layer has an opening, the opening exposes the contact region and part of the sidewall and top surface of the source and drain region close to the contact region; step S2: forming a second spacer layer and a first spacer material layer in sequence, the first spacer material layer covers the exposed sidewall and top surface of the source and drain region, the second spacer layer covers the sidewall of the first spacer material layer on the top surface of the source and drain region wall; step S3: forming a first ohmic contact layer, wherein the first ohmic contact layer covers a portion of the contact area at the bottom of the opening; step S4: etching the first sidewall material layer to form a first sidewall layer, and forming a contact hole between the bottom of the second sidewall layer and the top surface of the source and drain area, wherein the contact hole is connected to the opening and exposes a portion of the top surface of the source and drain area, wherein the first sidewall layer covers a portion of the dielectric layer on the sidewall of the opening; step S5: etching the exposed source and drain area so that the sidewall of the source and drain area close to the contact area is stepped; step S6: forming a second ohmic contact layer, wherein the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the sidewall of the source and drain area close to the contact area, and the exposed top surface.

[0041] The following will be combined with the attached Figure 3~Figure 10 The method for forming the silicon carbide power semiconductor device provided in this embodiment is described in more detail.

[0042] Figure 3 FIG. 1 is a schematic diagram of a structure after an opening is formed in the method for forming a silicon carbide power semiconductor device provided in an embodiment of the present invention. Figure 3 As shown, step S1 is performed to provide a semiconductor substrate 101, on which a device layer 102 is formed, in which source and drain regions 104 are formed, in which a contact region 105 is formed between two adjacent source and drain regions 104, in which a top surface of the contact region 105 is lower than a top surface of the source and drain region 104, and on which a dielectric layer 110 is formed, in which an opening 120 is provided, and in which the opening 120 exposes part of the sidewalls and top surfaces of the contact region 105 and part of the source and drain regions 104. Specifically, the material of the semiconductor substrate 101 and the material of the device layer 102 are both silicon carbide.

[0043] Further, such as Figure 3 As shown, before forming the source and drain regions 104, a body region 103 is first formed in the device layer 102, and the conductivity type of the body region 103 may be P type. The body region 103 may be formed by an ion implantation process.

[0044] Then, source and drain regions 104 are formed in the body region 103, and each body region 103 has two source and drain regions 104 spaced apart from each other. The top surface of the body region 103 is flush with the top surface of the source and drain regions 104, and the implantation depth of the source and drain regions 104 is less than the implantation depth of the body region 103.

[0045] Afterwards, a contact region 105 is formed in the device layer 102 between two adjacent source and drain regions 104 by an ion implantation process. The device layer 102 between two adjacent source and drain regions 104 refers to the body region 103 area between two source and drain regions 104 located in the same body region 103 .

[0046] In this embodiment, the implantation depth of the contact region 105 is greater than the depth of the body region 103, that is, the contact region 105 penetrates the region between two adjacent source and drain regions 104 in the body region 103 in the depth direction, and extends to the device layer 102 at the bottom of the body region 103, that is, the contact region 105 extends from the top surface of the body region 103 to the device layer 102 at the bottom of the body region 103, in other words, the contact region 105 partially overlaps with the body region 103 between the two adjacent source and drain regions 104, and the implantation depth of the contact region 105 is greater than the implantation depth of the body region 103. The ions in the contact region 105 may be aluminum ions.

[0047] Afterwards, if Figure 3 As shown, a gate oxide layer 106 and a gate 107 are sequentially formed on the semiconductor substrate 101, the gate 107 is formed on the semiconductor substrate 101 between two adjacent contact regions 105, the gate oxide layer 106 is located between the gate 107 and the semiconductor substrate 101, the material of the gate oxide layer can be silicon oxide, and the material of the gate 107 can be polysilicon. The source and drain regions 104 on both sides of the gate 107 are the source and the drain, respectively.

[0048] Next, continue to refer to Figure 3As shown, a dielectric layer 110 is formed on the device layer 102, the dielectric layer covers the gate 107 and a portion of the top surface of the source and drain region 104, and the dielectric layer 110 is etched to form an opening 120, the opening 120 exposes the contact region 105 and a portion of the sidewall and top surface of the source and drain region 104 close to the contact region 105. Further, after the opening 120 is formed, the opening 120 can be etched by a wet etching process to increase the width of the opening 120.

[0049] It should be noted that, since the top surface of the source / drain region 104 and the top surface of the contact region 105 are at different heights, the sidewall of the opening 120 is in a step shape.

[0050] Figure 5 FIG. 1 is a schematic diagram of the structure after the second sidewall layer is formed in the method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention. Figure 5 As shown, step S2 is performed to sequentially form a second spacer layer 140a and a first spacer material layer 131, wherein the first spacer material layer 131 covers the exposed sidewalls and top surfaces of the source and drain regions 104, and the second spacer layer 140a is located on the first spacer material layer 131 on the top surface of the source and drain regions 104, and covers part of the sidewalls of the first spacer material layer 131.

[0051] Specifically, the method of sequentially forming the second spacer layer 140a and the first spacer material layer 131 includes: first, Figure 4 As shown, the initial first spacer material layer 130 and the second spacer material layer 140 are sequentially formed by chemical vapor deposition process, the initial first spacer material layer 130 covers the sidewall and bottom of the opening 120, and extends to cover the top surface of the dielectric layer 110, and the second spacer material layer 140 covers the initial first spacer material layer 130. It should be noted that, since the top surface of the contact area 105 is lower than the top surface of the source and drain area 104, there is a height difference between the source and drain area 104 and the contact area 105, that is, there is a step between the source and drain area 104 and the contact area 105, so after the initial first spacer material layer 130 is formed, the sidewall of the initial first spacer material layer 130 has a step. Wherein, the material of the initial first spacer material layer 130 can be silicon oxide, and the material of the second spacer material layer 140 can be silicon nitride.

[0052] Then, if Figure 5As shown, the second spacer material layer 140 and the initial first spacer material layer 130 are etched in sequence to remove the second spacer material layer 140 at the bottom of the opening 120 and the side walls of the source and drain regions 104 in the opening 120, and to remove the second spacer material layer 140 at the top surface of the dielectric layer 110, and retain the second spacer material layer 140 at the side walls of the dielectric layer 110 in the opening 120 to form a second spacer layer 140a, and to remove the initial first spacer material layer 130 at the bottom of the opening 120 and the top surface of the dielectric layer 110 to form a first spacer material layer 131, that is, the first spacer material layer 131 covers the side walls of the opening 120, that is, the first spacer material layer 131 covers the dielectric layer 110 at the side walls of the opening 120 and the exposed side walls and top surface of the source and drain regions 104. The second spacer layer 140a covers the side wall of the first spacer material layer 131 on the top surface of the source / drain region 104 , that is, the second spacer layer 140a is located on the first spacer layer 131a on the top surface of the source / drain region 104 (that is, the top surface at the step of the first spacer layer 131a ) and covers part of the side wall of the first spacer material layer 131 .

[0053] Figure 7 FIG. 1 is a schematic diagram of a structure after forming a first ohmic contact layer in a method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention. Figure 7 As shown, step S3 is performed to form a first ohmic contact layer 151, wherein the first ohmic contact layer 151 covers a portion of the contact area 105 at the bottom of the opening 120, that is, the first ohmic contact layer 151 is electrically connected to the contact area 105. The material of the first ohmic contact layer 151 is aluminum silicide, platinum silicide or cobalt silicide, so that when the first ohmic contact layer 151 contacts the P-type contact area 105, a good ohmic contact interface can be formed, thereby making the first ohmic contact layer 151 and the contact area 105 have good ohmic contact performance, thereby reducing the contact resistance between the first ohmic contact layer 151 and the contact area 105.

[0054] In this embodiment, the method for forming the first ohmic contact layer 151 includes: Figure 6 As shown, a first metal layer 150 is formed, and the first metal layer 150 covers the sidewalls of the opening 120, the contact area 105 and the top surface of the dielectric layer 110; Figure 7As shown, a first annealing process is performed to allow the first metal layer 150 to react with the silicon in the contact area 105 to form the first ohmic contact layer 151, wherein the temperature of the annealing process can be 950°C~1050°C; and a wet etching process is used to remove the first metal layer 150 on the top surface of the dielectric layer 110 and the side wall of the opening 120, that is, the first metal layer 150 that has not reacted with silicon in the annealing process is removed, wherein the etching solution used in the wet etching process is SPM solution (a mixed solution of sulfuric acid and hydrogen peroxide) or SC1 (a mixed solution of ammonia water, hydrogen peroxide and water).

[0055] Figure 8 FIG. 1 is a schematic diagram of the structure after forming contact holes in the method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention. Figure 8 As shown, step S4 is performed to etch the first spacer material layer 131 to form a first spacer layer 131a, and to form a contact hole 121 between the bottom of the second spacer layer 140a and the top surface of the source and drain region 104, wherein the contact hole 121 is connected to the opening 120, wherein the first spacer layer 131a covers the dielectric layer 110 on the side wall of the opening 120.

[0056] Preferably, the first spacer material layer 131 is etched by a wet etching process, thereby removing the first spacer material layer 131 between the bottom of the second spacer layer 140a and the top surface of the source and drain region 104, and removing the first spacer material layer 131 on the sidewall of the source and drain region 104, that is, removing the first spacer material layer 131 exposed in the opening 120, thereby forming a first spacer layer 131a. The etching solution used in the wet etching process includes hydrofluoric acid.

[0057] Next, execute step S5, such as Figure 8 As shown, the exposed source and drain regions 104 are etched so that the sidewalls of the source and drain regions 104 close to the contact regions 105 are stepped. A wet etching process may be used to etch the top surface and sidewalls of the exposed source and drain regions 104. The wet etching process may use a mixture of nitric acid and hydrofluoric acid as the etching medium.

[0058] like Figure 8As shown, after the exposed source and drain regions 104 are etched, the sidewalls of the remaining source and drain regions 104 close to the contact region 105 are in a step shape, that is, the remaining source and drain regions 104 include a first portion 104a and a second portion 104b, the second portion 104b is located on the first portion 104a, the width of the second portion 104b is smaller than the width of the first portion 104a, and a side wall (or a side edge) of the first portion 104a away from the contact region 105 is aligned with a side wall (or a side edge) of the second portion 104b away from the contact region 105, and a side wall of the second portion 104b close to the contact region 105 (that is, the other side wall or the other side edge of the second portion 104b) exposes a portion of the top surface of the first portion 104a, so that the side of the source and drain region 104 close to the contact region 105 is in a step shape, so that the contact area between the second ohmic contact layer 161 and the source and drain region 104 can be increased.

[0059] Fig.10 FIG. 1 is a schematic diagram of a structure after forming a second ohmic contact layer in a method for forming a silicon carbide power semiconductor device provided by an embodiment of the present invention. Fig.10 As shown, step S6 is performed to form a second ohmic contact layer 161, wherein the second ohmic contact layer 161 fills the contact hole 121 and covers the first ohmic contact layer 151, the sidewall of the source / drain region 104 close to the contact region 105, and the exposed top surface, that is, the second ohmic contact layer 161 is electrically connected to the source / drain region 104. Specifically, the method for forming the second ohmic contact layer 161 includes: Fig.10 As shown, a second metal layer 160 is formed. The material of the second metal layer 160 can be nickel or titanium. The second metal layer 160 fills the contact hole 121 and covers the first ohmic contact layer 151 and the exposed sidewalls of the source and drain regions 104. The second metal layer 160 extends to cover the second spacer layer 140a and the top surface of the dielectric layer 110. Furthermore, the second metal layer 160 also covers the top surface of the exposed contact region 105. Fig.10 As shown, an annealing process is performed to allow the second metal layer 160 to react with the silicon in the contact hole 121 to form the second ohmic contact layer 161. In addition, the second metal layer 160 also reacts with the surface of the first ohmic contact layer 151 and the contact layer 105 covered by it, so that the second ohmic contact layer 161 extends to cover the first ohmic contact layer 151.

[0060] The temperature of the annealing process can be 950°C~1050°C; and a wet etching process is used to remove the top surface of the dielectric layer 110 and the second metal layer 160 on the side wall of the second sidewall layer 140a, that is, to remove the unreacted second metal layer 160, wherein the etching solution used in the wet etching process is SPM solution (a mixed solution of sulfuric acid and hydrogen peroxide) or SC1 solution (a mixed solution of ammonia water, hydrogen peroxide and water). Since one side wall of the source / drain region 104 close to the contact region 105 is in a step shape, the contact area between the source / drain region 104 and the second ohmic contact layer 161 can be increased. Meanwhile, a contact hole 121 is provided between the bottom of the second sidewall layer 140a in the opening 120 and the top surface of the source / drain region 104. The contact hole 121 exposes a portion of the top surface of the source / drain region 104. The second ohmic contact layer 161 fills the contact hole 121, i.e., the second ohmic contact layer 161 covers the exposed top surface and side wall of the source / drain region 104. Therefore, the contact area between the second ohmic contact layer 161 and the source / drain region 104 is further increased, thereby reducing the contact resistance between the second ohmic contact layer 161 and the source / drain region 104.

[0061] Afterwards, if Figure 1 As shown, a conductive layer 170 is filled in the opening 120 , and the conductive layer 170 fills up the opening 120 and covers the top surface of the dielectric layer 110 , wherein the conductive layer 170 may be made of aluminum.

[0062] In summary, in the silicon carbide power semiconductor device and the formation method thereof provided in the embodiment of the present invention, the silicon carbide power semiconductor device includes at least two source and drain regions formed in the device layer, a contact region is formed in the device layer between two adjacent source and drain regions, and a side wall of the source and drain region close to the contact region is in a step shape; a dielectric layer is formed on the device layer, and an opening is provided in the dielectric layer, wherein the opening exposes the contact region and a portion of the side wall and a portion of the top surface of the source and drain region close to the contact region; a first ohmic contact layer, wherein the first ohmic contact layer covers a portion of the contact region at the bottom of the opening, and a contact hole is formed between the first ohmic contact layer and the top surface of the source and drain region; and a second ohmic contact layer, wherein the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the side wall of the source and drain region close to the contact region, and the exposed top surface. Since a side wall of the source / drain region close to the contact region is in a step shape, and there is a contact hole between the bottom of the second side wall layer in the opening and the top surface of the source / drain region, the second ohmic contact layer fills the contact hole and covers a side wall of the source / drain region close to the contact region, thereby increasing the contact area between the second ohmic contact layer and the source / drain region, thereby reducing the contact resistance between the second ohmic contact layer and the source / drain region.

[0063] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A silicon carbide power semiconductor device, characterized in that: include: A semiconductor substrate, wherein a device layer is formed on the semiconductor substrate, wherein a body region and at least two source and drain regions are formed in the device layer, wherein the source and drain regions are formed in the body region, wherein a contact region is formed in the device layer between two adjacent source and drain regions in the same body region, wherein a top surface of the contact region is lower than a top surface of the source and drain region, and a side wall of the source and drain region close to the contact region is in a step shape, wherein a dielectric layer is formed on the device layer, wherein an opening is provided in the dielectric layer, wherein the opening exposes the contact region and a portion of the side wall and a portion of the top surface of the source and drain region close to the contact region; A first spacer layer, wherein the first spacer layer covers a side wall of the opening; a second spacer layer, wherein the second spacer layer covers a portion of the first spacer layer, and a contact hole is provided between a bottom of the second spacer layer and a top surface of the source / drain region, wherein the contact hole is connected to the opening and exposes a portion of the top surface of the source / drain region; A first ohmic contact layer, wherein the first ohmic contact layer covers a portion of the contact area at the bottom of the opening; A second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the sidewalls of the source and drain regions close to the contact regions, and the exposed top surface.

2. The silicon carbide power semiconductor device according to claim 1, characterized in that: The source / drain region includes a first portion and a second portion, wherein the second portion is located on the first portion, a width of the second portion is smaller than a width of the first portion, a side wall of the first portion away from the contact region is aligned with a side wall of the second portion away from the contact region, and a side of the second portion close to the contact region exposes a portion of the top surface of the first portion.

3. The silicon carbide power semiconductor device according to claim 1, characterized in that: The conductivity type of the source and drain regions is N-type; the conductivity type of the contact region is P-type.

4. The silicon carbide power semiconductor device according to claim 1, characterized in that: The material of the first ohmic contact layer is different from that of the second ohmic contact layer, wherein the material of the first ohmic contact layer is aluminum silicide, platinum silicide or cobalt silicide, and the material of the second ohmic contact layer is nickel silicide or titanium silicide.

5. A method for forming a silicon carbide power semiconductor device, characterized in that: include: A semiconductor substrate is provided, wherein a device layer is formed on the semiconductor substrate, wherein a body region and at least two source and drain regions are formed in the device layer, wherein the source and drain regions are formed in the body region, wherein a contact region is formed in the device layer between two adjacent source and drain regions in the same body region, wherein a top surface of the contact region is lower than a top surface of the source and drain region, and wherein a dielectric layer is formed on the device layer, wherein the dielectric layer has an opening, wherein the opening exposes the contact region and a portion of sidewalls and a top surface of the source and drain regions close to the contact region; forming a second spacer layer and a first spacer material layer in sequence, wherein the first spacer material layer covers the exposed sidewalls and top surface of the source / drain region, and the second spacer layer covers the sidewalls of the first spacer material layer on the top surface of the source / drain region; forming a first ohmic contact layer, wherein the first ohmic contact layer covers a portion of the contact area at the bottom of the opening; Etching the first spacer material layer to form a first spacer layer, and forming a contact hole between the bottom of the second spacer layer and the top surface of the source and drain region, wherein the contact hole is connected to the opening and exposes a portion of the top surface of the source and drain region, wherein the first spacer layer covers a portion of the dielectric layer on the sidewall of the opening; Etching the exposed source and drain regions so that the sidewalls of the source and drain regions close to the contact regions are in a step shape; A second ohmic contact layer is formed, wherein the second ohmic contact layer fills the contact hole and covers the first ohmic contact layer, the sidewalls of the source and drain regions close to the contact regions, and the exposed top surface.

6. The method for forming a silicon carbide power semiconductor device according to claim 5, characterized in that: The source / drain region includes a first portion and a second portion, wherein the second portion is located on the first portion, a width of the second portion is smaller than a width of the first portion, a side wall of the first portion away from the contact region is aligned with a side wall of the second portion away from the contact region, and a side of the second portion close to the contact region exposes a portion of the top surface of the first portion.

7. The method for forming a silicon carbide power semiconductor device according to claim 5, characterized in that: The exposed top surface and sidewalls of the source and drain regions are etched using a wet etching process to form the contact holes.

8. The method for forming a silicon carbide power semiconductor device according to claim 5, characterized in that: The conductivity type of the source and drain regions is N-type; the conductivity type of the contact region is P-type.

9. The method for forming a silicon carbide power semiconductor device according to claim 5, characterized in that: The method of forming the first ohmic contact layer includes: forming a first metal layer, wherein the first metal layer covers the sidewalls of the opening, the contact area, and the top surface of the dielectric layer; performing a first annealing process to react the first metal layer with silicon in the contact region to form the first ohmic contact layer; and, A wet etching process is used to remove the top surface of the dielectric layer and the first metal layer on the sidewall of the opening.

10. The method for forming a silicon carbide power semiconductor device according to claim 5, characterized in that: The method of forming the second ohmic contact layer includes: forming a second metal layer, wherein the second metal layer fills the contact hole and covers the first ohmic contact layer and the exposed sidewalls of the source and drain regions, and the second metal layer extends to cover the second spacer layer and the top surface of the dielectric layer; performing an annealing process to allow the second metal layer to react with silicon in the contact hole to form the second ohmic contact layer; and, A wet etching process is used to remove the top surface of the dielectric layer and the second metal layer on the sidewall of the second spacer layer.

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