Light emitting diodes and articles with improved leakage

Abstract

The present disclosure provides a light emitting diode and an article for improving leakage, belonging to the technical field of optoelectronic manufacturing. The light emitting diode comprises: an epitaxial layer and a transparent conductive layer, the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked, the second semiconductor layer has a first through hole exposing the first semiconductor layer, the transparent conductive layer is located on the surface of the second semiconductor layer away from the first semiconductor layer, and the transparent conductive layer has a second through hole exposing the first through hole; the shortest distance between the sidewall of the transparent conductive layer and the sidewall of the epitaxial layer is greater than the shortest distance between the sidewall of the second through hole and the sidewall of the first through hole. The embodiment of the present disclosure can improve the problem of mask deviation during etching and cutting, which leads to etching deviation, and prevent the light emitting diode from easily leaking and short-circuiting.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode and article of improved leakage current. Background Technology

[0002] Light-emitting diodes (LEDs) are common products. LEDs are typically formed by creating various thin films on a substrate, patterning them, and then cutting them into individual LED chips.

[0003] In related technologies, the product typically includes a sapphire substrate, an epitaxial layer, and a transparent conductive layer. The epitaxial layer and the transparent conductive layer are sequentially stacked on the sapphire substrate. The epitaxial layer has dicing channels. In subsequent processes, a mask of appropriate size is designed according to the distribution of the dicing channels, and the epitaxial layer is etched along the dicing channels, which can divide the epitaxial layer into multiple independent light-emitting structures.

[0004] For vertically oriented light-emitting diodes (LEDs), the sapphire substrate is typically removed via laser lift-off after fabrication. Because the lattice parameters of the sapphire substrate are smaller than those of the epitaxial layer, the epitaxial layer grown on the sapphire substrate experiences compressive stress. After removing the sapphire substrate, the compressive stress on the epitaxial layer disappears, causing a certain degree of lateral expansion of the epitaxial layer's periphery in a direction parallel to the sapphire substrate. If the original-sized mask is used to etch the epitaxial layer, areas outside the etch marks will be etched, potentially leading to leakage and short circuits. Summary of the Invention

[0005] This disclosure provides a light-emitting diode and its product with improved leakage current, which can improve the problem of photomask misalignment during etching and cutting, thus preventing the light-emitting diode from easily experiencing leakage current and short circuits. The technical solution is as follows:

[0006] On one hand, this disclosure provides a light-emitting diode (LED) comprising: an epitaxial layer and a transparent conductive layer. The epitaxial layer comprises a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially. The second semiconductor layer has a first via exposing the first semiconductor layer. The transparent conductive layer is located on the surface of the second semiconductor layer away from the first semiconductor layer, and the transparent conductive layer has a second via exposing the first via. The shortest distance between the sidewall of the transparent conductive layer and the sidewall of the epitaxial layer is greater than the shortest distance between the sidewall of the second via and the sidewall of the first via.

[0007] Optionally, the shortest distance between the sidewall of the transparent conductive layer and the sidewall of the epitaxial layer is 15μm to 20μm, or 9μm to 12μm, and the shortest distance between the sidewall of the second via and the sidewall of the first via is 1μm to 5μm.

[0008] Optionally, the light-emitting diode further includes a reflective layer located on the surface of the transparent conductive layer away from the epitaxial layer, and the reflective layer has a third through-hole exposing the first through-hole and the second through-hole; the shortest distance between the sidewall of the reflective layer and the sidewall of the epitaxial layer is greater than the shortest distance between the sidewall of the third through-hole and the first through-hole.

[0009] Optionally, the shortest distance from the sidewall of the reflective layer to the sidewall of the epitaxial layer is 15 μm to 20 μm, or 9 μm to 12 μm, and the shortest distance from the sidewall of the reflective layer to the first through hole is 2 μm to 12 μm.

[0010] Optionally, the light-emitting diode further includes an electrode layer and a passivation layer; the electrode layer is located on the surface of the transparent conductive layer away from the epitaxial layer and wraps around the reflective layer; the passivation layer is located on the surface of the epitaxial layer and the surface of the transparent conductive layer away from the epitaxial layer, and wraps around the electrode layer.

[0011] Optionally, the passivation layer is also located within the first via, and the passivation layer has a groove exposing the first semiconductor layer; the light-emitting diode further includes a bonding metal layer and a conductive substrate, the bonding metal layer is located on the surface of the passivation layer away from the epitaxial layer and within the first via, and the bonding metal layer is electrically connected to the first semiconductor layer through the groove, and the conductive substrate is located on the surface of the bonding metal layer away from the epitaxial layer.

[0012] This disclosure provides an article comprising: an epitaxial layer and a transparent conductive layer; the surface of the epitaxial layer has cleaving channels dividing the epitaxial layer into a plurality of light-emitting structures; the transparent conductive layer is located on the surface of each of the light-emitting structures; the surface of the epitaxial layer has a central region and an annular region; the annular region surrounds the central region; a plurality of light-emitting structures are arranged in both the central region and the annular region; the allowable length of the light-emitting structures located in the annular region is greater than the allowable length of the light-emitting structures located in the central region; the allowable length is the shortest distance from the sidewall of the transparent conductive layer to the cleaving channel.

[0013] Optionally, the annular region includes multiple sub-annular regions, which sequentially surround the central region; for any two adjacent sub-annular regions, the remaining length of the light-emitting structure in the sub-annular region closer to the central region is less than the remaining length of the light-emitting structure in the sub-annular region farther from the central region.

[0014] Optionally, the annular region includes a first sub-annular region and a second sub-annular region that surround the central region in sequence; the margin length of the light-emitting structure in the first sub-annular region is 9 μm to 12 μm, the margin length of the light-emitting structure in the second sub-annular region is 15 μm to 20 μm, and the margin length of the light-emitting structure in the central region is 2 μm to 12 μm.

[0015] Optionally, the ratio of the width of the first sub-annular region to the radius of the epitaxial layer is 0.1 to 0.4, and the ratio of the width of the second sub-annular region to the radius of the epitaxial layer is 0.1 to 0.4.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The light-emitting diodes provided in this embodiment are distributed in the edge region of the substrate of the product before dicing. This increases the distance from the sidewall of the transparent conductive layer of the light-emitting structure in the annular region of the epitaxial layer to the dicing channel. After the sapphire substrate is removed, the compressive stress acting on the epitaxial layer disappears, causing the pattern already formed on the epitaxial layer to laterally expand towards the peripheral edge of the epitaxial layer. Since the size of this lateral expansion varies between different products, different allowance lengths are set at the edges and in the middle to ensure that the light-emitting structure at the edge does not shift beyond the safety window during subsequent photolithography due to the different lateral expansion. This way, even if the original size mask is used to etch the epitaxial layer, it is less likely that the lateral expansion of the epitaxial layer will cause the photolithography to deviate from the safety window, resulting in etching onto the transparent conductive layer and causing leakage and short circuits in the light-emitting diode. This improves the reliability of the light-emitting diode. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural schematic diagram of a product provided by related technologies;

[0020] Figure 2 This is a top view of a light-emitting diode provided by related technologies;

[0021] Figure 3 yes Figure 2 An AA cross-sectional view is provided;

[0022] Figure 4 This is a schematic diagram of GaN layer growth on a sapphire substrate provided by related technologies;

[0023] Figure 5 This is a schematic diagram of the etching process for a light-emitting diode provided by related technologies;

[0024] Figure 6 This is a schematic diagram of the structure of an article provided in an embodiment of this disclosure;

[0025] Figure 7 This is a schematic diagram of a light-emitting structure located in a ring-shaped region provided in this disclosure;

[0026] Figure 8 yes Figure 7 A BB cross-sectional view is provided;

[0027] Figure 9 This is a schematic diagram of a light-emitting structure located in the central region provided in this disclosure embodiment;

[0028] Figure 10 yes Figure 9 A CC cross-sectional view is provided;

[0029] Figure 11 This is a schematic diagram of a light-emitting structure located in a ring-shaped region provided in this disclosure;

[0030] Figure 12 yes Figure 11 A DD cross-sectional view is provided;

[0031] Figure 13 This is a schematic diagram of a light-emitting structure provided in an embodiment of this disclosure;

[0032] Figure 14 This is a diagram showing the experimental test parameters of an article provided in an embodiment of this disclosure;

[0033] Figure 15 It is a diagram of experimental test parameters for a product provided by related technologies;

[0034] Figure 16 This is a diagram showing the preparation state of an article provided in an embodiment of this disclosure;

[0035] Figure 17 This is a diagram showing the preparation state of an article provided in an embodiment of this disclosure.

[0036] The markings in the diagram are explained as follows:

[0037] 10. Substrate;

[0038] 20. Epitaxial layer; 201. Cutting channel; 202. First through-hole; 203. Light-emitting structure;

[0039] 210. Central region; 220. Circular region; 221. First sub-circular region; 222. Second sub-circular region;

[0040] 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor;

[0041] 30. Transparent conductive layer; 301. Second through-hole; 31. Reflective layer; 311. Third through-hole; 32. Electrode layer; 33. Passivation layer; 34. Conductive substrate; 35. Bonding metal layer. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] Figure 1 This is a structural schematic diagram of a product provided by related technologies. For example... Figure 1 As shown, the related technology includes a sapphire substrate 10 and an epitaxial layer 20, with the epitaxial layer 20 located on the surface of the sapphire substrate 10. The epitaxial layer 20 has dicing channels 201, which divide the epitaxial layer 20 into multiple light-emitting structures 203.

[0045] In subsequent processes, a mask of the corresponding size will be designed according to the distribution position of the cutting path 201. The epitaxial layer 20 will be etched along the cutting path 201 through the mask to divide the epitaxial layer 20 into multiple independent light-emitting structures 203.

[0046] Figure 2 This is a top view of a light-emitting diode provided by related technologies. Figure 2 It means Figure 1 Any one of the multiple light-emitting structures 203. Figure 3 yes Figure 2 An AA cross-sectional view is provided. For example... Figure 2 , 3 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22 and a second semiconductor layer 23 stacked sequentially on the sapphire substrate 10. The second semiconductor layer 23 has a plurality of first vias 202 exposing the first semiconductor layer 21, and the plurality of first vias 202 are arranged at intervals.

[0047] like Figure 3 As shown, the product also includes a transparent conductive layer 30. The epitaxial layer 20 and the transparent conductive layer 30 are sequentially stacked on the sapphire substrate 10, and the transparent conductive layer 30 is located on the surface of the second semiconductor layer 23. The transparent conductive layer 30 does not extend into the first via 202 and the dicing channel 201.

[0048] like Figure 3 As shown, the shortest distance L1 from the sidewall of the transparent conductive layer 30 near any of the first through holes 202 to the first through hole 202 is equal to the shortest distance L2 from the sidewall of the transparent conductive layer 30 near the cut channel 201 to the cut channel 201.

[0049] Because of the vertical structure of the light-emitting diode, the sapphire substrate 10 is usually removed by laser lift-off after fabrication.

[0050] Figure 4 This is a schematic diagram of a GaN layer grown on a sapphire substrate, provided by related technologies. (Example) Figure 4 As shown, the lattice parameter of the sapphire substrate is smaller than that of the epitaxial layer, which causes the epitaxial layer grown on the sapphire substrate to be subjected to compressive stress.

[0051] Figure 5 This is a schematic diagram of the etching process for a light-emitting diode (LED) provided by related technologies. For example... Figure 5 As shown, when the sapphire substrate is removed, the compressive stress acting on the epitaxial layer 20 disappears, causing the epitaxial layer 20 to expand laterally to a certain extent in the direction parallel to the sapphire substrate.

[0052] like Figure 5As shown, if the original size mask is used to etch the epitaxial layer 20, the area outside the dicing channel 201 of the epitaxial layer 20 (see X in the figure) will be etched. See Figure 5 After the epitaxial layer 20 is etched, the transparent conductive layer 30 is exposed, which can easily lead to leakage and short circuit problems.

[0053] In particular, the peripheral edges of the epitaxial layer 20 are more prone to exhibiting significant horizontal line expansion after the sapphire substrate 10 is removed.

[0054] Therefore, this disclosure provides an article of manufacture. Figure 6 This is a schematic diagram of the structure of an article provided in an embodiment of this disclosure. For example... Figure 6 As shown, the article includes an epitaxial layer 20 and a transparent conductive layer. The surface of the epitaxial layer 20 has cleaving channels 201 that divide the epitaxial layer 20 into a plurality of light-emitting structures 203.

[0055] like Figure 6 As shown, the surface of the epitaxial layer 20 has a central region 210 and an annular region 220, with the annular region 220 surrounding the central region 210. Multiple light-emitting structures 203 are arranged in both the central region 210 and the annular region 220.

[0056] Figure 7 This is a schematic diagram of a light-emitting structure 203 located in an annular region 220 provided in this disclosure. Figure 8 yes Figure 7 A BB cross-sectional view is provided. Figure 9 This is a schematic diagram of a light-emitting structure 203 located in the central region 210 provided in this disclosure. Figure 10 yes Figure 9 A CC cross-sectional view is provided.

[0057] like Figure 8 , 10 As shown, the transparent conductive layer 30 is located on the surface of each light-emitting structure 203.

[0058] See Figure 8 , 10 The margin length X1 of the light-emitting structure 203 located in the annular region 220 is greater than the margin length X2 of the light-emitting structure 203 located in the central region 210.

[0059] The allowance length is the shortest distance from the sidewall of the transparent conductive layer 30 to the cut channel 201.

[0060] The article provided in this embodiment includes an epitaxial layer 20 and a transparent conductive layer 30. The epitaxial layer 20 is divided into multiple light-emitting structures 203 by a dicing channel 201. The allowable length of the light-emitting structures 203 distributed in the annular region 220 of the epitaxial layer 20 is greater than the allowable length of the light-emitting structures 203 distributed in the central region 210 of the epitaxial layer 20. The allowable length refers to the shortest distance from the sidewall of the transparent conductive layer 30 to the dicing channel 201. That is, the distance from the sidewall of the transparent conductive layer 30 of the light-emitting structures 203 located in the annular region 220 of the epitaxial layer 20 to the dicing channel 201 is made larger. When the sapphire substrate 10 is removed, the compressive stress acting on the epitaxial layer 20 disappears, causing the patterns already formed on the epitaxial layer to laterally expand towards the peripheral edge of the epitaxial layer 20. Furthermore, different products have varying degrees of lateral expansion. Therefore, to ensure that the light-emitting structure located at the edge does not shift beyond the safety window during subsequent photolithography due to differences in lateral expansion, different allowance lengths are set at the edges and in the middle. This way, even when using a mask of the original size to etch the epitaxial layer, the lateral expansion of the epitaxial layer is less likely to cause the photolithography to deviate from the safety window, resulting in etching onto the transparent conductive layer and causing leakage and short circuits in the LED. This improves the reliability of the LED.

[0061] Optionally, such as Figure 6 , 8 As shown, the article may further include a substrate 10, with the epitaxial layer 20 located on the substrate 10. Exemplarily, the substrate may be a sapphire substrate 10. The sapphire substrate 10 has high light transmittance, meaning it is a transparent substrate. Furthermore, sapphire material is relatively hard and chemically stable, enabling the LED to have good luminous efficacy and stability.

[0062] Optionally, the transparent conductive layer can be an indium tin oxide (ITO) layer. ITO layers have good transmittance and low resistivity. Using an ITO layer as a transparent conductive layer allows more light to be transmitted through the transparent conductive layer, thus ensuring the light emission effect. At the same time, due to its low resistivity, it also facilitates carrier conduction and improves injection efficiency.

[0063] For example, the transparent conductive layer can be an indium zinc oxide (IZO) layer. IZO layers have good transmittance and low resistivity. Using an IZO layer as a transparent conductive layer allows more light to be transmitted through the transparent conductive layer, thus ensuring the light emission effect. At the same time, due to its low resistivity, it also facilitates carrier conduction and improves injection efficiency.

[0064] For example, the thickness of the transparent conductive layer can be from 600 angstroms to 2000 angstroms. For instance, the thickness of the transparent conductive layer 30 is 1500 angstroms.

[0065] Optionally, such as Figure 6 As shown, the central region 210 is circular, the annular region 220 is circular, and the central region 210 and the annular region 220 are concentrically distributed.

[0066] In this embodiment, the substrate is a four-inch circular wafer with a radius of 50,000 μm. The epitaxial layer 20 on the substrate is also circular. The radius of the epitaxial layer 20 is 1 μm to 100 μm smaller than the radius of the substrate. For example, the radius of the epitaxial layer 20 can be 49,950 μm.

[0067] Optionally, such as Figure 6 As shown, the epitaxial layer 20 is circular, and the ratio of the radius of the central region 210 to the radius of the epitaxial layer 20 is 0.1 to 0.4.

[0068] After removing the substrate, the epitaxial layer 20 located at the edge of the substrate is less constrained than the epitaxial layer 20 located in the central region 210 of the substrate. Therefore, the epitaxial layer 20 at the edge of the substrate is more prone to deformation and lateral expansion. That is, the lateral expansion of the transparent conductive layer 30 in the central region 210 of the epitaxial layer 20 is smaller, so the central region 210 can be made relatively larger. Since the distance from the transparent conductive layer to the dicing 201 in the light-emitting structure 203 in the central region 210 is closer, the area of ​​the transparent conductive layer covering the light-emitting structure 203 is larger, thereby improving the current spreading efficiency of the light-emitting structure 203, reducing the voltage, and thus improving the brightness of the light-emitting structure 203.

[0069] For example, the ratio of the radius of the central region 210 to the radius of the epitaxial layer 20 is 0.3.

[0070] Optionally, the ratio of the width of the annular region 220 to the radius of the epitaxial layer 20 is 0.6 to 0.9.

[0071] After the substrate is removed, the epitaxial layer 20 located at the edge of the substrate is less constrained than that located at the edge of the substrate. Therefore, the lateral extension of the transparent conductive layer 30 in the annular region 220 of the epitaxial layer 20 is larger. To prevent subsequent etching of the epitaxial layer 20 from reaching areas outside the etch path 201, the proportion of the annular region 220 in the epitaxial layer 20 can be controlled to be larger, thereby preventing leakage and short circuit problems in the light-emitting diode.

[0072] For example, the ratio of the radius of the annular region 220 to the radius of the epitaxial layer 20 is 0.7.

[0073] Optionally, such as Figure 6 As shown, the annular region 220 includes multiple sub-annular regions 220, which are sequentially surrounding the central region 210.

[0074] In this embodiment of the present disclosure, for any two adjacent sub-ring regions 220 among the plurality of sub-ring regions 220, the margin length of the light-emitting structure 203 in the sub-ring region 220 closer to the center region 210 is less than the margin length of the light-emitting structure 203 in the sub-ring region 220 farther from the center region 210.

[0075] After the substrate is removed, the epitaxial layer 20 located at the edge region of the substrate is less constrained than the epitaxial layer 20 located in the center region 210 of the substrate, and the constraint on the epitaxial layer 20 gradually decreases from the center of the substrate to the peripheral edge.

[0076] For each sub-annular region 220 within the annular region 220, the transparent conductive layer 30 of the light-emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is more likely to expand laterally. Therefore, the deformation degree of the transparent conductive layer 30 of the light-emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is also greater. Therefore, the allowable length of the light-emitting structure 203 in the sub-annular region 220 closer to the center region 210 is controlled to be less than the allowable length of the light-emitting structure 203 in the sub-annular region 220 farther from the center region 210. This results in a larger coverage of the transparent conductive layer 30 of the light-emitting structure 203 in the sub-annular region 220 closer to the center region 210, thereby improving the luminous brightness of the sub-annular region 220; while the coverage of the transparent conductive layer 30 of the light-emitting structure 203 in the sub-annular region 220 farther from the center region 210 is relatively smaller to prevent leakage and short circuit problems.

[0077] For example, such as Figure 6 As shown, the annular region 220 includes a first sub-annular region 221 and a second sub-annular region 222 that surround the central region 210 in sequence.

[0078] Figure 11 This is a schematic diagram of a light-emitting structure 203 located in an annular region 220 provided in this disclosure. Figure 12 yes Figure 11 A DD cross-sectional view is provided. Figure 11 , Figure 12 The illustration shows the light-emitting structure 203 of the first sub-annular region 221. Figure 7 , Figure 8 The illustration shows the light-emitting structure 203 of the second sub-annular region 222.

[0079] See Figure 8 , 12 The margin length X3 of the light-emitting structure 203 in the first sub-annular region 221 is less than the margin length X1 of the light-emitting structure 203 in the second sub-annular region 222.

[0080] Optionally, the margin length of the light-emitting structure 203 in the first sub-annular region 221 is 9 μm to 12 μm.

[0081] For example, the margin length of the light-emitting structure 203 in the first sub-annular region 221 is 10 μm.

[0082] Optionally, the margin length of the light-emitting structure 203 in the second sub-annular region 222 is 15 μm to 20 μm.

[0083] For example, the margin length of the light-emitting structure 203 in the second sub-annular region 222 is 17 μm.

[0084] Optionally, the margin length of the light-emitting structure 203 in the central region 210 is 1 μm to 5 μm.

[0085] For example, the margin length of the light-emitting structure 203 in the central region 210 is 3 μm.

[0086] The remaining length of the light-emitting structure 203 in the central region 210 is significantly reduced compared to the remaining length of the light-emitting structure 203 in the first sub-annular region 221 and the second sub-annular region 222. This ensures that the area of ​​the transparent conductive layer covering the light-emitting structure 203 is large enough to enhance the brightness of the light-emitting structure 203 in the central region 210, while also ensuring that the coverage of the transparent conductive layer 30 of the light-emitting structure 203 in the first sub-annular region 221 and the second sub-annular region 222, which are far from the central region 210, is relatively small to prevent leakage and short circuits.

[0087] Optionally, the ratio of the width of the first sub-annular region 221 to the radius of the epitaxial layer 20 is 0.1 to 0.4, and the ratio of the width of the second sub-annular region 222 to the radius of the epitaxial layer 20 is 0.1 to 0.4.

[0088] The width of the first sub-annular region 221 refers to the radial width of the first sub-annular region 221 in the epitaxial layer 20, that is, the distance between the inner ring and the outer ring of the first sub-annular region 221.

[0089] For example, the ratio of the width of the first sub-annular region 221 to the radius of the epitaxial layer 20 is 0.3.

[0090] For example, the ratio of the width of the second sub-annular region 222 to the radius of the epitaxial layer 20 is 0.3.

[0091] It should be noted that the widths of the first sub-annular region 221 and the second sub-annular region 222 may be the same or different, and this embodiment does not impose any restrictions.

[0092] Figure 13 This is a schematic diagram of a light-emitting structure 203 provided in an embodiment of this disclosure. Figure 13 As shown, the article also includes a reflective layer 31, an electrode layer 32, and a passivation layer 33. The reflective layer 31 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the electrode layer 32 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the electrode layer 32 covers the reflective layer 31.

[0093] By setting a reflective layer 31, light emitted from the epitaxial layer 20 can be reflected, allowing more light to be emitted from the light-emitting surface of the epitaxial layer 20, thereby increasing the luminous intensity of the light-emitting diode.

[0094] Meanwhile, an electrode layer 32 is also covered on the reflective layer 31, which can prevent the metal in the reflective layer 31 from migrating upward, and the electrode layer 32 is used to connect to an external power source to supply power to the epitaxial layer 20.

[0095] Optionally, the reflective layer 31 includes an Ag layer, a Ni layer, and a TiW layer stacked sequentially.

[0096] Since Ag has good reflective properties, setting an Ag layer in the reflective layer can enhance the reflection of light by the reflective layer and improve the light output brightness of the light-emitting surface 21 of the light-emitting diode.

[0097] The Ni layer exhibits excellent corrosion and wear resistance, while the TiW layer, acting as an adhesion layer, can be successfully deposited on other thin films without peeling or cracking. The alternating layers of Ni and TiW act as a barrier layer to protect the silver mirror.

[0098] For example, the thickness of the Ag layer is between 1400 angstroms and 1700 angstroms. For instance, the thickness of the Ag layer is 1500 angstroms.

[0099] For example, the thickness of the Ni layer is between 100 angstroms and 300 angstroms. For instance, the thickness of the Ni layer is 200 angstroms.

[0100] For example, the thickness of the TiW layer is between 700 angstroms and 1000 angstroms. For instance, the thickness of the TiW layer is 800 angstroms.

[0101] Optionally, the electrode layer 32 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer stacked sequentially. The thicknesses of each metal layer are 30 Å, 2000 Å, 1000 Å, 2000 Å, 1000 Å, 2000 Å, 500 Å, 2000 Å, and 500 Å, respectively.

[0102] like Figure 13 As shown, the passivation layer 33 is located on the surface of the epitaxial layer 20 and on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the passivation layer 33 covers the electrode layer 32.

[0103] In the above implementation, a passivation layer 33 is formed on the epitaxial layer 20, covering the electrode layer 32 and the transparent conductive layer 30 to provide protection. It also isolates the electrode layer 32 from other subsequently formed metal films, preventing electrical connections between the electrode layer 32 and other metal films, thus avoiding leakage problems.

[0104] Optionally, the passivation layer 33 is a silicon oxide layer or a distributed Bragg reflection (DBR) layer.

[0105] As an example, in this embodiment of the disclosure, the passivation layer 33 is a silicon oxide layer.

[0106] The silicon oxide layer has good insulation properties, which can prevent the epitaxial layer 20 from coming into contact with other impurities in the external environment and causing leakage, thereby improving the reliability of the light-emitting diode.

[0107] As an example, in an embodiment of this disclosure, the passivation layer 33 includes a plurality of alternating silicon oxide layers and a plurality of titanium oxide layers.

[0108] Among them, multiple periodically alternating SiO2 layers and TiO2 layers can form a DBR layer.

[0109] For example, the number of cycles in a DBR layer can be between 20 and 50. For instance, the number of cycles in a DBR layer is 32.

[0110] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0111] Optionally, such as Figure 13 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 stacked sequentially. The second semiconductor layer 23 has a first via 202 exposing the first semiconductor layer 21. A transparent conductive layer 30 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21. A passivation layer 33 is also located in the first via 202, and the passivation layer 33 has a groove exposing the first semiconductor layer 21.

[0112] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0113] For example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0114] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0115] Optionally, the multi-quantum-well layer 22 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer 22 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0116] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0117] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0118] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0119] like Figure 13 As shown, the product also includes a bonding metal layer 35 and a conductive substrate 34. The bonding metal layer 35 is located on the surface of the passivation layer 33 away from the epitaxial layer 20 and inside the first via 202. The bonding metal layer 35 is electrically connected to the first semiconductor layer 21 through a groove. The conductive substrate 34 is located on the surface of the bonding metal layer 35 away from the epitaxial layer 20.

[0120] In this embodiment of the present disclosure, the first via 202 exposes the first semiconductor layer 21 so that the bonding metal layer 35 can be electrically connected to the first semiconductor layer 21 through the first via 202. At the same time, a conductive substrate 34 is disposed on the bonding metal layer 35 so that an external power source can inject current into the first semiconductor layer 21 through the conductive substrate 34 and the bonding metal layer 35 in sequence.

[0121] Exemplarily, or optionally, the bonding metal layer 35 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked sequentially.

[0122] The thickness of the first Al layer is 8,000 to 12,000 angstroms, the thickness of the first Ti layer is 100 to 500 angstroms, the thickness of the second Al layer is 8,000 to 12,000 angstroms, the thickness of the second Ti layer is 500 to 1,500 angstroms, and the thickness of the Au layer is 2,000 to 5,000 angstroms.

[0123] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0124] For example, the conductive substrate 34 may be a silicon substrate.

[0125] Figure 14 This is a diagram showing the experimental test parameters of an article provided in an embodiment of this disclosure. Figure 15 This is a graph showing the experimental test parameters of a product provided by related technologies. For example... Figure 14 , 15 As shown, the area of ​​the purple region Q in the related art is larger than the area of ​​the purple region Q in the embodiment of this disclosure. The purple region Q represents excessive leakage current. Therefore, it can be determined that the product provided in this embodiment can effectively improve the problem of leakage and short circuits in light-emitting diodes.

[0126] This disclosure provides an embodiment of a light-emitting diode. For example... Figure 8 As shown, the light-emitting diode includes an epitaxial layer 20 and a transparent conductive layer 30. The epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 stacked sequentially. The second semiconductor layer 23 has a first through-hole 202 exposing the first semiconductor layer 21. The transparent conductive layer 30 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, and the transparent conductive layer 30 has a second through-hole 301 exposing the first through-hole 202.

[0127] like Figure 8 , 12 As shown, the shortest distances X1 and X3 from the sidewall of the transparent conductive layer 30 to the sidewall of the epitaxial layer 20 are greater than the shortest distance L1 from the sidewall of the second via 301 to the first via 202.

[0128] For example, the shortest distance L1 from the sidewall of the second through hole 301 to the first through hole 202 can be 1 μm to 5 μm.

[0129] For example, the shortest distance from the sidewall of the transparent conductive layer 30 to the sidewall of the epitaxial layer 20 can be 15 μm to 20 μm, or 9 μm to 12 μm.

[0130] In this embodiment of the disclosure, the light-emitting diode is a light-emitting device obtained by cutting a product. The sidewall of the epitaxial layer 20 is the sidewall of the light-emitting structure 203 after being cut from the location of the dicing 201 in the product.

[0131] In the above implementation, the light-emitting diodes (LEDs) are distributed in the edge region of the substrate of the product before dicing. This increases the distance from the sidewall of the transparent conductive layer 30 of the light-emitting structure 203 located in the annular region 220 on the epitaxial layer 20 to the dicing channel 201. After the sapphire substrate 10 is removed, the compressive stress acting on the epitaxial layer 20 disappears, causing the pattern already formed on the epitaxial layer to laterally expand towards the peripheral edge of the epitaxial layer 20. Furthermore, the size of this lateral expansion varies between different products. Therefore, to ensure that the light-emitting structure located at the edge does not shift beyond the safety window during subsequent photolithography due to the different lateral expansion, different allowance lengths are set at the edge and in the middle. Thus, even if the original size mask is used to etch the epitaxial layer, it is less likely that the lateral expansion of the epitaxial layer will cause the photolithography to deviate from the safety window, resulting in etching onto the transparent conductive layer and causing leakage and short circuits in the LED. This improves the reliability of the LED.

[0132] Optionally, such as Figure 13 As shown, the light-emitting diode also includes a reflective layer 31, which is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the reflective layer 31 has a third through hole 311 that exposes the first through hole 202 and the second through hole 301; the shortest distance between the sidewall of the reflective layer 31 and the sidewall of the epitaxial layer 20 is greater than the shortest distance between the sidewall of the third through hole 311 and the first through hole 202.

[0133] By ensuring that the shortest distance between the sidewall of the reflective layer 31 and the sidewall of the epitaxial layer 20 is greater than the shortest distance between the sidewall of the third via 311 and the first via 202, it is possible to avoid photolithography deviating from the safety window, which could lead to etching of the reflective layer and cause leakage and short circuit problems in the light-emitting diode.

[0134] For example, such as Figure 13 As shown, the shortest distance from the sidewall of the reflective layer 31 to the sidewall of the epitaxial layer 20 is 15 μm to 20 μm, or 9 μm to 12 μm.

[0135] For example, such as Figure 13 As shown, the shortest distance from the sidewall of the reflective layer 31 to the first through hole 202 is 2μm to 12μm.

[0136] Optionally, such as Figure 13 As shown, the light-emitting diode also includes an electrode layer 32 and a passivation layer 33; the electrode layer 32 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20 and wraps around the reflective layer 31.

[0137] like Figure 13As shown, the passivation layer 33 is located on the surface of the epitaxial layer 20 and on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and encapsulates the electrode layer 32.

[0138] Optionally, the electrode layer 32 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer stacked sequentially. The thicknesses of each metal layer are 30 Å, 2000 Å, 1000 Å, 2000 Å, 1000 Å, 2000 Å, 500 Å, 2000 Å, and 500 Å, respectively.

[0139] Optionally, the passivation layer is a silicon oxide layer or a distributed Bragg reflection (DBR) layer.

[0140] As an example, in this embodiment of the disclosure, the passivation layer is a silicon oxide layer.

[0141] Optionally, such as Figure 13 As shown, the passivation layer 33 is also located within the first via 202, and the passivation layer 33 has a groove that exposes the first semiconductor layer 21.

[0142] The light-emitting diode also includes a bonding metal layer 35 and a conductive substrate 34. The bonding metal layer 35 is located on the surface of the passivation layer 33 away from the epitaxial layer 20 and inside the first via 202. The bonding metal layer 35 is electrically connected to the first semiconductor layer 21 through a groove. The conductive substrate 34 is located on the surface of the bonding metal layer 35 away from the epitaxial layer 20.

[0143] In this embodiment, the bonding metal layer 35 can be electrically connected to the first semiconductor layer 21 through the first through hole 202 and the groove. At the same time, a conductive substrate 34 is disposed on the bonding metal layer 35 so that an external power source can inject current into the first semiconductor layer 21 through the conductive substrate 34 and the bonding metal layer 35 in sequence.

[0144] Exemplarily, or optionally, the bonding metal layer may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked sequentially.

[0145] The thickness of the first Al layer is 8,000 to 12,000 angstroms, the thickness of the first Ti layer is 100 to 500 angstroms, the thickness of the second Al layer is 8,000 to 12,000 angstroms, the thickness of the second Ti layer is 500 to 1,500 angstroms, and the thickness of the Au layer is 2,000 to 5,000 angstroms.

[0146] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0147] For example, the conductive substrate may be a silicon substrate.

[0148] This disclosure provides a method for fabricating a light-emitting diode, the method comprising:

[0149] Step 1: Grow an epitaxial layer 20 on a sapphire substrate 10.

[0150] like Figure 16 As shown, the epitaxial layer 20 grown on the sapphire substrate 10 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked sequentially.

[0151] The sapphire substrate 10 can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0152] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0153] For example, the first semiconductor layer 21 may be an n-type layer and the second semiconductor layer 23 may be a p-type layer.

[0154] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0155] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.

[0156] Optionally, the multi-quantum-well layer 22 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer 22 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0157] When growing the multi-quantum-well layer 22, the MOCVD reaction chamber pressure was controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature was 760℃ to 780℃. When growing the GaN quantum barrier layer, the reaction chamber temperature was 860℃ to 890℃.

[0158] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0159] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0160] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0161] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0162] Step 2: Etch epitaxial layer 20 to form a first via 202 exposing the first semiconductor layer 21 on the surface of the second semiconductor layer 23, and a dicing channel 201 dividing epitaxial layer 20 into multiple light-emitting structures 203.

[0163] like Figure 16 As shown, both the dicing channel 201 and the first via 202 are etched into the first semiconductor layer 21. This allows the dicing channel 201 and the first via 202 to be fabricated in a single etching process, improving fabrication efficiency.

[0164] Step 3: Form a transparent conductive layer 30 on the surface of the second semiconductor 23 layer.

[0165] like Figure 16 As shown, the transparent conductive layer 30 is located outside the first through hole 202 and the cut channel 201.

[0166] In this embodiment of the present disclosure, the surface of the epitaxial layer 20 has a central region 210 and an annular region 220, the annular region 220 surrounds the central region 210, and multiple light-emitting structures 203 are arranged in both the central region 210 and the annular region 220.

[0167] like Figure 16 As shown, when preparing the transparent conductive layer 30, the margin length of the light-emitting structure 203 located in the annular region 220 is controlled to be greater than the margin length of the light-emitting structure 203 located in the central region 210.

[0168] The allowance length is the shortest distance from the sidewall of the transparent conductive layer 30 to the cut channel 201.

[0169] For example, the transparent conductive layer 30 is an indium tin oxide layer or an indium zinc oxide layer.

[0170] For example, the thickness of the transparent conductive layer 30 is between 100 angstroms and 300 angstroms. For instance, the thickness of the transparent conductive layer 30 is 200 angstroms.

[0171] Step 4: Fabricate the reflective layer 31, electrode layer 32, and passivation layer 33.

[0172] like Figure 17As shown, a reflective layer 31 and an electrode layer 32 are formed on the surface of the transparent conductive layer 30, with the electrode layer 32 covering the reflective layer 31. A passivation layer 33 is located on the surface of the second semiconductor layer 23 and the surface of the transparent conductive layer 30, and the passivation layer 33 covers the electrode layer 32.

[0173] like Figure 17 As shown, the passivation layer 33 extends into the first via 202, and the passivation layer 33 has a groove that exposes the first semiconductor layer 21.

[0174] Step 5: Fabricate the bonding metal layer 35 and laser lift off the sapphire substrate 10.

[0175] First, such as Figure 13 As shown, a metal layer 35 is bonded to the surface of the passivation layer 33 away from the epitaxial layer 20 and within the first via 202, such that the bonded metal layer 35 is electrically connected to the first semiconductor layer 21 through the groove.

[0176] Then, as Figure 13 As shown, a conductive substrate 34 is also formed on the surface of the bonding metal layer 35.

[0177] For example, the conductive substrate 34 may be a silicon substrate.

[0178] Next, the sapphire substrate 10 is removed by laser lift-off to expose the first semiconductor layer 21.

[0179] Step 6: Cut the product along cutting track 201 to obtain multiple light-emitting diodes.

[0180] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (20) and a transparent conductive layer (30). The epitaxial layer (20) includes a first semiconductor layer (21), a multiple quantum well layer (22), and a second semiconductor layer (23) stacked sequentially. The second semiconductor layer (23) has a first via (202) exposing the first semiconductor layer (21). The transparent conductive layer (30) is located on the surface of the second semiconductor layer (23) away from the first semiconductor layer (21), and the transparent conductive layer (30) has a second via (301) exposing the first via (202). The shortest distance between the sidewall of the transparent conductive layer (30) and the sidewall of the epitaxial layer (20) is greater than the shortest distance (L1) between the sidewall of the second through hole (301) and the sidewall of the first through hole (202), and the shortest distance (L1) between the sidewall of the second through hole (301) and the sidewall of the first through hole (202) is greater than 0.

2. The light-emitting diode according to claim 1, characterized in that, The shortest distance between the sidewall of the transparent conductive layer (30) and the sidewall of the epitaxial layer (20) is 15μm to 20μm, or 9μm to 12μm, and the shortest distance (L1) between the sidewall of the second through hole (301) and the sidewall of the first through hole (202) is 1μm to 5μm.

3. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode further includes a reflective layer (31) located on the surface of the transparent conductive layer (30) away from the epitaxial layer (20), and the reflective layer (31) has a third through hole (311) exposing the first through hole (202) and the second through hole (301); the shortest distance between the sidewall of the reflective layer (31) and the sidewall of the epitaxial layer (20) is greater than the shortest distance between the sidewall of the third through hole (311) and the first through hole (202).

4. The light-emitting diode according to claim 3, characterized in that, The shortest distance from the sidewall of the reflective layer (31) to the sidewall of the epitaxial layer (20) is 15μm to 20μm, or 9μm to 12μm, and the shortest distance from the sidewall of the reflective layer (31) to the first through hole (202) is 2μm to 12μm.

5. The light-emitting diode according to claim 3 or 4, characterized in that, The light-emitting diode further includes an electrode layer (32) and a passivation layer (33); the electrode layer (32) is located on the surface of the transparent conductive layer (30) away from the epitaxial layer (20) and wraps around the reflective layer (31). The passivation layer (33) is located on the surface of the epitaxial layer (20) and on the surface of the transparent conductive layer (30) away from the epitaxial layer (20), and encapsulates the electrode layer (32).

6. The light-emitting diode according to claim 5, characterized in that, The passivation layer (33) is also located within the first via (202), and the passivation layer (33) has a groove that exposes the first semiconductor layer (21); The light-emitting diode further includes a bonding metal layer (35) and a conductive substrate (34). The bonding metal layer (35) is located on the surface of the passivation layer (33) away from the epitaxial layer (20) and inside the first via (202). The bonding metal layer (35) is electrically connected to the first semiconductor layer (21) through the groove. The conductive substrate (34) is located on the surface of the bonding metal layer (35) away from the epitaxial layer (20).

7. A semiconductor article, characterized in that, The semiconductor article includes: an epitaxial layer (20) and a transparent conductive layer (30), wherein the surface of the epitaxial layer (20) has cleaving channels (201) that divide the epitaxial layer (20) into a plurality of light-emitting structures (203), and the transparent conductive layer (30) is located on the surface of each of the light-emitting structures (203); The surface of the epitaxial layer (20) has a central region (210) and an annular region (220), the annular region (220) surrounding the central region (210), and a plurality of light-emitting structures (203) are arranged in both the central region (210) and the annular region (220). The margin length of the light-emitting structure (203) located in the annular region (220) is greater than the margin length of the light-emitting structure (203) located in the central region (210), and the margin length is the shortest distance from the sidewall of the transparent conductive layer (30) to the cut channel (201).

8. The semiconductor article according to claim 7, characterized in that, The annular region (220) includes a plurality of sub-annular regions (220), which sequentially surround the central region (210); For any two adjacent sub-ring regions (220) among the plurality of sub-ring regions (220), the margin length of the light-emitting structure (203) in the sub-ring region (220) closer to the central region (210) is less than the margin length of the light-emitting structure (203) in the sub-ring region (220) farther from the central region (210).

9. The semiconductor article according to claim 8, characterized in that, The annular region (220) includes a first sub-annular region (221) and a second sub-annular region (222) that surround the central region (210) in sequence. The light-emitting structure (203) in the first sub-annular region (221) has a margin length of 9 μm to 12 μm, the light-emitting structure (203) in the second sub-annular region (222) has a margin length of 15 μm to 20 μm, and the light-emitting structure (203) in the central region (210) has a margin length of 2 μm to 12 μm.

10. The semiconductor article according to claim 9, characterized in that, The ratio of the width of the first sub-annular region (221) to the radius of the epitaxial layer (20) is 0.1 to 0.4, and the ratio of the width of the second sub-annular region (222) to the radius of the epitaxial layer (20) is 0.1 to 0.4.

Images