Current limiting circuit for Ethernet power supply

Abstract

The invention relates to the technical field of Ethernet power supply, and discloses a current limiting circuit for Ethernet power supply, which comprises a logic control unit, an input capacitor C1, a DC-DC controller, a power tube M1, a load resistor R1, an operational amplifier LOAMP, a change-over switch S1 and a reference circuit, in actual use, the reference circuit for providing two reference voltages is arranged, and the logic control unit can provide different reference voltages for the positive input end Vp of the operational amplifier LOAMP by controlling the connection and disconnection of the common end and the input end of the change-over switch S1, so that different current limiting currents can be set, and the current limiting precision is improved. And different current limiting requirements of the powered device in the power-on starting process and the working process are met.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet power supply, and in particular to a current limiting circuit for Ethernet power supply. Background Art

[0002] With the development of science and technology, POE power supply technology only requires one network cable to achieve data transmission and power supply at the same time, which greatly facilitates the wiring between electronic devices. In addition, since there is no need to prepare power sockets specifically for electronic equipment, space and wiring costs are saved. Finally, POE power supply technology can also make the deployment of electronic equipment more flexible, and can meet various installation locations such as installation on ceilings and walls.

[0003] In the Ethernet system, the main devices are the power supply equipment PSE and the powered device PS. The power supply equipment PSE provides power to the powered device PS. In order to ensure that the Ethernet cable can safely transmit the power required by the powered device PD, the powered device needs to control and manage the input power. One aspect that needs to be controlled and managed is the need to limit the current.

[0004] During the startup and operation of the powered device PD, different current limiting values ​​are required. However, the existing current limiting circuit can only set one current limiting value, which is not well compatible with the operation process of the powered device PD. Summary of the invention

[0005] In view of the shortcomings of the background technology, the present invention provides a current limiting circuit for Ethernet power supply. The technical problem to be solved is that the existing current limiting circuit for Ethernet power supply can only provide a current limiting value and cannot take into account the entire process of the powered device PD.

[0006] To solve the above technical problems, the present invention provides the following technical solutions: A current limiting circuit for Ethernet power supply, comprising a logic control unit, an input capacitor C1, a DC-DC controller, a power tube M1, a load resistor R1, an operational amplifier LOAMP, a switch S1 and a reference circuit;

[0007] One end of the input capacitor C1 is electrically connected to the voltage input end and the external voltage input end VIN of the DC-DC controller respectively, and the other end of the input capacitor C1 is electrically connected to the voltage output end of the DC-DC controller and the drain of the power tube M1 respectively. The logic control unit is electrically connected to the DC-DC controller and is used to control the voltage output by the DC-DC controller;

[0008] The output end of the operational amplifier LOAMP is electrically connected to the gate of the power tube M1, the negative input end Vn of the operational amplifier LOAMP is electrically connected to the source of the power tube M1 and one end of the load resistor R1 respectively, the other end of the load resistor R1 is grounded, and the positive input end Vp of the operational amplifier LOAMP is electrically connected to the common end of the switch S1;

[0009] The reference circuit is electrically connected to the two input terminals of the switch S1 to provide different reference voltages for the two input terminals of the switch S1;

[0010] The logic control unit is electrically connected to the control end of the switch S1 and is used to control the on / off of the common end of the switch S1 and the two input ends of the switch S1.

[0011] In a certain embodiment, the reference circuit provides reference voltages Vref2 and Vref3 to the two input terminals of the switch S1, respectively, and the reference voltage Vref2 is less than the reference voltage Vref3;

[0012] The logic control unit controls the switch S1 to select the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP when the external voltage input terminal VIN starts to be powered on;

[0013] During the power-on process, when the current input to the power tube M1 is lower than the threshold, the operational amplifier LOAMP inputs a high-level signal Inrush to the logic control unit. Based on the signal Inrush, the logic control unit controls the switching switch S1 to select the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP, and the power-on process ends.

[0014] In some implementations, the logic control unit inputs a control signal CL_SW to the switch S1 to control the switch S1 to select the reference voltage Vref2 or the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

[0015] In a certain embodiment, when the control signal CL_SW is at a low level, the switch S1 selects the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP;

[0016] When the control signal CL_SW is at a high level, the switch S1 selects the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

[0017] In a certain embodiment, the present invention also includes a delay unit and a comparator CMP3, wherein the negative input terminal of the comparator CMP3 is electrically connected to the drain of the power tube M1, the positive input terminal of the comparator CMP3 is used to input a comparison reference voltage, the output terminal of the comparator CMP3 is electrically connected to the delay unit, the delay unit performs a delay when the comparator CMP3 outputs a high-level signal, and inputs a delay signal to the logic control unit after the delay time expires, and the logic control unit controls the switching switch S1 based on the delay signal and the high-level signal Inrush to select the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

[0018] In some implementations, the delay time is 400us.

[0019] In some implementations, the reference voltage Vref2 is 11.2 mV, and the reference voltage Vref3 is 80 mV.

[0020] In a certain embodiment, the operational amplifier LOAMP includes a MOS transistor P21, the source of the MOS transistor P21 is electrically connected to the source of the MOS transistor P24, the source of the MOS transistor P25, the source of the MOS transistor P29, the source of the MOS transistor P31, the source of the MOS transistor P33, the source of the MOS transistor P35 and the source of the MOS transistor P37, respectively, for inputting a power supply VCC;

[0021] The gate of the MOS transistor P21 is electrically connected to the gate of the MOS transistor P24, the gate of the MOS transistor P25, the drain of the MOS transistor P21 and the source of the MOS transistor P22 respectively, and is used to input a bias voltage VB7;

[0022] The drain of MOS tube P24 is electrically connected to the source of MOS tube P23, and the drain of MOS tube P25 is electrically connected to the source of MOS tube P26; the gate of MOS tube P22 is electrically connected to the gate of MOS tube P23, the gate of MOS tube P26, the drain of MOS tube P22 and the drain of MOS tube N9, respectively, for inputting bias voltage VB6; the drain of MOS tube P23 is electrically connected to the drain of MOS tube N14, the gate of MOS tube N14, the gate of MOS tube N15, the drain of MOS tube N13 and The gate of MOS tube N13 is electrically connected, the drain of MOS tube P26 is electrically connected to the source of MOS tube N13, the drain of MOS tube N15, the source of MOS tube P27 and the source of MOS tube P28 respectively; the source of MOS tube N14 is electrically connected to the collector of transistor Q5, the source of MOS tube N15 is electrically connected to the collector of transistor Q6, the base of transistor Q5 is electrically connected to the base of transistor Q6, the source of MOS tube N12 and the drain of MOS tube N11 respectively, the emitter of transistor Q5 is electrically connected to the base of transistor Q6, the emitter of transistor Q5 is electrically connected to the emitter of transistor Q6. The emitter of transistor Q3 is electrically connected, the emitter of transistor Q6 is electrically connected to the emitter of transistor Q4, the base of transistor Q3 is the positive input terminal Vp of operational amplifier LOAMP, the base of transistor Q4 is the negative input terminal Vn of operational amplifier LOAMP, the collector of transistor Q3 and the collector of transistor Q4 are both grounded; the gate of MOS tube N9 is electrically connected to the gate of MOS tube N20, the gate of MOS tube N21, the gate of MOS tube N25 and the gate of MOS tube N27 respectively, for inputting bias voltage V B5; the source of the MOS tube N9 is electrically connected to the drain of the MOS tube N10, and the gate of the MOS tube N10 is electrically connected to the gate of the MOS tube N11, the gate of the MOS tube N17, the gate of the MOS tube N18, the gate of the MOS tube N22 and the gate of the MOS tube N24, respectively, for inputting the bias voltage VB4; the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N22 and the source of the MOS tube N24 are all grounded;

[0023] The gate of MOS transistor P27 is electrically connected to the drain of MOS transistor P27, the drain of MOS transistor N16, the gate of MOS transistor N16, the gate of MOS transistor N19 and the gate of MOS transistor N28 respectively; the drain of MOS transistor N19 is electrically connected to the source of MOS transistor N20; the drain of MOS transistor N22 is electrically connected to the source of MOS transistor N21; the drain of MOS transistor N24 is electrically connected to the source of MOS transistor N25; the drain of MOS transistor N28 is electrically connected to the source of MOS transistor N27; the source of MOS transistor N16 is electrically connected to the drain of MOS transistor N17; the source of MOS transistor N17, the drain of MOS transistor P28, the source of MOS transistor N19 and the source of MOS transistor N28 are all grounded;

[0024] The drain of the MOS tube N31 is electrically connected to the gate of the MOS tube N12, and the drain of the MOS tube N12 is used to access the power supply VCC; the gate of the MOS tube N31 is electrically connected to the gate of the MOS tube N23, the drain of the MOS tube N23, the drain of the MOS tube P34 and the gate of the MOS tube N29 respectively, and the source of the MOS tube N23 and the source of the MOS tube N29 are both grounded; the source of the MOS tube N31 is electrically connected to the drain of the MOS tube N18;

[0025] The gate of the MOS transistor P29 is electrically connected to the gate of the MOS transistor P31, the drain of the MOS transistor P29, and the source of the MOS transistor P30 respectively; the drain of the MOS transistor P31 is electrically connected to the source of the MOS transistor P323; the gate of the MOS transistor P30 is electrically connected to the gate of the MOS transistor P32, the drain of the MOS transistor P30, and the drain of the MOS transistor N20 respectively; the drain of the MOS transistor P32 is electrically connected to the drain of the MOS transistor N21 and the input end of the Schmitt trigger SMT respectively; the output end of the Schmitt trigger SMT outputs the signal Inrush through the inverter INV1;

[0026] The gate of the MOS tube P33 is used to input the bias voltage VB7, the drain of the MOS tube P33 is electrically connected to the source of the MOS tube P34, the gate of the MOS tube P34 is used to input the bias voltage VB6, and the drain of the MOS tube P34 is electrically connected to the drain of the MOS tube N23;

[0027] The gate of MOS tube P35 is electrically connected to the gate of MOS tube P37, the drain of MOS tube P35 and the source of MOS tube P36 respectively. The drain of MOS tube P37 is electrically connected to the source of MOS tube P38. The gate of MOS tube P36 is electrically connected to the gate of MOS tube P38, the drain of MOS tube P36 and the drain of MOS tube N26 respectively. The gate of MOS tube N26 is electrically connected to the output end of inverter INV2. The source of MOS tube N26 is electrically connected to MOS The drain of the MOS tube N25 is electrically connected, the drain of the MOS tube P37 is electrically connected to the source of the MOS tube P38; the drain of the MOS tube P38 is electrically connected to the drain of the MOS tube N27, the gate of the MOS tube P28 and the drain of the MOS tube N30 respectively, which is the output end of the operational amplifier LOAMP, the gate of the MOS tube N30 is electrically connected to the input end of the inverter INV2 for inputting the enable signal EN, and the source of the MOS tube N30 is electrically connected to the drain of the MOS tube N29.

[0028] In some implementations, the power tube M1 is an NMOS tube.

[0029] In some implementations, the load resistor R1 is made of a metal layer parasitic resistor, and has a resistance of 80 mΩ.

[0030] Compared with the prior art, the present invention has the following beneficial effects: by setting a reference circuit that provides two reference voltages, the present invention allows the logic control unit to control the on-off of the common terminal and the input terminal of the switching switch S1, thereby providing different reference voltages for the positive input terminal Vp of the operational amplifier LOAMP, thereby setting different current limiting currents to meet different current limiting requirements of the powered device during the power-on startup process and the working process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of the present invention in an embodiment;

[0032] Figure 2 is a circuit diagram of an operational amplifier LOAMP in an embodiment;

[0033] Figure 3 A simulation diagram of transient simulation performed for the present invention;

[0034] Figure 4 This is a simulation diagram of DC scanning according to the present invention. DETAILED DESCRIPTION

[0035] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0036] like Figure 1 As shown, a current limiting circuit for Ethernet power supply includes a logic control unit 1, an input capacitor C1, a DC-DC controller 2, a power tube M1, a load resistor R1, an operational amplifier LOAMP, a switch S1 and a reference circuit 3; wherein the power tube M1 is an NMOS tube;

[0037] One end of the input capacitor C1 is electrically connected to the voltage input end of the DC-DC controller 2 and the external voltage input end VIN respectively, and the other end of the input capacitor C1 is electrically connected to the voltage output end of the DC-DC controller 2 and the drain of the power tube M1 respectively. The logic control unit 1 is electrically connected to the DC-DC controller to control the voltage output by the DC-DC controller 2;

[0038] The output end of the operational amplifier LOAMP is electrically connected to the gate of the power tube M1, the negative input end Vn of the operational amplifier LOAMP is electrically connected to the source of the power tube M1 and one end of the load resistor R1 respectively, the other end of the load resistor R1 is grounded, and the positive input end Vp of the operational amplifier LOAMP is electrically connected to the common end of the switching switch S1;

[0039] The reference circuit 3 is electrically connected to the two input terminals of the switch S1 to provide different reference voltages for the two input terminals of the switch S1;

[0040] The logic control unit 1 is electrically connected to the control end of the switch S1 and is used to control the on / off of the common end of the switch S1 and the two input ends of the switch S1.

[0041] Specifically, in this embodiment, the reference voltages provided by the reference circuit 3 to the two input terminals of the switch S1 are respectively the reference voltage Vref2 and the reference voltage Vref3, and the reference voltage Vref2 is less than the reference voltage Vref3;

[0042] When the external voltage input terminal VIN starts to be powered on, the logic control unit controls the switch S1 to select the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP;

[0043] During the power-on process, when the current input to the power tube M1 is lower than the threshold, the operational amplifier LOAMP inputs a high-level signal Inrush to the logic control unit 1. Based on the signal Inrush, the logic control unit 1 controls the switching switch S1 to select the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP, and the power-on process ends.

[0044] In this embodiment, the reference circuit 3 is an existing reference voltage generating circuit, which will not be described in detail.

[0045] In actual use, the present invention provides a reference circuit 3 that provides two reference voltages, so that the logic control unit 1 can provide different reference voltages for the positive input terminal Vp of the operational amplifier LOAMP by controlling the on-off of the common terminal and the input terminal of the switching switch S1, thereby setting different current limiting currents to meet the different current limiting requirements of the powered device during the power-on startup process and the working process.

[0046] In this embodiment, the logic control unit 1 controls the switch S1 as follows:

[0047] The logic control unit 1 inputs a control signal CL_SW to the switch S1 to control the switch S1 to select the reference voltage Vref2 or the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

[0048] Specifically, when the control signal CL_SW is at a low level, the switch S1 selects the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP;

[0049] When the control signal CL_SW is at a high level, the switch S1 selects the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

[0050] exist Figure 1In the present invention, the delay unit 4 and the comparator CMP3 are also included. The negative input terminal of the comparator CMP3 is electrically connected to the drain of the power tube M1. The positive input terminal of the comparator CMP3 is used to input the comparison reference voltage Vref1. The output terminal of the comparator CMP3 is electrically connected to the delay unit 5. The delay unit 5 performs a delay when the comparator CMP3 outputs a high-level signal, and inputs a delay signal Delay to the logic control unit 2 after the delay time is up. The logic control unit 1 controls the switching switch S1 to select the reference voltage Vref3 to input to the positive input terminal Vp of the operational amplifier LOAMP based on the delay signal Delay and the high-level signal Inrush. Among them, the delay time is 400us.

[0051] Specifically, in this embodiment, the reference voltage Vref2 is 11.2 mV, the reference voltage Vref3 is 80 mV, and the load resistor R1 is made of a metal layer parasitic resistor, and the resistance value is 80 mΩ.

[0052] right Figure 1 The circuit is analyzed as follows:

[0053] first Figure 1 The circuit clamps the current by sampling the voltage on the load resistor R1 and comparing it with the reference voltage. Different currents can be clamped by setting different reference voltages.

[0054] In actual use, when the circuit starts to power on, assuming that the potential of the external voltage input terminal VIN is Vin, the node RTN is at the Vin potential, the DC-DC controller 2 is turned off, the control signal CL_SW is at a low level, and the voltage of the positive input terminal Vp of the operational amplifier LOAMP is 11.2mV. At this time, the current limit point current is 140mA;

[0055] During the power-on process, the power tube M1 operates in the saturation region. The current input to the drain of the power tube M1 is recorded as I RTN , then the current I RTN To charge the input capacitor, the potential of the node RTN is continuously pulled down. When the potential of the node RTN is close to the ground, the power tube M1 will enter the linear region, and the current I RTN When the current I RTN When it drops to the threshold, the signal Inrush changes from a low level to a high level, and a high level signal is output through the comparator CMP3. After a delay of 400us in the delay unit 4, the delay signal Delay is input to the logic control unit. The logic control unit 1 changes the control signal CL_SW to a high level at this time, and the positive input terminal of the operational amplifier LOAMP inputs a reference voltage Vref3 of 80mV. At this time, the current limiting point current is switched to 1A, and the DC-DC controller 2 starts to work normally.

[0056] In actual use, the 400us delay generated by the comparator CMP3 and the delay unit 4 can make the time when the control signal CL_SW output by the logic control unit 1 changes from a low level to a high level lag behind the time when the signal Inrush changes from a low level to a high level, thereby effectively suppressing the dead time of the overall power supply circuit and achieving the function of reducing the output voltage change rate.

[0057] Specifically, in this embodiment, the operational amplifier LOAMP includes a MOS transistor P21, the source of the MOS transistor P21 is electrically connected to the source of the MOS transistor P24, the source of the MOS transistor P25, the source of the MOS transistor P29, the source of the MOS transistor P31, the source of the MOS transistor P33, the source of the MOS transistor P35 and the source of the MOS transistor P37, respectively, for inputting the power supply VCC;

[0058] The gate of the MOS transistor P21 is electrically connected to the gate of the MOS transistor P24, the gate of the MOS transistor P25, the drain of the MOS transistor P21 and the source of the MOS transistor P22 respectively, and is used to input a bias voltage VB7;

[0059] The drain of MOS tube P24 is electrically connected to the source of MOS tube P23, and the drain of MOS tube P25 is electrically connected to the source of MOS tube P26; the gate of MOS tube P22 is electrically connected to the gate of MOS tube P23, the gate of MOS tube P26, the drain of MOS tube P22 and the drain of MOS tube N9, respectively, for inputting bias voltage VB6; the drain of MOS tube P23 is electrically connected to the drain of MOS tube N14, the gate of MOS tube N14, the gate of MOS tube N15, the drain of MOS tube N13 and The gate of MOS tube N13 is electrically connected, the drain of MOS tube P26 is electrically connected to the source of MOS tube N13, the drain of MOS tube N15, the source of MOS tube P27 and the source of MOS tube P28 respectively; the source of MOS tube N14 is electrically connected to the collector of transistor Q5, the source of MOS tube N15 is electrically connected to the collector of transistor Q6, the base of transistor Q5 is electrically connected to the base of transistor Q6, the source of MOS tube N12 and the drain of MOS tube N11 respectively, the emitter of transistor Q5 is electrically connected to the base of transistor Q6, the emitter of transistor Q5 is electrically connected to the emitter of transistor Q6. The emitter of transistor Q3 is electrically connected, the emitter of transistor Q6 is electrically connected to the emitter of transistor Q4, the base of transistor Q3 is the positive input terminal Vp of operational amplifier LOAMP, the base of transistor Q4 is the negative input terminal Vn of operational amplifier LOAMP, the collector of transistor Q3 and the collector of transistor Q4 are both grounded; the gate of MOS tube N9 is electrically connected to the gate of MOS tube N20, the gate of MOS tube N21, the gate of MOS tube N25 and the gate of MOS tube N27 respectively, for inputting bias voltage V B5; the source of the MOS tube N9 is electrically connected to the drain of the MOS tube N10, and the gate of the MOS tube N10 is electrically connected to the gate of the MOS tube N11, the gate of the MOS tube N17, the gate of the MOS tube N18, the gate of the MOS tube N22 and the gate of the MOS tube N24, respectively, for inputting the bias voltage VB4; the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N22 and the source of the MOS tube N24 are all grounded;

[0060] The gate of MOS transistor P27 is electrically connected to the drain of MOS transistor P27, the drain of MOS transistor N16, the gate of MOS transistor N16, the gate of MOS transistor N19 and the gate of MOS transistor N28 respectively; the drain of MOS transistor N19 is electrically connected to the source of MOS transistor N20; the drain of MOS transistor N22 is electrically connected to the source of MOS transistor N21; the drain of MOS transistor N24 is electrically connected to the source of MOS transistor N25; the drain of MOS transistor N28 is electrically connected to the source of MOS transistor N27; the source of MOS transistor N16 is electrically connected to the drain of MOS transistor N17; the source of MOS transistor N17, the drain of MOS transistor P28, the source of MOS transistor N19 and the source of MOS transistor N28 are all grounded;

[0061] The drain of the MOS tube N31 is electrically connected to the gate of the MOS tube N12, and the drain of the MOS tube N12 is used to access the power supply VCC; the gate of the MOS tube N31 is electrically connected to the gate of the MOS tube N23, the drain of the MOS tube N23, the drain of the MOS tube P34 and the gate of the MOS tube N29 respectively, and the source of the MOS tube N23 and the source of the MOS tube N29 are both grounded; the source of the MOS tube N31 is electrically connected to the drain of the MOS tube N18;

[0062] The gate of the MOS transistor P29 is electrically connected to the gate of the MOS transistor P31, the drain of the MOS transistor P29, and the source of the MOS transistor P30 respectively; the drain of the MOS transistor P31 is electrically connected to the source of the MOS transistor P323; the gate of the MOS transistor P30 is electrically connected to the gate of the MOS transistor P32, the drain of the MOS transistor P30, and the drain of the MOS transistor N20 respectively; the drain of the MOS transistor P32 is electrically connected to the drain of the MOS transistor N21 and the input end of the Schmitt trigger SMT respectively; the output end of the Schmitt trigger SMT outputs the signal Inrush through the inverter INV1;

[0063] The gate of the MOS tube P33 is used to input the bias voltage VB7, the drain of the MOS tube P33 is electrically connected to the source of the MOS tube P34, the gate of the MOS tube P34 is used to input the bias voltage VB6, and the drain of the MOS tube P34 is electrically connected to the drain of the MOS tube N23;

[0064] The gate of MOS tube P35 is electrically connected to the gate of MOS tube P37, the drain of MOS tube P35 and the source of MOS tube P36 respectively. The drain of MOS tube P37 is electrically connected to the source of MOS tube P38. The gate of MOS tube P36 is electrically connected to the gate of MOS tube P38, the drain of MOS tube P36 and the drain of MOS tube N26 respectively. The gate of MOS tube N26 is electrically connected to the output end of inverter INV2. The source of MOS tube N26 is electrically connected to MOS The drain of the MOS tube N25 is electrically connected, the drain of the MOS tube P37 is electrically connected to the source of the MOS tube P38; the drain of the MOS tube P38 is electrically connected to the drain of the MOS tube N27, the gate of the MOS tube P28 and the drain of the MOS tube N30 respectively, which is the output end of the operational amplifier LOAMP, the gate of the MOS tube N30 is electrically connected to the input end of the inverter INV2 for inputting the enable signal EN, and the source of the MOS tube N30 is electrically connected to the drain of the MOS tube N29.

[0065] for Figure 2The circuit shown in the figure reduces the input offset voltage by compensating the base current of the transistor. In addition, the transistors Q3, Q4, Q5 and Q6 form an emitter follower-common base amplifier topology structure, which amplifies the signal input to the base of the transistor Q3 to the node VC, and then transmits it to the node VD through the diode structure composed of the MOS transistor P27. The pull-down current generated by the MOS transistor N28 controlled by the node VD is compared with the pull-up current generated by the MOS transistors P37 and P38 to control the output, and the output drives the power tube M1, thereby performing current limiting.

[0066] for Figure 2 The process of generating the signal Inrush is as follows:

[0067] When the circuit is powered on, the pull-up current formed by MOS tubes P31 and P32 exceeds the pull-down current formed by MOS tubes N21 and N22, so the signal Inrush is fixed at a low level. When the power tube M1 enters the linear region, the current I RTN drops near the end of power-on, causing node V D The voltage of the node RTN drops, and the pull-up current is smaller than the pull-down current, so the signal Inrush switches from a low level to a high level. At the same time, the voltage of the node RTN is lower than the reference voltage Vref1, and after the delay time has exceeded, the control signal CL-SW will switch to a high level to achieve the switching function of the current limit point.

[0068] The transient simulation of the circuit of the present invention is performed. Since the voltage of the circuit node RTN port is given by the DC-DC controller 2, the current source is used to simulate the current during power-on and normal operation. Figure 3 As shown. The current source changes from 0 to 1.2A within 2ms. Figure 3 (a) and Figure 3 (b) are transient simulation waveforms when the control signal CL-SW = 0 (low level) and 1 (high level). When CL-SW = 0, the current is limited to 141.7mA. When CL-SW = 1, the current is limited to 977.8mA. The simulation shows that this circuit can normally achieve current limiting of two thresholds.

[0069] The present invention is subjected to DC scanning, the control signal CL-SW is set at a low level, the current source changes from 0 to 600mA, and the simulation waveform is as follows: Figure 4 As shown in the figure: when the power-on is almost over, the current input to the power tube M1 will be limited to 144.2mA, and the signal inrush outputs a low level; and when the current input to the power tube M1 drops to 126.8mA, the signal inrush is triggered to flip to a high level. The simulation shows that the current limiting circuit of the present invention can realize the current limiting point switching function.

[0070] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A current limiting circuit for Ethernet power supply, characterized in that: It includes a logic control unit, an input capacitor C1, a DC-DC controller, a power tube M1, a load resistor R1, an operational amplifier LOAMP, a switching switch S1 and a reference circuit; One end of the input capacitor C1 is electrically connected to the voltage input end and the external voltage input end VIN of the DC-DC controller respectively, and the other end of the input capacitor C1 is electrically connected to the voltage output end of the DC-DC controller and the drain of the power tube M1 respectively. The logic control unit is electrically connected to the DC-DC controller and is used to control the voltage output by the DC-DC controller; The output end of the operational amplifier LOAMP is electrically connected to the gate of the power tube M1, the negative input end Vn of the operational amplifier LOAMP is electrically connected to the source of the power tube M1 and one end of the load resistor R1 respectively, the other end of the load resistor R1 is grounded, and the positive input end Vp of the operational amplifier LOAMP is electrically connected to the common end of the switch S1; The reference circuit is electrically connected to the two input terminals of the switch S1 to provide different reference voltages for the two input terminals of the switch S1; The logic control unit is electrically connected to the control end of the switch S1 and is used to control the on / off of the common end of the switch S1 and the two input ends of the switch S1.

2. A current limiting circuit for power over Ethernet according to claim 1, characterized in that: The reference voltages provided by the reference circuit to the two input terminals of the switch S1 are respectively a reference voltage Vref2 and a reference voltage Vref3, and the reference voltage Vref2 is less than the reference voltage Vref3; The logic control unit controls the switch S1 to select the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP when the external voltage input terminal VIN starts to be powered on; During the power-on process, when the current input to the power tube M1 is lower than the threshold, the operational amplifier LOAMP inputs a high-level signal Inrush to the logic control unit. Based on the signal Inrush, the logic control unit controls the switching switch S1 to select the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP, and the power-on process ends.

3. A current limiting circuit for Ethernet power supply according to claim 2, characterized in that: The logic control unit inputs a control signal CL_SW to the switch S1 to control the switch S1 to select the reference voltage Vref2 or the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

4. A current limiting circuit for power over Ethernet according to claim 3, characterized in that: When the control signal CL_SW is at a low level, the switch S1 selects the reference voltage Vref2 to be input to the positive input terminal Vp of the operational amplifier LOAMP; When the control signal CL_SW is at a high level, the switch S1 selects the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

5. A current limiting circuit for Ethernet power supply according to claim 2, characterized in that: It also includes a delay unit and a comparator CMP3, wherein the negative input terminal of the comparator CMP3 is electrically connected to the drain of the power tube M1, the positive input terminal of the comparator CMP3 is used to input a comparison reference voltage, the output terminal of the comparator CMP3 is electrically connected to the delay unit, the delay unit performs a delay when the comparator CMP3 outputs a high-level signal, and inputs a delay signal to the logic control unit after the delay time expires, and the logic control unit controls the switching switch S1 based on the delay signal and the high-level signal Inrush to select the reference voltage Vref3 to be input to the positive input terminal Vp of the operational amplifier LOAMP.

6. A current limiting circuit for Ethernet power supply according to claim 5, characterized in that: The delay time is 400us.

7. A current limiting circuit for Ethernet power supply according to claim 2, characterized in that: The reference voltage Vref2 is 11.2 mV, and the reference voltage Vref3 is 80 mV.

8. A current limiting circuit for Ethernet power supply according to claim 2, characterized in that: The operational amplifier LOAMP includes a MOS transistor P21, the source of which is electrically connected to the source of a MOS transistor P24, the source of a MOS transistor P25, the source of a MOS transistor P29, the source of a MOS transistor P31, the source of a MOS transistor P33, the source of a MOS transistor P35 and the source of a MOS transistor P37, respectively, for inputting a power supply VCC; The gate of the MOS transistor P21 is electrically connected to the gate of the MOS transistor P24, the gate of the MOS transistor P25, the drain of the MOS transistor P21 and the source of the MOS transistor P22, respectively, for inputting a bias voltage VB7; The drain of MOS tube P24 is electrically connected to the source of MOS tube P23, and the drain of MOS tube P25 is electrically connected to the source of MOS tube P26; the gate of MOS tube P22 is electrically connected to the gate of MOS tube P23, the gate of MOS tube P26, the drain of MOS tube P22 and the drain of MOS tube N9, respectively, for inputting bias voltage VB6; the drain of MOS tube P23 is electrically connected to the drain of MOS tube N14, the gate of MOS tube N14, the gate of MOS tube N15, the drain of MOS tube N13 and The gate of MOS tube N13 is electrically connected, the drain of MOS tube P26 is electrically connected to the source of MOS tube N13, the drain of MOS tube N15, the source of MOS tube P27 and the source of MOS tube P28 respectively; the source of MOS tube N14 is electrically connected to the collector of transistor Q5, the source of MOS tube N15 is electrically connected to the collector of transistor Q6, the base of transistor Q5 is electrically connected to the base of transistor Q6, the source of MOS tube N12 and the drain of MOS tube N11 respectively, the emitter of transistor Q5 is electrically connected to the base of transistor Q6, the emitter of transistor Q5 is electrically connected to the emitter of transistor Q6. The emitter of transistor Q3 is electrically connected, the emitter of transistor Q6 is electrically connected to the emitter of transistor Q4, the base of transistor Q3 is the positive input terminal Vp of operational amplifier LOAMP, the base of transistor Q4 is the negative input terminal Vn of operational amplifier LOAMP, the collector of transistor Q3 and the collector of transistor Q4 are both grounded; the gate of MOS tube N9 is electrically connected to the gate of MOS tube N20, the gate of MOS tube N21, the gate of MOS tube N25 and the gate of MOS tube N27 respectively, for inputting bias voltage V B5; the source of the MOS tube N9 is electrically connected to the drain of the MOS tube N10, and the gate of the MOS tube N10 is electrically connected to the gate of the MOS tube N11, the gate of the MOS tube N17, the gate of the MOS tube N18, the gate of the MOS tube N22 and the gate of the MOS tube N24, respectively, for inputting the bias voltage VB4; the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N17, the source of the MOS tube N18, the source of the MOS tube N22 and the source of the MOS tube N24 are all grounded; The gate of MOS transistor P27 is electrically connected to the drain of MOS transistor P27, the drain of MOS transistor N16, the gate of MOS transistor N16, the gate of MOS transistor N19 and the gate of MOS transistor N28 respectively; the drain of MOS transistor N19 is electrically connected to the source of MOS transistor N20; the drain of MOS transistor N22 is electrically connected to the source of MOS transistor N21; the drain of MOS transistor N24 is electrically connected to the source of MOS transistor N25; the drain of MOS transistor N28 is electrically connected to the source of MOS transistor N27; the source of MOS transistor N16 is electrically connected to the drain of MOS transistor N17; the source of MOS transistor N17, the drain of MOS transistor P28, the source of MOS transistor N19 and the source of MOS transistor N28 are all grounded; The drain of the MOS tube N31 is electrically connected to the gate of the MOS tube N12, and the drain of the MOS tube N12 is used to access the power supply VCC; the gate of the MOS tube N31 is electrically connected to the gate of the MOS tube N23, the drain of the MOS tube N23, the drain of the MOS tube P34 and the gate of the MOS tube N29 respectively, and the source of the MOS tube N23 and the source of the MOS tube N29 are both grounded; the source of the MOS tube N31 is electrically connected to the drain of the MOS tube N18; The gate of the MOS transistor P29 is electrically connected to the gate of the MOS transistor P31, the drain of the MOS transistor P29, and the source of the MOS transistor P30 respectively; the drain of the MOS transistor P31 is electrically connected to the source of the MOS transistor P323; the gate of the MOS transistor P30 is electrically connected to the gate of the MOS transistor P32, the drain of the MOS transistor P30, and the drain of the MOS transistor N20 respectively; the drain of the MOS transistor P32 is electrically connected to the drain of the MOS transistor N21 and the input end of the Schmitt trigger SMT respectively; the output end of the Schmitt trigger SMT outputs the signal Inrush through the inverter INV1; The gate of the MOS tube P33 is used to input the bias voltage VB7, the drain of the MOS tube P33 is electrically connected to the source of the MOS tube P34, the gate of the MOS tube P34 is used to input the bias voltage VB6, and the drain of the MOS tube P34 is electrically connected to the drain of the MOS tube N23; The gate of MOS tube P35 is electrically connected to the gate of MOS tube P37, the drain of MOS tube P35 and the source of MOS tube P36 respectively. The drain of MOS tube P37 is electrically connected to the source of MOS tube P38. The gate of MOS tube P36 is electrically connected to the gate of MOS tube P38, the drain of MOS tube P36 and the drain of MOS tube N26 respectively. The gate of MOS tube N26 is electrically connected to the output end of inverter INV2. The source of MOS tube N26 is electrically connected to MOS The drain of the MOS tube N25 is electrically connected, the drain of the MOS tube P37 is electrically connected to the source of the MOS tube P38; the drain of the MOS tube P38 is electrically connected to the drain of the MOS tube N27, the gate of the MOS tube P28 and the drain of the MOS tube N30 respectively, which is the output end of the operational amplifier LOAMP, the gate of the MOS tube N30 is electrically connected to the input end of the inverter INV2 for inputting the enable signal EN, and the source of the MOS tube N30 is electrically connected to the drain of the MOS tube N29.

9. A current limiting circuit for power over Ethernet according to claim 1, characterized in that: The power tube M1 is an NMOS tube.

10. The current limiting circuit for Ethernet power supply according to claim 1, characterized in that: The load resistor R1 is made of a metal layer parasitic resistor, and has a resistance of 80 mΩ.

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