Image sensor and readout circuit therefor

Abstract

The application provides an image sensor and a readout circuit thereof, wherein the readout circuit of the image sensor is connected with a ramp voltage circuit, a comparison circuit, a counter circuit and a negation control circuit; when switching the count, the counter circuit is controlled by the negation control circuit to negate the first digital code value to obtain the second digital code value; the counter circuit counts on the basis of the second digital code value to obtain the third digital code value in the second quantization time period; the correlated double sampling is realized; the fixed pattern noise is eliminated; the imaging quality is improved; no buffer and additional holding circuit are arranged in the readout circuit; the circuit structure is simplified; the power consumption is reduced; and the counter circuit can work in the high-frequency counting mode.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to an image sensor and its readout circuit. Background Technology

[0002] CMOS image sensors offer advantages such as low voltage, low power consumption, low cost, and high integration, making them valuable for applications in machine vision, consumer electronics, high-definition surveillance, and medical imaging. The analog-to-digital converter (ADC) is a crucial component of the readout circuitry of a CMOS image sensor, responsible for converting the analog signals output from pixels into digital signals. CMOS image sensors typically employ column-level ADCs, commonly including single-slope ADCs (SS SDC), successive approximation ADCs (SAR ADCs), and cyclic ADCs.

[0003] The counters in traditional SS ADCs are generally reversible counters, meaning they can switch between counting up and down, such as... Figure 1 As shown, the N-bit counter circuit consists of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage serves as the clock signal for the next stage, which is the up-counting mode; when count_up is 0, the output signal Q of the non-inverting output terminal of this stage serves as the clock signal for the next stage, which is the down-counting mode. After two count stops, the final count result D is... <n-1:0>Stored in memory.

[0004] Because the count_clk operates at a very high frequency (typically several hundred MHz or even exceeding 1 GHz), and traditional reversible counters require inserting 2-to-1 data selectors and buffers for driving between each counter stage, power consumption increases. Simultaneously, this structure faces the challenge of maintaining the stability of the first quantization result during up / down counting transitions, requiring additional hold circuitry, making the circuit layout more complex, increasing parasitic capacitance and resistance of the traces, further increasing power consumption, and limiting the maximum operating frequency of the counter. Summary of the Invention

[0005] The purpose of this invention is to provide a readout circuit for an image sensor, which aims to solve the problems of high power consumption and complex structure of traditional reversible counters.

[0006] A first aspect of this invention provides a readout circuit for an image sensor, comprising:

[0007] The ramp voltage circuit is configured to output ramp voltage signals during the first quantization time period and the second quantization time period of the pixel unit, respectively.

[0008] The comparison circuit has its first input terminal connected to the pixel unit and its second input terminal connected to the ramp voltage circuit. It is configured to compare the reset signal or pixel signal output by the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal.

[0009] A counter circuit, connected to the comparator circuit, is configured to count the first pulse signal and store the first digital code value during the first quantization time period; during the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, wherein the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal, respectively.

[0010] An inversion control circuit, connected to the counter circuit, outputs an inversion control signal triggered by a mode selection signal between the first quantization time period and the second quantization time period, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value into the second digital code value and store it.

[0011] A second aspect of the present invention provides an image sensor, including a pixel array, a control circuit, and a plurality of readout circuits for the image sensor as described above, wherein the pixel array includes a plurality of pixel units arranged in an array.

[0012] Each of the image sensors has a readout circuit that is connected to a plurality of pixel units arranged in a column, and each of the image sensors has a readout circuit that is also connected to the control circuit.

[0013] The beneficial effects of the present invention embodiment compared with the prior art are as follows: The readout circuit of the above-mentioned image sensor is connected by a ramp voltage circuit, a comparison circuit, a counter circuit and an inversion control circuit. When switching the count, the inversion control circuit controls the counter circuit to invert the first digital code value to the second digital code value. In the second quantization period, the counter circuit counts the second digital code value to obtain the third digital code value, realizing correlated double sampling, eliminating fixed pattern noise, improving imaging quality, and eliminating the need for buffers and additional holding circuits in the readout circuit, simplifying the circuit structure, reducing power consumption, and ensuring that the counter circuit works in high-frequency counting mode. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a circuit diagram of a traditional counter circuit;

[0016] Figure 2 This is a schematic diagram of the structure of the image sensor provided in Embodiment Six of the present invention;

[0017] Figure 3 for Figure 2 The circuit diagram of the pixel unit in the image sensor shown is shown.

[0018] Figure 4 This is a schematic diagram of the readout circuit provided in Embodiment 1 of the present invention;

[0019] Figure 5 This is a schematic diagram of the readout circuit provided in Embodiment 2 of the present invention;

[0020] Figure 6 This is a circuit diagram of the readout circuit provided in Embodiment 3 of the present invention;

[0021] Figure 7 These are schematic diagrams of the signal timing of the readout circuits provided in Embodiments 3 and 4 of the present invention;

[0022] Figure 8 This is a circuit diagram of the readout circuit provided in Embodiment 4 of the present invention;

[0023] Figure 9 These are schematic diagrams of the D flip-flops provided in Embodiments 3 and 4 of the present invention;

[0024] Figure 10 This is a schematic diagram of the readout circuit provided in Embodiment 5 of the present invention;

[0025] Figure 11 for Figure 10 The circuit diagram shown is a schematic of the storage circuit in the readout circuit. Detailed Implementation

[0026] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] Example 1

[0029] A first aspect of this invention provides a readout circuit for an image sensor, such as... Figure 2 As shown, an image sensor typically includes a control circuit 3, a pixel array 100, and a readout circuit 1. It may also include a clock generator and a digital I / O port. The pixel array 100 includes multiple pixel units arranged in an array. Multiple pixel units arranged in columns are connected together. The control circuit 3 selects each row of pixel units through a row selection signal and outputs the pixel signals of each row to the readout circuit 1 in sequence. Multiple pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3 so that the control circuit 3 can determine the image information based on the digital code value.

[0030] A pixel unit typically includes a photoelectric conversion element, a transmission transistor (TX), a reset transistor (RST), a source follower transistor (SF), and a row selection transistor (SEL). The photoelectric conversion element includes, but is not limited to, a photodiode (PD), such as a pin-type photodiode (PD). The number of photoelectric conversion elements, transmission transistors (TX), reset transistors (RST), source follower transistors (SF), and row selection transistors (SEL) can be one or more; that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transmission transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The cathode of the photodiode PD is connected to the first terminal of the transmission transistor TX. The second terminal of the transmission transistor TX, the first terminal of the reset transistor RST, and the controlled terminal of the source follower transistor SF are all coupled to the floating diffusion node. The anode of the photodiode PD is grounded. The second terminal of the reset transistor RST and the first terminal of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second terminal of the source follower transistor SF is connected to the first terminal of the row select transistor SEL. The second terminal of the row select transistor SEL constitutes the output terminal of the pixel unit 2 and is used to output the corresponding pixel signal.

[0031] CMOS image sensors employing column-arranged readout circuits (1) face the problem of fixed-pattern noise (FPN). This is because factors such as process technology and temperature cause a certain degree of mismatch in the threshold voltages of the transistors in each column of pixels. Under the same illumination, this mismatch leads to a deterioration in the column consistency of the pixel output signal. Using a method such as... Figure 3 The 4T active pixel structure shown can perform Correlated Double Sampling (CDS) operation, reading out the pixel's reset signal Vrst and exposure signal Vsig respectively, and then subtracting the two. Since both signals contain the same fixed pattern noise (FPN), the FPN can be eliminated by subtracting, thus improving image quality.

[0032] A common CDS operation involves using two ramp signals in an SS ADC to quantize the pixel's reset signal Vrst and exposure signal Vsig twice, respectively. A counter circuit is then controlled to count down and up during each quantization period, thus subtracting the analog voltage value output by the pixel in the digital domain. Therefore, the counter circuit in this structure is a reversible counter, meaning it can switch between counting up and down, as shown below. Figure 1 As shown, the N-bit counter circuit consists of cascaded counter units. When count_up is 1, the output signal QB of the inverting output terminal of this stage serves as the clock signal count_clk for the next stage, which is the up-counting mode; when count_up is 0, the output signal Q of the non-inverting output terminal of this stage serves as the clock signal count_clk for the next stage, which is the down-counting mode. After two count stops, the final count result D is... <n-1:0>Stored in memory.

[0033] Because the count_clk operates at a very high frequency (typically several hundred MHz or even exceeding 1 GHz), and traditional reversible counters require the insertion of a 2-to-1 data selector MUX1 and a buffer for driving between each counter unit, power consumption increases. Simultaneously, this structure faces the challenge of maintaining the stability of the first quantization result during up / down counting transitions, requiring additional hold circuitry, making the circuit layout more complex, increasing parasitic capacitance and resistance of the traces, further increasing power consumption, and limiting the maximum operating frequency of the counter.

[0034] To solve the above technical problems, such as Figure 4 As shown, in this embodiment, the readout circuit 1 of the image sensor includes:

[0035] The ramp voltage circuit 10 is configured to output ramp voltage signals during the first quantization time period and the second quantization time period of the pixel unit, respectively.

[0036] The comparator circuit 20 has its first input terminal connected to the pixel unit and its second input terminal connected to the ramp voltage circuit 10. It is configured to compare the reset signal or pixel signal output by the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal.

[0037] The counter circuit 30 is connected to the comparator circuit 20 and is configured to count the first pulse signal during a first quantization period and store the first digital code value; during a second quantization period, the counter circuit 30 counts the second pulse signal based on the second digital code value and stores it as a third digital code value. The first pulse signal and the second pulse signal are respectively a reset pulse signal and a pixel pulse signal.

[0038] The inverting control circuit 40 is connected to the counter circuit 30. Between the first quantization time period and the second quantization time period, it is triggered by the mode selection signal mode_sel to output the inverting control signal trig_pulse, so that the counter circuit 30 is triggered by the inverting control signal trig_pulse to invert the first digital code value into the second digital code value and store it.

[0039] In this embodiment, the ramp voltage circuit 10 generates two ramp voltage signals during the first quantization time period and the second quantization time period. The slope and gain of the two ramp voltage signals may be the same or different.

[0040] The ramp voltage signal corresponding to the time period is output to the comparator circuit 20. The comparator circuit 20 receives the reset signal or pixel signal of the pixel unit in the corresponding time period. The reset signal and the pixel signal are compared with the ramp voltage signal respectively. The reset signal and the ramp voltage signal are compared in the first quantization time period or the second quantization time period to generate a reset pulse signal. The pixel signal and the ramp voltage signal are compared in another quantization time period to generate a pixel pulse signal.

[0041] During the first quantization period, the counter circuit 30 counts the reset pulse signal or the pixel pulse signal upwards or downwards. When the first quantization ends, the counter circuit 30 generates and stores the first quantized digital code value. The counter circuit 30 has a rewritable function, that is, it inverts the digital code value stored by itself according to the invert control signal trig_pulse. For example, it inverts the first digital code value 0100 to generate 1011.

[0042] Between two quantization time periods, the inverting control circuit 40 receives the mode selection signal mode_sel and correspondingly triggers the output of the inverting control signal trig_pulse. The counter circuit 30 inverts its stored first digital code value according to the received inverting control signal trig_pulse to generate a second digital code value, which serves as the initial state for the second quantization, i.e., as the base value for the counter circuit 30 in the second counting.

[0043] At the beginning of the second quantization period, the mode selection signal mode_sel switches states, the counter circuit 30 returns to counting mode, and quantizes the second pulse signal during the second quantization period. The counter circuit 30 counts up or down based on the second digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, and the second quantization ends.

[0044] Since the second quantization is based on the inverted digital code value of the first quantization result, it is equivalent to performing a difference operation on the two digital code values. For example, if the first quantization result is the reset signal Vrst, and the inverted result is -Vrst, the second quantization result of the pixel signal is -Vrst + Vsig. Since the two signals contain the same FPN, the FPN can be eliminated by subtracting, thus improving the image quality.

[0045] Meanwhile, by adopting inverted counting, the counter circuit 30 does not need to switch between counting up and counting down, nor does it need to set up an additional holding circuit. Only the corresponding inverted control circuit 40 needs to be added. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, thus achieving the purpose of reducing power consumption.

[0046] The ramp voltage circuit 10 can be equipped with a corresponding signal source, voltage generation circuit, etc., for example... Figure 2 The ramp generator shown can employ a comparator or similar structure for its comparator circuit 20. Optionally, for example... Figure 2 As shown, the comparator circuit 20 includes a first capacitor, a second capacitor, and a comparator. The first terminal of the first capacitor is connected to the signal terminal of the ramp generation circuit. The first terminal of the second capacitor is used to input the reset signal or pixel signal output by the pixel unit. The second terminal of the first capacitor is connected to the non-inverting input terminal of the comparator, and the second terminal of the second capacitor is connected to the inverting input terminal of the comparator. When the ramp voltage signal is less than the corresponding reset signal or pixel signal, the comparator outputs a low level, and the counter circuit 30 starts counting. When the ramp voltage signal is greater than the corresponding reset signal or pixel signal, the comparator outputs a high level, and the counter circuit 30 stops counting. At this time, the counting result is the digital code value after signal quantization.

[0047] The quantization order of the reset pulse signal and the pixel pulse signal can be set according to requirements. The reset pulse signal can be quantized first, followed by the pixel pulse signal, or vice versa. The counter circuit 30 is configured to count the reset pulse signal and store the first digital code value during the first quantization period, and to count the pixel pulse signal based on the second digital code value during the second quantization period and store it as the third digital code value.

[0048] Alternatively, the counter circuit 30 is configured to count the pixel pulse signal and store a first digital code value during a first quantization time period, and to count the reset pulse signal based on the second digital code value during a second quantization time period and store it as a third digital code value.

[0049] When the reset pulse signal is quantized first and the pixel pulse signal is quantized later, during the first quantization period, the counter circuit 30 first quantizes the reset pulse signal and generates a first digital code value, such as Vrst. Between the two quantization periods, the counter circuit 30 receives the invert control signal trig_pulse and inverts the first digital code value corresponding to the reset pulse signal to generate a second digital code value, i.e., -Vrst. During the second quantization period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, i.e., -Vrst+Vsig. Since the two signals contain the same FPN, the FPN can be eliminated by subtraction, thus improving the imaging quality.

[0050] Alternatively, when the pixel pulse signal is quantized first and the reset pulse signal is quantized later, during the first quantization period, the counter circuit 30 first quantizes the pixel pulse signal and generates a first digital code value, such as Vsig. Between the two quantization periods, the counter circuit 30 receives the invert control signal trig_pulse and inverts the first digital code value corresponding to the pixel pulse signal to a second digital code value, i.e., generating -Vsig. During the second quantization period, the pixel pulse signal is quantized again, and the counter circuit 30 counts based on the second digital code value and generates a third digital code value, i.e., -Vsig+Vrst. Since the two signals contain the same FPN, the FPN can be eliminated by subtracting them, thus improving the imaging quality.

[0051] The counter circuit 30 can adopt a corresponding D flip-flop (DFF), latch, or other structure, and the inverting control circuit 40 can adopt a signal source, selection circuit, or other structure.

[0052] The beneficial effects of the present invention embodiment compared with the prior art are as follows: The readout circuit 1 of the above-mentioned image sensor is connected by a ramp voltage circuit 10, a comparison circuit 20, a counter circuit 30 and an inversion control circuit 40. When switching the count, the inversion control circuit 40 controls the counter circuit 30 to invert the first digital code value to obtain the second digital code value. In the second quantization period, the counter circuit 30 counts based on the second digital code value to obtain the third digital code value, realizing correlated double sampling, eliminating fixed pattern noise, improving imaging quality, and in the readout circuit 1, there is no need to set up a buffer and an additional holding circuit, which simplifies the circuit structure, reduces power consumption, and ensures that the counter circuit 30 works in high-frequency counting mode.

[0053] Example 2

[0054] Based on Embodiment 1, optimizations and specific modifications are made, such as... Figure 5 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0055] The inverting control circuit 40 includes n selection circuits. The first input terminal of the i-th selection circuit is used to input the inverting control signal trig_pulse. The second input terminal of the first selection circuit 41 is used to input the clock signal count_clk. The third input terminal of the first selection circuit 41 is used to input the comparator output signal cmp_out. The second input terminals of the second selection circuits 42 to the n-th selection circuit are connected to the output terminal of the (i-1)-th stage counter unit. The output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..., n.

[0056] The i-th selection circuit is controlled by the mode selection signal mode_sel, which outputs either the inverted control signal trig_pulse or the clock signal count_clk.

[0057] The first counter unit 31 to the nth counter unit are configured to count the first pulse signal during the first quantization time period and store the first count value of the current stage respectively. The count values ​​of each counter unit are combined to generate a first digital code value. Between the first quantization time period and the second quantization time period, the first counter unit 31 to the nth counter unit are inverted by the invert control signal trigger_pulse and stored as a second count value. The count values ​​of each counter unit are combined to generate a second digital code value.

[0058] During the second quantization period, the first counter unit 31 to the nth counter unit count the second pulse signal based on the second count value and store it as the third count value. The count values ​​of each counter unit are combined to generate the third digital code value.

[0059] In this embodiment, taking the first quantization reset pulse signal and the second quantization pixel pulse signal as examples, each selection circuit is connected to the front end of a counter unit and outputs the corresponding signal from the signal input terminal to its own output terminal according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and during the first quantization time period, the pixel unit outputs a reset signal to the comparator circuit 20. The comparator circuit 20 compares the reset signal with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection between its own second input terminal and output terminal. The first selection circuit 41 outputs a clock signal count_clk to the first counter unit 31. The subsequent selection circuit selects and outputs the count value of the previous stage counter unit to the next stage counter unit. Each stage counter unit stores the first count value of its own stage, and the first count values ​​of each stage counter unit are combined to generate the first digital code value.

[0060] Between the first quantization time period and the second quantization time period, the mode selection signal mode_sel switches to the second level. Each selection circuit outputs the invert control signal trig_pulse from the first input terminal to the counter unit at the back end. Each counter unit switches to invert mode and inverts the first count value stored in its internal memory to the second count value. The second count values ​​stored in each counter unit are combined to generate the second digital code value. Then, the mode selection signal mode_sel switches back to the first level, and the invert control signal trig_pulse also switches its level state. Each counter unit switches to counting mode.

[0061] During the second quantization period, each selection circuit triggers the output clock signal count_clk to the back-end counter unit based on the received first-level mode selection signal mode_sel. Each counter unit counts the second pulse signal based on the second count value and stores it as the third count value. The count values ​​of each counter unit are combined to generate the third digital code value and read out accordingly. Thus, a complete quantization cycle is completed, and the third digital code value obtained by subtracting the pixel reset signal and the pixel signal is finally obtained, eliminating fixed mode noise and improving image quality.

[0062] The selection circuit can be selected from corresponding switch structures, selectors, etc., and the counter unit can be selected from corresponding flip-flops, latches, etc.

[0063] Example 3

[0064] Based on Embodiment 2, further optimizations and modifications are made. In one optional embodiment, such as... Figure 6 As shown, the first selection circuit 41 includes an AND gate AND1, a 2-to-1 data selector MUX1, and a first inverter U1;

[0065] The first input terminal of AND gate AND1 is used to input the clock signal count_clk, the second input terminal of AND gate AND1 is used to input the comparator output signal cmp_out, the first input terminal of 2-to-1 data selector MUX1 is used to input the inverting control signal trig_pulse, the output terminal of AND gate AND1 is connected to the second input terminal of 2-to-1 data selector MUX1, the output terminal of 2-to-1 data selector MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 constitutes the output terminal of the first selection circuit 41;

[0066] The second selection circuit 42 to the nth selection circuit each include a 2-to-1 data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input terminal of the 2-to-1 data selector MUX1 is used to input the inverting control signal trig_pulse, the second input terminal of the 2-to-1 data selector MUX1 is used to input the value output by the previous stage counter unit, the output terminal of the 2-to-1 data selector MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 is used to form the output terminal of its selection circuit.

[0067] The counter unit includes a D flip-flop DFF and a second inverter U2;

[0068] The clock signal count_clk terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF. The output terminal of the second inverter U2 is connected to the second input terminal of the i+1-th selection circuit.

[0069] In this embodiment, the inverted output of the D flip-flop DFF is connected to the first inverter U1, and the output of the first inverter U1 serves as the counting output of the counter unit to achieve upward counting.

[0070] refer to Figure 6 and Figure 7 Before quantization, at time t1-t2, count_rst switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0071] At time t3, the first quantization is performed. At this time, the comparator output signal cmp_out switches to a high level. The clock signal count_clk is ANDed with the high level by an AND gate, and the clock signal count_clk is output to the second input of the 2-to-1 data selector MUX1. At this time, the mode selection signal mode_sel is high, and the clock signal count_clk is selected and output to the first inverter U1 and then to the D flip-flop DFF. The D flip-flop DFF counts up under the action of the clock signal count_clk.

[0072] At time t4, the output of comparator circuit 20 flips, the counting stops, the first quantization ends, the count value of the first quantization result is stored in each D flip-flop DFF, and the first count value output by each second inverter U2 is combined to generate the first digital code value.

[0073] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to invert mode.

[0074] At time t6, the inverting control signal trig_pulse switches to a low level and is selected by the 2-to-1 data selector MUX1 to output to the first inverter U1. A rising edge is generated at the clock input of the D flip-flop DFF, inverting the count value of the first quantization result stored in the D flip-flop DFF as the initial state before the second quantization. The second count values ​​output by each of the second inverters U2 are combined to generate the second digital code value.

[0075] At time t7, the mode selection signal mode_sel switches to high level, and the counter unit returns to counting mode. At time t8, the inverting control signal trig_pulse switches to high level.

[0076] At time t9, the second quantization of the pixel pulse signal begins from the initial state. At time t10, the output of comparator circuit 20 flips, the counting stops, and the second quantization ends. Between times t11 and t12, the final quantization result is stored in the corresponding memory module and then read out. This completes one full quantization cycle, ultimately yielding the digital code value obtained by subtracting the pixel's reset signal Vrst and exposure signal Vsig.

[0077] Example 4

[0078] Based on Embodiment 2, further optimizations and modifications are made. In another optional embodiment, such as... Figure 8 As shown, the first selection circuit 41 includes an AND gate AND1, a 2-to-1 data selector MUX1, and a first inverter U1;

[0079] The first input terminal of AND gate AND1 is used to input the clock signal count_clk, the second input terminal of AND gate AND1 is used to input the comparator output signal cmp_out, the first input terminal of 2-to-1 data selector MUX1 is used to input the inverting control signal trig_pulse, the output terminal of AND gate AND1 is connected to the second input terminal of 2-to-1 data selector MUX1, the output terminal of 2-to-1 data selector MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 constitutes the output terminal of the first selection circuit 41;

[0080] The second selection circuit 42 to the nth selection circuit each include a 2-to-1 data selector MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input terminal of the 2-to-1 data selector MUX1 is used to input the inverting control signal trig_pulse, the second input terminal of the 2-to-1 data selector MUX1 is used to input the value output by the previous stage counter unit, the output terminal of the 2-to-1 data selector MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 is used to form the output terminal of its selection circuit.

[0081] Optionally, the counter unit includes a D flip-flop (DFF);

[0082] The clock signal count_clk terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the data input terminal of the D flip-flop DFF. The non-inverted output terminal of the D flip-flop DFF is connected to the second input terminal of the i+1-th selection circuit.

[0083] In this embodiment, the non-inverting output of the D flip-flop DFF serves as the counting output of the counter unit, enabling downward counting.

[0084] refer to Figure 7 and Figure 8 Before quantization, at time t1-t2, count_rst switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0085] At time t3, the first quantization is performed. At this time, the comparator output signal cmp_out switches to a high level. The clock signal count_clk is ANDed with the high level by an AND gate, and the clock signal count_clk is output to the second input of the 2-to-1 data selector MUX1. At this time, the mode selection signal mode_sel is high, and the clock signal count_clk is selected and output to the first inverter U1 and then to the D flip-flop DFF. The D flip-flop DFF counts down under the action of the clock signal count_clk.

[0086] At time t4, the output of comparator circuit 20 flips, the counting stops, the first quantization ends, and the count value of the first quantization result is stored in each D flip-flop (DFF). The first count value output by each D flip-flop (DFF) is combined to generate the first digital code value.

[0087] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to invert mode.

[0088] At time t6, the inverting control signal trig_pulse switches to a low level and is selected by the 2-to-1 data selector MUX1 to output to the first inverter U1. A rising edge is generated at the clock input of the D flip-flop DFF, inverting the count value of the first quantization result stored in the D flip-flop DFF as the initial state before the second quantization. The second count values ​​output by each D flip-flop DFF are combined to generate the second digital code value.

[0089] At time t7, the mode selection signal mode_sel switches to high level, and the counter unit returns to counting mode. At time t8, the inverting control signal trig_pulse switches to high level.

[0090] At time t9, the second quantization of the pixel pulse signal begins from the initial state. At time t10, the output of comparator circuit 20 flips, the counting stops, and the second quantization ends. Between times t11 and t12, the final quantization result is stored in the corresponding memory module and then read out. This completes one full quantization cycle, ultimately yielding the digital code value obtained by subtracting the pixel's reset signal Vrst and exposure signal Vsig.

[0091] In order to achieve the inversion function of the D flip-flop (DFF) in Embodiments 3 and 4 above, as follows: Figure 9 As shown, optionally, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3, and a fourth transmission gate tran4.

[0092] The input terminal of the third inverter U3 forms the data input terminal of the D flip-flop (DFF). The output terminal of the third inverter U3, the source and drain of the PMOS transistor of the first transmission gate tran1 are connected together. The drain and source of the PMOS transistor of the first transmission gate tran1, the drain and source of the PMOS transistor of the first transmission gate tran1, the drain and source of the PMOS transistor of the second transmission gate tran2, and the input terminal of the fourth inverter U4 are connected together. The output terminal of the fourth inverter U4, the input terminal of the fifth inverter U5, the source and drain of the PMOS transistor of the third inverter U3 are connected together. The output terminal of the fifth inverter U5, the source and drain of the PMOS transistor of the second transmission gate tran2, and the drain and source of the NMOS transistor of the second transmission gate tran2 are connected together. The drain and source of the PMOS transistor of the third transmission gate tran3, the input terminal of the sixth inverter U6, and the fourth transmission gate tran4 are connected together. The drain of the PMOS transistor in the first transmission gate tran1 and the source of the NMOS transistor in the fourth transmission gate tran4 are connected together. The source of the PMOS transistor in the fourth transmission gate tran4, the drain of the NMOS transistor in the fourth transmission gate tran4, and the output of the seventh inverter U7 are connected together. The output of the sixth inverter U6, the input of the seventh inverter U7, and the input of the eighth inverter U8 are connected together. The output of the eighth inverter U8 constitutes the positive output of the D flip-flop DFF. The gates of the PMOS transistor in the first transmission gate tran1, the NMOS transistor in the second transmission gate tran2, the NMOS transistor in the third transmission gate tran3, and the PMOS transistor in the fourth transmission gate tran4 are connected together and input the clock signal count_clk. The gates of the NMOS transistor in the first transmission gate tran1, the PMOS transistor in the second transmission gate tran2, the PMOS transistor in the third transmission gate tran3, and the NMOS transistor in the fourth transmission gate tran4 are connected together and input the inverted signal of the clock signal count_clk.

[0093] In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5, and the second transmission gate tran2 form a master-level latch, and the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7, and the fourth transmission gate tran4 form a slave-level latch. The master-level latch is used to stably latch and output the input value of the D flip-flop DFF, and the slave-level latch is used to stably latch and output the output value of the master-level latch. The third inverter U3 is used to invert the input data signal and output it to the master-level latch, and the eighth inverter U8 is used to invert the output value of the slave-level latch. When the clock signal count_clk of the D flip-flop DFF receives a rising edge, the third inverter U3, the master-level latch, the slave-level latch, and the eighth inverter U8 invert the latched value and output it.

[0094] Example 5

[0095] Based on Embodiment 1, optimizations and specific modifications are made, such as... Figure 10 As shown, optionally, the readout circuit 1 of the image sensor further includes:

[0096] The storage circuit 50 is connected to the counter circuit 30 and is used to store the third digital code value, which is triggered to be read out by the readout control signal.

[0097] In this embodiment, after the counter circuit 30 completes the second quantization, it obtains the difference between the digital code values ​​corresponding to the reset pulse signal and the pixel pulse signal, i.e., the third digital code value, which is then referenced. Figure 7 As shown, during times t11-t12, the write signal output to the storage circuit 50 is enabled at a high level, writing the final quantization result into the storage circuit 50, and then reading it out. This completes one full quantization cycle, ultimately obtaining the digital code value obtained by subtracting the pixel's reset signal Vrst and exposure signal Vsig.

[0098] The storage circuit 50 can be selected as a single memory Mem or multiple memory Mem. When a single memory Mem is used, the memory Mem has multiple storage partitions, each of which stores a third count value. Multiple third count values ​​are combined to generate a third digital code value. When multiple memory Mem are used, each memory Mem stores a third count value.

[0099] In an alternative embodiment, such as Figure 11 As shown, the storage circuit 50 includes;

[0100] There are n memory units Mem, each connected to a counter unit, and each storing the count value of the corresponding number of bits of the third digital code value.

[0101] In this embodiment, a storage circuit 50 is composed of multiple memories Mem, each storing a third count value. Optionally, to simplify the structure, the memory of the memory Mem is 1 bit.

[0102] Example 6

[0103] This invention also proposes an image sensor, such as Figure 2 As shown, the image sensor includes a pixel array 100, a control circuit 3, and multiple image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The pixel array 100 includes multiple pixel units arranged in an array.

[0104] Each image sensor's readout circuit 1 is connected to a column of multiple pixel units, and each image sensor's readout circuit 1 is also connected to a control circuit 3.

[0105] In this embodiment, the image sensor typically includes a control circuit 3, a pixel array 100, and a readout circuit 1. It may also include a clock generator and a digital I / O port. The pixel array 100 includes multiple pixel units arranged in an array. Multiple pixel units arranged in columns are connected together. The control circuit 3 selects each row of pixel units through a row selection signal and outputs the pixel signals of each row to the readout circuit 1 in sequence. Multiple pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3 so that the control circuit 3 can determine the image information based on the digital code value.

[0106] A pixel unit typically includes a photoelectric conversion element, a transmission transistor (TX), a reset transistor (RST), a source follower transistor (SF), and a row selection transistor (SEL). The photoelectric conversion element includes, but is not limited to, a photodiode (PD), such as a pin-type photodiode (PD). The number of photoelectric conversion elements, transmission transistors (TX), reset transistors (RST), source follower transistors (SF), and row selection transistors (SEL) can be one or more; that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transmission transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The cathode of the photodiode PD is connected to the first terminal of the transmission transistor TX. The second terminal of the transmission transistor TX, the first terminal of the reset transistor RST, and the controlled terminal of the source follower transistor SF are all coupled to the floating diffusion node. The anode of the photodiode PD is grounded. The second terminal of the reset transistor RST and the first terminal of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second terminal of the source follower transistor SF is connected to the first terminal of the row select transistor SEL. The second terminal of the row select transistor SEL constitutes the output terminal of the pixel unit 2 and is used to output the corresponding pixel signal.

[0107] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, characterized in that, include: The ramp voltage circuit is configured to output ramp voltage signals during the first quantization time period and the second quantization time period of the pixel unit, respectively. The comparison circuit has its first input terminal connected to the pixel unit and its second input terminal connected to the ramp voltage circuit. It is configured to compare the reset signal or pixel signal output by the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal. A counter circuit, connected to the comparator circuit, is configured to count the first pulse signal and store the first digital code value during the first quantization time period; during the second quantization time period, the counter circuit counts the second pulse signal based on the second digital code value and stores it as a third digital code value, wherein the first pulse signal and the second pulse signal are the reset pulse signal and the pixel pulse signal, respectively. An inversion control circuit, connected to the counter circuit, outputs an inversion control signal triggered by a mode selection signal between the first quantization time period and the second quantization time period, so that the counter circuit is triggered by the inversion control signal to invert the first digital code value into the second digital code value and store it.

2. The readout circuit of the image sensor as described in claim 1, characterized in that, The counter circuit is configured to count the reset pulse signal and store the first digital code value during the first quantization time period, and to count the pixel pulse signal based on the second digital code value during the second quantization time period and store it as the third digital code value. Alternatively, the counter circuit is configured to count the pixel pulse signal during the first quantization time period and store the first digital code value, and during the second quantization time period, count the reset pulse signal based on the second digital code value and store it as the third digital code value.

3. The readout circuit of the image sensor as described in claim 1, characterized in that, The counter circuit includes a first counter unit to an nth counter unit; The inverting control circuit includes n selection circuits. The first input terminal of the i-th selection circuit is used to input the inverting control signal, the second input terminal of the first selection circuit is used to input the clock signal, the third input terminal of the first selection circuit is used to input the output signal of the comparator, the second input terminals of the second selection circuit to the n-th selection circuit are connected to the output terminal of the (i-1)-th stage counter unit, and the output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..., n. The i-th selection circuit outputs the inverted control signal or the clock signal based on the mode selection signal; The first counter unit to the nth counter unit are configured to count the first pulse signal during the first quantization time period and store the first count value of their respective levels. The count values ​​of each counter unit are combined to generate the first digital code value. Between the first quantization time period and the second quantization time period, the first counter unit to the nth counter unit are inverted by the inverting control signal and stored as a second count value. The count values ​​of each counter unit are combined to generate the second digital code value. During the second quantization time period, the first counter unit to the nth counter unit counts the second pulse signal based on the second count value and stores it as a third count value. The count values ​​of each counter unit are combined to generate the third digital code value.

4. The readout circuit of the image sensor as described in claim 3, characterized in that, The first selection circuit includes an AND gate, a 2-to-1 data selector, and a first inverter; The first input terminal of the AND gate is used to input the clock signal, the second input terminal of the AND gate is used to input the output signal of the comparator, the first input terminal of the 2-to-1 data selector is used to input the inverting control signal, the output terminal of the AND gate is connected to the second input terminal of the 2-to-1 data selector, the output terminal of the 2-to-1 data selector is connected to the input terminal of the first inverter, and the output terminal of the first inverter constitutes the output terminal of the first selection circuit. The second to nth selection circuits each include a 2-to-1 data selector and a first inverter. In the second to nth selection circuits, the first input terminal of the 2-to-1 data selector is used to input the inverting control signal, the second input terminal of the 2-to-1 data selector is used to input the value output by the previous stage counter unit, the output terminal of the 2-to-1 data selector is connected to the input terminal of the first inverter, and the output terminal of the first inverter is used to form the output terminal of its selection circuit.

5. The readout circuit of the image sensor as described in claim 3, characterized in that, The counter unit includes a D flip-flop and a second inverter; The clock signal terminal of the D flip-flop in the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop in the i-th stage counter unit is connected to the input terminal of the second inverter and the data input terminal of the D flip-flop. The output terminal of the second inverter is connected to the second input terminal of the (i+1)-th selection circuit.

6. The readout circuit of the image sensor as described in claim 3, characterized in that, The counter unit includes a D flip-flop; The clock signal terminal of the D flip-flop in the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit, the inverted output terminal of the D flip-flop in the i-th stage counter unit is connected to the data input terminal of the D flip-flop, and the non-inverted output terminal of the D flip-flop is connected to the second input terminal of the (i+1)-th stage selection circuit.

7. The readout circuit of the image sensor as described in claim 5 or 6, characterized in that, The D flip-flop includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; The input terminal of the third inverter constitutes the data input terminal of the D flip-flop. The output terminal of the third inverter, the source of the PMOS transistor of the first transmission gate, and the drain of the NMOS transistor of the first transmission gate are all connected together. The drain of the PMOS transistor of the first transmission gate, the source of the NMOS transistor of the first transmission gate, the drain of the PMOS transistor of the second transmission gate, the source of the NMOS transistor of the second transmission gate, and the input terminal of the fourth inverter are all connected together. The output terminal of the fourth inverter, the input terminal of the fifth inverter, the source of the PMOS transistor of the third inverter, and the drain of the NMOS transistor of the third inverter are all connected together. The output terminal of the fifth inverter, the source of the PMOS transistor of the second transmission gate, and the drain of the NMOS transistor of the second transmission gate are all connected together. The drain of the PMOS transistor of the third transmission gate, the source of the NMOS transistor of the third transmission gate, and the input terminal of the sixth inverter are all connected together. The drain of the PMOS transistor of the fourth transmission gate and the source of the NMOS transistor of the fourth transmission gate are connected together. The source of the PMOS transistor of the fourth transmission gate, the drain of the NMOS transistor of the fourth transmission gate, and the output terminal of the seventh inverter are connected together. The output terminal of the sixth inverter, the input terminal of the seventh inverter, and the input terminal of the eighth inverter are connected together. The output terminal of the eighth inverter constitutes the positive output terminal of the D flip-flop. The gates of the PMOS transistor of the first transmission gate, the NMOS transistor of the second transmission gate, the NMOS transistor of the third transmission gate, and the PMOS transistor of the fourth transmission gate are connected together and input a clock signal. The gates of the NMOS transistor of the first transmission gate, the PMOS transistor of the second transmission gate, the PMOS transistor of the third transmission gate, and the NMOS transistor of the fourth transmission gate are connected together and input an inverted clock signal.

8. The readout circuit of the image sensor as described in claim 3, characterized in that, The readout circuit of the image sensor also includes: A storage circuit, connected to the counter circuit, is used to store the third digital code value and is triggered to be read out by a readout control signal.

9. The readout circuit of the image sensor as described in claim 8, characterized in that, The storage circuit includes; n memories, each connected to one of the counter units, and each storing the count value of the corresponding number of bits of the third digital code value.

10. An image sensor, characterized in that, It includes a pixel array, a control circuit, and a readout circuit of a plurality of image sensors as described in any one of claims 1 to 9, wherein the pixel array includes a plurality of pixel units arranged in an array; Each of the image sensors has a readout circuit that is connected to a plurality of pixel units arranged in a column, and each of the image sensors has a readout circuit that is also connected to the control circuit.

Images