Image sensor and readout circuit therefor

Abstract

The application provides an image sensor and a readout circuit thereof, wherein the readout circuit of the image sensor comprises a slope voltage circuit, a comparison circuit, a counter circuit, a storage circuit and a NOT control circuit; the image sensor circuit quantizes a reset signal into a first digital code value and stores the reset signal in a reset sampling period; in a first exposure sampling period, the image sensor circuit quantizes a first pixel pulse signal on the basis of a second digital code value, so as to realize correlated double sampling; in a second exposure sampling period, the image sensor circuit quantizes a second pixel pulse signal on the basis of a fourth digital code value, so as to realize correlated double sampling; the second digital code value and the fourth digital code value are NOT values corresponding to the first digital code value; in the whole quantization process, the reset signal needs to be quantized only once; the pixel signals read out twice are time-division multiplexed by the counter circuit; one set of readout circuit can complete the quantization of the two pixel pulse signals, so that the structure of the image sensor is simplified and the power consumption is reduced.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to an image sensor and its readout circuit. Background Technology

[0002] CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application value in fields such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.

[0003] First, ALL Direction Auto Focus (ADAF) plays a crucial role in image sensors, such as... Figure 1 The pixel array shown has four pixels arranged in a 2×2 pattern, sharing a single floating diffuser node and a source follower transistor. During readout, TXA and TXC are first turned on to read the signals from the two rightmost pixels, obtaining the right phase information; then TXB and TXD are turned on to read the signals from the two leftmost pixels, obtaining the left phase information. Using these two phase information, the phase difference can be calculated for autofocus.

[0004] Secondly, dynamic range is a key factor in the imaging quality of an image sensor. Dual Conversion Gain (DCG) is applied to the pixel circuit of an image sensor. Under low illumination conditions, a smaller integral capacitor is used to increase the conversion gain to improve sensitivity; under high illumination conditions, a larger integral capacitor is used to increase the stored charge and reduce the conversion gain to improve dynamic range.

[0005] Correlated Double Sampling (CDS) can eliminate thermal noise and some fixed-pattern noise caused by pixel reset, significantly improving the noise performance of image sensors. CDS requires reading the pixel's reset signal Vrst and exposure signal Vsig separately, then subtracting them. Therefore, using CDS in a four-phase pixel structure or dual-conversion gain technology requires two sets of readout circuits per pixel column: one set to quantize the reset signal and the right pixel signal or high-gain pulse signal, and the other set to quantize the reset signal and the left pixel signal or low-gain pulse signal. This increases the structural complexity and power consumption of the image sensor. Summary of the Invention

[0006] The purpose of this invention is to provide a readout circuit for an image sensor, which aims to solve the problems of complex structure and high power consumption in traditional four-phase pixel structures or CDS technology used in dual-conversion gain technology.

[0007] A first aspect of this invention provides a readout circuit for an image sensor, the readout circuit comprising:

[0008] A ramp voltage circuit, configured to output a ramp voltage signal;

[0009] The comparison circuit has its first input terminal connected to the pixel unit and its second input terminal connected to the ramp voltage circuit. It is configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal and output at least one reset pulse signal and two pixel pulse signals at intervals.

[0010] A counter circuit, connected to a comparator circuit, is configured to count at least one reset pulse signal during at least one reset sampling period and store it as at least one first digital code value; and during a first exposure sampling period, to count a first pixel pulse signal based on a second digital code value and store it as a third digital code value; and during a second exposure sampling period, to count a second pixel pulse signal based on a fourth digital code value and store it as a fifth digital code value.

[0011] The storage circuit, connected to the counter circuit, is configured to store at least one first digital code value, and before the second exposure sampling period, is triggered by a write-back control signal to write back one of the at least one first digital code values ​​to the counter circuit;

[0012] The inverting control circuit, connected to the counter circuit and the storage circuit, is triggered by the mode selection signal to output an inverting control signal to the counter circuit before each exposure sampling period. This triggers the counter circuit to invert the first digital code value in memory to generate a second or fourth digital code value.

[0013] A second aspect of the present invention provides an image sensor, including a pixel array, a control circuit, and a readout circuit of a plurality of image sensors as described above, wherein the pixel array includes a plurality of pixel units arranged in an array.

[0014] Each image sensor's readout circuit is connected to a column of multiple pixel units, and each image sensor's readout circuit is also connected to a control circuit.

[0015] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The image sensor circuit described above quantizes the reset signal into a first digital code value and stores it during the reset sampling period; during the first exposure sampling period, it quantizes the first pixel pulse signal based on the second digital code value to achieve correlated double sampling; and during the second exposure sampling period, it quantizes the second pixel pulse signal based on the fourth digital code value to achieve correlated double sampling. The second and fourth digital code values ​​are the inverse values ​​of the corresponding first digital code values. In the entire quantization process, only the reset signal needs to be quantized once, and the two read-out pixel signals are time-division multiplexed using a set of counter circuits. Therefore, only one readout circuit is needed to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. Based on the quantization results of the two pixel pulse signals, image information is determined to achieve autofocus or high dynamic range, thereby improving imaging quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a first type of circuit for a pixel unit provided in an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of the readout circuit provided in an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the junction circuit of a pixel unit or sub-pixel provided in an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of the readout circuit provided in an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the first signal timing of the readout circuit provided in an embodiment of the present invention;

[0022] Figure 6 This is a second signal timing diagram of the readout circuit provided in an embodiment of the present invention;

[0023] Figure 7 This is a first circuit diagram of the readout circuit provided in an embodiment of the present invention;

[0024] Figure 8 This is a third signal timing diagram of the readout circuit provided in an embodiment of the present invention;

[0025] Figure 9 This is a fourth signal timing diagram of the readout circuit provided in an embodiment of the present invention;

[0026] Figure 10 This is a second circuit diagram of the readout circuit provided in an embodiment of the present invention;

[0027] Figure 11 This is a third circuit diagram of the readout circuit provided in an embodiment of the present invention;

[0028] Figure 12 This is a circuit diagram of the D flip-flop in the readout circuit provided in an embodiment of the present invention. Detailed Implementation

[0029] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0031] Example 1

[0032] A first aspect of this invention provides a readout circuit for an image sensor, such as... Figure 2 As shown, an image sensor typically includes a control circuit 3, a pixel array 100, and a readout circuit 1. It may also include a clock generator and a digital I / O port. The pixel array 100 includes multiple pixel units arranged in an array. Multiple pixel units arranged in columns are connected together. The control circuit 3 selects each row of pixel units through a row selection signal and outputs the pixel signals of each row to the readout circuit 1 in sequence. Multiple pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3 so that the control circuit 3 can determine the image information based on the digital code value.

[0033] In this context, a pixel unit typically has at least one sub-pixel, for example... Figure 1 The pixel unit shown includes at least four sub-pixels arranged in a 2×2 pattern, wherein at least two sub-pixels form a pixel group and are controlled to output a reset signal Vrst or a pixel signal simultaneously. The sub-pixels in the pixel unit can be grouped in pairs or in other combinations, and the specific grouping method is not limited.

[0034] Each sub-pixel typically includes a photoelectric conversion element, a transmission transistor (TX), a reset transistor (RST), a source follower transistor (SF), and a row selection transistor (SEL). The photoelectric conversion element includes, but is not limited to, a photodiode (PD), such as a pin-type photodiode (PD). The number of photoelectric conversion elements, transmission transistors (TX), reset transistors (RST), source follower transistors (SF), and row selection transistors (SEL) can be one or more; that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. Figure 3 As shown, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transmission transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The cathode of the photodiode PD is connected to the first terminal of the transmission transistor TX. The second terminal of the transmission transistor TX, the first terminal of the reset transistor RST, and the controlled terminal of the source follower transistor SF are all coupled to the floating diffusion node. The anode of the photodiode PD is grounded. The second terminal of the reset transistor RST and the first terminal of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second terminal of the source follower transistor SF is connected to the first terminal of the row select transistor SEL. The second terminal of the row select transistor SEL constitutes the output terminal of the pixel unit 2 and is used to output the corresponding pixel signal.

[0035] When a pixel unit comprises at least four sub-pixels arranged in a 2×2 pattern, the four sub-pixels share a single floating diffuser node (FD) and a source follower transistor. During readout, TXA and TXC are first turned on to read the signals of the two rightmost pixels, obtaining right phase information; then TXB and TXD are turned on to read the signals of the two leftmost pixels, obtaining left phase information. (Alternatively: first, TXA and TXB are turned on to read the signals of the two uppermost pixels, obtaining upper phase information; then TXC and TXD are turned on to read the signals of the two lowermost pixels, obtaining lower phase information). Using this phase information, the phase difference can be calculated for autofocus.

[0036] To simplify the structure of the image sensor and its readout circuit 1 and reduce power consumption, in this embodiment, as follows: Figure 4 As shown, the readout circuit 1 includes:

[0037] The ramp voltage circuit 10 is configured to output a ramp voltage signal;

[0038] The comparator circuit 20 has its first input terminal connected to the pixel unit and its second input terminal connected to the ramp voltage circuit 10. It is configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal and output at least one reset pulse signal and two pixel pulse signals at intervals.

[0039] The counter circuit 30, connected to the comparator circuit 20, is configured to count at least one reset pulse signal during at least one reset sampling period and store it as at least one first digital code value; and during a first exposure sampling period, to count a first pixel pulse signal based on a second digital code value and store it as a third digital code value; and during a second exposure sampling period, to count a second pixel pulse signal based on a fourth digital code value and store it as a fifth digital code value.

[0040] The storage circuit 50, connected to the counter circuit 30, is configured to store at least one first digital code value, and before the second exposure sampling period, is triggered by the write-back control signal rewrite_en to write back one of the at least one first digital code values ​​to the counter circuit 30.

[0041] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, it is triggered by the mode selection signal mode_sel to output the inversion control signal trigger_pulse to the counter circuit 30, so as to trigger the counter circuit 30 to invert the first digital code value in memory to generate the second digital code value or the fourth digital code value.

[0042] In this embodiment, the ramp voltage circuit 10 may output the same or different ramp voltage signals during the reset sampling period and the exposure sampling period, and the specific magnitude is set according to the voltage amplitude of the reset signal and the pixel signal.

[0043] The reset signal Vrst may include one or more, and correspondingly, the reset sampling period may be one or more. When there is one reset signal Vrst, during the reset sampling period, the comparator circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts the reset pulse signal up or down, and when the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the reset signal Vrst ends, the counter circuit 30 counts to generate a first digital code value and stores it in itself and writes it into the storage circuit 50.

[0044] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored first digital code value to the second digital code value as the initial state for the first exposure sampling period. Then, the counter circuit 30 returns to counting mode. During the first exposure sampling period, the comparator circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates the first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops working, the quantization of the first pixel pulse signal ends, and the counter circuit 30 counts to generate the third digital code value. The third digital code value is the difference between the first pixel signal and the digital code value corresponding to the reset signal Vrst, realizing correlated double sampling, reducing noise impact, and improving image quality.

[0045] Afterwards, the counter circuit 30 resets. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal `rewrite_en` and writes back the stored first digital code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal `trig_pulse` and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the counter circuit 30 resumes counting mode and quantizes the second pixel signal during the second exposure sampling period. Comparison circuit 2... The second pixel signal is compared with the pixel ramp voltage signal, and a second pixel pulse signal is generated. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the second pixel pulse signal ends, and the counter circuit 30 generates a fifth digital code value. The fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the reset signal Vrst, realizing correlation double sampling, reducing noise impact, and improving imaging quality.

[0046] Meanwhile, the third and fifth digital code values ​​obtained from the two quantizations are finally stored in the storage circuit 50 and read out to the corresponding control circuit 3 under the control of the readout control signal. The control circuit 3 determines the image information based on the third and fifth digital code values.

[0047] When the reset signal Vrst includes two reset signals Vrst corresponding to two pixel signals, during the first reset sampling period, the comparator circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30, which counts the first reset pulse signal up or down. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal Vrst1 ends, and the counter circuit 30 counts to generate the first first digital code value and writes it into the storage circuit 50.

[0048] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparator circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal and generates a second reset pulse signal. The second reset pulse signal is output to the counter circuit 30, which counts the second reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the second reset signal Vrst ends, and the counter circuit 30 counts to generate a second first digital code value and stores it internally.

[0049] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored second first digital code value to a second digital code value as the initial state for the first exposure sampling period. Then, the counter circuit 30 returns to counting mode. During the first exposure sampling period, the comparator circuit 20 compares the first pixel signal with the pixel ramp voltage signal and generates the first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops working, the quantization of the first pixel pulse signal ends, and the counter circuit 30 generates a third digital code value. The third digital code value is the difference between the first pixel signal and the digital code value corresponding to the second reset signal Vrst2, realizing correlated double sampling, reducing noise impact, and improving image quality.

[0050] Afterwards, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first digital code value to the counter circuit 30. At the same time, the counter circuit 30 receives the invert control signal trig_pulse and inverts the first written-back digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the counter circuit 30 resumes counting mode and quantizes the second pixel signal during the second exposure sampling period. The comparator circuit 20 compares the second pixel signal with the pixel ramp voltage signal and generates a second pixel pulse signal. The second pixel pulse signal is output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the second pixel pulse signal ends, and the counter circuit 30 generates a fifth digital code value. The fifth digital code value is the difference between the second pixel signal and the digital code value corresponding to the second reset signal Vrst2, realizing correlated double sampling, reducing noise impact, and improving image quality.

[0051] Meanwhile, the third and fifth digital code values ​​obtained from the two quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. The control circuit 3 determines the image information based on the third and fifth digital code values.

[0052] During the entire quantization process, only the reset signal Vrst needs to be quantized once, and the two readout pixel signals are time-division multiplexed using a set of counter circuits 30. Therefore, only one set of readout circuits 1 is needed to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. Based on the quantization results of the two pixel pulse signals, image information is determined to achieve autofocus or high dynamic range, thereby improving image quality.

[0053] The ramp voltage circuit 10 can be a corresponding signal source, voltage generation circuit, etc., such as a ramp generator. The comparator circuit 20 can be a comparator or the like. Optionally, the comparator circuit 20 includes a first capacitor, a second capacitor, and a comparator. The first terminal of the first capacitor is connected to the signal terminal of the ramp generation circuit. The first terminal of the second capacitor is used to input the reset signal Vrst or pixel signal output by the pixel unit. The second terminal of the first capacitor is connected to the non-inverting input terminal of the comparator. The second terminal of the second capacitor is connected to the inverting input terminal of the comparator. When the ramp voltage signal is less than the corresponding reset signal Vrst or pixel signal, the comparator outputs a low level, and the counter circuit 30 starts counting. When the ramp voltage signal is greater than the corresponding reset signal Vrst or pixel signal, the comparator outputs a high level, and the counter circuit 30 stops counting. At this time, the counting result is the digital code value after signal quantization.

[0054] The counter circuit 30, the inverting control circuit 40, and the storage circuit 50 can be specifically determined according to the corresponding reset signal Vrst, the type of pixel signal, and the input / output logic.

[0055] Furthermore, the write-back path of the storage circuit 50 can be either a direct output to the counter circuit 30 or an indirect output to the counter circuit 30 via the inverting control circuit 40; the specific write-back method is not limited.

[0056] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-described image sensor circuit quantizes the reset signal Vrst into a first digital code value and stores it during the reset sampling period; during the first exposure sampling period, it quantizes the first pixel pulse signal based on the second digital code value to achieve correlated double sampling; and during the second exposure sampling period, it quantizes the second pixel pulse signal based on the fourth digital code value to achieve correlated double sampling. The second digital code value and the fourth digital code value are the inverse values ​​of the corresponding first digital code value. In the entire quantization process, only the reset signal Vrst needs to be quantized once, and the two read-out pixel signals are time-division multiplexed using a set of counter circuits 30. Therefore, only one set of readout circuits 1 is needed to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. Based on the quantization results of the two pixel pulse signals, image information is determined to achieve autofocus or high dynamic range, thereby improving imaging quality.

[0057] Example 2

[0058] Based on the optimization and specification of Embodiment 1, in an optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in a 2×2 array, wherein at least two sub-pixels constitute a pixel group and are controlled to output a reset signal Vrst or a pixel signal.

[0059] At least one reset signal Vrst is a reset signal Vrst generated when pixel units are reset simultaneously;

[0060] The first pixel pulse signal and the second pixel pulse signal are respectively one of the pixel group pulse signal under simultaneous exposure of the pixel group and the image pulse signal under simultaneous exposure of the sub-pixels in the pixel unit.

[0061] In this embodiment, the readout circuit 1 is suitable for ADAF technology. Four sub-pixels share a floating diffusion node and a source follower transistor. During readout, the pixel group is first turned on, and the pixel group signal Vsigl of at least two sub-pixels in the pixel group is read out. For example, the right two pixel signals are read out to obtain the right phase information.

[0062] Then all sub-pixels of the pixel unit are turned on, and the image signal Vsig corresponding to the pixel unit is read out. Correspondingly, the comparison circuit 20 obtains the full phase information.

[0063] Specifically, refer to Figure 5 As shown, during the reset sampling period, the comparator circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30, which counts the reset pulse signal up or down. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the reset signal Vrst ends, and the counter circuit 30 counts to generate the first digital code value and stores it in itself and writes it into the storage circuit 50.

[0064] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored first digital code value to the second digital code value as the initial state for the first exposure sampling period. Then, the counter circuit 30 returns to counting mode. During the first exposure sampling period, the comparator circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal and generates a pixel group pulse signal. The pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops working, the quantization of the pixel group pulse signal ends, and the counter circuit 30 generates a third digital code value. The third digital code value is the difference between the pixel group signal Vsigl and the corresponding digital code value of the reset signal Vrst, i.e., Vsigr-Vrst, which realizes correlated double sampling, reduces noise impact, and improves image quality.

[0065] Afterwards, the counter circuit 30 resets. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal `rewrite_en` and writes back the stored first digital code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal `trig_pulse` and inverts the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the counter circuit 30 resumes counting mode and quantizes the image signal `Vsig` during the second exposure sampling period. The comparison circuit 20 then... The image signal Vsig is compared with the pixel ramp voltage signal to generate an image pulse signal. The image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the image pulse signal ends, and the counter circuit 30 generates a fifth digital code value. The fifth digital code value is the difference between the digital code value corresponding to the second pixel signal and the reset signal Vrst, i.e., Vsigr + Vsigl - Vrst. This achieves correlation double sampling, reduces noise, and improves image quality.

[0066] Meanwhile, the third and fifth digital code values ​​obtained from the two quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. Based on the fifth and third digital code values, the control circuit 3 can determine the left and right pixel information or the top and bottom pixel information, and obtain the phase difference through the pixel information to perform autofocus and improve the user experience.

[0067] Furthermore, during the quantization process, only one reset signal Vrst needs to be quantized, and the two read pixel signals are time-division multiplexed using a set of counter circuits 30, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, enabling autofocus and improving image quality.

[0068] Example 3

[0069] Based on Embodiment 1, further optimizations and specificities are made. In another optional embodiment, the reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal.

[0070] The first pixel pulse signal and the second pixel pulse signal are respectively one of the high-gain image pulse signal and the low-gain image pulse signal;

[0071] The counter circuit 30 is configured to count one of the reset pulse signals during the first reset sampling period and generate a first digital code value.

[0072] During the second reset sampling period, another reset pulse signal is counted to generate another first digital code value;

[0073] During the first exposure sampling period, the pulse signal of the first pixel is counted based on the second digital code value and stored as the third digital code value;

[0074] During the second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as the fifth digital code value.

[0075] In this embodiment, the readout circuit 1 is suitable for HDR technology. The pixel unit or sub-pixel includes different integrating capacitors and switches between different integrating capacitors under different illumination conditions. Specifically, under low illumination conditions, a smaller integrating capacitor is used to increase the conversion gain and improve sensitivity; under high illumination conditions, a larger integrating capacitor is used to increase the stored charge and reduce the conversion gain to improve the dynamic range.

[0076] Correspondingly, the reset signal Vrst includes a low-gain reset signal lcg_rst and a high-gain reset signal hcg_rst, see reference. Figure 6As shown, during the first reset sampling period, the comparator circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30, which counts the first reset pulse signal up or down. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the first reset signal Vrst1 ends, and the counter circuit 30 counts to generate the first digital code value and writes it into the storage circuit 50.

[0077] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparator circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal and generates a second reset pulse signal, which is output to the counter circuit 30. The counter circuit 30 counts the second reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting. The quantization of the second reset signal Vrst2 ends, and the counter circuit 30 counts to generate a second first digital code value and stores it internally.

[0078] Among them, the second reset signal Vrst2 and the first reset signal Vrst1 are respectively a high-gain reset signal hcg_rst and a low-gain reset signal lcg_rst. Correspondingly, the second reset pulse signal and the first reset pulse signal are respectively a high-gain reset pulse signal and a low-gain reset pulse signal.

[0079] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored second first digital code value to a second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal. The first pixel signal and the second reset signal Vrst2 are the image signal and reset signal Vrst2 at the same gain. For example, t represents the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, respectively. The first pixel pulse signal is generated by comparison and output to the counter circuit 30. The counter circuit 30 counts the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops working, the quantization of the first pixel pulse signal ends, and the counter circuit 30 counts to generate the third digital code value. The third digital code value is the difference between the digital code value corresponding to the first pixel signal and the second reset signal Vrst2, realizing correlation double sampling, reducing the influence of noise, and improving the imaging quality.

[0080] Subsequently, the counter circuit 30 is reset. Before the second exposure sampling period, the storage circuit 50 receives the write-back control signal `rewrite_en` and writes back the stored first digital code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal `trig_pulse` and inverts the written-back first digital code value to generate a fourth digital code value. This fourth digital code value serves as the initial state for the second exposure sampling. Then, the counter circuit 30 resumes counting mode and quantizes the second pixel signal during the second exposure sampling period. The second pixel signal and the first reset signal `Vrst1` are the image signal and reset signal `Vrst` at the same gain, for example, the low-gain image signal and reset signal `Vrst`, respectively. The second pixel signal is compared with the pixel ramp voltage signal by the comparator circuit 20 using the lcg_sig and low-gain reset signals lcg_rst. The second pixel pulse signal is then output to the counter circuit 30. The counter circuit 30 counts the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, marking the end of the second pixel pulse signal quantization. The counter circuit 30 then generates a fifth digital code value, which is the difference between the second pixel signal and the corresponding digital code value of the first reset signal Vrst1. This achieves correlated double sampling, reduces noise, and improves image quality.

[0081] Meanwhile, the third and fifth digital code values ​​obtained from the two quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. The control circuit 3 determines the image information based on the third and fifth digital code values.

[0082] During the entire quantization process, only the reset signal Vrst needs to be quantized once, and the two readout pixel signals are time-division multiplexed using a set of counter circuits 30. Therefore, only one set of readout circuits 1 is needed to complete the quantization of two pixel pulse signals, which simplifies the structure of the image sensor and reduces power consumption. The image information is determined based on the quantization results of the two pixel pulse signals, achieving high dynamic range and improving imaging quality.

[0083] Corresponding to the signal input / output logic of Embodiments 2 and 3 above, optionally, as follows: Figure 7 As shown, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0084] The storage circuit 50 includes n storage units, such as the first storage unit 51, the second storage unit 52, etc., and each storage unit is connected to a counter unit and an inverting control circuit 40 respectively.

[0085] Each memory cell includes a first memory Mem1, a second memory Mem2, and a NOR gate NOR1;

[0086] The input terminals of the first memory Mem1 and the second memory Mem2 are respectively connected to a counter unit. The output terminal of the first memory Mem1 is connected to the first input terminal of the NOR gate NOR1. The second input terminal of the NOR gate NOR1 is used to input the write-back control signal rewrite_en. The NOR gate NOR1 constitutes the output terminal of the memory unit.

[0087] The first memory Mem1 is configured to store a corresponding bit count value in at least one first digital code value;

[0088] The first memory Mem1 and the second memory Mem2 respectively store the corresponding bit count value of one of the third digital code value and the fifth digital code value.

[0089] When applied to the readout circuit 1 of Embodiment 2, refer to Figure 4 , Figure 5 and Figure 7As shown, during the reset sampling period, the comparator circuit 20 compares the reset signal Vrst with the reset ramp voltage signal and generates a reset pulse signal. The reset pulse signal is input to the counter circuit 30 and output to the first counter unit 31 to the nth counter unit through the inverting control circuit 40. The n counter units count the reset pulse signal up or down. When the output of the comparator circuit 20 flips, the n counter units stop counting, the quantization of the reset signal Vrst ends, the n counter units count and generate the count values ​​of each bit of the first digital code value and store them, and store the count values ​​of each bit of the first digital code value into the first memory Mem1 respectively.

[0090] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The n counter units switch to inverting mode and invert the stored first digital code value to a second digital code value, serving as the initial state for the first exposure sampling period. Then, the n counter units return to counting mode. During the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal and generates a pixel group pulse signal. The pixel group pulse signal is transmitted through the inverting control circuit... The output of circuit 40 is sent to n counter units. The n counter units count the pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparator circuit 20 flips, the n counter units stop counting, the quantization of the pixel group pulse signal ends, and the n counter units count to generate a third digital code value. The third digital code value is the difference between the digital code value corresponding to the pixel group signal Vsigr and the reset signal Vrst, i.e., Vsigr-Vrst. This achieves correlation double sampling, reduces noise, and improves image quality. The n-bit count value in the third digital code value is stored in n second memories Mem2 respectively.

[0091] Afterwards, the n counter units are reset. Before the second exposure sampling period, the first memory Mem1 receives the write-back control signal rewrite_en and writes the stored first digital code value back to the counter circuit 30 through the NOR gate NOR1 and the inversion control circuit 40. At the same time, the n counter units receive the inversion control signal trigger_pulse and invert the written-back first digital code value to generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the n counter units resume counting mode and quantize the image signal Vsig during the second exposure sampling period. The comparison circuit 20 converts the image signal... The signal Vsig is compared with the pixel ramp voltage signal to generate an image pulse signal. The image pulse signal is output to n counter units. The n counter units count the image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the image pulse signal ends, and the counter circuit 30 generates a fifth digital code value. The n-bit count value of the fifth digital code value is stored in the first memory Mem1. The fifth digital code value is the difference between the digital code value corresponding to the second pixel signal and the reset signal Vrst, i.e., Vsigr + Vsigl - Vrst, which realizes correlation double sampling, reduces the influence of noise, and improves the imaging quality.

[0092] When applied to the readout circuit 1 of Embodiment 3, refer to Figure 4 , Figure 6 and Figure 7 As shown, during the first reset sampling period, the comparator circuit 20 compares the first reset signal Vrst1 with the reset ramp voltage signal and generates a first reset pulse signal. The first reset pulse signal corresponds to the pulse signal of the high-gain reset signal hcg_rst or the low-gain reset signal lcg_rst. The first reset pulse signal is input to n counter units through the inverting control circuit 40. The n counter units count the first reset pulse signal up or down. When the output of the comparator circuit 20 flips, the n counter units stop counting, the quantization of the first reset signal Vrst1 ends, the n counter units count to generate count values, and the n count values ​​are combined to generate the first first digital code value and written into n first memories Mem1.

[0093] Before the second reset sampling period, n counter units are reset. During the second reset sampling period, the comparator circuit 20 compares the second reset signal Vrst2 with the reset ramp voltage signal. The second reset signal Vrst2 and the first reset signal Vrst1 are respectively a high-gain reset signal hcg_rst and a low-gain reset signal lcg_rst, generating a second reset pulse signal. The second reset pulse signal and the first reset pulse signal are respectively a high-gain reset pulse signal and a low-gain reset pulse signal. The second reset pulse signal is output to the n counter units through the inverting control circuit 40. The n counter units count the second reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the n counter units stop counting. The quantization of the second reset signal Vrst2 ends. The n counter units count and generate n count values. The n count values ​​are combined to generate the second first digital code value and stored in the n counter units themselves.

[0094] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel and outputs the inversion control signal trigger_pulse to the n counter units. The n counter units switch to inversion mode and invert their stored count values. The inverted count values ​​are combined to generate a second digital code value, which serves as the initial state for the first exposure sampling period. Then, the n counter units return to counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal, generating the first pixel pulse signal. The pixel pulse signal is output to n counter units through the inversion control circuit 40. The n counter units count the first pixel pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the n counter units stop working, the quantization of the first pixel pulse signal ends, and the n counter units count to generate the third digital code value. Each bit of the third digital code value is stored in each of the second memories Mem2. The third digital code value is the difference between the digital code value corresponding to the first pixel signal and the second reset signal Vrst2, realizing correlation double sampling, reducing the impact of noise and improving the imaging quality.

[0095] Subsequently, the n counter units are reset. Before the second exposure sampling period, each of the first memories Mem1 receives the write-back control signal rewrite_en and writes back the stored first digital code value to the n counter units. At the same time, the n counter units receive the invert control signal trigger_pulse and invert the first written-back digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the n counter units resume counting mode and quantize the second pixel signal during the second exposure sampling period. The comparison circuit 20 compares the second pixel signal with the pixel ramp voltage signal. The second pixel pulse signal is generated and output to n counter units. The n counter units count the second pixel pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the n counter units stop counting, the quantization of the second pixel pulse signal ends, and the n counter units count to generate a fifth digital code value. The fifth digital code value is the difference between the digital code value of the second pixel signal and the digital code value corresponding to the first reset signal Vrst1. The n-bit count value of the fifth digital code value is stored in n first memories Mem1 respectively to realize correlation double sampling, reduce noise influence, and improve imaging quality.

[0096] Example 4

[0097] Based on the optimization and specification of Embodiment 1, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in a 2×2 array, wherein at least two sub-pixels constitute a pixel group and are controlled to output a reset signal Vrst or a pixel signal simultaneously.

[0098] The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0099] The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of pixel groups in low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in pixel units.

[0100] The second exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period;

[0101] The first digital code value includes a first sub-digit code value and a second sub-digit code value;

[0102] The counter circuit 30 is configured to count the low-gain reset pulse signal during the first reset sampling period and generate the first sub-digit code value.

[0103] During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value;

[0104] During the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as the third digital code value;

[0105] The fifth digit code value includes the fifth sub-digit code value and the sixth sub-digit code value;

[0106] During the third exposure sampling period, the pulse signal of the low-gain pixel group is counted based on the fourth digital code value and stored as the fifth sub-digital code value;

[0107] During the fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as the sixth sub-digital code value;

[0108] The storage circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digit code value. Before the third exposure sampling period and the fourth exposure sampling period, the first sub-digit code value is written back to the counter circuit 30 by the write-back control signal rewrite_en.

[0109] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the counter circuit 30 is triggered by the inversion control signal trigger_pulse to invert the first sub-digital code value in memory to generate the fourth digital code value, and to invert the second sub-digital code value to generate the second digital code value.

[0110] In this embodiment, the readout circuit 1 is suitable for achieving autofocus under low conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain image pulse signal. The second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of pixel groups in low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in pixel units.

[0111] refer to Figure 8During the first reset sampling period, the comparator circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal, generates a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low-gain reset pulse signal up or down, and stops counting when the output of the comparator circuit 20 flips. The quantization of the low-gain reset signal lcg_rst ends, and the counter circuit 30 counts to generate the first sub-digit code value and writes it into the storage circuit 50.

[0112] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparator circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, which counts the high-gain reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst ends, and the counter circuit 30 counts to generate the second sub-digit code value and stores it internally.

[0113] Before the first exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored second sub-digit code value to the second digital code value as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to counting mode. During the first exposure sampling period, the comparator circuit 20 compares the high-gain image signal hcg_sig with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparator circuit 20 flips, the counter circuit 30 stops working, the quantization of the high-gain image pulse signal ends, and the counter circuit 30 generates a third digital code value. The third digital code value is the difference between the high-gain image signal hcg_sig and the corresponding digital code value of the high-gain reset signal hcg_rst, realizing correlated double sampling, reducing noise impact, and improving image quality.

[0114] Afterwards, the counter circuit 30 is reset. Before the third exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digit code value to the counter circuit 30. At the same time, the counter circuit 30 receives the invert control signal trig_pulse and inverts the written-back first sub-digit code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the third exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the low-gain pixel group signal lcg_sigl during the third exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with... The pixel ramp voltage signals are compared, and a low-gain pixel group pulse signal is generated. The low-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain pixel group pulse signal ends, and the counter circuit 30 generates a fifth sub-digital code value. The fifth sub-digital code value is the difference between the digital code value corresponding to the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, realizing correlated double sampling, reducing noise impact, and improving image quality.

[0115] Then, the counter circuit 30 resets again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digit code value to the counter circuit 30. At the same time, the counter circuit 30 receives the invert control signal trigger_pulse and inverts the written-back first sub-digit code value to generate the fourth digital code value. The fourth digital code value serves as the initial state for the fourth exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the low-gain image signal lcg_sig during the fourth exposure sampling period. The comparator circuit 20 then quantizes the low-gain image signal lcg_sig. The ig signal is compared with the pixel ramp voltage signal, and a low-gain image pulse signal is generated. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain image pulse signal ends, and the counter circuit 30 generates the sixth sub-digital code value. The sixth sub-digital code value is the difference between the digital code value corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, realizing correlation double sampling, reducing noise impact, and improving image quality.

[0116] Meanwhile, the third, fifth, and sixth sub-digital codes obtained from the three quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. The control circuit 3 determines the image information based on the third, fifth, and sixth sub-digital codes and realizes autofocus in low conversion gain mode, thereby improving image quality and user experience.

[0117] Example 5

[0118] Based on the optimization and specification of Embodiment 1, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes four sub-pixels arranged in a 2×2 array, wherein two sub-pixels form a pixel group and are controlled to output a reset signal Vrst or a pixel signal.

[0119] The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0120] The first pixel pulse signal includes the high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in high-gain mode and the high-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0121] The second pixel pulse signal includes a low-gain image pulse signal;

[0122] The first exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period;

[0123] The first digital code value includes a first sub-digit code value and a second sub-digit code value;

[0124] The counter circuit 30 is configured to count the low-gain reset pulse signal during the first reset sampling period and generate the first sub-digit code value.

[0125] During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value;

[0126] The third digital code value includes the third sub-digit code value and the fourth sub-digit code value;

[0127] During the third exposure sampling period, the pulse signal of the high-gain pixel group is counted based on the second digital code value and stored as the third sub-digital code value;

[0128] During the fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as the fourth sub-digital code value;

[0129] During the second exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as the fifth digital code value;

[0130] The storage circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digital code value and the second sub-digital code value. Before the fourth exposure sampling period and the second exposure sampling period, it is triggered by the write-back control signal rewrite_en to write back the second sub-digital code value and the first sub-digital code value to the counter circuit 30.

[0131] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the counter circuit 30 is triggered by the inversion control signal trig_pulse to invert the second sub-digit code value in memory to generate a second digital code value, and to invert the first sub-digit code value to generate a fourth digital code value.

[0132] In this embodiment, the readout circuit 1 is suitable for achieving autofocus under high conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset signal lcg_rst. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of pixel groups in high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in pixel units. The second pixel pulse signal includes a low-gain image pulse signal.

[0133] refer to Figure 9 During the first reset sampling period, the comparator circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal, generates a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low-gain reset pulse signal up or down, and stops counting when the output of the comparator circuit 20 flips. The quantization of the low-gain reset signal lcg_rst ends, and the counter circuit 30 counts to generate the first sub-digit code value and writes it into the storage circuit 50.

[0134] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparator circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, which counts the high-gain reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst ends, and the counter circuit 30 counts to generate the second sub-digit code value and stores it internally.

[0135] Before the third exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored second sub-digit code value to the second digit code value, which serves as the initial state for the third exposure sampling period. Then, the counter circuit 30 returns to counting mode and quantizes the high-gain pixel group signal hcg_sigl during the third exposure sampling period. The comparator circuit 20 compares the high-gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The high-gain pixel group pulse signal is generated and output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain pixel group pulse signal ends, and the counter circuit 30 generates a third sub-digital code value. The third sub-digital code value is the difference between the digital code value corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, realizing correlation double sampling, reducing noise influence, and improving imaging quality.

[0136] Then, the counter circuit 30 resets again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal `rewrite_en` and writes back the stored second sub-digit code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal `trig_pulse` and inverts the written-back second sub-digit code value to generate a second digital code value. This second digital code value serves as the initial state for the fourth exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the high-gain image signal `hcg_sig` during the fourth exposure sampling period. The comparator circuit 20 then quantizes the high-gain image signal `hcg_s`. The ig signal is compared with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain image pulse signal ends, and the counter circuit 30 generates a fourth sub-digital code value. The fourth sub-digital code value is the difference between the digital code value corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst. This achieves correlation double sampling, reduces noise, and improves image quality.

[0137] Then, the counter circuit 30 resets again, and before the second exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digit code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal trig_pulse and inverts the written-back first sub-digit code value to generate a fourth digit code value. This fourth digit code value serves as the initial state for the second exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the low-gain image signal lcg_sig during the second exposure sampling period. The comparator circuit 20 then quantizes the low-gain image signal lcg_... The sig signal is compared with the pixel ramp voltage signal, and a low-gain image pulse signal is generated. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain image pulse signal ends, and the counter circuit 30 generates a fifth digital code value. The fifth digital code value is the difference between the digital code value corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, realizing correlation double sampling, reducing noise impact, and improving image quality.

[0138] Meanwhile, the third, fourth, and fifth sub-digital code values ​​obtained from the three quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. The control circuit 3 determines the image information based on the third, fourth, and fifth sub-digital code values ​​and realizes autofocus in high conversion gain mode, thereby improving image quality and user experience.

[0139] Corresponding to the signal input / output logic of Embodiments 4 and 5 above, such as Figure 10 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0140] The storage circuit 50 includes n storage cells, and each storage cell is connected to a counter unit and an inverting control circuit 40 respectively.

[0141] Each memory cell includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a NOR gate NOR1, and a first 2-to-1 data selector MUX1;

[0142] The input terminals of the first memory Mem1, the second memory Mem2, and the third memory Mem3 are all connected to a counter unit. The output terminal of the first memory Mem1 is connected to the first input terminal of the first 2-to-1 data selector MUX1. The output terminal of the second memory Mem2 is connected to the second input terminal of the first 2-to-1 data selector MUX1. The control terminal of the first 2-to-1 data selector MUX1 is used to input the write-back selection signal mem_sel. The output terminal of the first 2-to-1 data selector MUX1 is connected to the first input terminal of the NOR gate NOR1. The second input terminal of the NOR gate NOR1 is used to input the write-back control signal rewrite_en. The NOR gate NOR1 constitutes the output terminal of the storage circuit 50.

[0143] The first memory Mem1 is used to store the corresponding bit count value in the first sub-digit code value;

[0144] The second memory Mem2 is used to store the corresponding bit count value in the second sub-digit code value;

[0145] The first memory Mem1, the second memory Mem2, and the third memory Mem3 also store the corresponding bit count value from the three digital code values ​​after three exposure samplings.

[0146] In this embodiment, the difference from the circuit structure used in Embodiments 2 and 3 is that the storage circuit 50 includes three memories and a first two-to-one data selector MUX1. The n first memories Mem1 are used to store the n-bit count value of the first sub-digit code value corresponding to the low-gain reset signal lcg_rst during the reset sampling period, and the n second memories Mem2 are used to store the n-bit count value of the second sub-digit code value corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0147] Meanwhile, when autofocus is achieved in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, so as to select the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0148] The n-bit counter unit counts the pulse signals input during the reset sampling period and the exposure sampling period, and generates corresponding digital code values.

[0149] After each exposure sampling period, the three quantized digital code values ​​are finally stored in the first memory Mem1, the second memory Mem2, and the third memory Mem3, respectively. For example, when the readout circuit 1 is used to achieve autofocus under low conversion gain, the third digital code value, the fifth sub-digital code value, and the sixth sub-digital code value obtained from three exposure samplings are stored in n first memories Mem1, the n-bit count value of the fifth sub-digital code value is stored in n second memories Mem2, and the n-bit count value of the sixth sub-digital code value is stored in n third memories Mem3.

[0150] Alternatively, when the readout circuit 1 is used to achieve autofocus under high conversion gain, the third, fourth, and fifth sub-digital code values ​​obtained from three exposure samplings are stored respectively. The n-bit count value of the third sub-digital code value is stored in n first memories Mem1, the n-bit count value of the fourth sub-digital code value is stored in n second memories Mem2, and the n-bit count value of the fifth sub-digital code value is stored in n third memories Mem3. The three memories are read out to the corresponding control circuit 3 according to the readout control signal, so that the control circuit 3 determines the image information according to the count code value of each storage circuit 50.

[0151] Example 6

[0152] Based on the optimization and specification of Embodiment 1, in another optional embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, and the readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes four sub-pixels arranged in a 2×2 array, wherein two sub-pixels form a pixel group and are controlled to output a reset signal Vrst or a pixel signal.

[0153] The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal;

[0154] The first pixel pulse signal includes the first pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in high gain mode and the first image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0155] The second pixel pulse signal includes the second pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in low gain mode and the second image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0156] The first exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period;

[0157] The second exposure sampling period includes the consecutive fifth and sixth exposure sampling periods;

[0158] The first digital code value includes a first sub-digit code value and a second sub-digit code value;

[0159] The counter circuit 30 is configured to count the low-gain reset pulse signal during the first reset sampling period and generate the first sub-digit code value.

[0160] During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value;

[0161] The third digital code value includes the third sub-digit code value and the fourth sub-digit code value;

[0162] During the third exposure sampling period, the pulse signal of the first pixel group is counted based on the second digital code value and stored as the third sub-digital code value;

[0163] During the fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as the fourth sub-digital code value;

[0164] The fifth digit code value includes the fifth sub-digit code value and the sixth sub-digit code value;

[0165] During the fifth exposure sampling period, the pulse signal of the second pixel group is counted based on the fourth digital code value and stored as the fifth sub-digital code value;

[0166] During the sixth exposure sampling period, the second image pulse signal is counted based on the fourth digital code value and stored as the sixth sub-digital code value;

[0167] The storage circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digit code value and the second sub-digit code value. Before the fourth exposure sampling period, it is triggered by the write-back control signal rewrite_en to write back the second sub-digit code value to the counter circuit 30. Before the fifth and sixth exposure sampling periods, it is triggered by the write-back control signal rewrite_en to write back the first sub-digit code value to the counter circuit 30.

[0168] The inversion control circuit 40 is connected to the counter circuit 30 and the storage circuit 50. Before each exposure sampling period, the counter circuit 30 is triggered by the inversion control signal trig_pulse to invert the second sub-digit code value in memory to generate a second digital code value, and to invert the first sub-digit code value to generate a fourth digital code value.

[0169] In this embodiment, the readout circuit 1 is suitable for simultaneously achieving autofocus under high conversion gain and low conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit. The second pixel pulse signal includes a low-gain image pulse signal. The second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit.

[0170] Combination Figure 8 and Figure 9 As shown, during the first reset sampling period, the comparator circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal, generates a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts the low-gain reset pulse signal up or down, and stops counting when the output of the comparator circuit 20 flips. The quantization of the low-gain reset signal lcg_rst ends, and the counter circuit 30 counts to generate the first sub-digit code value and writes it into the storage circuit 50.

[0171] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparator circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal and generates a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30, which counts the high-gain reset pulse signal in the same direction. When the output of the comparator circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst ends, and the counter circuit 30 counts to generate the second sub-digit code value and stores it internally.

[0172] Before the third exposure sampling period, the inverting control circuit 40 receives the mode selection signal mode_sel and outputs the inverting control signal trigger_pulse to the counter circuit 30. The counter circuit 30 switches to inverting mode and inverts the stored second sub-digit code value to the second digit code value, which serves as the initial state for the third exposure sampling period. Then, the counter circuit 30 returns to counting mode and quantizes the high-gain pixel group signal hcg_sigl during the third exposure sampling period. The comparator circuit 20 compares the high-gain pixel group signal hcg_sigl with the pixel ramp voltage signal. The high-gain pixel group pulse signal is generated and output to the counter circuit 30. The counter circuit 30 counts the high-gain pixel group pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain pixel group pulse signal ends, and the counter circuit 30 generates a third sub-digital code value. The third sub-digital code value is the difference between the digital code value corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, realizing correlation double sampling, reducing noise influence, and improving imaging quality.

[0173] Then, the counter circuit 30 resets again. Before the fourth exposure sampling period, the storage circuit 50 receives the write-back control signal `rewrite_en` and writes back the stored second sub-digit code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal `trig_pulse` and inverts the written-back second sub-digit code value to generate a second digital code value. This second digital code value serves as the initial state for the fourth exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the high-gain image signal `hcg_sig` during the fourth exposure sampling period. The comparator circuit 20 then quantizes the high-gain image signal `hcg_s`. The ig signal is compared with the pixel ramp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the high-gain image pulse signal in the same direction based on the second digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the high-gain image pulse signal ends, and the counter circuit 30 generates a fourth sub-digital code value. The fourth sub-digital code value is the difference between the digital code value corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst. This achieves correlation double sampling, reduces noise, and improves image quality.

[0174] Before the fifth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digit code value to the counter circuit 30. Simultaneously, the counter circuit 30 receives the invert control signal trig_pulse and inverts the written-back first sub-digit code value to generate a fourth digital code value. This fourth digital code value serves as the initial state for the fifth exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the low-gain pixel group signal lcg_sigl during the fifth exposure sampling period. The comparison circuit 20 compares the low-gain pixel group signal lcg_sigl with the pixel ramp voltage. The signals are compared, and a low-gain pixel group pulse signal is generated. The low-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain pixel group pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain pixel group pulse signal ends, and the counter circuit 30 generates a fifth sub-digital code value. The fifth sub-digital code value is the difference between the digital code value corresponding to the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst, realizing correlated double sampling, reducing the impact of noise, and improving the imaging quality.

[0175] Then, the counter circuit 30 resets again. Before the sixth exposure sampling period, the storage circuit 50 receives the write-back control signal rewrite_en and writes back the stored first sub-digit code value to the counter circuit 30. At the same time, the counter circuit 30 receives the invert control signal trig_pulse and inverts the written-back first sub-digit code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the sixth exposure sampling period. Then, the counter circuit 30 resumes counting mode and quantizes the low-gain image signal lcg_sig during the sixth exposure sampling period. The comparator circuit 20 then quantizes the low-gain image signal lcg_sig. The ig signal is compared with the pixel ramp voltage signal, and a low-gain image pulse signal is generated. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 counts the low-gain image pulse signal in the same direction based on the fourth digital code value. When the output of the comparison circuit 20 flips, the counter circuit 30 stops counting, the quantization of the low-gain image pulse signal ends, and the counter circuit 30 generates the sixth sub-digital code value. The sixth sub-digital code value is the difference between the digital code value corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, realizing correlation double sampling, reducing noise impact, and improving image quality.

[0176] Meanwhile, the third, fourth, fifth, and sixth sub-digital code values ​​obtained from the four quantizations are finally stored in the storage circuit 50 and read out in the readout control signal to the corresponding control circuit 3. The control circuit 3 determines the image information based on the third, fourth, and fifth sub-digital code values ​​and realizes autofocus in high conversion gain mode, thereby improving image quality and user experience.

[0177] Corresponding to the signal input / output logic of Embodiments 4 and 5 above, such as Figure 11 As shown, optionally, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0178] The storage circuit 50 includes n storage cells, and each storage cell is connected to a counter unit and an inverting control circuit 40 respectively.

[0179] Each memory cell includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a fourth memory Mem4, a NOR gate NOR1, and a first 2-to-1 data selector MUX1;

[0180] The input terminals of the first memory Mem1, the second memory Mem2, and the third memory Mem3 are all connected to a counter unit. The output terminal of the first memory Mem1 is connected to the first input terminal of the first 2-to-1 data selector MUX1. The output terminal of the second memory Mem2 is connected to the second input terminal of the first 2-to-1 data selector MUX1. The control terminal of the first 2-to-1 data selector MUX1 is used to input the write-back selection signal mem_sel. The output terminal of the first 2-to-1 data selector MUX1 is connected to the first input terminal of the NOR gate NOR1. The second input terminal of the NOR gate NOR1 is used to input the write-back control signal rewrite_en. The NOR gate NOR1 constitutes the output terminal of the storage circuit 50.

[0181] The first memory Mem1 is used to store the corresponding bit count value in the first sub-digit code value;

[0182] The second memory Mem2 is used to store the corresponding bit count value in the second sub-digit code value;

[0183] The first memory Mem1, the second memory Mem2, the third memory Mem3, and the fourth memory Mem4 also respectively store the corresponding one-bit count value from the third sub-digit code value, the fourth sub-digit code value, the fifth sub-digit code value, and the sixth sub-digit code value.

[0184] In this embodiment, the difference from the circuit structure used in Embodiments 4 and 5 is that the storage circuit 50 includes four memories: n first memories Mem1 are used to store the n-bit count value of the first sub-digit code value corresponding to the low-gain reset signal lcg_rst during the reset sampling period; and n second memories Mem2 are used to store the n-bit count value of the second sub-digit code value corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0185] Meanwhile, when autofocus is achieved in low gain mode or high gain mode, before the corresponding exposure sampling period, the corresponding write-back selection signal mem_sel is output to the first two-to-one data selector MUX1 according to the first sub-digital code value or the second sub-digital code value to be written back, so as to select the first sub-digital code value or the second sub-digital code value to be written back to n counter units through the inversion control circuit 40.

[0186] The n-bit counter unit counts the pulse signals input during the reset sampling period and the exposure sampling period, and generates corresponding digital code values.

[0187] After each exposure sampling period, the four digital code values ​​obtained by quantization are finally stored in the first memory Mem1, the second memory Mem2, the third memory Mem3 and the fourth memory Mem4 respectively. The four memories are read out to the corresponding control circuit 3 according to the readout control signal, so that the control circuit 3 determines the image information according to the count code value of each storage circuit 50.

[0188] Optionally, in some embodiments, the corresponding digital code value can be read out of the memory in advance and then reset, so that the memory read out in advance can be reused as the memory for subsequent digital code values, which can further reduce the number of memories and reduce the occupied area.

[0189] Example 7

[0190] Based on embodiments one to one, optimizations and specific modifications are made. Optionally, such as... Figure 7 , Figure 10 and Figure 11 As shown, the counter circuit 30 includes a first counter unit 31 to an nth counter unit;

[0191] The inverting control circuit 40 includes n selection circuits;

[0192] The first input terminal of the i-th selection circuit is used to input the inverting control signal trig_pulse. The second input terminal of the first selection circuit 41 is used to input the clock signal count_clk. The second input terminals of the second selection circuit 42 to the n-th selection circuit are connected to the output terminal of the (i-1)-th stage counter unit. The third input terminal of the i-th selection circuit is used to input a low-level signal. The fourth input terminal of the first selection circuit 41 is used to input the output signal count_out of the comparator circuit 20. The output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..., n.

[0193] The i-th selection circuit outputs the signal input to its first input terminal, second input terminal, or third input terminal, subject to the mode selection signal mode_sel and the write-back control signal.

[0194] In this embodiment, the inverting control circuit 40 is used to transmit the inverting control signal trig_pulse, the written-back digital code value, and the clock signal count_clk.

[0195] Each selection circuit is connected to the front end of a counter unit and outputs the corresponding signal from its input terminal to its own output terminal according to the received mode selection signal mode_sel. Before quantization, each counter unit is reset, and during the reset sampling period, the pixel unit outputs a reset signal Vrst to the comparator circuit 20. The comparator circuit 20 compares the reset signal Vrst with the ramp voltage signal and generates a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the first level mode selection signal mode_sel and triggers the connection between its second input terminal and output terminal. The first selection circuit 41 outputs a clock signal count_clk to the first counter unit 31. Subsequent selection circuits select and output the count value of the previous stage counter unit to the next stage counter unit. Each stage counter unit stores the first count value of its own stage, and the first count values ​​of each stage counter unit are combined to generate the first digital code value.

[0196] During the exposure sampling period, in the inverted mode, the mode selection signal mode_sel switches to the second level. Each selection circuit outputs the inverted control signal trig_pulse from the first input terminal to the counter unit at the back end. Each counter unit switches to inverted mode and inverts the first count value stored inside to the second count value or the fourth digital code value. Then, the mode selection signal mode_sel switches back to the first level, and the inverted control signal trig_pulse also switches its level state. Each counter unit switches to counting mode.

[0197] In the write-back mode during the exposure sampling period, after receiving the write-back control signal rewrite_en, the storage circuit 50 writes back the stored corresponding first digital code value to n selection circuits, and the n selection circuits write back the first digital code value to n counter units.

[0198] The selection circuit can be selected from corresponding switch structures, selectors, etc., and the counter unit can be selected from corresponding flip-flops, latches, etc.

[0199] Please continue reading as follows Figure 7 , Figure 10 and Figure 11 Optionally, the first selection circuit 41 includes an AND gate AND1, a second 2-to-1 data selector MUX2, a third 2-to-1 data selector MUX3, and a first inverter U1;

[0200] The first input of AND gate AND1 is used to input the clock signal count_clk, and the second input of AND gate AND1 is used to input the output signal count_out of comparator circuit 20. The first input of the second 2-to-1 data selector MUX2 is used to input the inverting control signal trigger_pulse. The output of AND gate AND1 is connected to the second input of its 2-to-1 data selector. The second input of the second 2-to-1 data selector MUX2 is used to input the low-level signal tie_lo. The control terminal of the second 2-to-1 data selector MUX2 is connected to the output of storage circuit 50. The output of X2 is connected to the first input of its third 2-to-1 data selector MUX3. The second input of MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit. The control terminal of MUX3 is used to input the mode selection signal mode_sel. The output of MUX3 is connected to the input of the first inverter U1. The output of U1 is used to output one of the following signals: the inverted control signal trigger_pulse, the clock signal count_clk, and the low-level signal tie_lo.

[0201] The second selection circuit 42 to the nth selection circuit respectively include a second 2-to-1 data selector MUX2, a third 2-to-1 data selector MUX3 and a first inverter U1;

[0202] The first input terminal of the second 2-to-1 data selector MUX2 is used to input the inverting control signal trig_pulse. The second input terminal of the second 2-to-1 data selector MUX2 is used to input the low-level signal tie_lo. The control terminal of the second 2-to-1 data selector MUX2 is connected to the output terminal of its storage circuit 50. The output terminal of the second 2-to-1 data selector MUX2 is connected to the first input terminal of its third 2-to-1 data selector MUX3. The second input terminal of the third 2-to-1 data selector MUX3 is used to input the clock signal count_clk or the value output by the previous stage counter unit. The control terminal of the third 2-to-1 data selector MUX3 is used to input its mode selection signal mode_sel. The output terminal of the third 2-to-1 data selector MUX3 is connected to the input terminal of its first inverter U1. The output terminal of the first inverter U1 is used to output one of the following signals: the inverting control signal trig_pulse, the clock signal count_clk, the low-level signal tie_lo, and the value output by the previous stage counter unit.

[0203] The counter unit includes a D flip-flop DFF and a second inverter U2;

[0204] The clock signal count_clk terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF. The output terminal of the second inverter U2 is connected to the second input terminal of the i+1-th selection circuit.

[0205] Alternatively, the counter unit may include a D flip-flop (DFF).

[0206] The clock signal count_clk terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF of the i-th stage counter unit is connected to the data input terminal of the D flip-flop DFF. The non-inverted output terminal of the D flip-flop DFF is connected to the second input terminal of the i+1-th selection circuit.

[0207] In this embodiment, when the inverted output of the D flip-flop DFF is connected to the second inverter U2, and the second inverter U2 serves as the output of the counter unit, the counter unit constitutes an up counter. When the non-inverted output of the D flip-flop DFF serves as the output of the counter unit, the counter unit constitutes a down counter. By inverting and writing back the reset signal Vrst, the counter unit does not need to switch between up counting and down counting when continuously quantizing the reset signal Vrst and the pixel signal, nor does it need to set up an additional holding circuit. Compared with the traditional counter circuit 30, the number of transistors can be reduced, thereby reducing the layout area and optimizing the routing, achieving the purpose of reducing power consumption.

[0208] refer to Figure 5 and Figure 6 As shown, taking upward counting as an example, when the selection circuit and counter unit are applied to ADAF mode, the timing of a complete quantization cycle in ADAF mode is as follows:

[0209] At time t0-t1, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0210] At time t2, the reset signal Vrst is quantized. At this time, the output signal count_out of the comparator circuit 20 is switched to a high level. The clock signal count_clk is ANDed with the high level by an AND gate, and the clock signal count_clk is output to the second input terminal of the third 2-to-1 data selector MUX3. At this time, the mode selection signal mode_sel is high, and the clock signal count_clk is selected and output to the first inverter U1 and then to the first D flip-flop DFF. Each D flip-flop DFF counts upward under the action of the clock signal count_clk.

[0211] At time t3, the output of comparator circuit 20 flips, the counting stops, the quantization of the reset signal Vrst ends, and the count values ​​of each bit of the first digital code value of the quantization result of the reset signal Vrst are stored in each D flip-flop DFF. The first count values ​​output by each second inverter U2 are combined to generate the first digital code value.

[0212] At time t4-t5, the readout control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0213] At time t5, the mode selection signal mode_sel switches to a low level, and each counter unit switches to invert mode.

[0214] At time t6, the inverting control signal trig_pulse switches to a low level and generates a rising edge at the clock input of each D flip-flop (DFF) through the second 2-to-1 data selector MUX2 and the third 2-to-1 data selector MUX3. This inverts the digital code of the first quantization result stored in each D flip-flop (DFF) and uses it as the initial state before the second quantization.

[0215] At time t7, the mode selection signal mode_sel switches to a high level, and the counter unit returns to counting mode; at time t8, the inverting control circuit 40 switches to a high level.

[0216] At time t9, the pixel group signal Vsigl is quantized from the initial state. At time t10, the output of the comparator circuit 20 flips, the counting stops, the quantization of the pixel group signal Vsigl ends, and the third digital code value of the difference between the pixel group signal Vsigl and the reset signal Vrst is stored in the D flip-flop DFF.

[0217] At times t11-t12, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2, which is then read out.

[0218] At times t12-t13, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0219] At time t13, the mode selection signal mode_sel switches to low level, the write-back control signal rewrite_en switches to high level, and the counter unit switches to write-back mode.

[0220] At time t14, the inverting control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D flip-flop DFF through the second 2-to-1 data selector MUX2 and the third 2-to-1 data selector MUX3. This writes the first digital code value stored in the first memory Mem1 into the n-bit counter unit and inverts it, serving as the initial state before quantization of the image signal Vsig.

[0221] At time t15, the mode selection signal mode_sel switches to high level, and the counter unit resumes counting mode. At time t16, the inverting control signal trig_pulse switches to high level.

[0222] At time t17, the quantization of the image signal Vsig begins from the initial state. At time t18, the output of the comparator circuit 20 flips, the counting stops, the quantization of the image signal Vsig ends, and the difference between the image signal Vsig and the reset signal Vrst is stored in the D flip-flop DFF, which is the correlated double-sampled image quantization value.

[0223] At times t19-t20, the readout control signal is enabled, and the final quantization result is stored in the first memory Mem1, and then read out.

[0224] refer to Figure 5 and Figure 7 As shown, when the selection circuit is applied to PGHDR mode, the timing of a complete quantization cycle in PGHDR mode is as follows:

[0225] At time t0-t1, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0226] At time t2, the low-gain reset signal lcg_rst is quantized. At this time, the output signal count_out of the comparator circuit 20 switches to a high level. After the clock signal count_clk is ANDed with the high level, the clock signal count_clk is output to the second input of the third 2-to-1 data selector MUX3. At this time, the mode selection signal mode_sel is high. The clock signal count_clk is selected and output to the first inverter U1 and then to the first D flip-flop DFF. Each D flip-flop DFF counts upward under the action of the clock signal count_clk.

[0227] At time t3, the output of comparator circuit 20 flips, the counting stops, the quantization of the low-gain reset signal lcg_rst ends, and the first sub-digit code of the quantization result of the low-gain reset signal lcg_rst is stored in the D flip-flop DFF.

[0228] At time t4-t5, the readout control signal switches to a high level, storing the first sub-digit code in each of the first memories Mem1.

[0229] Between times t5 and t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0230] At time t7, the high-gain reset signal hcg_rst is quantized from the initial state. At time t8, the output of comparator circuit 20 flips, the counting stops, the quantization of the high-gain reset signal hcg_rst ends, and the second sub-digit code of the high-gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0231] At time t9, the mode selection signal mode_sel switches to low level, and the counter switches to invert mode; at time t10, the invert control signal trig_pulse switches to low level, and the rising edge is generated by the output of the second 2-to-1 data selector MUX2 and the third 2-to-1 data selector MUX3 to the clock input of the D flip-flop DFF, which inverts the digital code of the second quantization result stored in each D flip-flop DFF to the second digital code value, as the initial state before the second quantization.

[0232] At time t11, the mode selection signal mode_sel switches to a high level, and the counter unit returns to counting mode; at time t12, the mode selection signal mode_sel switches to a high level.

[0233] At time t13, quantization of the high-gain image signal hcg_sig begins from the initial state. At time t14, the output of comparator circuit 20 flips, counting stops, and the quantization of the high-gain image signal hcg_sig ends. The difference between the high-gain image signal hcg_sig and the reset signal Vrst is stored in the D flip-flop DFF, which is the quantized image value of correlated double sampling under high conversion gain. Between times t15 and t16, sram_wrt is enabled, storing the final quantization result in the second memory Mem2, which is then read out.

[0234] At time t16-t17, count_rstb switches to low level, resetting the values ​​in all D flip-flops (all outputs become 0); at time t17, the mode selection signal mode_sel switches to low level, the write-back control signal rewrite_en switches to high level, and the counter unit switches to write-back mode.

[0235] At time t18, the inverting control signal trig_pulse switches to a low level, generating a rising edge at the clock input of the D flip-flop DFF. The first sub-digit code value corresponding to the low-gain reset signal lcg_rst stored in the first memory Mem1 is written back to the counter unit and inverted, serving as the initial state before quantization of the low-gain image signal lcg_sig.

[0236] At time t19, the mode selection signal mode_sel switches to a high level, and the counter unit returns to counting mode; at time t20, the invert control signal trig_pulse switches to a high level.

[0237] At time t21, quantization of the low-gain image signal lcg_sig begins from the initial state. At time t22, the output of comparator circuit 20 flips, counting stops, and quantization of the low-gain image signal lcg_sig ends. The difference between the low-gain image signal lcg_sig and the reset signal Vrst is stored in the D flip-flop DFF, which is the quantized image value of correlated double sampling under low conversion gain. Between times t23 and t24, the readout control signal is enabled, and the final quantization result is stored in the first memory Mem1, followed by readout.

[0238] This completes one full quantization cycle, ultimately yielding the image quantization values ​​under high conversion gain and low conversion gain (correlation double sampling).

[0239] And when the selection circuit is applied to implement ADAF mode under low conversion gain, the timing within a complete quantization cycle is as follows: Figure 5 As shown:

[0240] At time t0-t1, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0241] At time t2, the low-gain reset signal lcg_rst is quantized, and the counter counts upward under the action of the high-speed clock count_clk. At time t3, the output of comparator circuit 20 flips, the counting stops, the quantization of the low-gain reset signal lcg_rst ends, and the first sub-digit code value of the quantization result of the low-gain reset signal lcg_rst is stored in the D flip-flop DFF.

[0242] At time t4-t5, the readout control signal is switched to a high level, and the first quantization result is stored in the first memory Mem1.

[0243] Between times t5 and t6, count_rstb switches to a low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0).

[0244] At time t7, the high-gain reset signal hcg_rst is quantized from the initial state. At time t8, the output of comparator circuit 20 flips, the counting stops, the quantization of the high-gain reset signal hcg_rst ends, and the second sub-digit code value of the high-gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0245] At time t9, the mode selection signal mode_sel switches to low level, disconnecting the stages of the counter. At time t10, the inverting control signal trig_pulse switches to low level, generating a rising edge at the clock input of the D flip-flop DFF, inverting the digital code of the second quantization result stored in the D flip-flop DFF, and using it as the initial state before the third quantization.

[0246] At time t11, the mode selection signal mode_sel switches to a high level, and the counter resumes counting mode; at time t12, the inverting control signal trig_pulse switches to a high level.

[0247] At time t13, quantization of the high-gain image signal hcg_sig begins from the initial state; at time t14, the output of comparator circuit 20 flips, counting stops, quantization of the high-gain image signal hcg_sig ends, and the difference between the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst is stored in the D flip-flop DFF, which is the image quantization value of the correlated double sampling under high conversion gain.

[0248] At time t15, the write-back control signal rewrite_en and the mode selection signal mode_sel are switched to high level, the counter is switched to write-back mode, and the first sub-digit code value stored in the first memory Mem1 is selected to be written back into the counter; at times t15-t16, sram_wrt is enabled, the final quantization result is stored in the second memory Mem2, and then read out.

[0249] At times t16-t17, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0); at time t17, the mode selection signal mode_sel switches to low level, disconnecting the stages of the counter; at time t18, the inverting control signal trig_pulse switches to low level, generating a rising edge at the clock input of the D flip-flops, writing back the first sub-digit code value corresponding to the low-gain reset signal lcg_rst stored in the first memory Mem1 to the counter unit and inverting it; this serves as the initial state before the fourth quantization; at time t19, the mode selection signal mode_sel switches to high level, and the counter returns to counting mode; at time t20, the inverting control signal trig_pulse switches to high level.

[0250] At time t21, quantization of the low-gain pixel group signal lcg_sigl begins from the initial state. At time t22, the output of comparator circuit 20 flips, counting stops, and quantization of the low-gain pixel group signal lcg_sigl ends. The difference between the low-gain pixel group signal lcg_sigl and the low-gain reset signal lcg_rst is stored in the D flip-flop DFF, which is the quantized value of the correlated double-sampled pixel group signal Vsigl under low conversion gain. Between times t23 and t24, hcg_wrt is enabled, and the final quantization result is stored in the third memory Mem3, which is then read out.

[0251] At times t24-t25, count_rstb switches to low level, resetting the values ​​in all D flip-flops (DFFs) (all outputs become 0); at time t25, the mode selection signal mode_sel switches to low level, disconnecting the stages of the counter unit; at time t26, the inverting control signal trig_pulse switches to low level, generating a rising edge at the clock input of the D flip-flops, writing back the first digital code value stored in the first memory Mem1 to the counter and inverting it; this serves as the initial state before the fifth subquantization; at time t27, the mode selection signal mode_sel switches to high level, and the counter returns to counting mode; at time t28, the inverting control signal trig_pulse switches to high level.

[0252] At time t29, quantization of the low-gain image signal lcg_sig begins from the initial state. At time t30, the output of comparator circuit 20 flips, counting stops, and quantization of the low-gain image signal lcg_sig ends. The difference between the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst is stored in the D flip-flop DFF, which is the quantized image value of correlated double sampling under low conversion gain. Between times t31 and t32, lcg_wrt is enabled, storing the final quantization result in the first memory Mem1, which is then read out.

[0253] This completes one full quantization cycle, yielding sequentially the image quantization value under high conversion gain correlation double sampling, the pixel group quantization value under low conversion gain correlation double sampling, and the image quantization value under low conversion gain correlation double sampling.

[0254] Similarly, when the selection circuit is used to implement ADAF mode under high conversion gain, or to implement ADAF mode under both high and low conversion gain, the selection circuit selects and outputs the corresponding inverting control signal trigger_pulse or digital code value to the counter unit according to the received corresponding mode selection signal mode_sel or the written-back digital code value, so that the counter unit can perform counting, inverting and other operations.

[0255] After each quantization, the corresponding digital code value is stored in the corresponding memory. Each memory reads the value to the control circuit 3 according to the received readout control signal, so that the control circuit 3 can determine the image information based on each digital code value.

[0256] In order to achieve the inversion function of the D flip-flop (DFF) in Embodiments 3 and 4 above, as follows: Figure 12 As shown, optionally, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transmission gate tran1, a second transmission gate tran2, a third transmission gate tran3, and a fourth transmission gate tran4.

[0257] In this embodiment, the first transmission gate tran1, the fourth inverter U4, the fifth inverter U5, and the second transmission gate tran2 form a master-level latch, and the third transmission gate tran3, the sixth inverter U6, the seventh inverter U7, and the fourth transmission gate tran4 form a slave-level latch. The master-level latch is used to stably latch and output the input value of the D flip-flop DFF, and the slave-level latch is used to stably latch and output the output value of the master-level latch. The third inverter U3 is used to invert the input data signal and output it to the master-level latch, and the eighth inverter U8 is used to invert the output value of the slave-level latch. When the clock signal count_clk of the D flip-flop DFF receives a rising edge, the third inverter U3, the master-level latch, the slave-level latch, and the eighth inverter U8 invert the latched value and output it.

[0258] Example 8

[0259] This invention also proposes an image sensor, such as Figure 2 As shown, the image sensor includes a pixel array 100, a control circuit 3, and multiple image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The pixel array 100 includes multiple pixel units arranged in an array.

[0260] Each image sensor's readout circuit 1 is connected to a column of multiple pixel units, and each image sensor's readout circuit 1 is also connected to a control circuit 3.

[0261] In this embodiment, the image sensor typically includes a control circuit 3, a pixel array 100, and a readout circuit 1. It may also include a clock generator and a digital I / O port. The pixel array 100 includes multiple pixel units arranged in an array. Multiple pixel units arranged in columns are connected together. The control circuit 3 selects each row of pixel units through a row selection signal and outputs the pixel signals of each row to the readout circuit 1 in sequence. Multiple pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3 so that the control circuit 3 can determine the image information based on the digital code value.

[0262] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, characterized in that, The readout circuit includes: A ramp voltage circuit, configured to output a ramp voltage signal; The comparison circuit has a first input terminal connected to the pixel unit and a second input terminal connected to the ramp voltage circuit. It is configured to compare at least one reset signal or two pixel signals output by the pixel unit with the ramp voltage signal, and to output at least one reset pulse signal and two pixel pulse signals at intervals. A counter circuit, connected to the comparison circuit, is configured to count the at least one reset pulse signal during at least one reset sampling period and store it as at least one first digital code value; and during a first exposure sampling period, to count the first pixel pulse signal based on the second digital code value and store it as a third digital code value; and during a second exposure sampling period, to count the second pixel pulse signal based on the fourth digital code value and store it as a fifth digital code value. A storage circuit, connected to the counter circuit, is configured to store at least one first digital code value, and before the second exposure sampling period, is triggered by a write-back control signal to write back one of the at least one first digital code values ​​to the counter circuit; An inversion control circuit, connected to the counter circuit and the storage circuit, outputs an inversion control signal to the counter circuit before each exposure sampling period, triggered by a mode selection signal, to trigger the counter circuit to invert the first digital code value in memory to generate the second digital code value or the fourth digital code value.

2. The readout circuit of the image sensor as described in claim 1, characterized in that, The image sensor includes a pixel array, each pixel array includes pixel units arranged in an array, and the readout circuit of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in a 2×2 array, wherein at least two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The at least one reset signal is a reset signal generated when the pixel units are reset simultaneously; The first pixel pulse signal and the second pixel pulse signal are respectively one of the pixel group pulse signal corresponding to the simultaneous exposure of the pixel group and the image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

3. The readout circuit of the image sensor as described in claim 1, characterized in that, The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal; The counter circuit is configured to: count one of the reset pulse signals during the first reset sampling period to generate a first digital code value; During the second reset sampling period, another reset pulse signal is counted to generate another first digital code value; During the first exposure sampling period, the pulse signal of the first pixel is counted based on the second digital code value and stored as the third digital code value; During the second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as the fifth digital code value.

4. The readout circuit of the image sensor as described in claim 2 or 3, characterized in that, The counter circuit includes a first counter unit to an nth counter unit; The storage circuit includes n storage units, and each storage unit is connected to a counter unit and the inverting control circuit respectively. Each of the aforementioned memory cells includes a first memory, a second memory, and a NAND gate; The input terminals of the first memory and the second memory are respectively connected to a counter unit. The output terminal of the first memory is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input the write-back control signal. The NAND gate constitutes the output terminal of the memory unit. The first memory is configured to store a corresponding bit count value from at least one first digital code value; The first memory and the second memory respectively store a corresponding bit count value of one of the third digital code value and the fifth digital code value.

5. The readout circuit of the image sensor as described in claim 1, characterized in that, The image sensor includes a pixel array, each pixel array includes pixel units arranged in an array, and the readout circuit of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in a 2×2 array, wherein at least two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit. The second exposure sampling period includes a continuous third exposure sampling period and a fourth exposure sampling period; The first digital code value includes a first sub-digit code value and a second sub-digit code value; The counter circuit is configured to: count the low-gain reset pulse signal during the first reset sampling period to generate a first sub-digit code value; During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value; During the first exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as a third digital code value; The fifth digital code value includes a fifth sub-digit code value and a sixth sub-digit code value; During the third exposure sampling period, the pulse signal of the low-gain pixel group is counted based on the fourth digital code value and stored as the fifth sub-digital code value; During the fourth exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as the sixth sub-digital code value; A storage circuit, connected to the counter circuit, is configured to store the first sub-digital code value, and before the third exposure sampling period and the fourth exposure sampling period, triggers the write-back control signal to write the first sub-digital code value back to the counter circuit. An inversion control circuit, connected to the counter circuit and the storage circuit, is triggered by an inversion control signal before each exposure sampling period to control the counter circuit to invert the first sub-digital code value in memory to generate the fourth digital code value, and to invert the second sub-digital code value to generate the second digital code value.

6. The readout circuit of the image sensor as described in claim 1, characterized in that, The image sensor includes a pixel array, each pixel array includes pixel units arranged in an array, and the readout circuit of each image sensor is connected to a column of multiple pixel units respectively. The pixel unit includes four sub-pixels arranged in a 2×2 array, wherein two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal includes a low-gain image pulse signal; The first exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period; The first digital code value includes a first sub-digit code value and a second sub-digit code value; The counter circuit is configured to: count the low-gain reset pulse signal during the first reset sampling period to generate a first sub-digit code value; During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value; The third digital code value includes a third sub-digit code value and a fourth sub-digit code value; During the third exposure sampling period, the pulse signal of the high-gain pixel group is counted based on the second digital code value and stored as the third sub-digital code value; During the fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as the fourth sub-digital code value; During the second exposure sampling period, the low-gain image pulse signal is counted based on the fourth digital code value and stored as the fifth digital code value; A storage circuit, connected to the counter circuit, is configured to store the first sub-digital code value and the second sub-digital code value, and, before the fourth exposure sampling period and the second exposure sampling period, is triggered by a write-back control signal to write back the second sub-digital code value and the first sub-digital code value to the counter circuit. An inversion control circuit, connected to the counter circuit and the storage circuit, is triggered by an inversion control signal before each exposure sampling period to control the counter circuit to invert the second sub-digital code value in memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

7. The readout circuit of the image sensor as described in claim 5 or 6, characterized in that, The counter circuit includes a first counter unit to an nth counter unit; The storage circuit includes n storage units, and each storage unit is connected to a counter unit and the inverting control circuit respectively. Each of the aforementioned storage units includes a first memory, a second memory, a third memory, a NAND gate, and a first 2-to-1 data selector; The input terminals of the first memory, the second memory, and the third memory are all connected to a counter unit. The output terminal of the first memory is connected to the first input terminal of the first 2-to-1 data selector. The output terminal of the second memory is connected to the second input terminal of the first 2-to-1 data selector. The control terminal of the first 2-to-1 data selector is used to input a write-back selection signal. The output terminal of the first 2-to-1 data selector is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input the write-back control signal. The NAND gate constitutes the output terminal of the storage circuit. The first memory is used to store the corresponding bit count value in the first sub-digit code value; The second memory is used to store the corresponding bit count value in the second sub-digit code value; The first memory, the second memory, and the third memory also respectively store a corresponding bit count value from the three digital code values ​​after three exposure samplings.

8. The readout circuit of the image sensor as described in claim 1, characterized in that, The image sensor includes a pixel array, each pixel array includes pixel units arranged in an array, and the readout circuit of each image sensor is connected to a column of multiple pixel units respectively. The pixel unit includes four sub-pixels arranged in a 2×2 array, wherein two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal; The first pixel pulse signal includes a first pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in high gain mode and a first image pulse signal corresponding to the simultaneous exposure of sub-pixels in the pixel unit; The second pixel pulse signal includes the second pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in low gain mode and the second image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit; The first exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period; The second exposure sampling period includes a consecutive fifth exposure sampling period and a sixth exposure sampling period; The first digital code value includes a first sub-digit code value and a second sub-digit code value; The counter circuit is configured to: count the low-gain reset pulse signal during the first reset sampling period to generate a first sub-digit code value; During the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digit code value; The third digital code value includes a third sub-digit code value and a fourth sub-digit code value; During the third exposure sampling period, the pulse signal of the first pixel group is counted based on the second digital code value and stored as the third sub-digital code value; During the fourth exposure sampling period, the first image pulse signal is counted based on the second digital code value and stored as the fourth sub-digital code value; The fifth digital code value includes a fifth sub-digit code value and a sixth sub-digit code value; During the fifth exposure sampling period, the pulse signal of the second pixel group is counted based on the fourth digital code value and stored as the fifth sub-digital code value; During the sixth exposure sampling period, the second image pulse signal is counted based on the fourth digital code value and stored as the sixth sub-digital code value; The storage circuit, connected to the counter circuit, is configured to store the first sub-digit code value and the second sub-digit code value, and to write back the second sub-digit code value to the counter circuit before the fourth exposure sampling period, triggered by a write-back control signal, and to write back the first sub-digit code value to the counter circuit before the fifth and sixth exposure sampling periods, triggered by a write-back control signal. An inversion control circuit, connected to the counter circuit and the storage circuit, is triggered by an inversion control signal before each exposure sampling period to control the counter circuit to invert the second sub-digital code value in memory to generate the second digital code value, and to invert the first sub-digital code value to generate the fourth digital code value.

9. The readout circuit of the image sensor as described in claim 8, characterized in that, The counter circuit includes a first counter unit to an nth counter unit; The storage circuit includes n storage units, and each storage unit is connected to a counter unit and the inverting control circuit respectively. Each of the aforementioned storage units includes a first memory, a second memory, a third memory, a fourth memory, a NAND gate, and a first 2-to-1 data selector; The input terminals of the first memory, the second memory, the third memory, and the fourth memory are all connected to a counter unit. The output terminal of the first memory is connected to the first input terminal of the first 2-to-1 data selector. The output terminal of the second memory is connected to the second input terminal of the first 2-to-1 data selector. The control terminal of the first 2-to-1 data selector is used to input a write-back selection signal. The output terminal of the first 2-to-1 data selector is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input the write-back control signal. The NAND gate constitutes the output terminal of the storage circuit. The output terminals of the third memory and the fourth memory are respectively connected to the control circuit. The first memory is used to store the corresponding bit count value in the first sub-digit code value; The second memory is used to store the corresponding bit count value in the second sub-digit code value; The first memory, the second memory, the third memory, and the fourth memory also respectively store a corresponding one-bit count value from the third sub-digit code value, the fourth sub-digit code value, the fifth sub-digit code value, and the sixth sub-digit code value.

10. The readout circuit of the image sensor as described in claim 1, characterized in that, The counter circuit includes a first counter unit to an nth counter unit; The inversion control circuit includes n selection circuits; The first input terminal of the i-th selection circuit is used to input the inverting control signal, the second input terminal of the first selection circuit is used to input the clock signal, the second input terminals of the second selection circuit to the n-th selection circuit are connected to the output terminal of the (i-1)-th stage counter unit, the third input terminal of the i-th selection circuit is used to input a low-level signal, the fourth input terminal of the first selection circuit is used to input the output signal of the comparator circuit, and the output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i is 1, 2, ..., n; The i-th selection circuit outputs signals from its first input terminal, second input terminal, or third input terminal, subject to the mode selection signal and the write-back control signal.

11. The readout circuit of the image sensor as described in claim 10, characterized in that, The first selection circuit includes an AND gate, a second 2-to-1 data selector, a third 2-to-1 data selector, and a first inverter; The first input terminal of the AND gate is used to input the clock signal, the second input terminal of the AND gate is used to input the output signal of the comparator circuit, the first input terminal of the second 2-to-1 data selector is used to input the inverting control signal, the output terminal of the AND gate is connected to the second input terminal of the 2-to-1 data selector, the second input terminal of the second 2-to-1 data selector is used to input the low-level signal, the control terminal of the second 2-to-1 data selector is connected to the output terminal of the storage circuit, the output terminal of the second 2-to-1 data selector is connected to the first input terminal of the third 2-to-1 data selector, the second input terminal of the third 2-to-1 data selector is used to input the clock signal or the value output by the previous stage counter unit, the control terminal of the third 2-to-1 data selector is used to input the mode selection signal, the output terminal of the third 2-to-1 data selector is connected to the input terminal of the first inverter, and the output terminal of the first inverter is used to output one of the corresponding signals of the inverting control signal, the clock signal, and the low-level signal. The second to the nth selection circuits each include a second 2-to-1 data selector, a third 2-to-1 data selector, and a first inverter. The first input terminal of the second 2-to-1 data selector is used to input the inverting control signal, the second input terminal of the second 2-to-1 data selector is used to input the low-level signal, the control terminal of the second 2-to-1 data selector is connected to the output terminal of its storage circuit, the output terminal of the second 2-to-1 data selector is connected to the first input terminal of its third 2-to-1 data selector, the second input terminal of the third 2-to-1 data selector is used to input the clock signal or the value output by the previous stage counter unit, the control terminal of the third 2-to-1 data selector is used to input its mode selection signal, the output terminal of the third 2-to-1 data selector is connected to the input terminal of its first inverter, and the output terminal of the first inverter is used to output one of the following signals: the inverting control signal, its clock signal, the low-level signal, and the value output by the previous stage counter unit.

12. The readout circuit of the image sensor as described in claim 10, characterized in that, The counter unit includes a D flip-flop and a second inverter; The clock signal terminal of the D flip-flop in the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop in the i-th stage counter unit is connected to the input terminal of the second inverter and the data input terminal of the D flip-flop. The output terminal of the second inverter is connected to the second input terminal of the (i+1)-th selection circuit.

13. The readout circuit of the image sensor as described in claim 10, characterized in that, The counter unit includes a D flip-flop; The clock signal terminal of the D flip-flop in the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit, the inverted output terminal of the D flip-flop in the i-th stage counter unit is connected to the data input terminal of the D flip-flop, and the non-inverted output terminal of the D flip-flop is connected to the second input terminal of the (i+1)-th stage selection circuit.

14. An image sensor, characterized in that, It includes a pixel array, a control circuit, and a readout circuit of a plurality of image sensors as described in any one of claims 1 to 13, wherein the pixel array includes a plurality of pixel units arranged in an array; Each of the image sensors has a readout circuit that is connected to a plurality of pixel units arranged in a column, and each of the image sensors has a readout circuit that is also connected to the control circuit.

Images