Memory system and operating method thereof, readable storage medium

Abstract

Embodiments of the present disclosure provide a memory system and an operating method thereof; wherein the memory system comprises at least one memory device and a memory controller coupled with the at least one memory device; the memory controller is configured to perform part of or all of at least two read error handling processes in response to a first read operation failure when performing a read operation on a storage area in the memory device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operation method, and a readable storage medium. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0004] According to one aspect of the embodiments of this disclosure, a memory system is provided, comprising:

[0005] At least one memory device and a memory controller coupled to said at least one memory device;

[0006] The memory controller is configured to:

[0007] In response to the failure of the first read operation when performing a read operation on a storage area in the memory device, at least some or all of the read error handling procedures are executed.

[0008] In some embodiments, the read error handling process of the memory device includes a first type of read error handling process and a second type of read error handling process executed sequentially; the average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

[0009] In some embodiments, in response to the failure of the first read operation after the storage area in the memory device has been restored to the operating state, at least two Type 1 read error handling procedures are executed.

[0010] In some embodiments, the memory controller is configured to:

[0011] A preset time interval is set between two adjacent Type I read error handling processes.

[0012] In some embodiments, the memory controller is configured to:

[0013] If the read operation still fails after executing the first type of read error handling procedure at least twice, the second type of read error handling procedure is executed.

[0014] In some embodiments, the first type of read error handling process includes: reread operation and software decoding operation;

[0015] The second type of read error handling process includes: independent disk redundant array RAID operation.

[0016] In some embodiments, the memory controller is configured to:

[0017] During each execution of the first type of read error handling process, in response to the failure of the reread operation, a software decoding operation is performed on the read data.

[0018] In some embodiments, the memory controller is configured to:

[0019] If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

[0020] In some embodiments, the first type of read error handling process includes: a reread operation;

[0021] The second type of read error handling process includes: software decoding operation.

[0022] In some embodiments, the memory controller is configured to:

[0023] Obtain a first duration; the first duration is greater than the duration for which the storage area in the memory device recovers to the operating state;

[0024] Based on the first duration, determine the number of times the first type of read error handling process is executed.

[0025] In some embodiments, the memory controller is configured to:

[0026] The first duration is determined based on the temperature at which the memory device is located; the first duration is negatively correlated with the temperature at which the memory device is located.

[0027] In some embodiments, the memory controller is configured to:

[0028] In response to the failure of the first read operation after the storage area in the memory device is restored to the operating state, the first type of read error handling process is executed multiple times until a preset number of times is reached.

[0029] In some embodiments, before performing a read operation on a storage area in the memory device, no operation is performed on the storage area of ​​the memory device for a preset time; or

[0030] The first read operation when performing a read operation on the storage area of ​​the memory device is the first read operation when performing a read operation on the storage area of ​​the memory device after the memory system is powered on.

[0031] In some embodiments, the memory system includes a general-purpose flash storage (UFS) device or an embedded multimedia card (eMMC) device.

[0032] According to one aspect of the embodiments of this disclosure, a method for operating a memory system is provided, including:

[0033] In response to an access command, a read operation is performed on a storage region in the memory device;

[0034] In response to the failure of the first read operation when performing a read operation on a storage area in the memory device, at least some or all of the read error handling procedures are executed.

[0035] In some embodiments, the read error handling process of the memory device includes a first type of read error handling process and a second type of read error handling process executed sequentially; the average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

[0036] In some embodiments, performing at least two reads of part or all of the error handling process includes:

[0037] In response to the failure of the first read operation after the storage area in the memory device is restored to the operating state, at least two Type 1 read error handling procedures are executed.

[0038] In some embodiments, the method further includes:

[0039] A preset time interval is set between two adjacent Type I read error handling processes.

[0040] In some embodiments, the method further includes:

[0041] If the read operation still fails after executing the first type of read error handling procedure at least twice, the second type of read error handling procedure is executed.

[0042] In some embodiments, the first type of read error handling process includes: reread operation and software decoding operation;

[0043] The second type of read error handling process includes: independent disk redundant array RAID operation.

[0044] In some embodiments, the method further includes:

[0045] During each execution of the first type of read error handling process, in response to the failure of the reread operation, a software decoding operation is performed on the read data.

[0046] In some embodiments, the method further includes:

[0047] If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

[0048] In some embodiments, the first type of read error handling process includes: a reread operation;

[0049] The second type of read error handling process includes: software decoding operation.

[0050] In some embodiments, the method further includes:

[0051] Obtain a first duration; the first duration is greater than the duration for which the storage area in the memory device recovers to the operating state;

[0052] Based on the first duration, determine the number of times the first type of read error handling process is executed.

[0053] In some embodiments, the method further includes:

[0054] The first duration is determined based on the temperature at which the memory device is located; the first duration is negatively correlated with the temperature at which the memory device is located.

[0055] In some embodiments, the method further includes:

[0056] In response to the failure of the first read operation after the storage area in the memory device is restored to the operating state, the first type of read error handling process is executed multiple times until a preset number of times is reached.

[0057] In some embodiments, before performing a read operation on a storage area in the memory device, no operation is performed on the storage area of ​​the memory device for a preset time; or

[0058] The first read operation when performing a read operation on the storage area of ​​the memory device is the first read operation when performing a read operation on the storage area of ​​the memory device after the memory system is powered on.

[0059] According to one aspect of the present disclosure, a readable storage medium is provided, the readable storage medium storing a computer program that, when executed, implements the operation method.

[0060] This disclosure provides a memory system including at least one memory device and a memory controller coupled to the at least one memory device. The memory controller is configured to: in response to a failure of the first read operation after the memory device has recovered to an operating state, execute part or all of the steps in at least two read error handling procedures. Without adding any steps to the original read operation procedure firmware or program, the default read operation firmware or program built into the original memory system is used to eliminate the situation where the first read error rate is high when the memory system recovers to the operating state. This improves the read efficiency of the memory system, facilitates the simplification of firmware or program to reduce development costs, and reduces the processing load of the memory controller. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0062] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0063] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0064] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0065] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0066] Figure 4 This is a schematic cross-sectional view of a memory array including NAND memory strings according to an embodiment of the present disclosure.

[0067] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0068] Figure 6 This is a schematic diagram of a conventional reading operation flow according to an embodiment of the present disclosure;

[0069] Figure 7a This is a schematic diagram of a read error handling process according to an embodiment of the present disclosure. Figure 1 ;

[0070] Figure 7b This is a second schematic diagram of a read error handling process according to an embodiment of the present disclosure;

[0071] Figure 7cSchematic diagram three illustrates a read error handling process according to an embodiment of this disclosure;

[0072] Figure 8 This is a flowchart illustrating the operation method of a memory system according to an embodiment of the present disclosure. Figure 1 ;

[0073] Figure 9 This is a schematic flowchart of an operation method of a memory system according to an embodiment of the present disclosure.

[0074] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0075] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0076] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0077] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0078] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0079] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0081] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0082] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0083] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0085] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0086] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0087] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0088] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0089] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0090] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0091] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0092] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal storage values ​​into the cell, while a fourth nominal storage value in addition to these three nominal storage values ​​can be used to indicate an erase state.

[0093] like Figure 3bAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0094] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, where page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0095] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0096] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0097] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0098] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0099] Return to reference Figure 3bThe peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0100] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0101] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0102] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel pre-charge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the channel pre-charge stage, a voltage generator can generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage can be applied to the selected word line; in the programming pulse stage, the target voltage for each programming operation can be applied to the selected word line. In the recovery stage, the voltage can be reduced to the corresponding voltage, such as Vcc or Vdd, for both unselected and selected word lines. The recovery stage can achieve this by stepping down the voltage to the corresponding voltage once or multiple times, for example, by first reducing the voltage to an intermediate voltage, maintaining it at that intermediate voltage for a period of time, and then reducing it to the corresponding voltage.

[0103] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0104] In specific application embodiments of some memory systems, when system 100 is running, host 108 sends commands to memory system 102 in response to user task requests, retrieving data from or storing data in memory system 102. When host 108 processes task requests from users, it needs to interact with memory system 102. The memory controller 106, memory device 104, and various interfaces in memory system 102 are in an operational state. At this time, memory system 102 can be defined as being in an operational state, or the storage area in memory device 104 can be defined as being in an operational state. In this embodiment, the storage area of ​​memory device 104 can be... Figure 3a The memory device 104 may include one, several, or all of the memory blocks shown; it may also include one, several, or all of the memory chips within a memory block. The memory device 104 may include multiple dies, and the memory regions within the memory device 104 may include one, several, or all of these dies. Each die includes multiple memory blocks. A die is a semiconductor structure including an array of memory cells, cut from a wafer along dicing lines during the fabrication of the memory device 104. Multiple dies are combined to form a chip through hybrid bonding or other integration methods. The operating state may include any one of programming, reading, or erasing operations. The memory regions within the memory device 104 being in an operating state may include a portion of the memory regions (a portion of the memory cell array) being in an operating state, or all of the memory regions (all of the memory cell array) being in an operating state.

[0105] In some embodiments, the memory controller 106 receives a command from the host 108 and controls the storage area in the memory device 104 to perform programming, reading, or erasing operations, and the memory device 104 is in an operational state. In some embodiments, when no command is received from the host 108, the memory controller 106 can control the memory device 104 to perform operations, such as garbage collection, wear leveling, etc.

[0106] In some specific application embodiments of memory systems, when a storage area in memory device 104 remains inactive for a period of time—that is, after a storage area in memory device 104 has been idle for a period of time without being programmed, read, or erased—the first read attempt will result in a high Fail Bit Count (FBC), indicating numerous read errors. Subsequent reads will see the FBC drop to a normal level. This phenomenon is known as Temporary Read Errors (TREs). The occurrence of TREs will, to some extent, reduce the service quality of the memory system.

[0107] In some embodiments, when the storage area in the memory device 104 is idle for a period of time and not operated, the memory device 104 may be in a power-on state, but no corresponding operating voltage is applied to the word line or bit line; the memory device 104 may also be in a power-off state (e.g., a power-off state). In both cases, a TRE phenomenon will occur when the device is restored to the operating state. Among these, the TRE phenomenon when the device is restored to the operating state from a power-off non-operating state is more severe than the TRE phenomenon when the device is restored to the operating state from a power-on non-operating state.

[0108] The cause of TREs in NAND flash memory can be explained based on the physical structure of the memory cells. In some embodiments, combined with Figure 4 As shown, the NAND memory string 308 has a semiconductor channel, which can include polysilicon or other semiconductor materials. The difference in the occupancy rate of grain boundary traps (GBTs) in the semiconductor channel is one of the reasons for the large difference in FBC between the first and second read operations. Taking a polysilicon semiconductor channel as an example, when the memory cells in the NAND memory string 308 are programmed (written), due to the high voltage of the word line, the GBTs in the quasi-Fermi level of the polysilicon channel are likely to be fully occupied. After programming, as the word line voltage gradually decreases from the programming voltage to 0V, electrons in the GBTs at different energy levels will gradually migrate and leak current. When the NAND memory string 308 changes from an operating state to a non-operating state without programming, reading, or erasing, more GBTs will leak current in the polysilicon channel, resulting in a lower GBT occupancy rate. When the NAND memory string 308 returns to the operating state, the first read operation may result in a higher read FBC due to the lower GBT occupancy rate. In other embodiments, the charge trapping / storage layer of the NAND storage string 308 may also experience a decrease in GBT occupancy due to the lack of voltage applied to the word lines, which can also cause TRE in the memory device 104. For example, some storage areas in the memory device 104 store cold data that is not frequently programmed, read, or erased. These storage areas remain inaccessible for extended periods, leading to a more severe TRE when they are restored to an operational state, resulting in a higher FDC on the first read.

[0109] The second read operation following the first read operation results in a higher GBT occupancy rate, approaching the occupancy rate at the beginning of programming, due to the applied read voltage or pass voltage (Vpass) on the word line during the first read operation (which can exceed 5V). This leads to a smaller read FBC. Therefore, a higher GBT occupancy rate in the polysilicon channel results in a smaller read FBC. A longer first read operation duration and longer applied voltage on the word line result in more leaky GBTs being filled, leading to a lower read FBC. The non-operating states here include both power-on and power-off states. The TRE (Transient Reaction Time) upon returning to the operating state after power-off is more severe than that upon returning to the operating state after power-on. TRE at low temperatures is more severe than TRE at high temperatures, and the thicker the polysilicon channel film layer, the more severe the TRE. More severe TRE requires a longer first read operation duration to eliminate.

[0110] In some exemplary embodiments of this disclosure, the Time-Recovery (TRE) phenomenon can be eliminated or mitigated by optimizing the operating logic of the memory system 102 and the manufacturing process of the memory device 104, thereby reducing the time it takes for the memory device 104 to recover from a non-operating state to a normal read operation. For example, TRE can be reduced by decreasing the film thickness of the semiconductor channel; improving the film uniformity of the semiconductor channel can reduce void defects and thus reduce TRE. For another example, the first read operation can be defined as a pseudo-read operation, and subsequent read operations are considered normal read operations. This pseudo-read operation can last for a period of time to eliminate the TRE phenomenon, such as 60ms or longer. The memory controller 106 determines that the memory device 104 has recovered to a normal read level by monitoring that the FBC during the pseudo-read is less than a preset value for normal reads, thus enabling the memory system 102 to resume normal read operations.

[0111] The processing time for pseudo-read operations can be determined by setting different processing times for pseudo-read operations on the memory device 104 and testing the read function key (FBC). A test model can be established using machine learning and big data analysis to determine the time required to eliminate temporary repetitive errors (TREs) under various operating conditions. Based on this, the processing time can be appropriately increased to achieve better read performance. For example, at 25°C, the processing time for pseudo-read operations to eliminate TREs on the memory device 104 is 60ms; at 55°C, it is 20ms; and at 85°C, it is 10ms. The processing time is negatively correlated with temperature. The longest processing time for pseudo-read operations is determined based on the minimum operating temperature specified in the design standard of the memory device 104. This also eliminates TREs when the memory device 104 is at other high temperatures. Alternatively, temperature compensation can be performed based on this relationship between processing time and temperature, appropriately reducing the processing time based on the longest processing time at the lowest temperature to eliminate TREs under different operating conditions.

[0112] Reference Figure 6 As shown, the conventional read operation process in this embodiment may include a default read operation (FW default read) set in the firmware. If the default read operation fails, a read retry operation is performed. If the read retry operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation stops and fails due to the inability to correct errors. The memory controller 106 sends a read failure signal to the host 108. Error correction operations such as the read retry, soft decode, and RAID operation can be controlled by the error correction module (e.g., ECC module) in the memory controller 106, which controls the memory device 104. Control commands are sent from the memory controller 106 to the memory device 104 via interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via interface 516. It should be noted that subsequent operations can stop after any one of the read retry, soft decode, or RAID operation is successful.

[0113] In some exemplary embodiments, after the memory controller 106 sends the execution command, logical-physical address, and processing time of the pseudo-read operation to the memory device 104, the memory device 104 does not read information from the memory cell and send it to the memory controller 106 after completing the pseudo-read operation. This saves bandwidth on the bus or interface 516. Therefore, the pseudo-read operation is generally independent of... Figure 6The read operation flow is shown. Based on this, setting a pseudo-read operation to eliminate the TRE phenomenon will introduce additional firmware or operating procedures, increasing the complexity of the firmware or program of the memory controller 106 and the memory device 104, and reducing the efficiency of the read operation.

[0114] According to some aspects of embodiments of the present disclosure, a memory system 102 and a method of operating the memory system 102 are provided. The memory system 102 includes: at least one memory device 104 and a memory controller 106 coupled to the at least one memory device 104; the memory controller 106 is configured to:

[0115] In response to the failure of the first read operation when performing a read operation on the storage area in the memory device 104, at least some or all of the read error handling procedures are executed.

[0116] In some embodiments, before performing a read operation on a storage area in the memory device 104, no operation is performed on the storage area in the memory device 104 for a preset time; wherein, the operation may include a programming operation, a read operation, or an erase operation;

[0117] or

[0118] The first read operation when performing a read operation on the storage area in the memory device 104 is the first read operation when performing a read operation on the storage area in the memory device 104 after the memory system 102 is powered on.

[0119] In this embodiment, the first read operation can be the first read operation after the powered-on memory device 104 has been idle for a period of time (preset time), or it can be the first read operation after the powered-off memory device 104 has been powered on again. It can also be referred to as the first read operation after the storage area in the memory device 104 has returned to an operational state. The test method for the preset time may include: setting two read operations with different intervals, testing the increase in FBC (Fault-Based Curve) of the second read operation compared to the first read operation to establish a correspondence with the interval. The longer the interval, the more severe the TRE (True Error Reaction) phenomenon, and the greater the increase in FBC. When the preset time exceeds a certain value, at least some or all of the read error handling procedures need to be executed twice to eliminate the TRE phenomenon.

[0120] According to some aspects of embodiments of the present disclosure, embodiments of the present disclosure provide a memory system 102 and a method of operating the memory system 102, the memory system 102 including: at least one memory device 104 and a memory controller 106 coupled to the at least one memory device 104; the memory controller 106 is configured to: in response to a failure of the first read operation after the memory device 104 has recovered to an operating state, execute part or all of the processes in at least two read error handling processes.

[0121] The memory controller 106 interacts with the host 108 via an interface (e.g., PCIe interface, SATA interface). The memory controller 106 receives read commands from the host 108 through interfaces such as PCIe, and, based on the logical-physical address mapping table, controls the control logic in the memory device 104 to read the memory cells corresponding to the physical addresses in the memory cell array. The read information is then sent back to the memory controller 106, which in turn sends the read information back to the host 108. When the memory controller 106 controls the memory device 104 to perform a default read operation, the read operation can be hardware-decoded. If a read error occurs, error correction operations, such as ECC error correction, will be triggered.

[0122] When the host 108 needs relevant data, it sends a read command to the memory controller 106. In response to the data read command from the host 108, the memory controller 106 controls the memory device 104 to return from a non-operational state to an operational state. At this time, the memory device 104 and its interfaces, such as PCIe, are powered on and in their rated operating state. The memory controller 106 controls the memory device 104 to read the memory cell corresponding to the physical address of the logical address. Alternatively, based on the memory system 102's own management needs or performance optimization, the memory controller 106 can control the memory device 104 to perform operations such as garbage collection and wear leveling when there are no commands from the host 108. The memory controller 106 then controls the memory device 104 to return to an operational state.

[0123] Memory controller 106 controls memory device 104 based on Figure 6 The conventional read operation process shown first performs an initial default read operation on the corresponding memory cell. The read voltage is the default read voltage from the relevant read voltage lookup table. This read operation may succeed or fail due to the TRE phenomenon. When the memory controller 106 determines that the initial default read operation has failed, the memory controller 106 controls the memory device 104 to execute part or all of the two read error handling processes. The read error handling process in this embodiment may include... Figure 6The error correction operations shown, such as rereading, software decoding, and RAID (Redundant Array of Independent Disks) operations, are executed in the same order and logic as described above. Figure 6 shown.

[0124] Specifically, refer to Figure 7a As shown, when the memory controller 106 determines that the first default read operation fails, it performs two or more reread operations. The reread operation can apply hardware decoding operation, and a preset time interval can be set between two adjacent reread operations.

[0125] In some specific embodiments, the process of determining the reread voltage may include: the memory controller 106 (e.g., the ECC module in the memory controller 106) queries the corresponding reread table to obtain the corresponding voltage offset value, which can be a positive or negative offset value. This voltage offset value is then summed with the default read voltage to obtain the reread voltage. The memory controller 106 controls the memory device 104 to perform a reread operation on the memory cell at the corresponding physical address using this reread voltage. It should be noted that the memory controller 106 may use a polling method when querying the reread table. A reread table may include multiple sub-tables, such as m sub-tables, where m is a natural number greater than 1. Each sub-table may include a voltage offset value for the corresponding storage state of the corresponding memory cell. The process involves sequentially querying from the first sub-table to the m-th sub-table, obtaining one voltage offset value per query, and then summing these values ​​to obtain a reread voltage. The memory device 104 then uses this reread voltage for reading. Therefore, a single reread operation can have up to m sub-read operations. This embodiment does not limit this, as long as the total processing time can eliminate the TRE phenomenon, the normal read operation process can be restored.

[0126] In some specific embodiments, the processing time of each reread operation can be the average processing time obtained by the memory device 104 through multiple tests before it leaves the factory. The total processing time of multiple reread operations (excluding the preset interval) is greater than or equal to the processing time of the false read in some embodiments, that is, greater than or equal to the minimum time for eliminating TRE phenomenon at the current temperature. The total processing time can be the first time for eliminating TRE phenomenon determined according to the temperature of the memory device 104, that is, the time for the memory device 104 to recover to the point where it can execute. Figure 6 The duration of the operation status in the typical read operation process shown.

[0127] For example, at 25°C, the total processing time for multiple reread operations is greater than or equal to 60ms. The preset interval duration can range from 0 to 100ms, for example, 10ms. This preset duration can be determined based on the GBT leakage rate of the semiconductor channel when the memory device 104 is in operation. Within this preset interval, the GBT of the semiconductor channel has virtually no leakage or minimal leakage, and the GBT occupancy rate does not decrease significantly or decreases only slightly, so as not to cause a large increase in FBC. At this time, the default read voltage can still distinguish the different storage states of the memory cell. Within this preset interval duration, the memory controller 106 can determine whether the reread operation has passed, or determine whether the FDC meets the preset conditions of the operation state and thus the TRE phenomenon has been eliminated. This determines whether to continue subsequent reread operations, thereby saving operation time and improving the read rate. When multiple reread operations fail, the TRE phenomenon has been eliminated. If the read operation still fails, it can be determined that the read operation failure is not caused by the TRE phenomenon, and a software decoding operation can be performed.

[0128] In some embodiments, continue to refer to Figure 7a As shown, the process can exit when a single reread operation is sufficient for a successful read, or when the preset number of reread operations has not been reached (i.e., the total processing time of multiple reread operations has not reached the preset time (first time)). Figure 7a The read error handling process shown can be entered during the next read. Figure 6 The diagram illustrates the standard read operation flow. In some other embodiments, multiple reread operations are performed regardless of whether the reread operation succeeds or fails, to ensure that the TRE phenomenon is eliminated. If the last reread operation fails, one or more reread operations can be performed, or the software decoding operation can be initiated.

[0129] In some embodiments, refer to Figure 7b As shown, the reread operation and software decoding operation are treated as a whole processing flow. The process of sequentially executing the reread operation and software decoding operation can be defined as the first type of read error handling flow, and the parity check operation of the Redundant Array of Independent Disks (RAID) can be defined as the second type of read error handling flow. The average processing time of the first type of read error handling flow is less than the average processing time of the second type of read error handling flow. When the memory controller 106 determines that the first default read operation has failed, it executes the first type of read error handling flow two or more times. The interval between adjacent first type of read error handling flows can be set. Within a first type of read error handling flow, there can also be a time interval between a reread operation and a software decoding operation. When multiple first type of read error handling flows still fail, the TRE phenomenon has been eliminated. If the read operation still fails, it can be determined that the read operation failure is not caused by the TRE phenomenon. At this time, the Redundant Array of Independent Disks (RAID) operation can be executed.

[0130] In some embodiments, refer to Figure 7c As shown, the read re-read operation, software decoding operation, and Redundant Array of Independent Disks (RAID) operation will be executed sequentially, and repeated two or more times, that is, all processes in the entire read error handling process will be executed two or more times. In some specific embodiments, the software decoding operation can be understood as performing data re-decoding through the decoding unit (e.g., software decoder) in the memory controller 106, and then performing a read operation based on the re-decoded data. The Redundant Array of Independent Disks (RAID) operation can be understood as achieving data mirroring through secondary encoding, reconstructing the stored data and its parity check data. Typically, the re-encoding of the stored data for the redundant array is performed in the data buffer of the memory controller 106.

[0131] In some specific embodiments, the memory controller 106 can obtain the current temperature of the memory device 104 or the memory system 102 to determine the total processing time of the read error handling process. The lower the temperature, the more severe the TRE phenomenon of the memory device 104, and the longer the total processing time of the read error handling process needs to be. This can be flexibly selected. Figures 7a to 7c The processing flow is shown below. When the memory system 102 leaves the factory, Figure 6 The standard read operation flow shown has been written into the execution firmware or program, and the processing time for each step is fixed. For the same total processing time, Figure 7a The reread operation shown has the most iterations. Figure 7b The loop count shown is the number of times the first type of read error handling process is executed. Figure 7c The example shown minimizes the number of loops required to execute all read error handling procedures. Conversely, for different total processing times, the option with the minimum total processing time is [optional]. Figure 7a The processing flow shown allows you to select the total processing time. Figure 7b The processing flow shown allows you to select the option with the maximum total processing time. Figure 7c The processing flow is shown below.

[0132] The embodiments disclosed herein are based on Figure 6The illustrated conventional read operation flow, including error correction operations, replaces the pseudo-read operation with multiple partial or full steps from error correction operations such as reread operations, software decoding, and independent disk redundant array (RAID) operations after the initial default read failure. The total duration of these steps is greater than or equal to the duration of the pseudo-read operation in related technical solutions (i.e., the duration of TRE elimination) to eliminate the TRE phenomenon when the storage area in the memory device 104 recovers to the operational state. This embodiment eliminates the TRE phenomenon using the default read operation firmware or program built into the original memory system 102 without adding any steps to the original read operation flow firmware or program. This facilitates firmware or program simplification, reducing development costs and the processing load on the memory controller 106.

[0133] In some embodiments, refer to Figure 7b As shown, the read error handling process of the memory device 104 includes a first type of read error handling process and a second type of read error handling process executed sequentially; the average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

[0134] In some embodiments, refer to Figure 7b As shown, the first type of read error handling process includes: reread operation and software decoding operation; the second type of read error handling process includes: independent disk redundant array RAID operation. Figure 7b In the operation flowchart, the first type of read error handling process is marked with a dashed box. In response to the failure of the first default read operation when the storage area in the memory device 104 is restored to the operating state, the memory controller 106 performs a reread operation and a software decoding operation in sequence.

[0135] In some embodiments, refer to Figure 7b As shown, the memory controller 106 is configured as follows:

[0136] During each execution of the Type I read error handling process, in response to a failed reread operation, a software decoding operation is performed on the read data. In some other embodiments, in response to a successful reread operation, the software decoding operation is still performed until the preset number of Type I read error handling processes are completed, to ensure sufficient total processing time to eliminate the TRE phenomenon.

[0137] In some embodiments, refer to Figure 7b As shown, in response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, at least two Type 1 read error handling procedures are executed.

[0138] In some embodiments, refer to Figure 7b As shown, the memory controller 106 is configured as follows:

[0139] If the read operation still fails after executing the first type of read error handling procedure at least twice, the second type of read error handling procedure is executed.

[0140] In this embodiment, if multiple Type I read error handling processes still fail, the TRE phenomenon has been eliminated. If the read operation still fails, it can be determined that the failure is not caused by the TRE phenomenon, and a Redundant Array of Independent Disks (RAID) operation can be performed. Alternatively, if multiple Type I read error handling processes still fail, it is considered that the total processing time of the multiple Type I read error handling processes is insufficient to eliminate the TRE phenomenon, and the operation time needs to be increased further. In this case, a Redundant Array of Independent Disks (RAID) operation with a longer processing time is performed to eliminate the TRE phenomenon. Regardless of which operation process succeeds, the process can be exited. Figure 7b The error handling process shown will proceed to the next read operation. Figure 6 The above describes the standard read operation flow. Alternatively, regardless of whether the reread operation succeeds or not, the Type I read error handling process must be executed multiple times to ensure that the TRE phenomenon is eliminated.

[0141] In some embodiments, refer to Figure 7b As shown, the memory controller 106 is configured as follows:

[0142] If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

[0143] After performing the reread operation, software decoding operation, and the relatively long-processing independent disk redundant array RAID operation, sufficient processing time has been given to eliminate the TRE phenomenon. If the read operation still fails at this point, it is considered that the error correction mechanism of the memory controller 106 cannot correct the error. At this time, the data may be lost or corrupted, and the memory controller 106 issues a read fail message to the host 108. The second read operation can proceed as follows: Figure 6 The standard reading process is as shown.

[0144] In some embodiments, the memory controller 106 is configured to:

[0145] A preset time interval is set between two adjacent Type I read error handling processes.

[0146] The first type of read error handling includes a single reread operation, or a loop of reread and software decoding operations. A preset time interval can be maintained between each first type of read error handling process, or between each reread and software decoding operation. The preset time interval can range from 0 to 100 ms, for example, 10 ms. This short interval will not cause new TRE phenomena. The memory controller 106 can determine whether the read operation has succeeded within this preset time interval, or whether the FDC (Frequency Directional Control) meets the usual preset conditions to determine that the TRE phenomenon has been eliminated; thereby determining whether to continue subsequent operations, thus saving operation time and improving the read rate.

[0147] In some embodiments, different Figure 7b As shown, Figure 7a The first type of read error handling shown includes one operation, and the first type of read error handling process includes: reread operation;

[0148] The second type of read error handling process includes: software decoding operation.

[0149] If multiple read operations fail, a software decoding operation is performed. If the software decoding operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the memory controller 106 sends a read failure message to the host 108.

[0150] In some embodiments, refer to Figure 7c As shown, the first type of read error handling may include a reread operation. In some embodiments, the memory controller 106 is configured to:

[0151] Obtain a first duration; the first duration is longer than the duration for which the storage area in the memory device 104 returns to the operating state;

[0152] Based on the first duration, determine the number of times the first type of read error handling process will be executed.

[0153] In some embodiments, the memory controller 106 is configured to:

[0154] The first duration is determined based on the temperature at which the memory device 104 is located; the first duration is negatively correlated with the temperature at which the memory device 104 is located.

[0155] In some embodiments, the memory controller 106 is configured to:

[0156] In response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, the first type of read error handling process is executed multiple times until the preset number of times is reached.

[0157] The first duration is the total processing time for multiple Type 1 read error handling processes, excluding the preset interval between each operation. After executing multiple Type 1 read error handling processes, the Type 1 read error process can be... Figure 7a A single reread operation in the middle can also be Figure 7b The sequence shown is reread operation and software decoding operation. The average processing time of a single reread operation and software decoding operation in the same memory system 102 can be determined according to the firmware. The first time can be determined based on the test data of eliminating TRE in the memory device 104 at different temperatures, and then the number of times the first time is executed can be determined. If the read is successful before the preset time is reached during the execution of the first type of read error handling process, the first type of read error handling process can be exited, and the next read operation will proceed according to the... Figure 6 The standard read operation procedure shown is followed. Alternatively, regardless of whether the read operation is successful or not, the first type of read error handling procedure is executed multiple times until a preset number of times is reached to ensure that the TRE phenomenon is eliminated, and the next read operation follows the procedure. Figure 6 The standard read operation process is as shown. If the first type of read error handling process fails after a preset number of iterations, a redundant array (RAID) operation is performed. If the operation still fails, the memory controller 106 sends a read failure message to the host 108.

[0158] In some embodiments, the memory system 102 includes a general-purpose flash storage (UFS) device or an embedded multimedia card (eMMC) device.

[0159] According to some aspects of embodiments of this disclosure, Figure 8 A flowchart illustrating an operation method for a memory system 102 is provided, the operation method including:

[0160] In response to an access command, a read operation is performed on a storage area in the memory device 104;

[0161] In response to the failure of the first read operation when performing a read operation on a storage area in the memory device 104, at least some or all of the read error handling procedures are executed.

[0162] In some embodiments, before performing a read operation on a storage area in the memory device 104, no operation is performed on the storage area in the memory device 104 for a preset time; wherein, the operation may include a programming operation, a read operation, or an erase operation;

[0163] or

[0164] The first read operation when performing a read operation on the storage area in the memory device 104 is the first read operation when performing a read operation on the storage area in the memory device 104 after the memory system 102 is powered on.

[0165] According to some aspects of embodiments of this disclosure, Figure 9 A flowchart illustrating an operation method for a memory system 102 is provided, the operation method including:

[0166] In response to an access command, the storage area in the memory device 104 is restored to the operational state;

[0167] In response to the failure of the first read operation after the storage area in the self-memory device 104 is restored to the operating state, at least some or all of the read error handling procedures are executed.

[0168] In this embodiment of the present disclosure, the access command can be sent from the host 108 to the memory controller 106 via an interface such as PCIe. In response to the access command, the memory controller 106 restores the storage area in the memory device 104 to an operational state. If the first read operation after the storage area in the memory device 104 is restored to the operational state fails, the memory controller 106 controls the memory device 104 to execute part or all of the steps in the at least two read error handling processes. Alternatively, based on the memory system 102's own management needs or performance optimization commands, the memory controller 106 can, without instructions from the host 108, control the storage area in the memory device 104 to restore to an operational state and perform operations such as garbage collection and wear leveling.

[0169] In some embodiments, the read error handling process of the memory device 104 includes a first type of read error handling process and a second type of read error handling process executed sequentially; the average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

[0170] In some embodiments, performing at least two reads of part or all of the error handling process includes:

[0171] Execute the first type of read error handling process at least twice.

[0172] In some embodiments, the operating method further includes:

[0173] A preset time interval is set between two adjacent Type I read error handling processes.

[0174] In some embodiments, the operating method further includes:

[0175] If the read operation still fails after at least two first-type read error handling procedures, the second-type read error handling procedure is executed.

[0176] In some embodiments, the first type of read error handling process includes: reread operation and software decoding operation;

[0177] The second type of read error handling process includes: independent disk redundant array RAID operation.

[0178] In some embodiments, the operating method further includes:

[0179] During each execution of the first type of read error handling process, in response to the failure of the reread operation, a software decoding operation is performed on the read data.

[0180] In some embodiments, the operating method further includes:

[0181] If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

[0182] In some embodiments, the first type of read error handling process includes: a reread operation;

[0183] The second type of read error handling process includes: software decoding operation.

[0184] In some embodiments, the operating method further includes:

[0185] Obtain a first duration; the first duration is longer than the duration for which the storage area in the memory device 104 returns to the operating state;

[0186] Based on the first duration, determine the number of times the first type of read error handling process will be executed.

[0187] In some embodiments, the operating method further includes:

[0188] The first duration is determined based on the temperature at which the memory device 104 is located; the first duration is negatively correlated with the temperature at which the memory device 104 is located.

[0189] In some embodiments, the operating method further includes:

[0190] In response to the failure of the first read operation after the storage area in the memory device 104 is restored to the operating state, the first type of read error handling process is executed multiple times until the preset number of times is reached.

[0191] According to some aspects of embodiments of this disclosure, a readable storage medium is provided, the readable storage medium storing a computer program that, when executed, implements the operation methods of the above embodiments. The readable storage medium may include NAND flash memory, and the storage cells of the NAND flash memory may include floating-gate type storage cells with floating-gate transistors, or charge-trapping type storage cells with charge-trapping transistors.

[0192] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory system, characterized in that, include: At least one memory device and a memory controller coupled to said at least one memory device; The memory controller is configured to: In response to the failure of the first read operation after no operating voltage has been applied to the word line or bit line of the storage area in the memory device for more than a preset time, some or all of the processes in the multiple read error handling process are executed on the storage area until the preset number of times is reached. A first duration is determined based on the temperature at which the memory device is located, and the first duration is negatively correlated with the temperature at which the memory device is located; Based on the first duration, determine the preset number of times to execute part or all of the read error handling process; Specifically, when any part of the read error handling process is successfully corrected, the current read error handling process is exited.

2. The memory system according to claim 1, characterized in that, The read error handling process of the memory device includes a first type of read error handling process and a second type of read error handling process executed sequentially. The average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

3. The memory system according to claim 2, characterized in that, In response to the failure of the first read operation after the storage area in the memory device is restored to the operating state, a first type of read error handling process is executed a preset number of times.

4. The memory system according to claim 3, characterized in that, The memory controller is configured to: A preset time interval is set between two adjacent Type I read error handling processes.

5. The memory system according to claim 3, characterized in that, The memory controller is configured to: If the read operation still fails after the first type of read error handling process has been executed a preset number of times, the second type of read error handling process will be executed.

6. The memory system according to claim 5, characterized in that, The first type of read error handling process includes: reread operation and software decoding operation; The second type of read error handling process includes: independent disk redundant array RAID operation.

7. The memory system according to claim 6, characterized in that, The memory controller is configured to: During each execution of the first type of read error handling process, in response to the failure of the reread operation, a software decoding operation is performed on the read data.

8. The memory system according to claim 6, characterized in that, The memory controller is configured to: If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

9. The memory system according to claim 5, characterized in that, The first type of read error handling process includes: reread operation; The second type of read error handling process includes: software decoding operation.

10. The memory system according to claim 3, characterized in that, The memory controller is configured to: The first duration is obtained; the first duration is greater than the duration for which the storage area in the memory device recovers to the operating state; Based on the first duration, determine the number of times the first type of read error handling process is executed.

11. The memory system according to claim 10, characterized in that, The memory controller is configured to: The first type of read error handling process is executed multiple times until the preset number of times is reached.

12. The memory system according to claim 1, characterized in that, Before performing a read operation on the storage area in the memory device, no operation has been performed on the storage area in the memory device for a preset time; or The first read operation when performing a read operation on the storage area of ​​the memory device is the first read operation when performing a read operation on the storage area of ​​the memory device after the memory system is powered on.

13. The memory system according to any one of claims 1 to 12, characterized in that, The memory system includes: a general-purpose flash storage (UFS) device or an embedded multimedia card (eMMC) device.

14. A method for operating a memory system, characterized in that, include: In response to an access command, a read operation is performed on a storage region in the memory device; In response to the failure of the first read operation after no operating voltage has been applied to the word line or bit line of the storage area in the memory device for more than a preset time, some or all of the processes in the multiple read error handling process are executed on the storage area until the preset number of times is reached. A first duration is determined based on the temperature at which the memory device is located, and the first duration is negatively correlated with the temperature at which the memory device is located; Based on the first duration, determine the preset number of times to execute part or all of the read error handling process; Specifically, when any part of the read error handling process is successfully corrected, the current read error handling process is exited.

15. The operating method according to claim 14, characterized in that, The read error handling process of the memory device includes a first type of read error handling process and a second type of read error handling process executed sequentially. The average processing time of the first type of read error handling process is less than the average processing time of the second type of read error handling process.

16. The operating method according to claim 15, characterized in that, The step of performing part or all of the steps in the multiple read error handling process on the storage area until a preset number of times is reached includes: In response to the failure of the first read operation after the storage area in the memory device is restored to the operating state, a first type of read error handling process is executed a preset number of times.

17. The operating method according to claim 16, characterized in that, The method further includes: A preset time interval is set between two adjacent Type I read error handling processes.

18. The operating method according to claim 16, characterized in that, The method further includes: If the read operation still fails after the first type of read error handling process has been executed a preset number of times, the second type of read error handling process will be executed.

19. The operating method according to claim 18, characterized in that, The first type of read error handling process includes: reread operation and software decoding operation; The second type of read error handling process includes: independent disk redundant array RAID operation.

20. The operating method according to claim 19, characterized in that, The method further includes: During each execution of the first type of read error handling process, in response to the failure of the reread operation, a software decoding operation is performed on the read data.

21. The operating method according to claim 19, characterized in that, The method further includes: If the read operation still fails after completing the second type of read error handling process, a read failure message is issued.

22. The operating method according to claim 18, characterized in that, The first type of read error handling process includes: reread operation; The second type of read error handling process includes: software decoding operation.

23. The operating method according to claim 16, characterized in that, The method further includes: The first duration is obtained; the first duration is greater than the duration for which the storage area in the memory device recovers to the operating state; Based on the first duration, determine the number of times the first type of read error handling process is executed.

24. The operating method according to claim 23, characterized in that, The method further includes: The first type of read error handling process is executed multiple times until the preset number of times is reached.

25. The operating method according to claim 14, characterized in that, Before performing a read operation on the storage area in the memory device, no operation has been performed on the storage area in the memory device for a preset time; or The first read operation when performing a read operation on the storage area of ​​the memory device is the first read operation when performing a read operation on the storage area of ​​the memory device after the memory system is powered on.

26. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed, implements the operating method as described in any one of claims 14-25.

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