Pixel circuit and driving method thereof, display panel and display device

Abstract

The embodiment of the invention provides a pixel circuit and a driving method thereof, a display panel and a display device, relates to the technical field of display, and aims to reduce a flicker value. The pixel circuit comprises a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit and a storage sub-circuit. The driving sub-circuit is configured to control the conduction and cut-off of a circuit between the second node and the third node under the control of the voltage of the first node. And the compensation sub-circuit is configured to respond to a first scanning signal received at the first scanning signal end and control conduction and cut-off of a circuit between the first node and the third node. The reset sub-circuit is configured to transmit a first initialization signal received at a first initialization signal end to the first node in response to a reset signal received at a reset signal end. The storage sub-circuit is configured to store voltages of a first node and a second node. The method is used for image display.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] With the rapid development of display technology, display devices have gradually become prevalent in people's lives. Among them, organic light emitting diodes (OLED) have been widely used in smart products such as mobile phones, TVs, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display.

[0003] Currently, display devices use display panels with variable refresh rates to meet users' needs for low power consumption and high refresh rates. However, when displaying at a low frequency, the frame rate of the display panel is reduced, and the human eye is more sensitive to the flicker of the display panel, causing the human eye to perceive flickering on the display screen. Summary of the invention

[0004] The present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device, so as to reduce the flicker value of the display panel and improve the problem that the human eye can perceive flickering on the display screen.

[0005] In one aspect, a pixel circuit is provided, wherein the pixel circuit comprises a driving subcircuit, a compensation subcircuit, a reset subcircuit and a storage subcircuit.

[0006] The driving subcircuit is coupled to the first node, the second node and the third node, and is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node.

[0007] The compensation subcircuit is coupled to the first scan signal terminal, the first node and the third node, and is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to the first scan signal received at the first scan signal terminal.

[0008] The reset subcircuit is coupled to the first initialization signal terminal, the reset signal terminal and the first node. The reset subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal received at the reset signal terminal.

[0009] The storage subcircuit is coupled to the first voltage signal terminal, the first node and the second node. The storage subcircuit is configured to store voltages of the first node and the second node.

[0010] In some embodiments, the storage subcircuit includes a first storage capacitor and a second storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the first node. A first plate of the second storage capacitor is connected to the first voltage signal terminal, and a second plate of the second storage capacitor is connected to the second node.

[0011] In some embodiments, the compensation subcircuit includes a first sub-transistor and a second sub-transistor connected in series, the first end of the first sub-transistor is connected to the first node, the second end of the first sub-transistor and / or the first end of the second sub-transistor is connected to a fourth node, the second end of the second sub-transistor is connected to the third node, and the control electrodes of the first sub-transistor and the second sub-transistor are connected to the first scanning signal terminal. The pixel circuit also includes an anti-leakage subcircuit, which is coupled to a control signal terminal, a constant voltage terminal and the fourth node. The anti-leakage subcircuit is configured to transmit the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.

[0012] In some embodiments, the pixel circuit further includes a light emitting control subcircuit, the light emitting control subcircuit is coupled to the first voltage signal terminal, the enable signal terminal, the second node, the third node and the fifth node. The fifth node is connected to the anode of the light emitting device. The light emitting control subcircuit is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal and the second node in response to the enable signal received at the enable signal terminal; and control the conduction and cutoff of the circuit between the third node and the fifth node; wherein the signals received at the enable signal terminal and the control signal terminal are the same.

[0013] In some embodiments, the pixel circuit further includes a data writing subcircuit, the data writing subcircuit is coupled to the data signal terminal, the second scanning signal terminal and the second node. The data writing subcircuit is configured to transmit the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal; and transmit the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal; the data refresh signal is the data signal received by the pixel circuits of other rows.

[0014] In some embodiments, the cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal. Moreover, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to one row scanning period. The row scanning period is the duration of one working voltage of the second scanning signal.

[0015] In some embodiments, the start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal. Moreover, the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period. The row scanning period is the duration of one working voltage of the second scanning signal.

[0016] In some embodiments, the transistor included in the compensation subcircuit is a P-type transistor. The duration of the operating voltage of the first scanning signal is greater than or equal to 4 row scanning periods. The voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works. The row scanning period is the duration of an operating voltage of the second scanning signal. The time of the first operating voltage of the second scanning signal coincides with the 2Nth row scanning period of the operating voltage of the first scanning signal, N≥2, and N is an integer.

[0017] In some embodiments, the start and end time of the second operating voltage of the second scanning signal is between the end time of the operating voltage of the first scanning signal and the start time of the operating voltage of the enable signal. Moreover, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period. The time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period. The row scanning period is the duration of one operating voltage of the second scanning signal.

[0018] In some embodiments, the data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.

[0019] In some embodiments, the reset subcircuit is further coupled to the second initialization signal terminal, the third scan signal terminal and the fifth node. The reset subcircuit is further configured to transmit the second initialization signal received at the second initialization signal terminal to the fifth node under the control of the operating voltage of the third scan signal received at the third scan signal terminal.

[0020] In some embodiments, the start time of the working voltage of the reset signal is before the start time of the working voltage of the first scanning signal. Moreover, the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods. And / or; the end time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal; and the time interval between the end time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods.

[0021] In the pixel circuit of the disclosed embodiment, after a frame of display starts, the storage subcircuit can store the voltage at the second node after the previous frame of display ends, so that the second node maintains a relatively stable electric potential corresponding to the first voltage signal, thereby causing the first node and the third node of the driving subcircuit to generate a stable and large bias voltage, improving the hysteresis characteristics of the driving subcircuit, thereby improving the afterimage performance of the sub-pixel, reducing the flicker value of the display panel, and improving the problem of the human eye being able to perceive flickering in the display screen.

[0022] On the other hand, a method for driving a pixel circuit is provided. The method for driving a pixel circuit is used to drive the pixel circuit as described in any of the above embodiments. A display frame includes a refresh frame, and the refresh frame includes a first reset phase and a second reset phase.

[0023] In the first reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal. And, the storage subcircuit stores the voltage of the second node after the end of the previous frame. In the second reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal. The compensation subcircuit transmits the voltage of the first node to the third node in response to the operating voltage of the first scan signal received at the first scan signal terminal. And, the driving subcircuit transmits the voltage of the third node to the second node under the control of the voltage of the first node.

[0024] In some embodiments, the pixel circuit further includes a data writing subcircuit, and the refresh frame further includes a first data writing phase and a second data writing phase.

[0025] In the first data writing phase, the data writing subcircuit transmits the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal, and writes the data signal into the storage subcircuit. The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node. The compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scanning signal received at the first scanning signal terminal.

[0026] In the second data writing phase, the storage subcircuit discharges and transmits the stored data signal to the second node. The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node. The compensation subcircuit transmits the voltage of the third node to the first node in response to the working voltage of the first scanning signal received at the first scanning signal terminal.

[0027] In some embodiments, the transistor included in the compensation subcircuit is a P-type transistor; the second reset phase includes at least 3 row scanning periods. In the second reset phase, the voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works. The first data writing phase is located after the second reset phase and coincides with the 2Nth row scanning period after the start time of the second reset phase, N≥2, and N is an integer.

[0028] In some embodiments, the pixel circuit includes a data writing subcircuit, the refresh frame further includes a third reset phase and a first light emitting phase, the third reset phase is located between the second data writing phase and the first light emitting phase. In the third reset phase, the data writing subcircuit transmits the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scan signal received at the second scan signal terminal.

[0029] In some embodiments, the difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scanning period. And / or, the difference between the end time of the third reset phase and the start time of the first light emitting phase is greater than or equal to one row scanning period.

[0030] In some embodiments, the difference between the start time of the first reset phase and the start time of a frame in which the first reset phase is located is greater than or equal to two row scanning periods.

[0031] In some embodiments, the pixel circuit includes a data writing subcircuit, a leakage prevention subcircuit, and a light emitting control subcircuit. The pixel circuit has a first refresh frequency and a second refresh frequency, and the second refresh frequency is less than the first refresh frequency. At the first refresh frequency, a display frame includes a refresh frame; at the second refresh frequency, a display frame includes a refresh frame and at least one holding frame. The holding frame includes a black insertion stage, a fourth reset stage, and a second light emitting stage.

[0032] In the black insertion stage, the light emitting control subcircuit is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal.

[0033] In the fourth reset phase, the data writing sub-circuit transmits the data holding signal received at the data signal terminal to the second node in response to the third operating voltage of the second scan signal received at the second scan signal terminal.

[0034] In the second light-emitting stage, the light-emitting control subcircuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the operating voltage of the enable signal received at the enable signal terminal; the driving subcircuit generates a driving current signal according to the voltage of the first node and the voltage of the second node; and the light-emitting control subcircuit transmits the driving current signal to the light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; the leakage prevention subcircuit transmits the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.

[0035] In some embodiments, the difference between the end time of the fourth resetting stage and the start time of the second light emitting stage is greater than or equal to one row scanning period.

[0036] In another aspect, a display panel is provided. The display device includes a plurality of pixel circuits as described in any of the above embodiments. The plurality of pixel circuits are arranged in M ​​rows and N columns, each row includes N pixel circuits arranged along a first direction, each column includes M pixel circuits arranged along a second direction, M>1, N>1, and M and N are both integers.

[0037] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0038] The display panel further includes a first gate driving circuit, which includes M+Q cascaded first shift registers, from the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers; each of the first shift registers includes a first signal output terminal. The first scanning signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P+Qth first shift register; the reset signal terminal of the P-th row pixel circuit is connected to the first output terminal of the Pth first shift register; P≤M, Q>0, and P and Q are both integers.

[0039] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.

[0040] The display panel also includes a second gate driving circuit and a third gate driving circuit. The second gate driving circuit includes M cascaded second shift registers, from the first stage second shift register to the last stage second shift register, and the M second shift registers are respectively the 1st to the Mth second shift registers. Each of the second shift registers includes a second signal output terminal. Among them, the first scanning signal terminal of the Pth row pixel circuit is connected to the second signal output terminal of the Pth second shift register, P≤M, and P is an integer;

[0041] The third gate driving circuit includes M cascaded third shift registers, from the first stage third shift register to the last stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers. Each of the third shift registers includes a third signal output terminal. The reset signal terminal of the Pth row pixel circuit is connected to the third signal output terminal of the Pth third shift register, P≤M, and P is an integer.

[0042] In another aspect, a display device is provided, wherein the display device comprises the display panel as described in any one of the above embodiments.

[0043] The beneficial effects of the driving method of the pixel circuit, the display panel, and the display device provided in the embodiments of the present disclosure are the same as the beneficial effects of the pixel circuit provided by the above technical solution, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0045] Figure 1 is a structural diagram of a display device according to some embodiments;

[0046] Figure 2 is a structural diagram of another display device according to some embodiments;

[0047] Figure 3 for Figure 1 A sectional view along the section line AA';

[0048] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0049] Figure 5 for Figure 4 A cross-sectional view along the section line CC';

[0050] Figure 6 is a structural block diagram of a pixel circuit according to some embodiments;

[0051] Figure 7 for Figure 6 A circuit diagram of a pixel circuit shown;

[0052] Fig. 8A is a structural block diagram of another pixel circuit according to some embodiments;

[0053] Figure 8B is a structural block diagram of yet another pixel circuit according to some embodiments;

[0054] Fig.9A for Fig. 8A A circuit diagram of a pixel circuit shown;

[0055] Fig. 9B for Figure 8B A circuit diagram of a pixel circuit shown;

[0056] Fig.10 is a structural diagram of a gate driving circuit of a display panel according to some embodiments;

[0057] Fig.11 is a structural diagram of another gate driving circuit of a display panel according to some embodiments;

[0058] Fig.12 is a structural diagram of a gate driving circuit of another display panel according to some embodiments;

[0059] Fig.13 is a timing diagram of a pixel circuit according to some embodiments;

[0060] Fig.14 is another timing diagram of a pixel circuit according to some embodiments;

[0061] Fig.15 is another timing diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0062] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0063] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0064] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0065] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0066] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0067] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0068] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0069] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0070] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0071] As used herein, "about," "approximately," or "substantially" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0072] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0073] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0074] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0075] In this specification, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that, unless explicitly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as an ideal or overly formal meaning.

[0076] In the present disclosure, terms such as "lower", "below", "above", and "upper" and the like are used to explain the relationship between components shown in the drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or may be described based on the order in which the process steps are formed, but are not limited thereto.

[0077] The term "opposed to" means that the first element may be directly or indirectly opposed to the second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element may be understood to be indirectly opposed to each other although still opposed to each other.

[0078] In the embodiments of the present disclosure, the transistors used may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples.

[0079] In the embodiments of the present disclosure, the control electrode of each thin film transistor used is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0080] In the embodiments of the present disclosure, the capacitor may be a capacitor device manufactured separately through a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each capacitor electrode of the capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or realized by utilizing the parasitic capacitor between the circuits of the circuit itself.

[0081] In the embodiments of the present disclosure, the first node, the second node, the first control node, the second control node and other nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0082] In the embodiments of the present disclosure, “operating voltage” refers to a voltage that can turn on the operated transistor included therein; correspondingly, “non-operating voltage” refers to a voltage that cannot turn on the operated transistor included therein.

[0083] In the embodiments of the present disclosure, "low level" refers to a voltage that can turn on the operated P-type transistor included therein, but cannot turn on the operated N-type transistor included therein (i.e., the N-type transistor is turned off); correspondingly, "high level" refers to a voltage that can turn on the operated N-type transistor included therein, but cannot turn on the operated P-type transistor included therein (i.e., the P-type transistor is turned off).

[0084] like Figure 1 and Figure 2 As shown, some embodiments of the present disclosure provide a display device 1000, which may be any device that displays images, whether in motion (eg, video) or fixed (eg, still image), and whether text or text.

[0085] Exemplarily, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0086] For example, Figure 1 As shown, the display device 1000 may be a portable display product; for example, the display device 1000 may be Figure 1 For another example, see Figure 2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be Figure 2 The watch shown in.

[0087] The display device 1000 is used as an example below. Figure 1 Taking the mobile phone shown as an example, some embodiments of the present disclosure are schematically described, but the implementation methods of the present disclosure are not limited thereto.

[0088] In some embodiments, see Figure 3 , the display device 1000 includes a display panel 100 .

[0089] The display panel 100 includes a light-emitting side and a non-light-emitting side that are arranged opposite to each other. The light-emitting side is the side of the display panel 100 used for display, that is, Figure 3 The upper side of the .

[0090] For example, Figure 3 As shown, the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 and other electronic components.

[0091] See also Figure 3The cover plate 300 may be a single-layer glass cover plate, or may include a stack of multiple layers of sub-cover plates, which is not specifically limited in the embodiments of the present disclosure.

[0092] like Figure 3 As shown, the longitudinal section of the housing 200 may be, for example, U-shaped, the display panel 100 and the circuit board 400 are disposed in the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on a side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the display panel 100 with the required display signal.

[0093] The display panel 100 may be of various types and may be selected according to actual needs.

[0094] Exemplarily, the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.

[0095] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0096] In some embodiments, see Figure 5 , the display panel 100 includes a display substrate 110 and an encapsulation layer 120 for encapsulating the display substrate 110 .

[0097] The encapsulation layer 120 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the embodiments of the present disclosure.

[0098] In some embodiments, see Figure 4 The display panel 100 has a display area A, which is a region for displaying images and is configured to set a plurality of sub-pixels P.

[0099] For example, see Figure 4 The display panel 100 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A.

[0100] There are many types of the substrate 11, which can be selected according to actual needs.

[0101] For example, the substrate 11 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0102] For another example, the substrate 11 may be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0103] Among them, see Figure 4 and Figure 5 Each sub-pixel P includes a light emitting device 10 and a pixel circuit 20. The pixel circuit 20 includes a plurality of thin film transistors 30.

[0104] like Figure 5 As shown, the thin film transistor 30 includes a semiconductor channel 31 , a source 32 , a drain 33 , and a gate 34 , and both the source 32 and the drain 33 are in contact with the semiconductor channel 31 .

[0105] like Figure 5 As shown, the light emitting device 10 includes a first electrode 11, a light emitting functional layer 12 and a second electrode 13. The first electrode 11 is electrically connected to a source electrode 32 or a drain electrode 33 of a thin film transistor 30. Figure 5 In the figure, the electrical connection between the first electrode 11 and the drain electrode 33 of the thin film transistor 30 is taken as an example for illustration.

[0106] It should be noted that the above-mentioned light-emitting functional layer 12 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL) and a hole injection layer (HIL).

[0107] Currently, display devices use display panels with variable refresh rates to meet users' needs for low power consumption and high refresh rates. However, when displaying at a low frequency, the frame rate of the display panel is reduced, making the human eye more sensitive to the flicker of the display panel, causing the human eye to perceive flickering on the display screen.

[0108] Research has found that the channel of the driving transistor in the pixel circuit itself exhibits obvious hysteresis effect due to the large number of defect states, resulting in the image of the previous moment (previous frame cycle) often being retained in the image display of the next moment, causing the display screen to flicker.

[0109] It should be noted that the hysteresis effect refers to an uncertainty in the electrical characteristics of the driving transistor under a certain bias voltage, that is, the magnitude of the current of the driving transistor is not only related to the current bias voltage, but also to the bias state in the previous period.

[0110] Based on this, see Figure 6 Some embodiments of the present disclosure provide a pixel circuit 20 that includes a driving sub-circuit 21 , a compensation sub-circuit 22 , a reset sub-circuit 23 and a storage sub-circuit 24 .

[0111] In some examples, such as Figure 6 As shown, the driving subcircuit 21 is coupled to the first node N1, the second node N2 and the third node N3. The driving subcircuit 21 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and generate a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0112] For example, Figure 7 As shown, the driving subcircuit 21 includes an eighth transistor T8 (ie, the driving transistor mentioned above), a first electrode of the eighth transistor T8 is connected to the second node N2, a second electrode of the eighth transistor T8 is connected to the third node N3, and a control electrode of the eighth transistor T8 is connected to the first node N1.

[0113] In some examples, such as Figure 6 As shown, the compensation subcircuit 22 is coupled to the first scan signal terminal GATE1, the first node N1 and the third node N3. The compensation subcircuit 22 is configured to control the conduction and cutoff of the circuit between the first node N1 and the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1.

[0114] For example, see Figure 7 The compensation sub-circuit 22 includes a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series, a first end of the first sub-transistor T1-1 is connected to the first node N1, a second end of the first sub-transistor T1-1 and / or a first end of the second sub-transistor T1-2 is connected to a fourth node N4, a second end of the second sub-transistor is connected to a third node N3, and control electrodes of the first sub-transistor T1-1 and the second sub-transistor T1-2 are connected to the first scan signal terminal GATE1.

[0115] It should be noted that there may be other transistors connected in series between the first sub-transistor T1-1 and the second sub-transistor T1-2, that is, the compensation sub-circuit 22 may also include three, four or more transistors connected in series, which is not specifically limited in the embodiment of the present disclosure.

[0116] Below, some embodiments of the present disclosure are schematically described by taking the compensation sub-circuit 22 including the first sub-transistor T1-1 and the second sub-transistor T1-2 connected in series as an example, but the implementation of the present disclosure is not limited to this, and it can also be considered that the compensation sub-circuit 22 includes three, four or more transistors connected in series, as long as the same technical concept is applied.

[0117] In some examples, such as Figure 6 As shown, the reset subcircuit 23 is coupled to the first initialization signal terminal VINIT1, the reset signal terminal RESET and the first node N1. The reset subcircuit 23 is configured to transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the working voltage of the reset signal received at the reset signal terminal RESET, so as to reset the voltage of the first node N1.

[0118] For example, see Figure 7 The reset sub-circuit 23 includes a plurality of fifth transistors T5 connected in series, one end of the plurality of fifth transistors T5 is connected to the first initialization signal terminal VINIT1, the other end is connected to the first node N1, and the control electrode of each fifth transistor T5 is connected to the reset signal terminal RESET.

[0119] For example, Figure 7 As shown, the reset sub-circuit 23 includes two fifth transistors T5 connected in series, and the two fifth transistors T5 form a double-gate transistor to reduce leakage current.

[0120] Among them, see Fig.13 , Fig.14 and Fig.15 , the starting time of the working voltage of the reset signal is before the starting time of the working voltage of the first scanning signal; and the time interval between the starting time of the working voltage of the reset signal and the starting time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods. Fig.13 In the figure, the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is 8 row scanning periods as an example for illustration.

[0121] In addition, see Fig.13 , Fig.14 and Fig.15 The cut-off time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal. Moreover, the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods. Fig.13 In the figure, the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is 3 row scanning periods as an example for illustration.

[0122] In some examples, such as Figure 6 As shown, the storage sub-circuit 24 is coupled to the first voltage signal terminal VDD, the first node N1 and the second node N2. The storage sub-circuit 24 is configured to store the voltages of the first node N1 and the second node N2.

[0123] For example, Figure 7 As shown, the storage subcircuit 24 includes a first storage capacitor C1 and a second storage capacitor C2, wherein the first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, and the second plate of the first storage capacitor C1 is connected to the first node N1. The first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and the second plate of the second storage capacitor C2 is connected to the second node N2.

[0124] In this case, after a frame of display begins, the storage subcircuit 24 can store the voltage at the second node N2 after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first node N1 and the third node N3 of the driving subcircuit 21 to generate a stable and large bias voltage, thereby improving the hysteresis characteristics of the driving subcircuit 21, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of the human eye being able to perceive flickering in the display screen.

[0125] That is to say, after a frame of display starts, the second storage capacitor C2 can store the voltage at the second node N2 (i.e., the first electrode of the eighth transistor T8) after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first electrode (second node N2) and the control electrode (third node N3) of the eighth transistor T8 to generate a stable and large bias voltage, thereby improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering in the display screen that can be perceived by the human eye.

[0126] In some embodiments, Fig. 8A As shown, the pixel circuit 20 further includes a leakage prevention sub-circuit 25 .

[0127] In some examples, such as Fig. 8A and Fig. 9B As shown, the leakage prevention subcircuit 25 is coupled to the control signal terminal K, the constant voltage terminal VC and the fourth node N4. The leakage prevention subcircuit 25 is configured to transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the working voltage of the control signal received at the control signal terminal K.

[0128] The voltage of the constant voltage signal is -7V to 7V. For example, the voltage of the constant voltage signal is any one of -7V, -6V, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V. Specifically, according to experimental tests, a voltage value with a better anti-leakage effect can be obtained as the actual voltage value of the constant voltage signal, which is not specifically limited in the embodiments of the present disclosure.

[0129] For example, Fig. 9B As shown, the leakage prevention sub-circuit 25 includes a second transistor T2, a first electrode of the second transistor T2 is connected to the constant voltage terminal VC, a second electrode of the second transistor T2 is connected to the fourth node N4, and a control electrode of the second transistor T2 is connected to the control signal terminal K.

[0130] In this case, during the light-emitting stage, the anti-leakage sub-circuit 25 can respond to the operating voltage of the control signal received at the control signal terminal K, and transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, so as to reduce the voltage difference between the fourth node N4 and the first node N1, and reduce the risk of leakage of the first node N1, thereby reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive flickering in the display screen.

[0131] In some embodiments, Fig. 8A As shown, the pixel circuit 20 further includes a light emission control subcircuit 26 .

[0132] In some examples, such as Fig. 8A As shown, the light emitting control subcircuit 26 is coupled to the first voltage signal terminal VDD, the enable signal terminal EM, the second node N2, the third node N3 and the fifth node N5. The light emitting control subcircuit 26 is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal VDD and the second node N2 in response to the enable signal received at the enable signal terminal EM; and control the conduction and cutoff of the circuit between the third node N3 and the fifth node N5.

[0133] Here, the first voltage signal may be a signal of the positive electrode of a DC power supply. For example, the first voltage signal may be 5V.

[0134] It should be noted that the fifth node N5 is connected to the anode of the light emitting device 10 so that the driving current signal can be transmitted to the light emitting device 10 .

[0135] For example, Fig. 9BAs shown, the light emitting control subcircuit 26 includes a third transistor T3 and a fourth transistor T4. A first electrode of the third transistor T3 is connected to the first voltage signal terminal VDD, a second electrode of the third transistor T3 is connected to the second node N2, and a control electrode of the third transistor T3 is connected to the enable signal terminal EM. A first electrode of the fourth transistor T4 is connected to the third node N3, a second electrode of the fourth transistor T4 is connected to the fifth node N5, and a control electrode of the fourth transistor T4 is connected to the enable signal terminal EM.

[0136] On this basis, if Fig. 9B As shown, the signals received at the enable signal terminal EM and the control signal terminal K are the same. In this case, the enable signal terminal EM and the control signal terminal K can be connected to the same signal line, such as a gate line mentioned below, to simplify the circuit structure. That is, in the light-emitting stage, the anti-leakage sub-circuit 25 responds to the operating voltage of the control signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, so as to reduce the voltage difference between the fourth node N4 and the first node N1, reduce the risk of leakage of the first node N1, thereby reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering on the display screen.

[0137] In some embodiments, Fig. 8A As shown, the pixel circuit 20 further includes a data writing subcircuit 27 .

[0138] In some examples, such as Fig. 8A As shown, the data writing sub-circuit 27 is coupled to the data signal terminal DATA, the second scanning signal terminal GATE2 and the second node N2. The data writing sub-circuit 27 is configured to transmit the data signal received at the data signal terminal DATA to the second node N2 in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal GATE2; and transmit the data refresh signal received at the data signal terminal DATA to the second node N2 in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal GATE2. The data refresh signal is a data signal received by the pixel circuit 20 of other rows, for example, a data signal received by the pixel circuit 20 of the next adjacent row.

[0139] It should be noted that the first operating voltage and the second operating voltage of the second scanning signal may be the same in magnitude, but the timings of the first operating voltage and the second operating voltage are different.

[0140] For example, see Fig.13 , Fig.14 and Fig.15The cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal. Moreover, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to one row scanning period H.

[0141] It should be noted that the row scanning period H is the duration of a working voltage of the second scanning signal.

[0142] For example, Fig.13 As shown, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is 5 row scanning periods H.

[0143] For example, see Fig.13 , Fig.14 and Fig.15 The start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal. Moreover, the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period H.

[0144] For example, Fig.13 As shown, the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is 2 row scanning periods H.

[0145] In some embodiments, see Fig. 9B The compensation sub-circuit 22 includes a transistor which is a P-type transistor. Fig.13 , Fig.14 and Fig.15 , the duration of the working voltage of the first scanning signal is greater than or equal to 4 row scanning periods H. The voltage of the first row scanning period H after the first scanning signal works is greater than the voltage of the second row scanning period H after the first scanning signal works. The row scanning period H is the duration of one working voltage of the second scanning signal. In other words, the stability of the first scanning signal output in the even-numbered row scanning period H is greater than the stability of the odd-numbered row scanning period H.

[0146] In the present disclosure, the voltage of the first row scanning period H after the first scanning signal is working can be understood as the first period after the effective level of the first scanning signal starts to be input, that is, Fig.13 The first row scanning period H after the first falling edge of the first scanning signal terminal GATE1, that is, the first row scanning period H from left to right in the second reset phase P12; or, it is understood as the first row scanning period H for Fig.9A The first period after the level input in which the first sub-transistor T1-1 is turned on.

[0147] In the present disclosure, the voltage of the second row scanning period H after the first scanning signal is working can be understood as the second period after the effective level of the first scanning signal starts to be input, that is, Fig.13 The second row scanning period H after the first falling edge of the first scanning signal terminal GATE1, that is, the second row scanning period H counted from left to right in the second reset phase P12; or, it is understood as the second row scanning period H for Fig.9A The second period after the level input that turns on the first sub-transistor T1-1 in the circuit.

[0148] On this basis, the time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period H of the working voltage of the first scanning signal, where N≥2, and N is an integer.

[0149] For example, Fig.13 As shown, the duration of the working voltage of the first scanning signal is 11 row scanning periods H, and the duration of the first working voltage of the second scanning signal coincides with the sixth row scanning period H of the working voltage of the first scanning signal, that is, N=3.

[0150] In addition, see Fig.13 , Fig.14 and Fig.15 The start and end time of the second operating voltage of the second scanning signal is between the end time of the operating voltage of the first scanning signal and the start time of the operating voltage of the enable signal.

[0151] Moreover, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period H. The time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period H.

[0152] For example, Fig.13 As shown, the time interval between the start time of the second working voltage of the second scanning signal and the end time of the working voltage of the first scanning signal is 2 row scanning periods H. The time interval between the end time of the second working voltage of the second scanning signal and the start time of the working voltage of the enable signal is 1 row scanning period H.

[0153] In some embodiments, as shown, the data writing subcircuit 27 is further configured to transmit the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2.

[0154] Here, the voltage range of the data retention signal is 0V~V GMP Among them, V GMPIt refers to the black state voltage of the sub-pixel P. When the target grayscale of a sub-pixel P is 0, the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light.

[0155] Exemplarily, the voltage of the data hold signal ranges from 0V to 7V, for example, the voltage of the data hold signal is any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V. Here, the voltage value of the data hold signal can be determined based on experimental tests, and a voltage value with a lower flicker value can be used as the actual voltage value of the data hold signal, which is not specifically limited in the embodiments of the present disclosure.

[0156] It should be noted that the first operating voltage, the second operating voltage and the third operating voltage of the second scanning signal may be the same in magnitude, but the timings of the first operating voltage, the second operating voltage and the third operating voltage are different.

[0157] In some embodiments, Fig. 9B As shown, the data writing sub-circuit 27 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is connected to the data signal terminal DATA, a second electrode of the seventh transistor T7 is connected to the second node N2, and a control electrode of the seventh transistor T7 is connected to the second scan signal terminal GATE2.

[0158] In some embodiments, Fig. 8A As shown, the reset subcircuit 23 is also coupled to the second initialization signal terminal VININT2, the third scan signal terminal GATE3 and the fifth node N5. The reset subcircuit 23 is also configured to, under the control of the operating voltage of the third scan signal received at the third scan signal terminal GATE3, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light emitting device 10.

[0159] For example, Fig.9A As shown, the reset subcircuit 23 further includes a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2, a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5, and a control electrode of the sixth transistor T6 is connected to the third scan signal terminal GATE3.

[0160] In this case, the control electrode of the sixth transistor T6 that resets the anode (fifth node N5) of the light-emitting device 10 can be controlled by the third scan signal terminal GATE3, so that the anode (fifth node N5) of the light-emitting device 10 can be reset to improve the light-emitting efficiency.

[0161] In addition, the third scan signal terminal GATE3 can be connected to the same signal line as the second scan signal terminal GATE2, that is, the signals received by the third scan signal terminal GATE3 and the second scan signal terminal GATE2 can be the same, and the third scan signal terminal GATE3 can also be called the second scan signal terminal GATE2.

[0162] At this time, if Figure 8B As shown, the reset subcircuit 23 is coupled to the second initialization signal terminal VININT2, the second scan signal terminal GATE2 and the fifth node N5. The reset subcircuit 23 is configured to, under the control of the operating voltage of the third scan signal received at the second scan signal terminal GATE2, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light emitting device 10.

[0163] For example, Fig. 9B As shown, the reset subcircuit 23 further includes a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2, a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5, and a control electrode of the sixth transistor T6 is connected to the second scan signal terminal GATE2.

[0164] In this case, the control electrode of the sixth transistor T6 for resetting the anode (fifth node N5) of the light-emitting device 10 and the control electrode of the seventh transistor T7 can both be controlled by the second scanning signal terminal GATE2, so that during the data writing process, the anode (fifth node N5) of the light-emitting device 10 can be reset at the same time, simplifying the circuit structure.

[0165] The following takes the example that the third scan signal terminal GATE3 and the second scan signal terminal GATE2 are connected to the same signal line to schematically illustrate some embodiments of the present disclosure, but the implementation manner of the present disclosure is not limited thereto.

[0166] In some embodiments, Figure 4 As shown, all pixel circuits 20 are arranged in multiple rows and columns, each row includes multiple pixel circuits 20 arranged along a first direction X, and each column includes multiple pixel circuits 20 arranged along a second direction Y. The first direction X and the second direction Y are substantially perpendicular.

[0167] It should be noted that the first direction X may be, for example, a row direction in which the plurality of pixel circuits 20 are arranged, and the second direction Y may be, for example, a column direction in which the plurality of pixel circuits 20 are arranged.

[0168] In the following, some embodiments of the present disclosure are described by way of example, taking all pixel circuits 20 arranged in multiple rows and columns as an example, but the embodiments of the present disclosure are not limited thereto. In addition, a plurality of pixel circuits 20 arranged along a first direction X is referred to as a row of pixel circuits 20, and a plurality of pixel circuits 20 arranged along a second direction Y is referred to as a column of pixel circuits 20.

[0169] On this basis, the display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first power lines VDL, a plurality of first initialization signal lines VL1, a plurality of second initialization signal lines VL2, and a plurality of constant voltage signal lines VCL.

[0170] like Figure 4 As shown, each gate line GL extends substantially along the first direction X, and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, and an enable signal (control signal). Wherein, a gate line GL, for example, can be connected to any one of a first scan signal terminal GATE1, a second scan signal terminal GATE2, a reset signal terminal RESET, and an enable signal terminal EN (control signal terminal K) of a row of pixel circuits 20.

[0171] like Figure 4 As shown, the data line DL extends substantially along the second direction Y and is configured to transmit a data signal. For example, one data line DL may be connected to a data signal terminal DATA of a column of pixel circuits 20 .

[0172] like Figure 4 As shown, the first power line VDL extends substantially along the second direction Y and is configured to transmit a first power voltage signal. For example, one first power line VDL may be connected to the first voltage signal terminal VDD of a column of pixel circuits 20 .

[0173] like Figure 4 As shown, the first initialization signal line VL1 extends substantially along the first direction X and is configured to transmit a first initialization signal. One first initialization signal line VL1 may be connected to the first initialization signal terminal VINIT1 of a row of pixel circuits 20 , for example.

[0174] like Figure 4 As shown, the second initialization signal line VL2 extends substantially along the first direction X and is configured to transmit a second initialization signal. One second initialization signal line VL2 may be connected to the second initialization signal terminal VINIT2 of a row of pixel circuits 20, for example.

[0175] like Figure 4 As shown, the constant voltage signal line VCL extends substantially along the second direction Y and is configured to transmit a constant voltage signal. One constant voltage signal line VCL may be connected to the constant voltage signal terminal VC of a row of pixel circuits 20, for example.

[0176] like Figure 5 As shown, along a direction perpendicular to the substrate 11 and away from the substrate 11, the display panel 100 includes a substrate 11, a semiconductor layer ACT, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source and drain conductive layer SD1, a first planar layer PLN1, a second source and drain conductive layer SD2 and a second planar layer PLN2.

[0177] On this basis, see Figure 4 and Figure 5 , the semiconductor channel 31 of the transistor may be located, for example, in the semiconductor layer ACT, the gate line GL, the gate 34 of the transistor and the first plate of the capacitor (the first capacitor C1 and the second capacitor C2) may be located, for example, in the first gate conductive layer GT1. The second plate of the capacitor (the first capacitor C1 and the second capacitor C2), the first initialization signal line VL1 and the second initialization signal line may be located, for example, in the second gate conductive layer GT2. The source 32, the drain 33, the first power line VDL and the constant voltage signal line VCL of the transistor may be located, for example, in the first source-drain conductive layer SD1. The data line DL may be located, for example, in the second source-drain conductive layer SD2.

[0178] In some embodiments, Figure 5 As shown, the display panel 100 further includes a pixel defining layer PDL, the pixel defining layer PDL is provided with a plurality of openings, and one light emitting device 10 is located in one opening.

[0179] In some embodiments, Figure 5 As shown, the display panel 100 further includes a spacer PS, which can be disposed between the pixel defining layer PDL and the first electrode 11 of the light emitting device 10 to support the mask during the process so that the gap between the mask and the pixel defining layer PDL is uniform.

[0180] In some embodiments, see Figure 4 The display panel 100 further has a peripheral area B, which is disposed on at least one side of the display area A. Figure 4 In the figure, the peripheral area B is arranged around the display area A for illustration.

[0181] like Figure 4 As shown, the peripheral area B includes a first border area B1, a second border area B2, a third border area B3 and a fourth border area B4. Along the first direction X, the first border area B1 and the second border area B2 are located on two opposite sides of the display area A. Along the second direction Y, the third border area B3 and the fourth border area B4 are located on the other opposite sides of the display area A.

[0182] The peripheral area B is a region where no image is displayed and is configured to set up a gate driving circuit 130 and a source driving circuit 140 and the like.

[0183] In some embodiments, see Fig. 9B and 10 The gate driving circuit 130 includes a first gate driving circuit 131, the first gate driving circuit 131 includes a plurality of cascaded first shift registers RS1, each first shift register RS1 includes a first signal output end, and the first signal output end of each first shift register RS1 is connected to the first scanning signal end GATE1 and / or the reset signal end RESET of at least one row of pixel circuits 20.

[0184] For example, Fig. 9B and 10 As shown, a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. Fig.10 2480 rows of pixel circuits 20 are taken as an example for illustration.

[0185] The first gate driving circuit 131 includes M+Q cascaded first shift registers RS1 , from the first stage first shift register RS1 to the last stage first shift register RS1 , the M+Q first shift registers RS1 are respectively the 1st to the M+Qth first shift registers RS1 . Fig.10 In the figure, Q equals 8 as an example.

[0186] On this basis, the first scanning signal terminal GATE1 of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P+Q-th first shift register RS1. The reset signal terminal RESET of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P-th first shift register RS1. Moreover, P≤M, Q>0, and P and Q are both integers.

[0187] In this case, the first gate driving circuit 131 can provide the first scanning signal and the reset signal to the first scanning signal terminal GATE1 and the reset signal terminal RESET of all pixel circuits 20, respectively. That is, the first scanning signal terminal GATE1 and the reset signal terminal RESET of a pixel circuit 20 can share a gate driving circuit 130, which is beneficial to the display device 1000 (see Figure 1 )’s narrow bezel design.

[0188] In some examples, such as Fig.10As shown, along the first direction X, the first gate driving circuit 131 is arranged in the display area A (see Figure 4 ) side, and from the display area A (see Figure 4 ) drives each row of pixel circuits 20 row by row in sequence, that is, single-sided driving.

[0189] In other examples, such as Fig.11 As shown, along the first direction X, two first gate driving circuits 131 are arranged in the display area A (see Figure 4 ) on opposite sides, and through the two first gate driving circuits 131, simultaneously from the display area A (see Figure 4 ) drives each row of pixel circuits 20 row by row in sequence on opposite sides, that is, double-sided driving.

[0190] In other embodiments, see Fig.12 The gate driving circuit 130 includes a second gate driving circuit 132 and a third gate driving circuit 133 .

[0191] Among them, Fig. 9B and Fig.12 As shown, the second gate driving circuit 132 includes a plurality of cascaded second shift registers RS2 , each of which includes a second signal output terminal, and the second signal output terminal of each second shift register RS2 is connected to the first scanning signal terminal GATE1 of at least one row of pixel circuits 20 .

[0192] For example, Fig.12 As shown, a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. Fig.12 2480 rows of pixel circuits 20 are taken as an example for illustration.

[0193] The second gate driving circuit 132 includes M cascaded second shift registers RS2, from the first second shift register RS2 to the last second shift register RS2, the M second shift registers RS2 are respectively the first to the Mth second shift registers RS2. Each second shift register RS2 includes a second signal output terminal.

[0194] On this basis, the first scanning signal terminal GATE1 of the pixel circuit 20 in the P-th row is connected to the second signal output terminal of the P-th second shift register RS2, P≤M, and P is an integer.

[0195] In addition, if Fig. 9B and Fig.12 As shown, the third gate driving circuit 133 includes a plurality of cascaded third shift registers RS3 , each of which includes a third signal output terminal, and the third signal output terminal of each third shift register RS3 is connected to the reset signal terminal RESET of at least one row of pixel circuits 20 .

[0196] For example, Fig.12 As shown, a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. Fig.12 2480 rows of pixel circuits 20 are taken as an example for illustration.

[0197] The third gate driving circuit 133 includes M cascaded third shift registers RS3, from the first stage third shift register RS3 to the last stage third shift register RS3, the M third shift registers RS3 are respectively the first to the Mth third shift registers RS3. Each third shift register RS3 includes a third signal output terminal.

[0198] On this basis, the reset signal terminal RESET of the pixel circuit in the Pth row is connected to the third signal output terminal of the Pth third shift register RS3, P≤M, and P is an integer.

[0199] In this case, the second gate driving circuit 132 can provide the first scanning signal to the first scanning signal terminal GATE1 of all the pixel circuits 20, and the third gate driving circuit 133 can provide the reset signal to the reset signal terminal RESET of all the pixel circuits 20. In this case, the ratio of the duration of the first scanning signal received by the first scanning signal terminal GATE1 of the pixel circuit 20 and the duration of the reset signal received by the reset signal terminal RESET can be adjusted arbitrarily, which is conducive to improving the afterimage performance, reducing flicker, and thus improving the display quality.

[0200] In some examples, such as Fig.12 As shown, along the first direction X, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged in the display area A (see Figure 4 ), that is, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged on the first frame area B1 (see Figure 4 ) and the second border area B2 (see Figure 4 ), and from display area A (see Figure 4) drives each row of pixel circuits 20 row by row, which is beneficial to reducing the size of the display device 1000 (see Figure 1 ) borders to increase the screen-to-body ratio.

[0201] In some embodiments, see Figure 10 to Figure 12 The gate driving circuit 130 also includes a fourth gate driving circuit 134 .

[0202] Among them, Fig. 9B and Fig.10 As shown, the fourth gate driving circuit 134 includes a plurality of cascaded fourth shift registers RS4 , each of which includes a fourth signal output terminal, and the fourth signal output terminal of each fourth shift register RS4 is connected to the enable signal terminal EM of at least one row of pixel circuits 20 .

[0203] For example, Fig.10 As shown, a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. Fig.10 2480 rows of pixel circuits 20 are taken as an example for illustration.

[0204] The fourth gate driving circuit 134 includes M cascaded fourth shift registers RS4, from the first stage fourth shift register RS4 to the last stage fourth shift register RS4, the M fourth shift registers RS4 are respectively the first to the Mth fourth shift registers RS4. Each of the fourth shift registers RS4 includes a fourth signal output terminal.

[0205] On this basis, the enable signal terminal EM of the P-th row pixel circuit 20 is connected to the fourth signal output terminal of the P-th fourth shift register RS4 of the fourth gate driving circuit 134, P≤M, and P is an integer.

[0206] like Fig.10 As shown, in the case where the display panel 100 includes a first gate driving circuit 131, the first gate driving circuit 131 and the fourth gate driving circuit 134 are respectively arranged in the first frame area B1 (see Figure 4 ) and the second border area B2 (see Figure 4 ), which is beneficial to the display device 1000 (see Figure 1 )’s narrow bezel design.

[0207] like Fig.11As shown, when the display panel 100 includes two first gate driving circuits 131, and the two first gate driving circuits 131 are respectively arranged in the first border area B1 and the second border area B2, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 can be respectively arranged in the first border area B1 and the second border area B2 to form a cross drive, so as to make full use of the areas of the first border area B1 and the second border area B2 and improve the uniformity of the picture display.

[0208] like Fig.12 As shown, in the case where the display panel 100 includes a second gate driving circuit 132 and a third gate driving circuit 133, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 are respectively arranged in the first border area B1 and the second border area B2 to form a cross drive, so as to make full use of the areas of the first border area B1 and the second border area B2 and improve the uniformity of the picture display.

[0209] In some embodiments, see Figure 10 to Figure 12 The gate driving circuit 130 also includes a fifth gate driving circuit 135 .

[0210] Among them, Fig. 9B and Fig.12 As shown, the fifth gate driving circuit 135 includes a plurality of cascaded fifth shift registers RS5 , each of which includes a fifth signal output terminal, and the fifth signal output terminal of each fifth shift register RS5 is connected to the second scanning signal terminal GATE2 of at least one row of pixel circuits 20 .

[0211] For example, Fig.12 As shown, a plurality of pixel circuits 20 are arranged in M ​​rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are the 1st to Mth rows of pixel circuits 20, respectively. Fig.12 2480 rows of pixel circuits 20 are taken as an example for illustration.

[0212] The fifth gate driving circuit 135 includes M cascaded fifth shift registers RS5, from the first stage fifth shift register RS5 to the last stage fifth shift register RS5, the M fifth shift registers RS5 are respectively the first to the Mth fifth shift registers RS5. Each fifth shift register RS5 includes a fifth signal output terminal.

[0213] On this basis, the enable signal terminal EM of the pixel circuit 20 in the Pth row is connected to the fourth signal output terminal of the Pth fifth shift register RS5 of the fourth gate driving circuit 134, P≤M, and P is an integer.

[0214] In some examples, such as Figure 10 to Figure 12 As shown, the display panel 100 includes two fifth gate driving circuits 135, and the two fifth gate driving circuits 135 are respectively arranged in the first frame area B1 (see Figure 4 ) and the second border area B2 (see Figure 4 ). That is, the second scanning signal terminal GATE2 of the pixel circuit 20 of the Pth row is connected to the fifth signal output terminal of the Pth fifth shift register RS5 of the two fifth gate driving circuits 135 to form a double-sided drive, P≤M, and P is an integer. In this way, the influence of the voltage drop on the second scanning signal can be reduced, thereby improving the brightness uniformity of the display screen.

[0215] Some embodiments of the present disclosure further provide a driving method of a pixel circuit 20 , which is used to drive the pixel circuit 20 as in any of the above embodiments.

[0216] Among them, Fig.13 As shown, a display frame F includes a refresh frame F1, and the refresh frame F1 includes a first reset phase P11 and a second reset phase P12.

[0217] In the first reset phase P11, the reset subcircuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the working voltage of the reset signal of the reset signal terminal RESET, so as to reset the first node N1. In addition, the storage subcircuit 24 stores the voltage of the second node N2 after the previous frame ends, so that the second node N2 can form a relatively stable potential (the voltage of the second voltage signal).

[0218] That is to say, Fig. 9B As shown, the fifth transistor T5 is turned on under the control of the reset signal received at the reset signal terminal RESET, and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. Also, the second storage capacitor C2 stores the voltage of the second node N2 after the previous frame ends.

[0219] At this time, in the first reset stage P11, a large bias voltage can be formed between the second node N2 and the first node N1, so that a stable and large bias voltage is generated between the source terminal and the control terminal of the eighth transistor T8, thereby improving the hysteresis characteristic of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering in the display screen.

[0220] It should be noted that the difference between the start time of the first reset stage P11 and the start time of a frame F in which the first reset stage P11 is located is greater than or equal to two row scanning periods H, so as to avoid the rising and falling edges of various signals of the first reset stage P11 being interlaced at the end of the previous frame F, thereby affecting the first reset stage P11.

[0221] In the second reset phase P12, the reset sub-circuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the operating voltage of the reset signal at the reset signal terminal RESET. The compensation sub-circuit 22 transmits the voltage of the first node N1 to the third node N3 in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1. And, the driving sub-circuit 21 transmits the voltage of the third node N3 to the second node N2 under the control of the voltage of the first node N1, so as to reset the third node N3 and the second node N2 in sequence.

[0222] That is to say, Fig. 9B As shown, the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the first scan signal received at the first scan signal terminal GATE1, and the voltage of the first node N1 is transmitted to the third node N3. Moreover, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and the voltage of the third node N3 is transmitted to the second node N2.

[0223] At this time, in the second reset stage P12, the second node N2 and the third node N3 may be reset to reduce the influence of the residual voltage of the previous frame on the data writing of this frame, thereby improving the brightness uniformity of the display screen.

[0224] In some embodiments, Fig.13 As shown, the refresh frame F1 further includes a first data writing phase P21 and a second data writing phase P22.

[0225] In the first data writing phase P21, the data writing sub-circuit 27 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal GATE2, and writes the data signal into the storage sub-circuit 24. The driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3 under the control of the voltage of the first node N1. The compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the operating voltage of the first scanning signal received at the first scanning signal terminal GATE1.

[0226] That is to say, Fig. 9BAs shown, the seventh transistor T7 is turned on under the control of the first working voltage of the second scan signal received at the second scan signal terminal GATE2, and transmits the data signal received at the data signal terminal DATA to the second node N2. The second storage capacitor C2 stores the voltage of the data signal written to the second node N2.

[0227] Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and transmits the voltage of the third node N3 to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, and transmit the voltage of the third node N3 to the first node N1.

[0228] At this time, in the first data writing phase P21, the data signal may be written into the first node N1 and the second storage capacitor C2.

[0229] In the second data writing phase P22, the storage sub-circuit 24 discharges and transmits the stored data signal to the second node N2. The driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3 under the control of the voltage of the first node N1. The compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the working voltage of the first scan signal received at the first scan signal terminal GATE1.

[0230] That is to say, Fig. 9B As shown, the second storage capacitor C2 is discharged, and the data signal written in the first data writing phase P21 is transmitted to the second node N2. The eighth transistor T8 is turned on under the control of the voltage of the first node N1, and the voltage of the third node N3 is transmitted to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the working voltage of the first scan signal received at the first scan signal terminal GATE1, and the voltage of the third node N3 is transmitted to the first node N1.

[0231] At this time, in the second data writing phase P22, the second storage capacitor C2 can be continuously discharged to continuously write the data signal to the first node N1, thereby increasing the data writing time, which is beneficial to improving the brightness uniformity of the display screen and enhancing the display effect.

[0232] In some embodiments, Fig. 9B and Fig.13 As shown, the compensation sub-circuit 22 includes transistors that are P-type transistors. Also, the second reset phase P12 includes at least three row scanning periods H.

[0233] In the second reset phase P12, the voltage of the first row scanning period H after the first scanning signal is working is greater than the voltage of the second row scanning period H after the first scanning signal is working. That is, the stability of the first scanning signal H output in the even row scanning period H is greater than the stability of the odd row scanning period H.

[0234] Exemplarily, the first scanning signal of the first signal output terminal of the first shift register RS1 is output by the clock signal line, and in the first row scanning period H of the second reset phase P12, the first signal output terminal outputs a high level signal of the clock signal line. In the second row scanning period H of the second reset phase P12, the first signal output terminal outputs a low level signal of the clock signal line.

[0235] Moreover, in other odd-numbered row scanning periods H in the second reset stage P12, the first signal output terminal is in a floating state. In other even-numbered row scanning periods H in the second reset stage P12, the first signal output terminal is a low-level signal of the output clock signal line. At this time, the stability of the first scanning signal output in the even-numbered row scanning period H is greater than the stability in the odd-numbered row scanning period H.

[0236] On this basis, the first data writing phase P21 is located after the second resetting phase P12 and coincides with the 2Nth row scanning period H after the start time of the second resetting phase P12, N≥2, and N is an integer.

[0237] In this case, the first data writing phase P21 is performed in the even-numbered row scanning period H when the stability of the first scanning signal is relatively high, which can improve the accuracy of data signal writing, thereby improving the brightness uniformity of the display screen. In particular, when the display panel 100 includes the first gate driving circuit 131, the risk of the last few rows of sub-pixels P being illuminated compared to other sub-pixels P can be reduced, thereby improving the brightness uniformity of the display screen.

[0238] For example, Fig.13 As shown, the second reset phase P12 includes three row scanning periods H. At this time, the sixth row scanning period H after the start time of the first data writing phase P21 and the second reset phase P12 coincides, that is, the sixth row scanning period H when the stability of the first scanning signal is relatively high is performed.

[0239] Furthermore, the falling edge of the second scanning signal and the rising edge of the reset signal can be staggered by two row scanning periods H, so as to avoid the influence of the second reset stage P12 on data writing, and the brightness uniformity of the display screen is higher.

[0240] In some embodiments, Fig.13 As shown, the refresh frame F also includes a first light emitting phase P3.

[0241] In the first light-emitting stage P3, the light-emitting control subcircuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The driving subcircuit 21 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0242] Furthermore, the light emitting control subcircuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The leakage prevention subcircuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0243] That is to say, Fig. 9B As shown, the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0244] Furthermore, the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the driving current signal to the light emitting device 10 to drive the light emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 to reduce the leakage current of the first node N1, thereby improving the brightness uniformity of the display screen.

[0245] On this basis, if Fig.13 As shown, the refresh frame F may further include a third reset phase P13, and the third reset phase P13 is located between the second data writing phase P22 and the first light emitting phase P3.

[0246] In the third reset phase P13 , the data writing sub-circuit 27 transmits the data refresh signal received at the data signal terminal DATA to the second node N2 in response to the second operating voltage of the second scan signal received at the second scan signal terminal GATE2 .

[0247] That is to say, Fig. 9B As shown, the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and the data refresh signal received at the data signal terminal DATA is transmitted to the second node N2, so that the data signal received by the pixel circuit 20 of other rows can be reused, and the second node N2 and the fourth node N4 are reset again to improve the brightness uniformity of the display screen without changing the circuit structure, and the structure is simple.

[0248] For some examples, see Fig.13 , Fig.14 and Fig.15 The difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is greater than or equal to one row scanning period H, so as to reduce the risk of the rising edge and the falling edge of each signal in the third reset phase P13 and the second data writing phase P2 being interlaced, thereby affecting data writing or resetting.

[0249] For example, Fig.13 As shown, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is 2 row scanning periods H, so as to avoid the rising edge and falling edge of each signal in the third reset phase P13 and the second data writing phase P2 from interlacing, which may affect data writing or resetting.

[0250] For some examples, see Fig.13 , Fig.14 and Fig.15 The difference between the end time of the third reset stage P13 and the start time of the first light-emitting stage P3 is greater than or equal to a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the first light-emitting stage P3 from interlacing, which may affect data writing or light emission.

[0251] For example, Fig.13 As shown, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is 1 row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset phase P13 and the second data writing phase P2 from interlacing, which may affect data writing or resetting.

[0252] In some embodiments, see Fig. 9B and Fig.13 The pixel circuit 20 has a first refresh frequency and a second refresh frequency, and the second refresh frequency is less than the first refresh frequency. At the first refresh frequency, a display frame F includes a refresh frame F1. At the second refresh frequency, a display frame F includes a refresh frame F1 and at least one hold frame F2.

[0253] At this time, the display panel 100 can display high and low frequency conversion at 30 Hz, 40 Hz, 60 Hz and 120 Hz, or high and low frequency conversion at 40 Hz, 55 Hz, 82 Hz and 165 Hz, for example, but the embodiments of the present disclosure are not limited thereto.

[0254] Among them, Fig.13 As shown, the holding frame F2 includes a black insertion phase P4, a fourth resetting phase P5 and a second light emitting phase P6.

[0255] In the black insertion phase P4 , the light emitting control subcircuit 26 is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal EM.

[0256] That is to say, Fig. 9B As shown, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal received at the enable signal terminal EM, thereby controlling the circuit for transmitting the driving current signal to be turned off.

[0257] At this time, after the first light-emitting stage P3 of the refresh frame F1, a black screen can be inserted to provide a rest time for the light-emitting device 10, thereby avoiding abnormal light emission of the light-emitting device 10 caused by long-term bias, improving the image display effect and extending the service life of the light-emitting device 10.

[0258] In the fourth reset phase P5 , the data writing sub-circuit 27 transmits the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2 .

[0259] It should be noted that the voltage range of the data retention signal is 0V~V GMP Among them, V GMP Refers to the black state voltage of the sub-pixel P. The black state voltage means that when the target grayscale of a sub-pixel P is 0, the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light. Exemplarily, the voltage range of the data holding signal is 0V to 7V, such as the voltage of the data holding signal is any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V. Here, the voltage value of the data holding signal can be specifically based on experimental tests, and the voltage value with a lower flicker value can be used as the actual voltage value of the data holding signal, which is not specifically limited in the embodiments of the present disclosure.

[0260] That is to say, Fig. 9B As shown, the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and transmits the data holding signal received at the data signal terminal DATA to the second node N2 to reset the second node N2.

[0261] In the second light-emitting stage P6, the light-emitting control subcircuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The driving subcircuit 21 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0262] Furthermore, the light emitting control subcircuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM. The leakage prevention subcircuit 22 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0263] That is to say, Fig. 9B As shown, the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.

[0264] Furthermore, the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the driving current signal to the light emitting device 10 to drive the light emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 to reduce the leakage current of the first node N1, thereby improving the brightness uniformity of the display screen.

[0265] For some examples, see Fig.13 , Fig.14 and Fig.15 The difference between the end time of the fourth reset stage P5 and the start time of the second light-emitting stage P6 is greater than or equal to a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the fourth reset stage P5 and the second light-emitting stage P6 from interlacing, which affects the reset or light-emitting.

[0266] For example, Fig.13 As shown, the difference between the end time of the fourth reset stage P5 and the start time of the second light-emitting stage P6 is a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the fourth reset stage P5 and the second light-emitting stage P6 from interlacing, thereby affecting the reset or light-emitting.

[0267] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A pixel circuit, characterized in that: include: A driving subcircuit coupled to the first node, the second node and the third node; the driving subcircuit is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node; a compensation subcircuit coupled to the first scan signal terminal, the first node and the third node; the compensation subcircuit is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to the first scan signal received at the first scan signal terminal; a reset subcircuit coupled to the first initialization signal terminal, the reset signal terminal and the first node; the reset subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal received at the reset signal terminal; The storage sub-circuit is coupled to the first voltage signal terminal, the first node and the second node; the storage sub-circuit is configured to store the voltages of the first node and the second node.

2. The pixel circuit according to claim 1, characterized in that: The storage sub-circuit comprises: a first storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the first node; A second storage capacitor, wherein a first plate of the second storage capacitor is connected to the first voltage signal terminal, and a second plate of the second storage capacitor is connected to the second node.

3. The pixel circuit according to claim 1, characterized in that: The compensation subcircuit comprises: a first sub-transistor and a second sub-transistor connected in series, wherein a first end of the first sub-transistor is connected to the first node, a second end of the first sub-transistor and / or a first end of the second sub-transistor is connected to a fourth node, a second end of the second sub-transistor is connected to the third node, and control electrodes of the first sub-transistor and the second sub-transistor are connected to the first scan signal terminal; The pixel circuit further includes: An anti-leakage subcircuit is coupled to the control signal terminal, the constant voltage terminal and the fourth node; the anti-leakage subcircuit is configured to transmit the constant voltage signal received at the constant voltage terminal to the fourth node in response to the working voltage of the control signal received at the control signal terminal.

4. The pixel circuit according to claim 3, characterized in that: Also includes: A light emitting control subcircuit, coupled to the first voltage signal terminal, the enable signal terminal, the second node, the third node and the fifth node; The fifth node is connected to the anode of the light emitting device; The light-emitting control subcircuit is configured to, in response to an enable signal received at the enable signal terminal, control the conduction and cutoff of the circuit between the first voltage signal terminal and the second node; and control the conduction and cutoff of the circuit between the third node and the fifth node; wherein the signals received at the enable signal terminal and the control signal terminal are the same.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that: Also includes: a data writing subcircuit coupled to the data signal terminal, the second scanning signal terminal and the second node; the data writing subcircuit is configured to transmit the data signal received at the data signal terminal to the second node in response to a first operating voltage of the second scanning signal received at the second scanning signal terminal; And, in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal, the data refresh signal received at the data signal terminal is transmitted to the second node; the data refresh signal is a data signal received by other row pixel circuits.

6. The pixel circuit according to claim 5, characterized in that: The cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal; Moreover, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to a row scanning period; the row scanning period is the duration of a working voltage of the second scanning signal.

7. The pixel circuit according to claim 5, characterized in that: The start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal; Moreover, the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period; the row scanning period is the duration of one working voltage of the second scanning signal.

8. The pixel circuit according to claim 5, characterized in that: The compensation subcircuit includes a transistor which is a P-type transistor; The duration of the working voltage of the first scanning signal is greater than or equal to 4 row scanning periods; the voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works; the row scanning period is the duration of one working voltage of the second scanning signal; The time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period of the working voltage of the first scanning signal, where N≥2 and N is an integer.

9. The pixel circuit according to claim 5, characterized in that: The start and end time of the second working voltage of the second scanning signal is between the end time of the working voltage of the first scanning signal and the start time of the working voltage of the enable signal; Moreover, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period; the time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period; the row scanning period is the duration of an operating voltage of the second scanning signal.

10. The pixel circuit according to claim 5, characterized in that: The data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.

11. The pixel circuit according to claim 5, characterized in that: The reset sub-circuit is also coupled to the second initialization signal terminal, the third scan signal terminal and the fifth node; the reset sub-circuit is also configured to transmit the second initialization signal received at the second initialization signal terminal to the fifth node under the control of the working voltage of the third scan signal received at the third scan signal terminal.

12. The pixel circuit according to claim 1, characterized in that: The starting time of the working voltage of the reset signal is before the starting time of the working voltage of the first scanning signal; and the time interval between the starting time of the working voltage of the reset signal and the starting time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods; and / or; The cut-off time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal; and the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods.

13. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 12, wherein a display frame includes a refresh frame, and the refresh frame includes a first reset phase and a second reset phase; In the first reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal at the reset signal terminal; and the storage subcircuit stores the voltage of the second node after the previous frame ends; In the second reset phase, the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the working voltage of the reset signal at the reset signal terminal; The compensation subcircuit transmits the voltage of the first node to the third node in response to the working voltage of the first scan signal received at the first scan signal terminal; And, the driving sub-circuit transmits the voltage of the third node to the second node under the control of the voltage of the first node.

14. The driving method according to claim 13, characterized in that: The pixel circuit further includes a data writing subcircuit, and the refresh frame further includes a first data writing phase and a second data writing phase; In the first data writing phase, the data writing subcircuit transmits the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal, and writes the data signal into the storage subcircuit; The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node; The compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal; In the second data writing phase, the storage sub-circuit discharges and transmits the stored data signal to the second node; The driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node; the compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal.

15. The driving method according to claim 14, characterized in that: The transistors included in the compensation subcircuit are P-type transistors; the second reset phase includes at least 3 row scanning periods; In the second reset stage, the voltage in the first row scanning period after the first scanning signal works is greater than the voltage in the second row scanning period after the first scanning signal works; The first data writing phase is located after the second resetting phase and coincides with the 2Nth row scanning period after the start time of the second resetting phase, where N≥2 and N is an integer.

16. The driving method according to claim 13, characterized in that: The pixel circuit includes a data writing subcircuit, the refresh frame also includes a third reset phase and a first light emitting phase, and the third reset phase is located between the second data writing phase and the first light emitting phase; In the third reset phase, the data writing sub-circuit transmits the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scan signal received at the second scan signal terminal.

17. The driving method according to claim 16, characterized in that: The difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scanning period; and / or the difference between the end time of the third reset phase and the start time of the first light-emitting phase is greater than or equal to one row scanning period.

18. The driving method according to any one of claims 13 to 17, characterized in that: The pixel circuit includes a data writing subcircuit, a leakage prevention subcircuit and a light emitting control subcircuit; the pixel circuit has a first refresh frequency and a second refresh frequency, the second refresh frequency is less than the first refresh frequency; at the first refresh frequency, a display frame includes a refresh frame; at the second refresh frequency, a display frame includes a refresh frame and at least one holding frame; the holding frame includes a black insertion stage, a fourth reset stage and a second light emitting stage; In the black insertion stage, the light emitting control subcircuit is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal; In the fourth reset phase, the data writing sub-circuit transmits the data holding signal received at the data signal terminal to the second node in response to the third operating voltage of the second scan signal received at the second scan signal terminal; In the second light-emitting stage, the light-emitting control subcircuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the operating voltage of the enable signal received at the enable signal terminal; The driving subcircuit generates a driving current signal according to the voltage of the first node and the voltage of the second node; Moreover, the light-emitting control subcircuit transmits the driving current signal to the light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; the leakage prevention subcircuit transmits the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.

19. The driving method according to claim 18, characterized in that: The difference between the end time of the fourth resetting stage and the start time of the second light emitting stage is greater than or equal to one row scanning period.

20. A display panel, characterized in that: include: A plurality of pixel circuits as claimed in any one of claims 1 to 12, wherein the plurality of pixel circuits are arranged in M ​​rows and N columns, each row includes N pixel circuits arranged along a first direction, each column includes M pixel circuits arranged along a second direction, M>1, N>1, and M and N are both integers.

21. The display panel according to claim 20, characterized in that: Along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The first gate driving circuit comprises M+Q cascaded first shift registers, from the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers; each of the first shift registers comprises a first signal output terminal; Among them, the first scan signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P+Q-th first shift register; the reset signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P-th first shift register; P≤M, Q>0, and P and Q are both integers.

22. The display panel according to claim 20, characterized in that: Along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits; The display panel further includes: The second gate driving circuit comprises M cascaded second shift registers, from the first stage second shift register to the last stage second shift register, the M second shift registers are respectively the first to the Mth second shift registers; each of the second shift registers comprises a second signal output terminal; wherein the first scanning signal terminal of the pixel circuit of the Pth row is connected to the second signal output terminal of the Pth second shift register, P≤M, and P is an integer; The third gate driving circuit includes M cascaded third shift registers, from the first-stage third shift register to the last-stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers; each of the third shift registers includes a third signal output terminal; wherein the reset signal terminal of the P-th row pixel circuit is connected to the third signal output terminal of the P-th third shift register, P≤M, and P is an integer.

23. A display device, characterized in that: include: The display panel according to any one of claims 20 to 22.

Images