Dual-port storage and calculation integrated unit circuit and dual-port storage and calculation integrated array circuit

Abstract

The embodiment of the invention discloses a dual-port storage and calculation integrated unit circuit, a dual-port storage and calculation integrated array circuit, a chip and electronic equipment, and the dual-port storage and calculation integrated unit circuit comprises two storage units, a write selection unit, a calculation selection unit and a calculation unit. A write selection unit selects an input data storage unit from the two storage units and stores the weight data into the input data storage unit; the calculation selection unit generates to-be-calculated data according to the initial to-be-calculated data and generates a calculation control signal according to the calculation selection signal; and the calculation unit determines the calculation data storage unit according to the calculation control signal, and calculates the weight data in the calculation data storage unit and the to-be-calculated data. According to the embodiment of the invention, when the weight data is written into some storage units, the other storage units are used for calculation, so that the calculation efficiency is greatly improved. And the calculation unit can realize the functions of selecting the storage unit and calculating, so that the area, power consumption and cost of the circuit are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a dual-port storage-computation-in-one unit circuit, a dual-port storage-computation-in-one array circuit, a chip and an electronic device. Background Art

[0002] Computing-in-Memory (CIM) refers to the technology of combining computing with storage and directly embedding algorithms inside the memory. Simply put, it is to operate the data input into the neural network with the weight parameters pre-stored in the memory unit to realize the weighted accumulation of the input data, which is the convolution operation. The convolution operation is the core component unit of the deep learning algorithm and accounts for more than 90% of the operations in most current artificial intelligence (AI) chips. This means that through the new architecture of computing-in-memory, 90% or even more of the operations can be completed and output directly by the memory.

[0003] The integration of storage and computing solves the long-standing problems of "storage wall" and "power consumption wall", completely eliminates memory access delays, and greatly reduces data transfer power consumption, resulting in ultra-high computing power and energy efficiency. It is an architecture that is more suitable for AI computing than the von Neumann architecture.

[0004] The common storage-computing-in-memory is generally a single-port computing-computing-in-memory (SP-CIM), that is, one port is provided to access the memory. This architecture provides a clock and a set of address signal lines. When writing is enabled and calculation is disabled, CIM enters write mode, and controls the order of writing weight data and determines the address of writing weight data through the clock and the above set of address signal lines, so as to perform regular write operations; when calculation is enabled and writing is disabled, CIM enters calculation mode, and controls the order of calculation and determines the address of weight data involved in the calculation through the clock and the above set of address signal lines, and controls the order of data input into the neural network through the clock, so that the data input into the neural network is calculated with the weight data pre-stored in the CIM and the result is output.

[0005] In the calculation of neural networks, data processing is mainly performed in the form of a matrix rather than a single row or column. Each write operation can only write one row of weight data, which means that before the calculation, at least Y write operations are required to ensure that the storage cell array in the CIM is filled with weight data, where Y is the total number of rows in the storage cell array.

[0006] However, SP-CIM has only one port and cannot support simultaneous writing and computing operations, so it is impossible for SP-CIM to maintain peak computing power for a long time. In addition, since it takes a long time to write a large amount of data to SP-CIM, the long writing time will interrupt the computing process, thus affecting the final computing efficiency. Summary of the invention

[0007] An embodiment of the present disclosure provides a dual-port integrated storage and computing unit circuit, which includes: two storage units, a write selection unit, a calculation selection unit and a calculation unit; the write selection unit is used to select an input data storage unit for storing currently input weight data from the two storage units according to an input write selection signal, and store the weight data in the input data storage unit; the calculation selection unit is used to receive input initial data to be calculated and a calculation selection signal; according to the calculation selection signal, determine the output terminal of the data to be calculated and the control signal output terminal from the two output terminals of the calculation selection unit; generate the data to be calculated according to the initial data to be calculated, and output the data to be calculated from the output terminal of the data to be calculated to the calculation unit; generate a calculation control signal according to the calculation selection signal, and output the calculation control signal from the control signal output terminal to the calculation unit; the calculation unit is used to determine the calculation data storage unit from the two storage units according to the calculation control signal, and calculate the weight data and the data to be calculated stored in the calculation data storage unit to obtain the calculation result and output the calculation result.

[0008] In some embodiments, the first output end of the two output ends of the calculation selection unit corresponds to the first storage unit of the two storage units, and is used to output the data to be calculated that is calculated with the weight data in the first storage unit. The second output end of the two output ends of the calculation selection unit corresponds to the second storage unit of the two storage units, and is used to output the data to be calculated that is calculated with the weight data in the second storage unit; the calculation selection unit is further used to: when the calculation selection signal is the first signal, use the first output end as the output end of the data to be calculated, and output the data to be calculated to the calculation unit; use the second output end as the control signal output end, generate a calculation control signal and send the calculation control signal The signal is output to the calculation unit; when the calculation selection signal is the second signal, the second output end is used as the output end of the data to be calculated, and the data to be calculated is output to the calculation unit; the first output end is used as the control signal output end, a calculation control signal is generated and the calculation control signal is output to the calculation unit; the calculation unit is further used for: when receiving the calculation control signal output from the second output end, calculating the weight data and the data to be calculated stored in the first storage unit, obtaining the calculation result and outputting the calculation result; when receiving the calculation control signal output from the first output end, calculating the weight data and the data to be calculated stored in the second storage unit, obtaining the calculation result and outputting the calculation result.

[0009] In some embodiments, the calculation unit includes a first multiplier and a second multiplier, the first multiplier corresponds to the first storage unit and the first output end, and the second multiplier corresponds to the second storage unit and the second output end; the second multiplier is used to prohibit the calculation of the weight data in the second storage unit when receiving the calculation control signal output by the second output end; the first multiplier is used to calculate the weight data stored in the first storage unit and the data to be calculated when receiving the data to be calculated output by the first output end, obtain the multiplication result and output the multiplication result; the first multiplier is used to prohibit the calculation of the weight data in the first storage unit when receiving the calculation control signal output by the first output end; the second multiplier is used to calculate the weight data stored in the second storage unit and the data to be calculated when receiving the data to be calculated output by the second output end, obtain the multiplication result and output the multiplication result.

[0010] In some embodiments, the first multiplier includes a first NOR gate, and the second multiplier includes a second NOR gate; the calculation selection unit includes an inverter and an output end selector; the inverter is used to invert the initial data to be calculated to obtain the data to be calculated; the output end selector is used to output the data to be calculated from the first output end to the first NOR gate when the calculation selection signal is the first signal; and, when the calculation selection signal is the second signal, output the data to be calculated from the second output end to the second NOR gate; the first NOR gate is used to receive the first inverted weight data output by the first storage unit, and perform an NOR calculation on the data to be calculated and the first inverted weight data to obtain the multiplication calculation result of the weight data in the first storage unit and the initial data to be calculated, wherein the first inverted weight data is the inverted data of the weight data in the first storage unit; the second NOR gate is used to receive the second inverted weight data output by the second storage unit, and perform an NOR calculation on the data to be calculated and the second inverted weight data to obtain the multiplication calculation result of the weight data in the second storage unit and the initial data to be calculated, wherein the second inverted weight data is the inverted data of the weight data in the second storage unit.

[0011] In some embodiments, the calculation selection unit is further used to: in response to receiving a read data mode selection signal, generate a corresponding read control signal according to the calculation selection signal, and output the read control signal through two output terminals included in the calculation selection; the calculation unit is also used to: determine the read data storage unit from the two storage units according to the read control signal, and output the weight data stored in the read data storage unit.

[0012] In some embodiments, the computing unit is used to: when the read control signal is a third signal, control the line between the first storage unit and the data output end of the computing unit to be conductive, and output the weight data in the first storage unit from the data output end; when the read control signal is a fourth signal, control the line between the second storage unit and the data output end of the computing unit to be conductive, and output the weight data in the second storage unit from the data output end.

[0013] In some embodiments, the computing unit is further used to: when the read control signal is a third signal, control the conduction of a line between the first storage unit and the data output end of the computing unit; receive the first inverted weight data output by the first storage unit, and invert the first inverted weight data to obtain the weight data stored in the first storage unit, and output the weight data stored in the first storage unit; when the read control signal is a fourth signal, control the conduction of a line between the second storage unit and the data output end of the computing unit; receive the second inverted weight data output by the second storage unit, and invert the second inverted weight data to obtain the weight data stored in the second storage unit, and output the weight data stored in the second storage unit.

[0014] According to another aspect of the embodiments of the present disclosure, a dual-port storage-computing integrated array circuit is provided, the dual-port storage-computing integrated array circuit comprising: a controller, a first preset number of calculation selection units and a dual-port storage-computing module array; the dual-port storage-computing module array comprises a first preset number of dual-port storage-computing module groups, each dual-port storage-computing module group comprises a second preset number of dual-port storage-computing modules, each dual-port storage-computing module comprises two storage units, a write selection unit and a calculation unit in the above-mentioned dual-port storage-computing integrated unit circuit, and each dual-port storage-computing module group corresponds to the calculation selection unit in the above-mentioned dual-port storage-computing integrated unit circuit; the controller is used to send a write selection signal to the write selection unit included in each dual-port storage-computing module, and the write selection unit converts the input The weight data is stored in the storage unit corresponding to the write selection signal; the controller is also used to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group; for each calculation selection unit in the first preset number of calculation selection units, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal according to the calculation selection signal, and output the calculation control signal and the data to be calculated corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit; the calculation unit is used to determine the calculation data storage unit from the corresponding two storage units according to the calculation control signal, and calculate the weight data stored in the calculation data storage unit and the received data to be calculated, obtain the calculation result and output the calculation result.

[0015] According to another aspect of the embodiments of the present disclosure, a chip is provided, which includes the above-mentioned dual-port storage-computation-in-one unit circuit or dual-port storage-computation-in-one array circuit.

[0016] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, the electronic device comprising the above chip.

[0017] The dual-port storage and computing integrated unit circuit and the dual-port storage and computing integrated array circuit, chip and electronic device provided by the above-mentioned embodiments of the present disclosure include two storage units, a write selection unit, a calculation selection unit and a calculation unit in the dual-port storage and computing integrated unit circuit. The write selection unit selects an input data storage unit from the two storage units according to an input write selection signal, and stores the weight data into the input data storage unit. The calculation selection unit generates and outputs a calculation control signal according to the input calculation selection signal and outputs the data to be calculated to the calculation unit. The calculation unit determines the calculation data storage unit from the two storage units according to the calculation control signal, and calculates the weight data and the data to be calculated stored in the calculation data storage unit. The circuit provided by the embodiment of the present disclosure can enable two storage units to perform data writing operations and data calculation operations at the same time. Compared with the existing single-port storage and calculation integrated memory, while writing weight data to a part of the storage units in the storage and calculation array, the stored weight data can be extracted from another part of the storage units for calculation with the input initial data to be calculated, and the calculation efficiency is greatly improved, and the writing and calculation of the weight data are independent and do not interfere with each other. The two can be performed in parallel, and the circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the two storage units, the write selection unit and the calculation unit included in the dual-port storage and calculation integrated unit circuit provided by the embodiment of the present disclosure can be included in the storage and calculation basic unit of the dual-port storage and calculation integrated array circuit. The calculation unit can complete the calculation of the stored weight data and the input data to be calculated, and can switch the storage unit participating in the calculation in the two storage units according to the calculation control signal. There is no need to set a device for switching the path of the weight data entering the calculation unit separately before the calculation unit, thereby improving the integration of the circuit, reducing the number of components, and thus reducing the area, power consumption and cost of the circuit.

[0018] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0020] Figure 1 is a structural schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure;

[0021] Figure 2 is another structural schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure;

[0022] Figure 3 is another structural schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure;

[0023] Figure 4 It is a structural diagram of a dual-port storage-computation-in-one array circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0025] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0026] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0027] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0028] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0029] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0030] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0031] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0032] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0033] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0034] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0035] Application Overview

[0036] In order to solve the problem of computing efficiency bottleneck in the current single-port storage and computing integrated memory, the embodiments of the present invention provide a dual-port storage and computing integrated unit circuit and a dual-port storage and computing integrated array circuit. Multiple dual-port storage and computing integrated unit circuits can be included in the dual-port storage and computing integrated array circuit. The dual-port storage and computing integrated unit circuit is composed of two storage units, a write selection unit, a calculation selection unit, and a calculation unit. Through the write selection unit and the calculation selection unit, the two storage units can perform data writing operations and data calculation operations at the same time. Compared with the existing single-port storage and computing integrated memory, the circuit provided by the embodiments of the present invention can write weight data to a part of the storage units in the storage and computing array while extracting the stored weight data from another part of the storage units to perform operations on the input feature data, thereby achieving the writing and calculation of weight data independently and without interfering with each other. The two can be performed in parallel, and the circuit has a longer peak computing power retention time, higher effective computing power, more flexible design space and a wider range of applications.

[0037] In addition, the basic unit of the current storage-computing integrated memory includes a computing unit (Computing Cell) in addition to the memory cell (Memory Cell) responsible for storing data. Compared with ordinary memory, the storage and computing array occupies a larger area in the storage-computing integrated memory. In circuit design, on the premise of ensuring that the storage and computing basic unit has as rich functions as possible, it is also necessary to control the number of devices such as MOS tubes as much as possible. Therefore, on the basis of solving the low computing efficiency of the single-port storage-computing integrated memory, it is also necessary to make the circuit structure of the computing unit in the storage-computing basic unit as simple as possible to reduce the area, power consumption and cost of the storage-computing integrated memory. The two storage units, write selection unit and calculation unit included in the dual-port storage and calculation unit circuit provided in the embodiment of the present disclosure can be included in the basic storage and calculation unit of the dual-port storage and calculation array circuit. The calculation unit can not only complete the calculation of the stored weight data and the input data to be calculated, but also switch the storage unit involved in the calculation between the two storage units according to the calculation control signal. There is no need to separately set a device for switching the path of the weight data entering the calculation unit before each calculation unit, thereby improving the integration of the circuit, reducing the number of components, and further reducing the area, power consumption and cost of the dual-port storage and calculation unit circuit and the dual-port storage and calculation array circuit.

[0038] Exemplary Structure

[0039] Figure 1 The schematic diagram is a schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0040] like Figure 1 As shown, the circuit includes: two storage units 101 , a write selection unit 102 , a calculation selection unit 103 and a calculation unit 104 .

[0041] In this embodiment, the write selection unit 102 is used to select an input data storage unit for storing currently input weight data from the two storage units 101 according to the input write selection signal, and store the weight data into the input data storage unit. Generally, the circuit provided in this embodiment can be applied in a neural network accelerator, so the weight data can be a weight parameter involved in the calculation in the neural network.

[0042] The two storage units 101 are usually used to store single bits included in the input multi-bit weight data, and the single bits are the weight data described above. The dual-port storage-computation-integrated unit circuit provided in this embodiment can usually constitute a storage-computation-integrated module in a storage-computation-integrated array. Figure 1As shown, WD ij is the input single-bit weight data, i and j represent the position of the storage-computation-integrated module based on the dual-port storage-computation-integrated unit circuit in the storage-computation-integrated array, i is the row number, and j is the column number. Figure 1 When the first storage unit 1011 in is an input data storage unit, the single-bit weight data input to the first storage unit 1011 is represented as WD ij [0], when the write selection unit 102 selects Figure 1 When the second storage unit 1012 in FIG. 1 is an input data storage unit, the single-bit weight data input to the second storage unit 1012 is represented as WD ij [1].

[0043] The write selection unit 102 may be implemented by using a device such as a transistor, for example, an analog switch device, and the state of the analog switch device may be changed by changing the write selection signal. Figure 1 As shown, the write selection signal is represented by WRT_MUX_SEL, and WRT_MUX_SELB is the inversion of WRT_MUX_SEL. When WRT_MUX_SEL is 1 and WRT_MUX_SELB is 0, the write selection signal will be WD ij When the first storage unit 1011 is input, WRT_MUX_SEL is 0 and WRT_MUX_SELB is 1, the write selection signal WD ij Input second storage unit 1012.

[0044] In this embodiment, the calculation selection unit 103 is used to receive input initial data to be calculated and a calculation selection signal; according to the calculation selection signal, the calculation selection unit 103 determines the output terminal of the data to be calculated and the output terminal of the control signal from the two output terminals included in the calculation selection unit 103.

[0045] The initial data to be calculated may be data in the neural network to be used for calculation with weight data, such as text data, image data, audio data, video data, and feature data obtained by extracting features from the above data. Usually, the initial data to be calculated is single-bit data, for example, the initial data to be calculated may be a bit included in multi-bit feature data in the neural network. Figure 1 As shown, NN j The initial data to be calculated.

[0046] The calculation selection unit 103 can realize its function by using a transistor device, for example. Figure 1As shown, the calculation selection signal is represented by CIM_MUX_SEL. When CIM_MUX_SEL is 1, the first output terminal 1031 is used as the output terminal of the data to be calculated, and when CIM_MUX_SEL is 0, the second output terminal 1032 is used as the output terminal of the data to be calculated.

[0047] The calculation selection unit 103 can further generate data to be calculated based on the initial data to be calculated, and output the data to be calculated from the data to be calculated output terminal to the calculation unit 104. For example, the calculation selection unit 103 can perform an inversion operation on the initial data to be calculated, and output the inverted data as the data to be calculated from the data to be calculated output terminal. Alternatively, the calculation selection unit 103 can directly output the initial data to be calculated from the data to be calculated output terminal, in which case the data to be calculated is the same as the initial data to be calculated. Figure 1 As shown, the data outputted by the first output terminal 1031 is represented as NN j b0, the data outputted by the second output terminal 1032 is represented as NN j b1, when NN j When b0 is the data to be calculated, NN j b1 is the calculation control signal. On the contrary, when NN j When b1 is the data to be calculated, NN j b0 is the calculation control signal.

[0048] The calculation selection unit 103 may further generate a calculation control signal according to the calculation selection signal, and output the calculation control signal from the control signal output terminal to the calculation unit 104 .

[0049] Specifically, the calculation control signal is used to control the on-off of the line of the weight data input to the calculation unit in the two storage units 101. Generally, the calculation control signal can be a fixed high level (indicating "1") or a low level (indicating "0"). As an example, Figure 1 As shown, when the calculation selection signal CIM_MUX_SEL is 1, the second output terminal 1032 is used as the control signal output terminal, and when CIM_MUX_SEL is 0, the first output terminal 1031 is used as the control signal output terminal.

[0050] In this embodiment, the calculation unit 104 is used to determine the calculation data storage unit from the two storage units 101 according to the calculation control signal, and calculate the weight data and the data to be calculated stored in the calculation data storage unit to obtain the calculation result and output the calculation result.

[0051] Specifically, the computing unit 104 may control the computing data storage unit in the two storage units 101 to be connected to the computing unit 104 according to the received computing control signal, and at the same time, control the other storage unit to be disconnected from the computing unit 104 .

[0052] For example, Figure 1 As shown, the first output terminal 1031 corresponds to the first storage unit 1011, and the second output terminal 1032 corresponds to the second storage unit 1012. If the calculation selection signal indicates that the weight data Bit0 in the first storage unit 1011 and the initial data to be calculated NN j If the calculation selection signal indicates that the weight data and the initial data to be calculated in the second storage unit 1012 are to be calculated, a calculation control signal (e.g., "1") is output from the second output terminal 1032, and the switch inside the calculation unit 104 disconnects the line between the second storage unit 1012 and the calculation unit 104, and connects the first storage unit 1011 to the calculation unit 104, and receives the data to be calculated input from the first output terminal 1031 for calculation. Similarly, if the calculation selection signal indicates that the weight data and the initial data to be calculated in the second storage unit 1012 are to be calculated, a calculation control signal (e.g., "1") is output from the first output terminal 1031, and the switch inside the calculation unit 104 disconnects the line between the first storage unit 1011 and the calculation unit 104, and connects the second storage unit 1012 to the calculation unit 104, and receives the data to be calculated input from the second output terminal 1032 for calculation.

[0053] It should be noted that the computing unit 104 in this embodiment can be set according to the application scenario of the dual-port storage-computation integrated unit circuit. For example, the computing unit 104 can be a multiplier, a NOR gate, etc. Generally, when the dual-port storage-computation integrated unit circuit provided in this embodiment is used for the operation of a neural network, the calculation result output by the computing unit 104 is the product of the initial data to be calculated and the weight data.

[0054] The dual-port storage-computation integrated unit circuit provided by the above-mentioned embodiment of the present disclosure is provided, in which two storage units, a write selection unit, a calculation selection unit, and a calculation unit are set. The write selection unit selects the input data storage unit from the two storage units according to the input write selection signal, and stores the weight data in the input data storage unit. The calculation selection unit generates and outputs the calculation control signal and outputs the data to be calculated to the calculation unit according to the input calculation selection signal. The calculation unit determines the calculation data storage unit from the two storage units according to the calculation control signal, and calculates the weight data stored in the calculation data storage unit and the data to be calculated. The dual-port storage-computation integrated unit circuit provided by the embodiment of the present disclosure can calculate by using another storage unit while writing weight data to one storage unit. Compared with the existing single-port storage-computation integrated memory, it can extract the stored weight data from another part of the storage unit and the input initial data to be calculated while writing weight data to a part of the storage units in the storage and calculation array. The calculation efficiency is greatly improved, and the writing and calculation of the weight data are realized to be independent and non-interfering. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications. In addition, the circuit provided in the embodiment of the present disclosure includes a computing unit that can not only complete the calculation of the stored weight data and the input data to be calculated, but also switch the storage unit participating in the calculation between the two storage units according to the calculation control signal. There is no need to separately set a device for switching the path of the weight data entering the calculation unit before the calculation unit, thereby improving the integration of the circuit, reducing the number of components, and further reducing the area, power consumption and cost of the circuit.

[0055] In some optional implementations, such as Figure 1 As shown, the first output terminal 1031 of the two output terminals included in the calculation selection unit 103 corresponds to the first storage unit 1011 of the two storage units 101, and is used to output the data to be calculated that is calculated with the weight data in the first storage unit; the second output terminal 1032 of the two output terminals included in the calculation selection unit 103 corresponds to the second storage unit 1012 of the two storage units 101, and is used to output the data to be calculated that is calculated with the weight data in the first storage unit.

[0056] The calculation selection unit 103 is further used for:

[0057] When the calculation selection signal is the first signal, the first output terminal 1031 is used as the output terminal of the data to be calculated, and the data to be calculated is output to the calculation unit 104; the second output terminal 1032 is used as the control signal output terminal, a calculation control signal is generated and the calculation control signal is output to the calculation unit 104;

[0058] When the calculation selection signal is the second signal, the second output terminal 1032 is used as the output terminal of the data to be calculated, and the data to be calculated is output to the calculation unit 104; the first output terminal 1031 is used as the control signal output terminal to generate a calculation control signal and output the calculation control signal to the calculation unit 104.

[0059] The calculation unit 104 is used for:

[0060] When receiving the calculation control signal output by the second output terminal 1032, the weight data stored in the first storage unit 1011 and the data to be calculated are calculated to obtain the calculation result and output the calculation result;

[0061] When the calculation control signal outputted by the first output terminal 1031 is received, the weight data stored in the second storage unit 1012 and the data to be calculated are calculated to obtain a calculation result and output the calculation result.

[0062] Specifically, assuming that the first signal is digital "1", the second signal is digital "0", the calculation control signal is digital "1". Figure 1 As shown, if the calculation selection signal CIM_MUX_SEL is "1", the calculation unit 104 receives the signal to be calculated from the first output terminal 1031, and at the same time, the controlled switch connected to the second output terminal 1032 inside the calculation unit 104 disconnects the line between the second storage unit 1012 and the calculation unit 104 under the action of the calculation control signal, and connects the line between the first storage unit 1011 and the calculation unit 104, and the calculation unit 104 can then calculate the weight data stored in the first storage unit 1011 and the input data to be calculated. Similarly, if the calculation selection signal CIM_MUX_SEL is "0", the calculation unit 104 receives the signal to be calculated from the second output terminal 1032, and the controlled switch connected to the first output terminal 1031 in the calculation unit 104 disconnects the line between the first storage unit 1011 and the calculation unit 104 under the action of the calculation control signal, and connects the line between the second storage unit 1012 and the calculation unit 104, and the calculation unit 104 can then calculate the weight data stored in the second storage unit 1012 and the input data to be calculated. The above-mentioned controlled switch can use devices such as transistors to realize its function.

[0063] This embodiment sets the first output end of the calculation selection unit to correspond to the first storage unit, and sets the second output end to correspond to the second storage unit, so that the calculation unit can receive weight data from the currently selected storage unit more quickly and specifically, and receive data to be calculated from the corresponding output end of the calculation selection unit, thereby facilitating flexible switching of storage units involved in the calculation and improving calculation efficiency.

[0064] In some optional implementations, such as Figure 2 As shown, the calculation unit 104 includes a first multiplier 1041 and a second multiplier 1042. The first multiplier 1041 corresponds to the first storage unit 1011 and the first output terminal 1031, and the second multiplier 1042 corresponds to the second storage unit 1012 and the second output terminal 1032.

[0065] The second multiplier 1042 is used to prohibit the calculation of the weight data in the second storage unit 1012 when receiving the calculation control signal output by the second output terminal 1032; the first multiplier 1041 is used to calculate the weight data stored in the first storage unit 1011 and the data to be calculated when receiving the data to be calculated output by the first output terminal 1031, obtain the multiplication result and output the multiplication result.

[0066] The first multiplier 1041 is used to prohibit the calculation of the weight data in the first storage unit 1011 when receiving the calculation control signal output by the first output terminal 1031; the second multiplier 1042 is used to calculate the weight data stored in the second storage unit 1012 and the data to be calculated when receiving the data to be calculated output by the second output terminal 1032, obtain the multiplication result and output the multiplication result.

[0067] Specifically, Figure 2 As shown, the first multiplier 1041 is connected to the first output terminal 1031, and the second multiplier 1042 is connected to the second output terminal 1032, and the first multiplier 1041 and the second multiplier 1042 are physically connected. When CIM_MUX_SEL is "1", the initial data NN to be calculated is j After being processed by the calculation selection unit 103, the data to be calculated NN is generated j b0 (for example, it can be NN j Inverted data, or directly NN j As the data output to be calculated), NN j b0 is output from the first output terminal 1031 to the first multiplier 1041. At the same time, the second output terminal 1032 is connected to a fixed level (e.g., a high level), that is, the calculation control signal "1" is output from the second output terminal 1032 to the second multiplier 1042, and the controlled switch device included in the second multiplier 1042 disconnects the line between the second storage unit 1012 and the second multiplier 1042, and at the same time activates the function of the first multiplier 1041. The first multiplier 1041 compares the inverted data Bitb0 of the weight data Bit0 stored in the first storage unit 1011 with NN. j b0 (or directly process Bit0 and NN j b0 is processed) to obtain the multiplication result (i.e. Bit0*NNj 0).

[0068] Similarly, when CIM_MUX_SEL is "1", NN j After being processed by the calculation selection unit 103, the data to be calculated NN is generated j b1,NN j b1 is output from the second output terminal 1032 to the second multiplier 1042. At the same time, the first output terminal 1031 outputs the calculation control signal "1" to the first multiplier 1041, and the controlled switch device included in the first multiplier 1041 disconnects the line between the first storage unit 1011 and the first multiplier 1041, and activates the function of the second multiplier 1042. The second multiplier 1042 compares the inverted data Bitb1 of the weight data Bit1 stored in the second storage unit 1012 with NN. j b1 (or directly process Bit1 and NN j b1 is processed) to obtain the multiplication result (i.e. Bit1*NN j 1).

[0069] It should be noted that this embodiment does not limit the implementation method of the multiplier. For example, the multiplication calculation can be implemented by an AND gate, or by a combination of a NOT gate and a NOR gate.

[0070] This embodiment realizes switching between the first multiplier and the second multiplier according to the calculation selection signal by setting the first multiplier and the second multiplier in the calculation unit, and the first multiplier and the second multiplier perform multiplication calculations on the weight data and the initial data to be calculated in the first storage unit and the second storage unit in turn. This circuit can be applied to processes such as convolution operations of neural networks, which helps to improve the calculation efficiency of neural network accelerators. In addition, in the neural network accelerator, multiple calculation units can correspond to the same calculation selection unit, so there is no need to provide such a calculation selection unit for each pair of storage units. The first multiplier and the second multiplier of the calculation unit can realize switching between different storage units, which simplifies the circuit structure and improves the integration of the circuit.

[0071] In some optional implementations, such as Figure 3 As shown, the first multiplier 1041 includes a first NOR gate, and the second multiplier 1042 includes a second NOR gate; the calculation selection unit 103 includes an inverter 1033 and an output end selector 1034.

[0072] The inverter 1033 is used to perform an inversion operation on the initial data to be calculated to obtain the data to be calculated.

[0073] The output selector 1034 is used to output the data to be calculated from the first output terminal 1031 to the first NOR gate when the calculation selection signal is the first signal; and to output the data to be calculated from the second output terminal 1032 to the second NOR gate when the calculation selection signal is the second signal.

[0074] The first NOR gate is used to receive the first inverted weight data output by the first storage unit 1011, and perform NOR calculation on the data to be calculated and the first inverted weight data to obtain the multiplication result of the weight data in the first storage unit 1011 and the initial data to be calculated, wherein the first inverted weight data is the inverted data of the weight data in the first storage unit 1011.

[0075] The second NOR gate is used to receive the second inverted weight data output by the second storage unit 1012, and perform NOR calculation on the data to be calculated and the second inverted weight data to obtain the multiplication result of the weight data in the second storage unit 1012 and the initial data to be calculated, wherein the second inverted weight data is the inverted data of the weight data in the second storage unit 1012.

[0076] Specifically, Figure 3 As shown, the first NOR gate may include P1, P2, N2, N4, and the second NOR gate may include P3, P4, N1, N3. The first NOR gate and the second NOR gate have a common data output terminal Q. P1, P2, P3, P4 are P-type MOS transistors, and N1, N2, N3, N4 are N-type MOS transistors. VDD represents a high level, and GND represents a low level.

[0077] Typically, each storage unit may include two data output terminals, one of which is used to output the stored weight data, and the other is used to output the inverted data of the weight data. Figure 3 As shown, Bitb0 is the inverted data of the weight data Bit0 in the first storage unit 1011, and the first storage unit 1011 outputs Bitb0 to the first NOR gate. Bitb1 is the inverted data of the weight data Bit1 in the second storage unit 1012, and the second storage unit 1012 outputs Bitb1 to the second NOR gate.

[0078] Figure 3 The specific execution process of the circuit shown is: when CIM_MUX_SEL is 1, the first output terminal 1031 outputs NN j The inverted data NN j b0, and at the same time, the NN outputted by the second output terminal 1032 j If b1 is high (indicating digital "1"), P4 is turned off and N3 is turned on. The second NOR gate composed of P3, P4, N1, and N3 cannot perform NOR calculation. The first NOR gate composed of P1, P2, N2, and N4 inputs NN.j b0 and Bitb0 are ORed, and the calculation result output at the Q end is equivalent to NN j The product of bit 1 and bit 0.

[0079] When CIM_MUX_SEL is 0, the second output terminal 1032 outputs NN j The inverted data NN j b1, and at the same time, the NN outputted by the first output terminal 1031 j If b0 is high, P2 is turned off and N4 is turned on. The first NOR gate cannot perform NOR calculation. The second NOR gate inputs NN. j b1 and Bitb1 are ORed, and the calculation result output at the Q end is equivalent to NN j The product of bit 1 and bit 2.

[0080] It should be understood that Figure 3 The circuit structure is only an exemplary structure, and the type and position of the components constituting the calculation unit 104 can be arbitrarily set as needed. As long as the circuit architecture can realize the functions of the first multiplier 1041 and the second multiplier 1042, it is within the scope of the embodiment of the present disclosure. Figure 3 Bitb0 in the input is changed from input P1 to input P2, and NN j b0 is changed from input P2 to input P1.

[0081] In this embodiment, by setting the first NOR gate and the second NOR gate, the two output ends of the calculation selection unit switch the first NOR gate and the second NOR gate. There is no need to set other control elements in the calculation unit to select the storage unit participating in the calculation between the first storage unit and the second storage unit, thereby reducing the number of components used, simplifying the circuit structure, helping to reduce the area occupied by the circuit, and reducing power consumption and cost.

[0082] In some optional implementations, the calculation selection unit 103 is further configured to:

[0083] In response to receiving the read data mode selection signal, a corresponding read control signal is generated according to the calculation selection signal, and the read control signal is output through two output terminals included in the calculation selection unit 103.

[0084] like Figure 3 As shown, BIST_MODE represents the input mode selection signal. When BIST_MODE=0, it indicates that the read data mode selection signal is received. Correspondingly, when BIST_MODE=1, it indicates that the calculation mode selection signal is received. It should be understood that the schemes described in the above embodiments are all operating processes in the calculation mode.

[0085] As an example, Figure 3 When the calculation selection signal CIM_MUX_SEL shown is 1, a read data control signal indicating that the weight data is read from the first storage unit 1011 can be generated, and when CIM_MUX_SEL is 0, a read data control signal indicating that the weight data is read from the second storage unit 1012 can be generated. The read data control signal can be composed of the signals output by the first output terminal 1031 and the second output terminal 1032. For example, when Figure 3 The NN shown j b0 is "0", NN j When b1 is "1", it indicates that the weight data is read from the first storage unit 1011. j b0 is "1", NN j When b1 is “0”, it indicates that the weight data is read from the second storage unit 1012 .

[0086] The calculation unit 104 is further configured to:

[0087] According to the read control signal, the read data storage unit is determined from the two storage units 101, and the weight data stored in the read data storage unit is output.

[0088] Specifically, when the read control signal indicates that the first storage unit 1011 is a read data storage unit, the switching device inside the computing unit 104 can prohibit the second storage unit 1012 from outputting weight data and allow the first storage unit 1011 to output weight data; when the read control signal indicates that the second storage unit 1012 is a read data storage unit, the switching device inside the computing unit 104 can prohibit the first storage unit 1011 from outputting weight data and allow the first storage unit 1011 to output weight data.

[0089] This embodiment realizes switching between the data reading mode and the calculation mode by using the calculation selection unit, and can flexibly control the function of the circuit without changing the circuit structure, thereby further expanding the application scope of the circuit.

[0090] In some optional implementations, the computing unit 104 is configured to:

[0091] When the read control signal is the third signal, the line between the second storage unit 1012 and the data output end of the calculation unit 104 is controlled to be cut off, the line between the first storage unit 1011 and the data output end of the calculation unit 104 is controlled to be turned on, and the weight data in the first storage unit 1011 is output from the data output end.

[0092] When the read control signal is the fourth signal, the line between the first storage unit 1011 and the data output end of the calculation unit 104 is controlled to be cut off, the line between the second storage unit 1012 and the data output end of the calculation unit 104 is controlled to be turned on, and the weight data in the second storage unit 1012 is output from the data output end.

[0093] Specifically, the third signal and the fourth signal may be a combination signal of the first output terminal 1031 and the second output terminal 1032. Figure 3 The NN shown j b0 is "0", NN j When b1 is "1", it indicates that the read data signal is the third signal; when NN j b0 is "1", NN j When b1 is "0", it indicates that the read data signal is the fourth signal.

[0094] like Figure 3 As shown, when NN j b0 is "0", NN j When b1 is "1", P4 is turned off and N3 is turned on, and the output terminal Q of the calculation unit 104 cannot change with the change of Bitb1. At the same time, P2 is turned on and N4 is turned off, and the Q terminal can change with the change of Bitb0, thereby realizing the reading of weight data from the first storage unit 1011.

[0095] Similarly, when NN j b0 is "1", NN j When b1 is “0”, the Q terminal cannot change with the change of Bitb0, but can change with the change of Bitb1, thereby realizing the reading of weight data from the second storage unit 1012.

[0096] This embodiment achieves accurate reading of weight data from the storage unit by controlling the on / off of the line between the output end of the calculation unit 104 and the two storage units 101 through a read control signal, thereby improving the convenience of reading data in the read data mode.

[0097] In some optional implementations, the computing unit 104 is further configured to:

[0098] When the read control signal is the third signal, the line between the first storage unit 1011 and the data output end of the calculation unit 104 is controlled to be conductive; the first inverted weight data output by the first storage unit 1011 is received, and the first inverted weight data is inverted to obtain the weight data stored in the first storage unit 1011, and the weight data stored in the first storage unit 1011 is output.

[0099] When the read control signal is the fourth signal, the line between the second storage unit 1012 and the data output end of the calculation unit 104 is controlled to be conductive; the second inverted weight data output by the second storage unit 1012 is received, and the second inverted weight data is inverted to obtain the weight data stored in the second storage unit 1012, and the weight data stored in the second storage unit 1012 is output.

[0100] Specifically, Figure 3 As shown, the first inverted weight data is Bitb0, and the second inverted weight data is Bitb1. j b0 is "0", NN j When b1 is "1", it means that the read data signal is the third signal. At this time, P4 is off, N3 is on, P2 is on, N4 is off, and P1, P2, N3, and N2 form an inverter. Therefore, the Q terminal outputs the inverted data Bit0 of Bitb0, that is, the Q terminal outputs the weight data stored in the first storage unit 1011. Similarly, when NN j b0 is "1", NN j When b1 is "0", it means that the read data signal is the fourth signal. At this time, P2 is cut off, P4 is turned on, N3 is cut off, N4 is turned on, P3, P4, N1, and N4 form an inverter. Therefore, the Q end outputs the inverted data Bit1 of Bitb1, that is, the Q end outputs the weight data stored in the second storage unit 1012.

[0101] This embodiment implements the inversion operation on the inverted weight data output by the storage unit without changing the structure of the calculation unit, thereby outputting the weight data in the storage unit, effectively utilizing the structure of the calculation unit, and realizing an efficient weight data reading function.

[0102] Figure 4 The schematic diagram of the structure of a dual-port storage-computation integrated array circuit provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0103] like Figure 4 As shown, the circuit includes: a controller 401, a first preset number of calculation selection units 402 and a dual-port storage and calculation module array 403.

[0104] In this embodiment, the dual-port storage and computing module array 403 includes a first preset number of dual-port storage and computing module groups, each of which includes a second preset number of dual-port storage and computing modules, and each dual-port storage and computing module includes the above Figure 1-Figure 3The two storage units, write selection units and computing units in the dual-port storage and computing unit circuit described in any corresponding embodiment, each dual-port storage and computing module group corresponds to a computing selection unit, and the computing selection unit is the computing selection unit in the above-mentioned dual-port storage and computing unit circuit.

[0105] like Figure 4 As shown, the first preset number may be the number of rows of the dual-port storage and computing module array 403, and the second preset number may be the number of columns of the dual-port storage and computing module array 403. The number of rows and the number of columns of the dual-port storage and computing module array 403 in the figure are Y, and X, respectively. 0,0 、2P-CIM C 0,1 ……2P-CIM C Y-1,X-1 Each row of the dual-port storage and calculation module array 403 in the figure corresponds to a calculation selection unit (including CIM_SEL0-CIM_SEL Y-1 ).

[0106] Each row of the dual-port storage and calculation module array 403 can simultaneously input multi-bit weight data, and each bit of the multi-bit weight data is correspondingly stored in a storage unit of a dual-port storage and calculation module. Figure 4 As shown, the single-bit weight data included in the L multi-bit weight data corresponding to the input in row 0 is represented as WD 0,0 -WD 0,X-1 The single-bit weight data included in the L multi-bit weight data corresponding to the input in the Y-1th row is represented as WD Y-1,0 -WD Y-1,X-1 WD 0,0 -WD 0,X-1 is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. Similarly, WD Y-1,0 -WD Y-1,X-1 It is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. For example, X is 32, and a row can store 4 8-bit weight data. The initial data to be calculated input to each row can usually be a single bit contained in a multi-bit data (such as N-bit data), that is, the single bit contained in the multi-bit data is expressed as NN0-NN N-1 The multi-bit data may be, for example, multi-bit feature data to be calculated in a neural network. During calculation, based on the calculation clock, multiple groups of data to be calculated are calculated in sequence. For example, in the first calculation clock cycle, NN0-NN1 of the first multi-bit data is calculated. N-1 The corresponding rows are input respectively, and each calculation unit included in the corresponding row calculates the input data to be calculated and the stored weight data; in the second calculation clock cycle, NN0-NN of the second multi-bit data is calculated.N-1 The corresponding rows are input respectively, and the calculation units included in the corresponding rows calculate the input data to be calculated and the stored weight data. This process is repeated until the calculation of multiple multi-bit data is completed.

[0107] It should be noted that the number of bits N of the input multi-bit data may be the same as or different from the number of rows Y of the dual-port storage and computing module array 403. For the convenience of description in the drawings, the number of bits N and Y of the multi-bit data shown in 4 are the same, that is, the data to be calculated input in each calculation cycle includes NN0-NN Y-1 . In order to make the dual-port storage and computing module array 403 more versatile, the number of rows Y of the dual-port storage and computing module array 403 is usually set to a larger value, and the number of bits N of the input multi-bit data is less than Y. Therefore, one or more multi-bit data can be input in one calculation cycle. For example, when N is 8 and Y is 16, one multi-bit data can be input in one calculation cycle, that is, NN0-NN7 are input to 8 rows respectively, or 2 multi-bit data can be input in one calculation cycle, that is, NN0-NN7 of the first multi-bit data are input to the first 8 rows respectively, and NN0-NN7 of the second multi-bit data are input to the second 8 rows respectively.

[0108] In this embodiment, the controller 401 is used to send a write selection signal to the write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into the data storage unit corresponding to the write selection signal. Figure 4 As shown, the write selection signals corresponding to each row are all WRT_MUX_SEL, that is, weight data can be written to each row at the same time.

[0109] Optional, such as Figure 4 As shown, each row of the dual-port memory module array 403 corresponds to two word lines, WWL i [0] (first word line) and WWL i [1] (second word line), where i is the row number. i [0] corresponds to the first storage unit of each dual-port storage and computing module in the i-th row, WWL i [1] The second storage unit included in each dual-port storage and computing module corresponding to the i-th row. For a row of the dual-port storage and computing module array 403, each write selection unit located in the row can select a target word line from the first word line and the second word line corresponding to the row according to the received write selection signal, and store the input weight data into the storage unit corresponding to the target word line.

[0110] In this embodiment, the controller 401 is further configured to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group. Figure 4As shown, the calculation selection signals corresponding to each row are all CIM_MUX_SEL, that is, each row can be controlled to perform calculation at the same time.

[0111] Typically, the write selection signal and the calculation selection signal sent at the same time correspond to different storage units in each dual-port storage and calculation module. In the current calculation operation, the controller 401 can send a calculation selection signal for selecting a first storage unit from the corresponding two storage units for calculation to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the second storage unit of the two storage units, the controller 401 can send a write selection signal for selecting the second storage unit from the corresponding two storage units for data writing to the write selection unit included in each dual-port storage and calculation module. The write selection unit can store the received weight data in the second storage unit according to the write selection signal.

[0112] After at least one calculation operation is completed using the first storage unit included in each dual-port storage and calculation module, if it is necessary to use the weight data stored in the second storage unit included in each dual-port storage and calculation module to perform a calculation operation, the controller 401 can send a calculation selection signal for selecting the second storage unit from the corresponding two storage units to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the first storage unit of the two storage units, the controller 401 can also send a write selection signal for selecting the first storage unit from the corresponding two storage units to write data to the write selection unit included in each dual-port storage and calculation module, and the write selection unit can store the received weight data in the first storage unit according to the write selection signal.

[0113] Through the above process, in the process of performing a calculation operation using a storage unit included in each dual-port storage and calculation module, another storage unit included in each dual-port storage and calculation module can store the currently input weight data. After the calculation operation is completed, if it is necessary to switch the weight data and the input data to be calculated for calculation, the storage unit participating in the calculation can be switched between the two storage units included in each dual-port storage and calculation module, and new weight data can be input to the other storage unit at the same time, thereby realizing the independence of the write operation and the calculation operation of the dual-port storage and calculation module array 403.

[0114] In this embodiment, for each calculation selection unit in the first preset number of calculation selection units 402, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal based on the calculation selection signal, and output the calculation control signal and the data to be calculated corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit.

[0115] In this embodiment, the calculation unit is used to determine the calculation data storage unit from the corresponding two storage units according to the calculation control signal, and calculate the weight data stored in the calculation data storage unit and the received data to be calculated, obtain the calculation result and output the calculation result.

[0116] Specifically, Figure 4 The first output terminal and the second output terminal of each calculation selection unit are connected to each calculation unit in the corresponding row. Each calculation unit can simultaneously use the to-be-calculated data and the calculation control signal received from the first output terminal and the second output terminal to perform calculation. The calculation process can refer to the above Figure 1-Figure 3 The contents described in the corresponding embodiments will not be repeated here.

[0117] The dual-port storage and calculation integrated array circuit provided by the above embodiment of the present disclosure, by using the above dual-port storage and calculation integrated unit circuit, constructs a dual-port storage and calculation integrated module array including a dual-port storage and calculation integrated module array, and can write weight data to a part of the storage units in the dual-port storage and calculation integrated module array, while extracting the stored weight data from another part of the storage units and the input data to be calculated for calculation, the calculation efficiency is greatly improved, and the writing and calculation of the weight data are realized to be independent and non-interfering, the circuit has a longer peak computing power retention time, has a higher effective computing power, a more flexible design space and a wider range of applications. In addition, since the same calculation selection unit can control the calculation process of a dual-port storage and calculation module group, and the calculation unit included in each dual-port storage and calculation module can not only complete the calculation of the stored weight data and the input data to be calculated, but also switch the storage unit participating in the calculation in the two storage units according to the calculation control signal, there is no need to set a device for switching the path of the weight data entering the calculation unit separately before each calculation unit, thereby improving the integration of the circuit, reducing the number of components, and thus reducing the area, power consumption and cost of the circuit.

[0118] Optional, such as Figure 4 As shown, the circuit further includes an addition tree 404 and a shift accumulator 405 .

[0119] The addition tree 404 is used to accumulate the calculation results output by the dual-port storage and calculation modules located at the same position in each dual-port storage and calculation module group to obtain a first accumulation result. Figure 4 As shown in the figure, when each row of the dual-port storage and calculation modules is used as a dual-port storage and calculation module group, when each dual-port storage and calculation module finishes calculating, the addition tree 404 can accumulate the calculation results respectively output by the dual-port storage and calculation modules included in each column of the array to obtain the first accumulation result corresponding to each column (s0-s1 in the figure). X-1 ). It should be noted that s0-s X-1are the results of multiplying and adding Y single-bit weight data and the data to be calculated, that is, s0-s X-1 are all multi-bit data. For example, if the number of rows Y is 32, then s0-s X-1 It is the result of multiplication and addition of 32 pairs of single-bit data, and the number of bits can be 6.

[0120] The shift accumulator 405 is used to perform shift accumulation on each first accumulation result to obtain a second accumulation result (SUM0-SUM L-1 ). Usually, when the shift accumulator 405 performs a shift-accumulate operation, it targets s0-s X-1 For example, if the number of columns X involved in the operation is 32, and each row stores 4 (i.e. L is 4) 8-bit weight data, then s0-s X-1 It can be divided into 4 groups, and each group of data performs shift accumulation respectively, and the obtained SUM contains 4 second accumulation results, and each second accumulation result is the result of multiplying and adding Y 8-bit weight data and Y data to be calculated.

[0121] Optionally, since the neural network usually performs multiplication and addition calculations on a one-to-one correspondence of a plurality of multi-bit input data (such as feature data) and a plurality of multi-bit weight data. Therefore, after performing multiplication and accumulation calculations on a plurality of single-bit data to be calculated and a plurality of single-bit weight data input each time, the second accumulation results obtained each time can be shifted and accumulated multiple times to obtain the multiplication and addition results of the plurality of multi-bit input data and the plurality of multi-bit weight data. For example, the SUM0 obtained by multiple calculations is shifted and accumulated one by one to obtain the multiplication and addition results of the Y multi-bit weight data contained in the 0th group and the Y multi-bit input data input.

[0122] This embodiment realizes the calculation and shift accumulation of multiple multi-bit feature data and multiple multi-bit weight data by setting an addition tree and a shift accumulator. Therefore, when the dual-port storage and computing module array is applied to a neural network computing scenario, the neural network calculation and the weight data are written to the dual-port storage and computing module array efficiently at the same time, thereby improving the efficiency of the neural network calculation.

[0123] Optionally, the circuit can also switch between calculation mode and read data mode. The controller 401 can send a read data mode selection signal or a calculation mode selection signal to the calculation selection unit. The first preset number of calculation selection units 402 can generate a corresponding read control signal in response to receiving the read data mode selection signal according to the calculation selection signal, and output the read control signal to the corresponding calculation unit through the two output ends of the calculation selection unit. Each calculation unit determines the read data storage unit from the corresponding two storage units according to the read control signal, and outputs the weight data stored in the read data storage unit.

[0124] like Figure 4 As shown, BIST_MODE indicates the input mode selection signal, and when BIST_MODE=0, it indicates the read data mode selection signal. Correspondingly, when BIST_MODE=1, it indicates the calculation mode selection signal.

[0125] It should be understood that the calculation processes described in the above embodiments are all operating processes in the calculation mode. In addition, for the working process in the data reading mode, reference can be made to the relevant description of the above dual-port storage and calculation integrated unit circuit.

[0126] The embodiment of the present disclosure further provides a chip, on which a dual-port storage-computing integrated unit circuit or a dual-port storage-computing integrated array circuit is integrated. The technical details of the dual-port storage-computing integrated unit circuit are as follows: Figure 1-Figure 3 As shown in the relevant description, the technical details of the dual-port storage and computing array circuit are as follows Figure 4 As shown in the relevant description, no further description is given here.

[0127] The embodiments of the present disclosure also provide an electronic device, which includes the chip described in the above embodiments. In addition, the electronic device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting weight data, feature data, etc. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting calculation results, etc. The memory is used to store the data input by the above input device, as well as the data generated during the operation of the dual-port storage and calculation unit circuit or the dual-port storage and calculation array circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0128] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0129] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0130] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0131] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0132] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0133] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0134] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A dual-port storage and computing integrated unit circuit, comprising: two storage units, a write selection unit, a calculation selection unit and a calculation unit; The write selection unit is used to select an input data storage unit for storing currently input weight data from the two storage units according to an input write selection signal, and store the weight data in the input data storage unit; The calculation selection unit is used to receive input initial data to be calculated and a calculation selection signal; According to the calculation selection signal, determining the output terminal of the data to be calculated and the output terminal of the control signal from the two output terminals of the calculation selection unit; Generate data to be calculated according to the initial data to be calculated, and output the data to be calculated from the data to be calculated output terminal to the calculation unit; generating a calculation control signal according to the calculation selection signal, and outputting the calculation control signal from the control signal output terminal to the calculation unit; The calculation unit is used to determine the calculation data storage unit from the two storage units according to the calculation control signal, and calculate the weight data stored in the calculation data storage unit and the data to be calculated to obtain a calculation result and output the calculation result.

2. The circuit according to claim 1, wherein The first output end of the two output ends of the calculation selection unit corresponds to the first storage unit of the two storage units, and is used to output the data to be calculated that is calculated with the weight data in the first storage unit; the second output end of the two output ends of the calculation selection unit corresponds to the second storage unit of the two storage units, and is used to output the data to be calculated that is calculated with the weight data in the second storage unit; The calculation selection unit is further used for: When the calculation selection signal is the first signal, the first output terminal is used as an output terminal of data to be calculated, and the data to be calculated is output to the calculation unit; Using the second output terminal as a control signal output terminal, generating a calculation control signal and outputting the calculation control signal to the calculation unit; When the calculation selection signal is the second signal, the second output terminal is used as an output terminal of data to be calculated, and the data to be calculated is output to the calculation unit; the first output terminal is used as a control signal output terminal, a calculation control signal is generated, and the calculation control signal is output to the calculation unit; The computing unit is further configured to: When receiving the calculation control signal output by the second output terminal, calculating the weight data stored in the first storage unit and the data to be calculated, obtaining a calculation result and outputting the calculation result; When the calculation control signal outputted from the first output terminal is received, the weight data stored in the second storage unit and the data to be calculated are calculated to obtain a calculation result and output the calculation result.

3. The circuit according to claim 2, wherein: The calculation unit includes a first multiplier and a second multiplier, the first multiplier corresponds to the first storage unit and the first output end, and the second multiplier corresponds to the second storage unit and the second output end; The second multiplier is used to prohibit the calculation of the weight data in the second storage unit when receiving the calculation control signal output by the second output terminal; the first multiplier is used to calculate the weight data stored in the first storage unit and the data to be calculated when receiving the data to be calculated output by the first output terminal, obtain a multiplication result and output the multiplication result; The first multiplier is used to prohibit the calculation of the weight data in the first storage unit when receiving the calculation control signal output by the first output end; the second multiplier is used to calculate the weight data stored in the second storage unit and the data to be calculated when receiving the data to be calculated output by the second output end, obtain the multiplication result and output the multiplication result.

4. The circuit according to claim 3, wherein: The first multiplier includes a first NOR gate, and the second multiplier includes a second NOR gate; the calculation selection unit includes an inverter and an output terminal selector; The inverter is used to perform an inversion operation on the initial data to be calculated to obtain the data to be calculated; The output terminal selector is used to output the data to be calculated from the first output terminal to the first NOR gate when the calculation selection signal is a first signal; and to output the data to be calculated from the second output terminal to the second NOR gate when the calculation selection signal is a second signal; The first NOR gate is used to receive the first inverted weight data output by the first storage unit, and perform NOR calculation on the data to be calculated and the first inverted weight data to obtain a multiplication result of the weight data in the first storage unit and the initial data to be calculated, wherein the first inverted weight data is the inverted data of the weight data in the first storage unit; The second NOR gate is used to receive the second inverted weight data output by the second storage unit, and perform NOR calculation on the data to be calculated and the second inverted weight data to obtain the multiplication result of the weight data in the second storage unit and the initial data to be calculated, wherein the second inverted weight data is the inverted data of the weight data in the second storage unit.

5. The circuit according to any one of claims 1 to 4, wherein: The calculation selection unit is further used for: In response to receiving a read data mode selection signal, generating a corresponding read control signal according to the calculation selection signal, and outputting the read control signal through two output terminals of the calculation selection unit; The computing unit is also used for: According to the read control signal, a read data storage unit is determined from the two storage units, and the weight data stored in the read data storage unit is output.

6. The circuit according to claim 5, wherein: The computing unit is used for: When the read control signal is a third signal, controlling the line between the first storage unit and the data output terminal of the calculation unit to be turned on, and outputting the weight data in the first storage unit through the data output terminal; When the read control signal is the fourth signal, the line between the second storage unit and the data output terminal of the calculation unit is controlled to be connected, and the weight data in the second storage unit is outputted from the data output terminal.

7. The circuit according to claim 6, wherein: The computing unit is further configured to: When the read control signal is the third signal, control the line between the first storage unit and the data output terminal of the calculation unit to be turned on; receive the first inverted weight data output by the first storage unit, perform an inverting operation on the first inverted weight data, obtain the weight data stored in the first storage unit, and output the weight data stored in the first storage unit; When the read control signal is the fourth signal, controlling the line between the second storage unit and the data output terminal of the calculation unit to be turned on; The second inverted weight data output by the second storage unit is received, and an inverting operation is performed on the second inverted weight data to obtain the weight data stored in the second storage unit, and the weight data stored in the second storage unit is output.

8. A dual-port storage and computing integrated array circuit, comprising: A controller, a dual-port storage and computing module array, and a first preset number of computing selection units; The dual-port storage and computing module array includes a first preset number of dual-port storage and computing module groups, each dual-port storage and computing module group includes a second preset number of dual-port storage and computing modules, each dual-port storage and computing module includes two storage units, a write selection unit and a computing unit in the dual-port storage and computing integrated unit circuit according to any one of claims 1 to 7, each dual-port storage and computing module group corresponds to a computing selection unit, and the computing selection unit is the computing selection unit in the dual-port storage and computing integrated unit circuit according to any one of claims 1 to 7; The controller is used to send a write selection signal to the write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into the storage unit corresponding to the write selection signal; The controller is also used to send a calculation selection signal to the calculation selection unit corresponding to each dual-port storage and calculation module group; For each of the first preset number of calculation selection units, the calculation selection unit is used to generate a calculation control signal corresponding to the calculation selection signal according to the calculation selection signal, and output the calculation control signal and the to-be-calculated data corresponding to the calculation selection unit to the second preset number of calculation units corresponding to the calculation selection unit; The calculation unit is used to determine the calculation data storage unit from the corresponding two storage units according to the calculation control signal, and calculate the weight data stored in the calculation data storage unit and the received data to be calculated, obtain the calculation result and output the calculation result.

9. A chip, comprising the dual-port storage-computation-in-one unit circuit according to any one of claims 1 to 7 or the dual-port storage-computation-in-one array circuit according to claim 8.

10. An electronic device comprising the chip according to claim 9.

Images