Cell rows with mixed height and mixed nanobelt width

Abstract

Techniques are described for designing and forming cells including transistor devices for integrated circuits. In an example, an integrated circuit structure includes a plurality of cells arranged in rows, where some rows have different cell heights than other rows. In addition, the cells of each row may include semiconductor nanobelts having different widths between different rows. For example, any number of first row cells may each have a first height, any number of second row cells may each have a second height, the second height being less than the first height. The first row of cells may include transistors of semiconductor nanobelts having a first width, and the second row of cells may include transistors of semiconductor nanobelts having a second width, the second width being smaller than the first width. In some cases, any cell of the first row of cells may also include a transistor having a semiconductor nanobelt of a second width.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly to designing and forming cells including transistor devices for integrated circuits. Background Art

[0002] When designing and forming an integrated circuit structure, a standard unit cell library is developed with a given number of transistors per unit cell. Multiple signal tracks can also be used in the interconnect layer about the transistors to form connections to each transistor element. As devices and unit cells become smaller and smaller, it becomes difficult to maximize the available space and reduce parasitic effects at the same time. Therefore, in order to improve PPA (power, performance and area) performance, there are still multiple challenges that cannot be ignored relative to designing the layout of each unit of the integrated circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure, the integrated circuit structure including cell rows with different heights and different nanoribbon widths.

[0004] Figure 1B is a plan view across multiple cells in an array showing rows of nanoribbons of different heights and having different widths according to an embodiment of the present disclosure.

[0005] Figure 2A-2I is a cross-sectional view illustrating stages in an exemplary process for forming an integrated circuit having rows of cells of varying heights and varying nanoribbon widths, according to some embodiments of the present disclosure.

[0006] Figure 3 A cross-sectional view of another integrated circuit including rows of cells having the same height and having different nanoribbon widths according to some embodiments of the present disclosure is shown.

[0007] Figure 4 A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0008] Figure 5 The invention is designed and formed according to the embodiment of the present invention. Figure 1A Or a flowchart of a method of an integrated circuit of 1B.

[0009] Figure 6 A computing system including one or more integrated circuits as described throughout this document is shown according to an embodiment of the present disclosure.

[0010] Although the detailed description section below will continue to refer to the exemplary embodiments, many alternatives, modifications and variations of the embodiments will be apparent in light of the present disclosure. It should also be recognized that the drawings are not necessarily drawn to scale and are not intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate ideal straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than ideal straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topography or otherwise exhibit non-smoothness, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0011] The described technology is used to design and form a unit including a transistor device for an integrated circuit. In an example, the integrated circuit structure includes a plurality of units arranged in rows, wherein some rows have different unit heights compared to other rows. In addition, the units of each row may include semiconductor nanoribbons (or nanowires, or other multi-gate channel structures) with different widths between different rows. For example, any number of first row units may all have a first height, and any number of second rows may all have a second height, the second height being at least 3nm less than the first height. The first row of units may include transistors having semiconductor nanoribbons of a first width, and the second row of units may include transistors having semiconductor nanoribbons of a second width, the second width being at least 5nm less than the first width. In some cases, any first row of the first row of units may also include transistors having semiconductor nanoribbons of a second width. In other examples, multiple unit rows may all have the same unit height, but have different configurations of nanoribbon widths between unit rows. In view of the present disclosure, many configurations and variations will be apparent.

[0012] General Overview

[0013] As noted above, there are also several challenges to forming various semiconductor structures that cannot be ignored. When manufacturing a large number of cells on a large array, many transistor structures remain the same along a given cell row, such as the same size of semiconductor nanoribbons. However, while this helps reduce variations that can reduce yield, it can also result in some parts of specific conductive structures not being utilized, such as gate structures, which can result in parasitic capacitance. These parasitic effects can reduce the number of switching times of the transistor and degrade overall performance.

[0014] Therefore, according to an embodiment of the present disclosure, a technique for forming cell rows with different cell heights is provided herein to accommodate nanoribbons of different sizes while minimizing wasted gate area. Thus, one or more first cell rows may have a first height, and one or more second cell rows may have a second height that is at least 3 nm, at least 5 nm, or at least 7 nm shorter than the first height. Due to process variations, there may be some slight variations between the heights of the first cells or between the heights of the second cells. For example, the first cells may all have a height within 1 nm of the first height, and the second cells may all have a height within 1 nm of the second height. The various exemplary heights discussed herein are along the Y-axis direction in the plan view orientation (e.g., as Figure 1B ). For example, each cell includes two or more transistor devices, and the various heights are measured along the length of the gate structure of a single cell. Therefore, the height of the cell is not a traditional vertical or Z-axis height, but rather, the height of a given cell is the distance between the relative first and second cell boundaries of the given cell (e.g., along the Y-axis direction in the plan view of the structure). It should be understood that the cell boundaries between adjacent cells do not refer to a specific structure, but rather identify the delineation between repeated transistor arrangements. In some examples, the cell boundaries between adjacent cell rows pass through gate cuts extending along the X direction.

[0015] According to some embodiments, the second unit having a second height includes one or more semiconductor devices having a semiconductor body having a shorter width than the semiconductor body found in the semiconductor device of the first unit having the first height. The semiconductor body width can be measured in the same direction as the unit height (e.g., along the Y axis). The semiconductor body can be a fin composed of a semiconductor material, or can be a nanoribbon extending between a source region and a drain region. The examples described and illustrated herein use a nanoribbon semiconductor body. In some embodiments, one or more semiconductor bodies within the first unit have a first width, and one or more semiconductor bodies within the second unit have a second width that is at least 5nm, at least 7nm, at least 10nm, or at least 15nm shorter than the first width.

[0016] The cell array may include any arrangement of multiple rows of first cells and multiple rows of second cells. In some embodiments, the cell array may include any number of rows of third cells having substantially the same height as the first cells (e.g., within 1 nm) but having a mixed arrangement of semiconductor body widths. For example, the third cell may include a first semiconductor device having a semiconductor body of a first width and a second semiconductor device having a semiconductor body of a second width.

[0017] In some embodiments, all rows of a cell array may include substantially the same cell height, but may include semiconductor bodies of different sizes. For example, some rows may include semiconductor bodies that all have a first width, some rows may include semiconductor bodies that all have a second width, and some rows may include one or more semiconductor bodies that have the first width and one or more semiconductor bodies that have the second width.

[0018] According to an embodiment, an integrated circuit structure includes a plurality of first units and a plurality of second units. Each first unit has a corresponding height within 1 nanometer (nm) of a first height along a first direction, and includes corresponding two or more transistor devices. Each second unit has a corresponding height within 1nm of a second height along a first direction, wherein the second height is at least 3nm less than the first height. Each second unit has corresponding two or more transistor devices. The first direction is parallel to the length of the gate structure of the first unit or the second unit. The plurality of first units are arranged into one or more first rows, and the plurality of second units are arranged into one or more second rows, so that the one or more first rows have a first height, and the one or more second rows have a second height. The corresponding two or more transistor devices of at least one first unit include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second unit include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction. The second width is at least 5nm shorter than the first width.

[0019] According to another embodiment, an integrated circuit design system includes at least one processor and a non-transitory storage medium storing instructions, which, when executed by the at least one processor, cause the system to perform a method. The method includes accessing a cell library having a first cell and a second cell, receiving data about a circuit to be implemented using the first and second cells, and designing one or more first rows including the first cell and one or more second rows including the second cell. Each first cell has a first height along a first direction, and each second cell has a second height along the first direction, wherein the second height is at least 3 nm less than the first height. Each first cell and each second cell includes corresponding two or more transistor devices, and the first direction is parallel to the length of the gate structure of the first cell or the second cell. One or more first rows each have a first height, and one or more second rows each have a second height. The corresponding two or more transistor devices of at least one first cell include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second cell include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, and the second width is at least 5 nm shorter than the first width.

[0020] According to another embodiment, an integrated circuit structure includes a plurality of first cells and a plurality of second cells. Each first cell has a corresponding height along a first direction, and each first cell has corresponding two or more transistor devices. Each second cell has a corresponding height substantially the same along the first direction, and each second cell has corresponding two or more transistor devices. The first direction is parallel to the length of the gate structure of the first cell or the second cell. The plurality of first cells are arranged in one or more first rows, and the plurality of second cells are arranged in one or more second rows. The corresponding two or more transistor devices of at least one first cell include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second cell include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, and the second width is at least 5nm shorter than the first width.

[0021] The technology can be used with any type of non-planar transistor, including fin FETs (sometimes called dual-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called gate-wrap transistors), to name a few. The source and drain regions can be, for example, doped portions of a given fin or substrate or epitaxial regions deposited during an etch-alternative source / drain formation process. The type of dopant in the source and drain regions will depend on the polarity of the respective transistors. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG process), or any other gate formation process. Any number of semiconductor materials can be used in the formation of the transistor, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0022] The use of the techniques and structures provided herein can be detected using tools, for example, electron microscopes including scanning / transmission electron microscopes (SEM / TEM), scanning transmission electron microscopes (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopes (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectrometers (EDX); secondary ion mass spectrometers (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, which are just a few suitable exemplary analytical tools. For example, in some exemplary embodiments, such tools can indicate that some rows have cell rows with shorter heights than other rows. In such an example, the height of a given cell can be measured between gate cuts extending along the cell boundaries between adjacent rows. In addition, transistor devices with different semiconductor body widths can be observed between a first cell of a first height and a second cell of a second height shorter than the first height. In view of this disclosure, many configurations and variations will be apparent.

[0023] It should be understood that the meaning of "on..." and "above..." in the present disclosure should be interpreted in the broadest manner, so that "on..." and "above..." not only refer to being directly on something, but also include being above something with intermediate features or layers therebetween. In addition, for the convenience of description, spatially related terms such as "under...", "below...", "down," "above...", "up," "top," "bottom," and the like may be used herein to describe the relationship between an element or feature and another element or features, as shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations during use or operation of the device other than the orientation shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0024] As used herein, the term "layer" refers to a portion of a material that includes an area with a thickness. A monoatomic layer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a continuous structure that is homogeneous or inhomogeneous, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (flat or curved), with a relatively uniform thickness throughout the layer.

[0025] As used herein, "compositionally different" or "compositionally distinct" materials refer to two materials that have different chemical compositions. Such compositional differences may be due, for example, to an element present in one material that is not present in the other (e.g., SiGe is compositionally distinct from silicon), or one material and a second material have all the same elements, but at least one of those materials is artificially provided in a different concentration in one material relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally distinct from SiGe with 25 atomic percent germanium). In addition to such chemical composition differences, the materials may also include different dopants (e.g., gallium and magnesium) or the same dopant at different concentrations. In other embodiments, compositionally different materials may also refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally distinct or different from (100) silicon. For example, the generation of stacks of different orientations may be accomplished using blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not present in the other material.

[0026] Architecture

[0027] Figure 1A is a cross-sectional view of a portion of an integrated circuit according to an embodiment of the present disclosure, the integrated circuit including semiconductor devices arranged within adjacent cells. Each semiconductor device can be a non-planar metal oxide semiconductor (MOS) transistor, for example, a tri-gate or gate-around (GAA) transistor, but other transistor topologies and types can also benefit from the techniques provided herein. The examples herein illustrate semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between source and drain regions). FIG. 1 shows four exemplary cells 102a-102d adjacent to each other along a first direction (e.g., the Y direction). Each cell can be a cell of a given cell row extending along a second direction (e.g., the X direction) into and out of the page, such as Figure 1B Thus, the illustrated cells 102a-102d may be part of the same column of cells.

[0028] One or more semiconductor regions of the device may include fins, which may be, for example, native to the substrate (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed from material deposited onto an underlying substrate. In one such exemplary case, a blanket layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In yet other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process in which one type of the alternating layers is selectively etched away, thereby freeing up another type of the alternating layers within the channel region, thereby enabling a gate wrap-around process to be performed later. Similarly, the alternating layers may be blanket deposited and then etched into fins, or deposited into fin-shaped trenches.

[0029] According to some embodiments, the semiconductor substrate is removed and replaced with a base dielectric layer 104. A backside removal process may be performed to form a backside interconnect structure and / or remove any semiconductor material from beneath the device that may form a parasitic channel. The base dielectric layer 104 may include any suitable dielectric material, such as silicon dioxide. In some examples, the base dielectric layer 104 represents a combination of various dielectric layers that may be formed at different stages of the manufacturing process.

[0030] Each unit 102a-102d includes two or more semiconductor devices. Although four nanoribbons are shown here for each semiconductor device, each semiconductor device may include any number of nanoribbons. In some examples, each semiconductor device includes only three nanoribbons. The illustrated view shows two semiconductor devices in each unit. Each semiconductor device includes one or more semiconductor regions, such as one or more first nanoribbons 106 or second nanoribbons 108 extending between corresponding epitaxial source regions or drain regions (not shown in this view) along the X-axis in the second direction. Nanoribbons 106 / 108 may include any suitable semiconductor material, such as silicon, germanium or silicon germanium. Compared with the width of the second nanoribbon 108, the first nanoribbon 106 may have a larger width (e.g., along the first direction). In some embodiments, the first nanoribbon 106 has a first width w1 between about 18nm and about 35nm, and the second nanoribbon 108 has a second width w2 between about 6nm and about 20nm. In some examples, the first width w1 is at least 5 nm, at least 7 nm, at least 10 nm, or at least 15 nm greater than the second width w2. It should be understood that the width of each nanoribbon or semiconductor fin of a given device can be tapered along a third direction (e.g., along the Z direction) due to manufacturing constraints. Therefore, the widths between different semiconductor devices are compared along a common XY plane passing through the nanoribbons or semiconductor fins of the device. In one example, the widths between different semiconductor devices having the first nanoribbon 106 or the second nanoribbon 108 are compared using the topmost or bottommost nanoribbon of each device.

[0031] According to some embodiments, some cells have different heights and different arrangements of transistors having the first nanoribbon 106 or the second nanoribbon 108. For example, the first cell 102a and the second cell 102b may both have a first height h1 along the first direction, and the third cell 102c and the fourth cell 102d may both have a second height h2 along the first direction. The first height h1 may be at least 3 nm, at least 5 nm, or at least 7 nm greater than the second height h2. All cells of a given row (e.g., along the X direction) may share the same cell height. According to some embodiments, cells having a shorter height h2, such as the third cell 102c and the fourth cell 102d, include only semiconductor devices of the second nanoribbon 108 having a smaller second width w2. According to some embodiments, cells having a greater height h1 may include only semiconductor devices having the first nanoribbon 106 (e.g., the first cell 102a), or may include at least one semiconductor device having the first nanoribbon 106 (e.g., the second cell 102b). Therefore, some rows of cells may include only semiconductor devices having the first width w1, some rows of cells may include only semiconductor devices having the second width w2, and some rows of cells may include one or more semiconductor devices having the first width w1 and one or more semiconductor devices having the second width w2. The cells including only semiconductor devices having the second width w2 may have a lower height, thereby eliminating unnecessary portions of the gate structure.

[0032] Each cell includes a corresponding gate structure 110a-110d extending longitudinally along the height of each cell (e.g., along the Y direction). Each gate structure includes a gate electrode and a gate dielectric to form a transistor gate. The gate dielectric can represent any number of dielectric layers. The gate electrode can include any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some embodiments, the gate electrode includes one or more work function metals around one or more semiconductor regions. In some embodiments, the p-channel device includes a work function metal having titanium around one or more semiconductor regions, and the n-channel device includes a work function metal having tungsten around one or more semiconductor regions. The gate electrode can also include a fill metal or other conductive material around the work function metal to provide an entire gate electrode structure. A given gate structure can extend over the semiconductor body of more than one semiconductor device. In the illustrated example, each gate structure 110a-110d extends over two corresponding semiconductor bodies to provide two semiconductor devices in each cell.

[0033] According to some embodiments, one or more dielectric walls 112 (e.g., gate cuts) extend across the gate structure in a second direction (e.g., along the X direction). The dielectric wall 112 may continue to extend across any number of other gate trenches and source / drain trenches along the second direction to separate the cell rows from each other. Thus, the cell boundaries (identified by dashed lines) between the rows may pass through the dielectric wall 112. In this way, the position of the dielectric wall 112 along the first direction may determine the position of the cell boundary and the corresponding height of the cell. According to some embodiments, the one or more dielectric walls 112 include any suitable dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. According to some embodiments, the one or more dielectric walls 112 extend at least through the entire thickness of the gate structures 110a-110d. In some examples, the one or more dielectric walls 112 also extend through the entire thickness of the base dielectric layer 104 (as shown). A dielectric cap 113 may be formed over the cell to provide separation between the transistor structures and any interconnect structures formed above them.

[0034] According to some embodiments, a plurality of first conductive layers 114 may be formed on cells 102a-102d and extend longitudinally along a second direction (e.g., the X direction). The first conductive layers 114 may be formed substantially in parallel strips that are equally spaced from one another. In some examples, the first conductive layer 114 represents a first metal layer of an interconnect structure on the cell. Thus, the first conductive layer 114 may be used to provide logic signals to any of the transistor elements of the cell. The first conductive layer 114 may include any suitable conductive material, such as copper, tungsten, molybdenum, or ruthenium.

[0035] According to some embodiments, cells of different heights have different numbers of first conductive layers 114 extending thereover. For example, the first cell 102a and the second cell 102b each have a first height h1 and four first conductive layers 114 disposed above the cell, and the third cell 102c and the fourth cell 102d each have a second height h2 and three first conductive layers 114 disposed above the cell. It should be noted that the first conductive layers 114 extending across the cell boundaries may be dummy structures that are not used to provide any signals to the circuit. In some examples, these dummy structures are completely omitted from the structure. In some embodiments, cells having a first height h1 include more first conductive layers 114 than cells having a second height h2.

[0036] According to some embodiments, a plurality of second conductive layers 116 may be formed under the cells 102a-102d and extend longitudinally along a second direction (e.g., the X direction). The second conductive layer 116 may be formed roughly in parallel strips that are equally spaced from each other. In some examples, the second conductive layer 116 represents a metal layer of a backside interconnect structure under the cell. Therefore, the second conductive layer 116 may be used to provide power or a ground signal to any element of each transistor element of the cell. The second conductive layer 116 may include any suitable conductive material, such as copper, tungsten, molybdenum, or ruthenium. In some embodiments, the second conductive layer 116 is aligned with a cell boundary between adjacent rows of cells. Therefore, the second conductive layer 116 may extend along the second direction at the same position as the cell boundary between adjacent rows of cells.

[0037] Figure 1B A plan view of a unit cell array having substantially the same cell width but different cell heights according to some embodiments is shown. Each cell row 118a-118f can include any number of cells extending along the second direction, wherein each cell of a given row has substantially the same height. In the illustrated example, cell rows 118a, 118b, 118d, and 118f have a first cell height h1, and cell rows 118c and 118e have a second cell height h2. Shorter cells include only semiconductor devices having narrower semiconductor bodies. Longer cells include either only semiconductor devices having wider semiconductor bodies, or a mixture between semiconductor devices having wider semiconductor bodies and semiconductor devices having narrower semiconductor bodies.

[0038] Preparation method

[0039] Figure 2A-2I are cross-sectional views according to embodiments of the present disclosure, which collectively illustrate an exemplary process for forming an integrated circuit having rows of cells of varying heights and varying nanoribbon widths. Each figure represents a cross-sectional view taken along the YZ plane of a given gate trench across a plurality of cells of a given column of cells. Each figure illustrates an exemplary structure resulting from the process flow up to that point in time, whereby the illustrated structure evolves as the process flow continues, ultimately resulting in Fig.2I The structure shown in Figure 1A . Such a structure may be part of an overall integrated circuit (e.g., a processor or memory chip), which includes, for example, digital logic cells and / or memory cells and analog mixed signal circuitry. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuit systems not shown. It should be appreciated that although exemplary materials and process parameters are given, it is not intended to limit the present disclosure to any specific such materials or parameters.

[0040] Figure 2AA cross-sectional view of multiple material layers formed on a substrate according to an embodiment of the present disclosure is shown. Alternating material layers may be deposited on a substrate 201, the alternating material layers including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 may be deposited on the substrate 201.

[0041] Substrate 201 may be, for example, a bulk substrate including a Group IV semiconductor material (e.g., silicon, germanium, or silicon germanium), a Group III-V semiconductor material (e.g., gallium arsenide, gallium indium arsenide, or indium phosphide), and / or any other suitable material on which a transistor can be formed. Alternatively, substrate 201 may be a semiconductor-on-insulator substrate having a desired semiconductor layer located above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, substrate 201 may be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating silicon and SiGe layers, or alternating gallium indium arsenide and indium phosphide layers). Any number of substrates may be used.

[0042] According to some embodiments, sacrificial layer 202 has a different material composition than semiconductor layer 204. In some embodiments, sacrificial layer 202 is silicon germanium (SiGe), while semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material, such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layer 202 and semiconductor layer 204, the germanium concentration is different between sacrificial layer 202 and semiconductor layer 204. For example, sacrificial layer 202 can include a higher germanium content than semiconductor layer 204.

[0043] Although there may be variations in the dimensions between different exemplary embodiments, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer 204 may be about the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and the semiconductor layer 204 may be deposited using any known material deposition technique such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0044] Figure 2B The embodiment according to the present invention is shown Figure 2A2 is a cross-sectional view of the structure shown in after forming a cap layer 206 and subsequently forming fins below the cap layer 206. The cap layer 206 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 206 is patterned into rows to form corresponding rows of fins from an alternating layer stack of sacrificial layers 202 and semiconductor layers 204. The rows of fins extend longitudinally in a second direction (e.g., into and out of the page of each cross-sectional view). Note that some fins are patterned to have a first width w1, while other fins are patterned to have a second width w2 that is less than the first width w1. Any number of fins having a first width w1 and fins having a second width w2 can be formed. Depending on where the cell boundaries are, the distance between adjacent fins may not be consistent.

[0045] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of the substrate 201, wherein the unetched portion of the substrate 201 located below the fin forms a sub-fin region 208. The etched portion of the substrate 201 can be filled with a dielectric filler 210, which acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler 210 can be any suitable dielectric material, such as silicon dioxide, and can be recessed to a desired depth as shown (in this exemplary case, recessed downwardly around the upper surface of the sub-fin region 208) to define the active portion of the fin that will be covered by the gate structure. In some embodiments, the dielectric filler 210 is recessed below the top surface of the sub-fin region 208.

[0046] Figure 2C According to some embodiments Figure 2B 2 is a cross-sectional view of the structure shown in FIG. 2 after forming a sacrificial gate 212 extending across the fin in a first direction. As described above, the first direction (e.g., along the Y direction) can be orthogonal to the second direction (e.g., along the X direction). According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and is removed in all areas not protected by the gate masking layer. The sacrificial gate 212 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 212 includes polysilicon.

[0047] The sacrificial gate 212 (along with any gate spacers formed on the sidewalls of the sacrificial gate 212) protects the lower portion of the fin, while the exposed portion of the fin between the gate spacers is etched away. According to some embodiments, both the semiconductor layer 204 and the sacrificial layer 202 are etched at substantially the same rate using an anisotropic RIE process to form source / drain trenches. In some embodiments, the inner gate spacer can be formed after etching the source / drain trenches and before forming any source or drain regions. For example, selective etching can be used to laterally recess the sacrificial layer 202, which can then be filled with an inner gate spacer material (e.g., silicon nitride or silicon oxynitride). Any excess gate spacer material can be removed using directional etching.

[0048] According to some embodiments, a source region or a drain region is formed after forming the sacrificial gate 212. The source region or the drain region is not shown in this cross section because they would be present at the end where the semiconductor layer 204 enters and exits the page. According to some embodiments, the source region or the drain region can be epitaxially grown from the exposed end of the semiconductor layer 204 so that the materials grow together or otherwise merge toward the middle of the trench between the fins. It should be noted that the epitaxial growth on one semiconductor layer 204 can be completely or partially merged with the epitaxial growth on one or more other semiconductor layers 204 in the same vertical stack. The extent of any such merger can vary between embodiments. In the example of a PMOS device, a given source region or a drain region can be a semiconductor material (e.g., a group IV or a group III-V semiconductor material) of a p-type dopant having a higher dopant concentration than an n-type dopant. In the example of an NMOS device, a given source region or a drain region can be a semiconductor material (e.g., a group IV or a group III-V semiconductor material) of an n-type dopant having a higher dopant concentration than a p-type dopant. According to some embodiments, source regions or drain regions grown from different semiconductor devices may be aligned along the source / drain trenches in the second direction.

[0049] Figure 2D According to some embodiments Figure 2C2 is a cross-sectional view of the structure shown in FIG. 2 after forming a first nanoribbon 214a and a second nanoribbon 214b from the semiconductor layer 204. Depending on the scale of the structure, the nanoribbons 214a / 214b may also be considered as nanowires or nanosheets. The sacrificial gate 212 may be removed using any wet or dry isotropic process to expose the alternating layer stack of fins within the trench left after the sacrificial gate 212 is removed. Once the sacrificial gate 212 is removed, the sacrificial layer 202 may also be removed using a selective isotropic etching process that removes the material of the sacrificial gate 202 but does not remove (or only removes very little) the semiconductor layer 204 or any other exposed layer (e.g., an inner gate spacer). At this point, the suspended (sometimes referred to as released) semiconductor layer 204 forms a nanoribbon 214a / 214b extending in a first direction (in and out of the page) between the corresponding source or drain regions. The first nanoribbon 214a may have a first width w1 between about 18 nm and about 35 nm, and the second nanoribbon 214b may have a second width w2 between about 6 nm and about 20 nm. In some examples, the first width w1 is at least 5 nm, at least 7 nm, at least 10 nm, or at least 15 nm greater than the second width w2.

[0050] Figure 2E According to some embodiments, Figure 2D 214a / 214b within the gate trenches. As described above, the gate structure includes both a gate dielectric and a gate electrode. The gate dielectric may be conformally deposited around the nanoribbons 214a / 214b using any suitable deposition process such as atomic layer deposition (ALD), and the gate dielectric may include any suitable dielectric (e.g., silicon dioxide and / or high-k dielectric material).

[0051] The gate electrode can be deposited above the gate dielectric and can be any conductive structure. In some embodiments, the gate electrode includes doped polysilicon, a metal or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper and their carbides and nitrides. The gate electrode can include (for example) one or more work function layers, a resistance reduction layer and / or a barrier layer. The work function layer can include, for example, a p-type work function material (for example, titanium nitride) for a PMOS gate, or an n-type work function material (for example, titanium aluminum carbide) for an NMOS gate.

[0052] Figure 2F According to some embodiments, Figure 2E2 is a cross-sectional view of the structure shown in FIG. 2 after forming a dielectric wall 218 extending between adjacent cells 220a-220d along the second direction. The dielectric wall 218 can separate the gate structure 216 into smaller gate structures within each cell (e.g., a first gate structure 216a of the first cell 220a, a second gate structure 216b of the second cell 220b, a third gate structure 216c of the third cell 220c, and a fourth gate structure 216d of the fourth cell 220d). The dielectric wall 218 extends to a depth that at least passes through the entire thickness of the gate structures 216a-216d to isolate independent gate structures along the second direction. In some embodiments, the dielectric wall 218 extends into at least a portion of the dielectric filler 210 or passes through the entire thickness of the dielectric filler 210. In some embodiments, the dielectric wall 218 extends through the entire dielectric filler 210 and into a portion of the substrate 201. The dielectric wall 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon carbide. In some examples, dielectric wall 218 includes a first dielectric layer deposited first and a second dielectric layer or dielectric filler formed on the first dielectric layer. The first dielectric layer may include a high-k dielectric material (e.g., a material with a dielectric constant higher than silicon oxide or higher than 3.9), and the second dielectric layer or dielectric filler may include a low-k dielectric material (e.g., a material with a dielectric constant equal to or lower than silicon oxide, such as porous silicon oxide or a material equal to or lower than 3.9). In some embodiments, the position of dielectric wall 218 along the first direction defines a cell boundary between adjacent row cells and may determine the cell height along the first direction.

[0053] Figure 2G According to some embodiments Figure 2F 2 is a cross-sectional view of the structure shown in FIG. 2 after forming a top-side interconnect structure, such as a first metal layer 222. The first metal layer 222 can be formed over a dielectric capping layer 224 to isolate the first metal layer 222 from the transistor structure below. The dielectric capping layer 224 can represent any number of various dielectric materials or layers.

[0054] The first conductive layer 222 can be formed into parallel strips that are approximately equally spaced from each other. In some examples, the first conductive layer 222 represents the first metal layer of the interconnect structure above the cell. Therefore, the first conductive layer 222 can be used to provide logic signals to any element of the transistor elements of the cell (e.g., using vias or contacts to connect to the transistor structure below). The first conductive layer 222 can include any suitable conductive material, such as copper, tungsten, molybdenum, or ruthenium.

[0055] Figure 2H Draws Figure 2G2 is a cross-sectional view of the structure shown in FIG. 2 after removing substrate 201. Any topside interconnect structures (e.g., back-end structures) may be formed before removing substrate 201. Substrate 201 may be polished via CMP or another grinding process to remove substrate material. According to some embodiments, thinning of substrate 201 continues, at least until dielectric fill 210 and / or sub-fin 208 are exposed.

[0056] Fig.2I According to some embodiments, Figure 2H 2 is a cross-sectional view of the structure shown in FIG. 2 after forming a base dielectric layer 228 and a back conductive structure on or below the base dielectric layer. The sub-fin 208 can be removed from the back side and replaced with a dielectric plug 226 to form a base dielectric layer 228 that can include both dielectric filler 210 and dielectric plug 226.

[0057] According to some embodiments, a second conductive layer 230 is formed on the back side of the structure below the base dielectric layer 228. The second conductive layer 230 can be formed into parallel strips that are approximately equally spaced from each other. In some examples, the second conductive layer 230 can be used to provide power or ground signals to any of the transistor elements of the cell. The second conductive layer 230 can include any suitable conductive material, such as copper, tungsten, molybdenum, or ruthenium. In some embodiments, the second conductive layer 230 is aligned with the cell boundary (identified by the dotted line) between adjacent rows of cells.

[0058] As described above, cells of different rows can be distinguished from each other by having different heights along the first direction, different numbers of first conductive layers 222 above the cells, and / or semiconductor devices having semiconductor bodies of different widths. In the illustrated example, the first cell 220a can have a height h1 substantially the same as the second cell 220b, wherein each of the first cell and the second cell includes at least one semiconductor device of a nanoribbon having a first width w1. The third cell 220c can have a second height h2 substantially the same as the fourth cell 220d, wherein the second height is less than the first height. In addition, the third cell 220c and the fourth cell 220d each include only semiconductor devices of nanoribbons having a second width w2. Cells having a first height h1 (e.g., the first cell 220a and the second cell 220b) can have more first conductive layers 222 extending above them in the second direction than cells having a second height h2 (e.g., the third cell 220c and the fourth cell 220d). In the illustrated example, a cell having a first height hi includes four first metal layers 222 and a cell having a second height h2 includes three first metal layers 222. Any arrangement of rows of semiconductor bodies having different heights and / or having different widths may be used.

[0059] Figure 3A cross-sectional view of another structure including adjacent cells 302a-302c having substantially the same height but different sized semiconductor devices according to some embodiments is shown. In the illustrated example, each cell 302a-302c may be a cell of a corresponding row of cells extending along the second direction, wherein each cell has substantially the same cell height h1.

[0060] According to some embodiments, each row of cells may include any combination of semiconductor devices having a semiconductor body with a first width w1 and semiconductor devices having a semiconductor body with a second width w2. In the illustrated example, the first cell 302a includes only semiconductor devices having the first width w1, the second cell 302b includes one or more semiconductor devices having the first width w1 and one or more semiconductor devices having the second width w2, and the third cell 302c includes only semiconductor devices having the second width w2.

[0061] Figure 4 An exemplary embodiment of a chip package 400 according to an embodiment of the present disclosure is shown. It can be seen that the chip package 400 includes one or more dies 402. The one or more dies 402 may include at least one integrated circuit having a semiconductor device, such as any semiconductor device disclosed herein. In some exemplary configurations, the one or more dies 402 may include any other circuit system for interfacing with other devices formed on the die or other devices connected to the chip package 400.

[0062] It can also be seen that the chip package 400 includes a housing 404 bonded to a package substrate 406. The housing 404 can be any standard or proprietary housing and can provide (for example) electromagnetic shielding and environmental protection for the components of the chip package 400. One or more dies 402 can be conductively coupled to the package substrate 406 using connections 408, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonds, to name a few. The package substrate 406 can be any standard or proprietary package substrate, but in some cases, includes a dielectric material having conductive paths (for example, including conductive vias and lines) extending through the dielectric material between the faces of the package substrate 406, or between different locations on each face. In some embodiments, the package substrate 406 can have a thickness of less than 1 mm (for example, between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 412 can be provided at the opposite faces of the package substrate 406 to conductively contact, for example, a printed circuit board (PCB). One or more vias 410 extend through the thickness of the package substrate 406 to provide a conductive path between one or more connections 408 to one or more contacts 412. For ease of illustration, the via 410 is shown as a single straight column through the package substrate 406, but other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 406 to contact one or more intermediate locations therein). In other embodiments, the via 410 is made by multiple smaller stacked vias, or the vias are staggered at different locations throughout the package substrate 406. In the illustrated embodiment, the contacts 412 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a pin grid array arrangement). In some embodiments, solder resist is provided between the contacts 412 to inhibit shorting.

[0063] In some embodiments, molding material 414 may be disposed around one or more dies 402 included within housing 404 (e.g., as an underfill material between die 402 and package substrate 406 and as an overfill material between die 402 and housing 404). Although the dimensions and properties of molding material 414 may vary between embodiments, in some embodiments the thickness of molding material 414 is less than 1 millimeter. Exemplary materials that may be used for molding material 414 include epoxy molding materials, where appropriate. In some cases, molding material 414 is thermally conductive in addition to being electrically insulating.

[0064] Methodology

[0065] Figure 5 A flowchart is shown according to some embodiments of the present disclosure, which illustrates the design and formation of Figure 1A Method 500 of an integrated circuit structure of or 1B.

[0066] In an example, a hardware computer may be used to implement one or more operations of method 500, such as operations 502, 504, and / or 506. The hardware computer may include a hardware processor communicatively coupled to a non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium including a set of executable instructions that, when executed, are capable of performing one or more designed operations of method 500. The hardware processor may execute instructions within the computer-readable storage medium to perform operations 502, 504, and / or 506 of method 500. In an example, the hardware processor is a central processing unit (CPU), a graphics processing unit (GPU), a distributed processing system, an application-specific integrated circuit (ASIC), and / or another suitable processor. In an example, the computer-readable storage medium is a suitable storage medium, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). The computer-readable storage medium has been incorporated herein in conjunction with the computer-readable storage medium. Figure 6 Examples of hardware processors and computer-readable storage media are discussed.

[0067] Method 500 includes operation 502, wherein a cell library is accessed, the cell library having a first cell of a first height and a second cell of a second height, the second height being different from the first height. Suitable integrated circuit design tools, such as EDA (electronic design automation) tools executed in a hardware computer, can be used to form and / or access the cell library and for subsequent design processes. In some examples, each of the first cell and the second cell includes the same number of transistors (e.g., each including two, four, or six transistors). The second height of the second cell may be at least 3nm, at least 5nm, or at least 7nm smaller than the first height of the first cell. In some embodiments, the transistor device of the first cell includes one or more transistors having a first width, and the transistor device of the second cell includes one or more transistors having a second width less than the first width.

[0068] Method 500 continues with operation 504 where data regarding a circuit to be implemented using the unit is received (eg, by a hardware computer).

[0069] The method 500 continues with operation 506, wherein an integrated circuit structure having an array of cells is designed. The cells may be arranged in an array of adjacent rows and columns. Any given row may include only the first cell or only the second cell, and the rows may be arranged in any order relative to each other. It should be understood that the array may also include spaces between any two cells.

[0070] According to some embodiments, one or more first rows may include a first cell having a first height and only including semiconductor devices having a first width. As described above, the width of a semiconductor device may be measured as the width of the semiconductor body of the device along the same direction as the cell height. According to some embodiments, one or more second rows may include a first cell having a first height and one or more semiconductor devices having a first width and one or more semiconductor devices having a second width. One or more first cells of the second row may include an equal number of semiconductor devices having a first width and semiconductor devices having a second width. According to some embodiments, one or more third rows may include a second cell having a second height and only including semiconductor devices having a second width.

[0071] Method 500 then proceeds to operation 508, where an integrated circuit having an array of unit cells and an interconnect structure is formed. Figure 2A-2I The integrated circuit may be formed by any of the techniques described.

[0072] Note that for ease of description, the operations of method 500 are shown in a particular order. However, according to some embodiments, one or more of the processes may be performed in a different order or may not be performed at all (thus being optional). Many variations on the method 500 and techniques described herein will become apparent in light of this disclosure.

[0073] Exemplary Systems

[0074] Figure 6 2 shows an integrated circuit structure (e.g., Figure 1A or the integrated circuit structure shown in 1B) implemented and / or used to implement the combination Figure 5 500. As can be seen, the computing system 600 houses a motherboard 602. The motherboard 602 may include several components, including, but not limited to, a processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to the motherboard 602 or otherwise integrated therein. It will be appreciated that the motherboard 602 may be, for example, any printed circuit board, whether a motherboard, a daughterboard mounted on a motherboard, or simply a board of the system 600, etc.

[0075] Depending on its application, the computing system 600 may include one or more other components that may be physically and electrically coupled or not coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 600 may include one or more integrated circuit structures or devices formed using the techniques disclosed in accordance with the example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 606 may be part of or integrated into the processor 604).

[0076] The communication chip 606 is capable of wireless communication for transmitting data to and from the computing system 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wiring, although in some embodiments they may not. The communication chip 606 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols known as 3G, 4G, 5G and higher generations. The computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 606 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO or others.

[0077] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the integrated circuit die of the processor includes onboard circuitry implemented using one or more semiconductor devices described in various ways herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0078] The communication chip 606 may also include an integrated circuit die packaged within the semiconductor chip 606. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices described in various ways herein. It will be appreciated in view of the present disclosure that it is noted that multi-standard wireless capabilities can be integrated directly into the processor 604 (e.g., where the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). It is also noted that the processor 604 can be a chipset with such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 can be employed. Similarly, any one chip or chipset can have multiple functions integrated therein.

[0079] In various embodiments, computing system 600 may be a laptop, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques described in various ways herein.

[0080] It should be appreciated that in some embodiments, the various components of computing system 600 may be combined or integrated into a system on chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0081] Other Example Embodiments

[0082] The following examples relate to other embodiments from which numerous permutations and configurations will be apparent.

[0083] Example 1 is an integrated circuit structure, the integrated circuit structure comprising a plurality of first cells and a plurality of second cells. Each of the first cells has a corresponding height within 1 nanometer (nm) of a first height along a first direction, and includes corresponding two or more transistor devices. Each of the second cells has a corresponding height within 1nm of a second height along the first direction, wherein the second height is at least 3nm less than the first height. Each of the second cells has corresponding two or more transistor devices. The first direction is parallel to the length of the gate structure of the first cell or the second cell. The plurality of first cells are arranged into one or more first rows, and the plurality of second cells are arranged into one or more second rows, so that the one or more first rows each have the first height, and the one or more second rows each have the second height. The corresponding two or more transistor devices of at least one first cell include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second cell include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction. The second width is at least 5nm shorter than the first width.

[0084] Example 2 includes the integrated circuit structure of Example 1, wherein the first semiconductor body includes one or more first semiconductor nanoribbons and the second semiconductor body includes one or more second semiconductor nanoribbons.

[0085] Example 3 includes the integrated circuit structure of Example 2, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0086] Example 4 includes the integrated circuit structure of any of Examples 1-3, further comprising a gate cut extending longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

[0087] Example 5 includes the integrated circuit structure of Example 4, wherein the first direction is orthogonal to the second direction.

[0088] Example 6 includes the integrated circuit structure of any of Examples 1-5, wherein a third transistor device of the two or more transistor devices of the at least one first cell includes a third semiconductor body having the second width.

[0089] Example 7 includes an integrated circuit structure according to any one of Examples 1-6, wherein each of the two or more transistor devices of the at least one first unit includes a corresponding semiconductor body having a substantially same first width, and each of the two or more transistor devices of the at least one second unit includes a corresponding semiconductor body having a substantially same second width.

[0090] Example 8 includes the integrated circuit structure of any of Examples 1-7, further comprising a first plurality of conductive layers extending longitudinally along a second direction different from the first direction and over a given first cell of the plurality of first cells; and a second plurality of conductive layers extending longitudinally along the second direction and over a given second cell of the plurality of second cells. The first plurality of conductive layers includes more conductive layers than the second plurality of conductive layers.

[0091] Example 9 includes the integrated circuit structure of Example 8, wherein the first plurality of conductive layers consists of four conductive layers and the second plurality of conductive layers consists of three conductive layers.

[0092] Example 10 includes the integrated circuit structure of any of Examples 1-9, wherein the second width along the first direction is at least 10 nm shorter than the first width.

[0093] Example 11 is a printed circuit board including the integrated circuit structure according to any one of Examples 1-10.

[0094] Example 12 is an integrated circuit design system, the integrated circuit design system comprising at least one processor and a non-transitory storage medium storing instructions, the instructions, when executed by the at least one processor, causing the system to perform a method. The method includes accessing a cell library having a first cell and a second cell, receiving data about a circuit to be implemented using the first cell and the second cell, and designing one or more first rows including the first cell and one or more second rows including the second cell. Each first cell has a first height along a first direction, and each second cell has a second height along the first direction, wherein the second height is at least 3nm smaller than the first height. Each first cell and each second cell includes two or more transistor devices, and the first direction is parallel to the length of the gate structure of the first cell or the second cell. The one or more first rows each have the first height, and the one or more second rows each have the second height. The two or more transistor devices of the at least one first cell include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the two or more transistor devices of the at least one second cell include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, and the second width is at least 5nm shorter than the first width.

[0095] Example 13 includes the integrated circuit design system of Example 12, wherein the designing includes designing a gate cut extending longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

[0096] Example 14 includes the integrated circuit design system of Example 13, wherein the first direction is orthogonal to the second direction.

[0097] Example 15 includes the integrated circuit design system of any of Examples 12-14, wherein a third transistor device of the two or more transistor devices of the at least one first cell includes a third semiconductor body having the second width.

[0098] Example 16 includes an integrated circuit design system according to any one of Examples 12-15, wherein each of the two or more transistor devices of the at least one first unit includes a corresponding semiconductor body having a substantially same first width, and each of the two or more transistor devices of the at least one second unit includes a corresponding semiconductor body having a substantially same second width.

[0099] Example 17 includes the integrated circuit design system of any one of Examples 12-16, wherein the method further comprises: designing a first plurality of conductive layers above a given first cell in the first cells, and designing a second plurality of conductive layers above a given second cell in the second cells. The first plurality of conductive layers extend longitudinally along a second direction different from the first direction, and the second plurality of conductive layers extend longitudinally along the second direction.

[0100] Example 18 includes the integrated circuit design system of Example 17, wherein the first plurality of conductive layers consists of four conductive layers and the second plurality of conductive layers consists of three conductive layers.

[0101] Example 19 includes the integrated circuit design system of any of Examples 12-18, wherein the second width along the first direction is at least 10 nm shorter than the first width.

[0102] Example 20 is an integrated circuit structure comprising a plurality of first units and a plurality of second units. Each first unit has a corresponding height along a first direction, and each first unit has corresponding two or more transistor devices. Each second unit has a corresponding height substantially the same along the first direction, and each second unit has corresponding two or more transistor devices. The first direction is parallel to the length of the gate structure of the first unit or the second unit. The plurality of first units are arranged in one or more first rows, and the plurality of second units are arranged in one or more second rows. The corresponding two or more transistor devices of at least one first unit include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second unit include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, and the second width is at least 5nm shorter than the first width.

[0103] Example 21 includes the integrated circuit structure of Example 20, wherein the first semiconductor body includes one or more first semiconductor nanoribbons and the second semiconductor body includes one or more second semiconductor nanoribbons.

[0104] Example 22 includes the integrated circuit structure of Example 21, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0105] Example 23 includes the integrated circuit structure of any of Examples 20-22, further comprising a gate cut extending longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

[0106] Example 24 includes the integrated circuit structure of Example 23, wherein the first direction is orthogonal to the second direction.

[0107] Example 25 includes the integrated circuit structure of any of Examples 20-24, wherein a third transistor device of the two or more transistor devices of the at least one first cell includes a third semiconductor body having the second width.

[0108] Example 26 includes an integrated circuit structure according to any one of Examples 20-24, wherein each of the two or more transistor devices of the at least one first unit includes a corresponding semiconductor body having a substantially same first width, and each of the two or more transistor devices of the at least one second unit includes a corresponding semiconductor body having a substantially same second width.

[0109] Example 27 includes the integrated circuit structure of Example 26, further comprising a plurality of third cells, each of the third cells having a corresponding height substantially the same along the first direction. Each third cell has corresponding two or more transistor devices, and the plurality of third cells are arranged in one or more third rows. At least one transistor device of the two or more transistor devices of at least one third cell includes a corresponding semiconductor body having a substantially same first width, and at least one transistor device of the two or more transistor devices of the at least one third cell includes a corresponding semiconductor body having a substantially same second width.

[0110] Example 28 includes the integrated circuit structure of any of Examples 20-27, wherein the second width along the first direction is at least 10 nm shorter than the first width.

[0111] Example 29 is a printed circuit board including the integrated circuit structure according to any of Examples 20-28.

[0112] The above description of the embodiments of the present disclosure has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed. Many modifications and variations are possible according to the present disclosure. It is not intended that the scope of the present disclosure be limited by this detailed description, but rather the scope of the present disclosure is defined by the appended claims.

Claims

1. An integrated circuit structure, comprising: a plurality of first cells, each first cell having a respective height within 1 nanometer (nm) of a first height along a first direction, wherein each first cell has respective two or more transistor devices; and a plurality of second cells, each second cell having a corresponding height along the first direction within 1 nm of a second height, the second height being at least 3 nm less than the first height, wherein each second cell has corresponding two or more transistor devices; Wherein, the first direction is parallel to the length of the gate structure of the first unit or the second unit; wherein the plurality of first units are arranged into one or more first rows and the plurality of second units are arranged into one or more second rows, such that the one or more first rows each have the first height and the one or more second rows each have the second height; and wherein the corresponding two or more transistor devices of at least one first unit include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second unit include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, the second width being at least 5 nm shorter than the first width.

2. The integrated circuit structure according to claim 1, wherein: The first semiconductor body includes one or more first semiconductor nanoribbons, and the second semiconductor body includes one or more second semiconductor nanoribbons.

3. The integrated circuit structure according to claim 2, wherein: The one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons include germanium, silicon, or any combination thereof. 4 . The integrated circuit structure according to claim 1 , further comprising a gate cutout extending longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

5. The integrated circuit structure according to claim 4, wherein: The first direction is orthogonal to the second direction.

6. The integrated circuit structure according to claim 1, wherein: A third transistor device of the two or more transistor devices of the at least one first cell includes a third semiconductor body having the second width.

7. The integrated circuit structure according to claim 1, wherein: Each of the two or more transistor devices of the at least one first cell includes a respective semiconductor body having substantially the same first width, and each of the two or more transistor devices of the at least one second cell includes a respective semiconductor body having substantially the same second width.

8. The integrated circuit structure according to any one of claims 1 to 7, further comprising: a first plurality of conductive layers extending longitudinally along a second direction different from the first direction and over a given first cell of the plurality of first cells; as well as A second plurality of conductive layers extends longitudinally along the second direction and over a given second cell of the plurality of second cells, wherein the first plurality of conductive layers includes more conductive layers than the second plurality of conductive layers.

9. The integrated circuit structure according to claim 8, wherein: The first plurality of conductive layers consists of four conductive layers, and the second plurality of conductive layers consists of three conductive layers.

10. The integrated circuit structure according to any one of claims 1 to 7, wherein: The second width along the first direction is at least 10 nm shorter than the first width.

11. A printed circuit board comprising the integrated circuit structure according to any one of claims 1-7.

12. An integrated circuit design system, comprising: at least one processor; as well as a non-transitory storage medium storing instructions that, when executed by the at least one processor, cause the system to perform a method comprising: accessing a cell library having first cells and second cells, wherein each first cell has a first height along a first direction and each second cell has a second height along the first direction, the second height being at least 3 nm less than the first height, wherein each first cell and each second cell comprises respective two or more transistor devices, and wherein the first direction is parallel to a length of a gate structure of the first cell or the second cell, receiving data about a circuit to be implemented using the first unit and the second unit, and One or more first rows including the first unit and one or more second rows including the second unit are designed so that the one or more first rows all have the first height and the one or more second rows all have the second height, wherein the corresponding two or more transistor devices of at least one first unit include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second unit include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, and the second width is at least 5nm shorter than the first width.

13. The integrated circuit design system according to claim 12, wherein: The designing includes designing a gate cut that extends longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

14. The integrated circuit design system according to claim 12, wherein: Each of the two or more transistor devices of the at least one first cell includes a respective semiconductor body having substantially the same first width, and each of the two or more transistor devices of the at least one second cell includes a respective semiconductor body having substantially the same second width.

15. The integrated circuit design system according to any one of claims 12 to 14, wherein: The method further comprises: designing a first plurality of conductive layers over a given one of the first cells, the first plurality of conductive layers extending longitudinally in a second direction different from the first direction; and A second plurality of conductive layers is designed over a given one of the second cells, the second plurality of conductive layers extending longitudinally along the second direction.

16. An integrated circuit structure comprising: a plurality of first cells, each first cell having a respective height along a first direction, wherein each first cell has respective two or more transistor devices; and a plurality of second cells, each second cell having a substantially same respective height along the first direction, wherein each second cell has respective two or more transistor devices; Wherein, the first direction is parallel to the length of the gate structure of the first unit or the second unit; wherein the plurality of first units are arranged into one or more first rows, and the plurality of second units are arranged into one or more second rows; and wherein the corresponding two or more transistor devices of at least one first unit include a first transistor device having a first semiconductor body, the first semiconductor body having a first width along the first direction, and the corresponding two or more transistor devices of at least one second unit include a second transistor device having a second semiconductor body, the second semiconductor body having a second width along the first direction, the second width being at least 5 nm shorter than the first width.

17. The integrated circuit structure according to claim 16, wherein: The first semiconductor body includes one or more first semiconductor nanoribbons, and the second semiconductor body includes one or more second semiconductor nanoribbons.

18. The integrated circuit structure according to claim 17, wherein: The one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons include germanium, silicon, or any combination thereof.

19. The integrated circuit structure of claim 16, further comprising a gate cutout extending longitudinally along a second direction different from the first direction and along a boundary between adjacent rows of first cells and / or second cells.

20. The integrated circuit structure of claim 19, wherein: The first direction is orthogonal to the second direction.

21. The integrated circuit structure of claim 16, wherein: A third transistor device of the two or more transistor devices of the at least one first cell includes a third semiconductor body having the second width.

22. The integrated circuit structure according to any one of claims 16 to 21, wherein: Each of the two or more transistor devices of the at least one first cell includes a respective semiconductor body having substantially the same first width, and each of the two or more transistor devices of the at least one second cell includes a respective semiconductor body having substantially the same second width.

23. The integrated circuit structure of claim 22, further comprising a plurality of third cells, each of the third cells having substantially the same respective height along the first direction, wherein: Each third unit has corresponding two or more transistor devices, wherein the plurality of third units are arranged into one or more third rows, and wherein at least one transistor device of the two or more transistor devices of at least one third unit includes a corresponding semiconductor body having substantially the same first width, and at least one transistor device of the two or more transistor devices of the at least one third unit includes a corresponding semiconductor body having substantially the same second width.

24. The integrated circuit structure according to any one of claims 16 to 21, wherein: The second width along the first direction is at least 10 nm shorter than the first width.

25. A printed circuit board comprising the integrated circuit structure according to any one of claims 16-21.

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