Array substrate, display panel and display device

Abstract

At least one embodiment of the invention provides an array substrate, a display panel and a display device.The array substrate comprises a semiconductor layer and a shading layer which are arranged on a substrate in a stacked mode, the semiconductor layer comprises a first branch part and a second branch part which are oppositely arranged, and a connecting part connecting the first branch part and the second branch part; the first branch part comprises a first channel region, the second branch part comprises a second channel region, one side, far away from the substrate, of the first branch part is provided with a first via hole structure, and the orthographic projection of the first via hole structure on the substrate is located in the orthographic projection of the end part, far away from the connecting part, of the first branch part on the substrate; according to the array substrate, the orthographic projection of the shading layer on the substrate at least covers the orthographic projection of the first channel region and the orthographic projection of the first via hole structure on the substrate, the leakage current phenomenon can be reduced by adjusting the design of the shading layer, the retention capacity of pixel capacitance is improved, the problem of flicker under low frequency is solved, and the aperture opening ratio of the display panel can be guaranteed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a display panel, and a display device. Background Art

[0002] Low-Temperature Polycrystalline Silicon ThinFilm Transistor (LTPS TFT) technology has become increasingly mature. Compared with amorphous silicon thin film transistors and metal oxide thin film transistors, low-temperature polycrystalline silicon thin film transistors have higher carrier mobility, which can enhance the driving capability of display devices using the low-temperature polycrystalline silicon thin film transistors to reduce power consumption. The current structure of low-temperature polycrystalline silicon thin film transistors is a top gate structure. When low-temperature polycrystalline silicon thin film transistors are used in liquid crystal display panels, a light shielding layer needs to be designed to completely cover the channel area, otherwise the channel area of ​​the low-temperature polycrystalline silicon will leak light. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an array substrate, a display panel and a display device. In the array substrate, the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projections of the first channel region and the first via structure on the base substrate. The array substrate can reduce the leakage current of the subsequently formed display panel by adjusting the design of the light-shielding layer to enhance the retention capacity of the pixel capacitor, thereby improving the problem of flickering at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.

[0004] At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of an end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

[0005] For example, in the array substrate provided in at least one embodiment of the present disclosure, the side of the second branch portion away from the base substrate has a second via structure, and the orthographic projection of the second via structure on the base substrate is located within the orthographic projection of the end of the second branch portion away from the connecting portion on the base substrate, and the minimum distance between the second via structure and the connecting portion is greater than or equal to the minimum distance between the first via structure and the connecting portion.

[0006] For example, in the array substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the light shielding layer on the base substrate.

[0007] For example, in the array substrate provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the base substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

[0008] For example, in the array substrate provided in at least one embodiment of the present disclosure, the first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the light shading layer covers at least part of the opening area.

[0009] For example, the array substrate provided by at least one embodiment of the present disclosure also includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

[0010] For example, in the array substrate provided in at least one embodiment of the present disclosure, there is a gap between the light shielding layer and the connecting portion in the first direction.

[0011] For example, in the array substrate provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the base substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

[0012] For example, in the array substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light-shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light-shielding portion on the base substrate.

[0013] At least one embodiment of the present disclosure also provides a display panel, which includes a first substrate and a second substrate arranged opposite to each other, wherein the first substrate includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate; the second substrate includes a black matrix; the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate, and at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

[0014] For example, in the display panel provided in at least one embodiment of the present disclosure, the end of the second branch portion away from the connecting portion corresponds to a second via structure, and the second via structure is farther away from the connecting portion than the first via structure.

[0015] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the light-shielding layer includes a conductive metal, the orthographic projection of the black matrix on the base substrate covers the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light-shielding layer on the base substrate.

[0016] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

[0017] For example, in the display panel provided in at least one embodiment of the present disclosure, the first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the light-shielding layer covers at least part of the opening area.

[0018] For example, in the display panel provided by at least one embodiment of the present disclosure, the first substrate also includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

[0019] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the first gate on the base substrate is within the orthographic projection of the black matrix on the base substrate, and the orthographic projection of the second gate on the base substrate is within the orthographic projection of the black matrix on the base substrate.

[0020] For example, in the display panel provided in at least one embodiment of the present disclosure, there is a gap between the light shielding layer and the connecting portion in the first direction.

[0021] For example, in the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion close to the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion close to the connecting portion on the base substrate.

[0022] For example, in the display panel provided by at least one embodiment of the present disclosure, the orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion farthest from the connecting portion on the base substrate and the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion farthest from the connecting portion on the base substrate overlap.

[0023] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the edge of the light-shielding layer away from the connecting portion on the base substrate includes a first part located on the side of the first via structure away from the connecting portion and a second part located on the side of the second via structure away from the connecting portion, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the edge of the black matrix farthest from the second via structure on the base substrate.

[0024] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

[0025] For example, in the display panel provided in at least one embodiment of the present disclosure, the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light-shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light-shielding portion on the base substrate.

[0026] For example, in the display panel provided in at least one embodiment of the present disclosure, the end of the second branch portion away from the connecting portion corresponds to a second via structure, and the maximum distance between the second via structure and the connecting portion is equal to the maximum distance between the first via structure and the connecting portion.

[0027] For example, in the display panel provided in at least one embodiment of the present disclosure, the material of the light-shielding layer includes a non-conductive light-shielding material, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the light-shielding layer on the base substrate both cover the orthographic projection of the second via structure on the base substrate.

[0028] For example, in the display panel provided in at least one embodiment of the present disclosure, a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure or a structure spaced apart from each other.

[0029] At least one embodiment of the present disclosure further provides a display device, which includes the array substrate described in any of the above embodiments, or the display panel described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0031] Figure 1 is a schematic diagram of a planar structure of a thin film transistor;

[0032] Figure 2 is a schematic diagram of a cross-sectional structure of an array substrate;

[0033] Figure 3 for Figure 1 A schematic diagram of a cross-sectional structure of a thin film transistor in FIG.

[0034] Figure 4 A schematic diagram of a planar structure of an array substrate and a black matrix provided in at least one embodiment of the present disclosure

[0035] Figure 5 A schematic diagram of a stacked structure of an array substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 6 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0037] Figure 7 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0038] Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure of the array substrate;

[0039] Fig. 9 A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure;

[0040] Fig.10 for Fig. 9 A schematic diagram of the cross-sectional structure of the array substrate shown;

[0041] Fig.11 A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure;

[0042] Fig.12 for Fig.11 A schematic diagram of the cross-sectional structure of the array substrate shown;

[0043] Fig.13 A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure;

[0044] Fig.14 for Fig.13 A schematic diagram of the cross-sectional structure of the array substrate shown;

[0045] Fig.15 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0046] Fig.16 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0047] Fig.17A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure;

[0048] Fig.18 A schematic diagram of a cross-sectional structure of a display panel provided in at least one embodiment of the present disclosure;

[0049] Fig.19 A schematic diagram of a planar structure of a display panel provided by at least one embodiment of the present disclosure;

[0050] Fig. 20 A schematic cross-sectional structure diagram of a first substrate provided in at least one embodiment of the present disclosure;

[0051] Fig.21 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0052] Fig. 22 for Fig.21 A schematic cross-sectional structure diagram of the first substrate;

[0053] Fig.23 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0054] Fig.24 for Fig.23 A schematic cross-sectional structure diagram of the first substrate;

[0055] Fig.25 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0056] Fig.26 for Fig.25 A schematic cross-sectional structure diagram of the first substrate;

[0057] Fig. 27 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0058] Fig.28 for Fig. 27 A schematic cross-sectional structure diagram of the first substrate;

[0059] Fig.29 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0060] Fig.30 for Fig.29 A schematic cross-sectional structure diagram of the first substrate shown;

[0061] Fig.31 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0062] Fig.32 for Fig.31 A schematic cross-sectional structure diagram of the first substrate shown;

[0063] Fig.33 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure;

[0064] Fig.34 A schematic diagram of a stacked structure of another display panel provided in at least one embodiment of the present disclosure;

[0065] Fig.35 A block diagram of a display panel provided for at least one embodiment of the present disclosure; and

[0066] Fig.36 A block diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0068] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0069] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present invention include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following text of the embodiments of the present invention, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0070] At present, mobile devices such as mobile phones, tablet computers and laptops have higher and higher requirements for low power consumption. Reducing the refresh rate of display panels has become the main method to reduce the power consumption of display panels. When the display panel has a low refresh rate, the retention time of the pixel capacitor is prolonged. When the leakage current of the thin film transistor (abbreviated as I off ) is large, the retention capacity of the pixel capacitor decreases, and the voltage difference between the pixel electrode and the common electrode decreases, which will cause the brightness of the display panel to decay, and then lead to the aggravation of the pixel flicker problem. At the same time, optical effects such as afterimages will also deteriorate due to the aggravation of the leakage current problem.

[0071] For example, Figure 1 is a schematic diagram of a planar structure of a thin film transistor. Figure 2 is a schematic diagram of a cross-sectional structure of an array substrate, combined with Figure 1 and Figure 2 An interlayer insulating layer 13 is provided between the pixel electrode 11 and the first source-drain electrode 12 of the thin film transistor. A first via hole structure 14 is provided in the interlayer insulating layer 13. In order to prevent light leakage from the first via hole structure 14, a black matrix 15 ( Figure 2The black matrix 15 (not shown) is configured to shield the first via structure 14, so that in the first direction X, at the right side of the black matrix 15 corresponding to the first via structure 14, the length L1 of the shielding portion of the black matrix 15 on the upper side of the channel region 16 (the upper side of the area covered by the gate line 17) is greater than the length L2 of the shielding portion on the lower side of the channel region 16 (the lower side of the area covered by the gate line 17), so the shielding range of the black matrix 15 on both sides of the channel region 16 in the first direction X is inconsistent, and the shielding area of ​​the black matrix 15 on the upper side of the channel region 16 is greater than the shielding area on the lower side of the channel region 16. Backlight is incident from the side where the low-temperature polycrystalline silicon thin film transistor is located. Under certain lighting conditions, photogenerated carriers will be excited in the channel region 16, resulting in a leakage current (I off ) increases, that is, the light intensity and the leakage current I off is positively correlated. A light shielding layer 18 is provided on the side of the channel region 16 close to the substrate 10. The light shielding layer 18 can reduce the light received by the channel region 16, thereby reducing the leakage current under light conditions. A first insulating layer 22 is provided between the light shielding layer 18 and the channel region 16, and a passivation layer 23 is provided between the first insulating layer 22 and the first source-drain electrode 12. The second source-drain electrode 21 and the first source-drain electrode 12 are arranged opposite to each other, and a gate and a gate insulating layer 20 are formed in the gap between the second source-drain electrode 21 and the first source-drain electrode 12. The display panel displays by line scanning. The pixel is charged for only a few microseconds in one frame, and the rest of the time is in the voltage holding stage. Under ideal conditions, the pixel voltage always maintains the set voltage, but due to the presence of leakage current in the thin film transistor, there will be voltage attenuation in the voltage holding stage. The degree of voltage attenuation is related to the leakage current I of the thin film transistor. off The voltage holding time is positively correlated, and the formula for the leakage current voltage drop is △V=I off *T hold / Cst. When the display panel is performing low-frequency display, the frame time is lengthened (when the refresh frequency is 60Hz, the frame time is 16.7ms; when the refresh frequency is 15Hz, the frame time is 66.7ms), the pixel voltage holding time is lengthened, and under the premise that the leakage current speed is the same, the voltage attenuation caused by the leakage current at a low refresh frequency will increase, and the brightness attenuation of the pixel will also increase, thereby aggravating the flicker problem.

[0072] For example, Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of a thin film transistor in FIG. Figure 3 As shown, two spaced-apart light shielding layers 18 shield the two channel regions 16 respectively, each light shielding layer 18 shields the entire corresponding channel region 16, and two adjacent light shielding layers 18 are symmetrically designed. Figure 1As shown, in one example, in the first direction X, the blocking length L3 of the light-shielding layer 18 on the upper side of the gate line 17 is 2.05 microns, and the blocking length L4 on the lower side of the gate line 17 is also 2.05 microns. In this way, a portion of the light-shielding layer 18 on the lower side of the gate line 17 has exceeded the blocking range of the black matrix 15 and entered the opening area, which will cause the aperture ratio of the pixels of the subsequently formed display panel to be reduced. For example, compared with the case where the light-shielding layer 18 does not enter the opening area, the aperture ratio of the pixel will decrease by 0.8%. The light shielding layer 18 also shields the two gates of the double-gate thin film transistor separately, so that the light shielding layer 18 does not shield the spacing area between the two channel regions 16. For each channel region 16, the distance L5 of the spacing area outside the channel region 16 shielded by the light shielding layer 18 in the second direction Y perpendicular to the first direction X is small. For example, in one example, the distance L5 is only 1.5 microns. The length L3 of the spacing area shielded by the light shielding layer 18 on the upper side of the gate line 17 in the first direction X is 2.05 microns. The length L3 is also small, which leads to a leakage current (I off ) is large, which has a greater impact on light effects such as flickering at low refresh rates.

[0073] It should be noted that in Figure 3 In the cross-sectional structure shown, the third direction Z is perpendicular to the plane where the first direction X and the second direction Y are located, that is, the third direction Z is a direction perpendicular to the main surface of the base substrate 10 .

[0074] The inventors of the present disclosure noticed that the channel regions corresponding to the two gates of the thin film transistor can be shielded by a whole shielding layer or a shielding layer with a larger area and spaced apart, and the shielding area of ​​the shielding layer on the side of the first source and drain electrode connected to the pixel electrode can be increased, that is, the first via structure in the above-mentioned interlayer insulating layer is shielded by a shielding layer, which can reduce the leakage current phenomenon of the display panel formed subsequently.

[0075] At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of an end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate, and the array substrate can reduce the leakage current of a display panel formed subsequently by adjusting the design of the light-shielding layer to enhance the retention capacity of the pixel capacitor, thereby improving the flickering problem at low frequency, and also ensuring the aperture ratio of the display panel formed subsequently.

[0076] For example, Figure 4 A schematic diagram of a planar structure of an array substrate and a black matrix provided in at least one embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the array substrate 21 includes a base substrate 211 and a semiconductor layer 212 and a light shielding layer 213 stacked on the base substrate 211, the semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122, the first branch portion 2121 includes a first channel region 2124, the second branch portion 2122 includes a second channel region 2125, and a first via structure 2126 is provided on a side of the first branch portion 2121 away from the base substrate 211, and the first via structure The orthographic projection of 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211; the orthographic projection of the light-shielding layer 213 on the base substrate 211 at least covers the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211. By adjusting the design of the light-shielding layer 213, the array substrate 21 can reduce the leakage current of the subsequently formed display panel to enhance the retention capacity of the pixel capacitor, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the subsequently formed display panel.

[0077] It should be noted that the semiconductor layer is in a state during the process of manufacturing the array substrate, and there are other subsequent processes to conductorize part of the semiconductor area, that is, after forming the gate and gate line mentioned later, there is a heavy doping step to make the part of the semiconductor layer outside the area covered by the gate into a conductor, so that the gate can block the channel area. Therefore, the channel area corresponding to the semiconductor layer is located below the gate line, and the conductorized part corresponds to the first source-drain electrode and the second source-drain electrode.

[0078] For example, Figure 4 As shown, two channel regions, a first channel region 2124 and a second channel region 2125, are shown in the array substrate 21. The end portion (first source-drain electrode) of the first branch portion 2121 corresponding to the first via structure 2126 is electrically connected to the pixel electrode 222 through the first via structure 2126, and the end portion (second source-drain electrode) of the second branch portion 2122 is connected to the data line 221. The data line 221 and the gate line 2128 intersect to define a pixel region, and the pixel electrode 222 is disposed in the pixel region.

[0079] It should be noted that in order to reflect the positional relationship between the light shielding layer and the semiconductor layer on the array substrate and the black matrix, Figure 4 The black matrix 223 is also shown in the figure, and the orthographic projection of the black matrix 223 on the base substrate 211 covers the orthographic projection of the data line 221, the gate line 2128, the light shielding layer 213, the first branch portion 2121, the second branch portion 2122 and the lower right corner of the connecting portion 2123 on the base substrate 211, but the black matrix 223 is not mentioned when describing the array substrate.

[0080] For example, Figure 4 As shown, the array substrate 21 also includes a touch signal line 224, which includes a first part 224a and a second part 224b arranged parallel to the data line 221, and the orthographic projection of the black matrix 223 on the base substrate 211 also covers the orthographic projection of the touch signal line 224 on the base substrate 211.

[0081] For example, Figure 5 A schematic diagram of a stacked structure of an array substrate provided in at least one embodiment of the present disclosure, such as Figure 5As shown, the array substrate 21 includes a base substrate 211 and a semiconductor layer 212 and a light shielding layer 213 stacked on the base substrate 211, the semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122, the first branch portion 2121 includes a first channel region 2124, the second branch portion 2122 includes a second channel region 2125, and a first via structure 2126 is provided on a side of the first branch portion 2121 away from the base substrate 211, and the first via structure The orthographic projection of 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211; the orthographic projection of the light-shielding layer 213 on the base substrate 211 at least covers the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211. By adjusting the design of the light-shielding layer 213, the array substrate 21 can reduce the leakage current of the subsequently formed display panel to enhance the retention capacity of the pixel capacitor, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the subsequently formed display panel.

[0082] For example, Figure 5 As shown, the side of the second branch portion 2122 away from the base substrate 211 has a second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211, and the minimum distance between the second via structure 2127 and the connecting portion 2123 is greater than the minimum distance between the first via structure 2126 and the connecting portion 2123, that is, the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126. In other examples, the minimum distance between the second via structure 2127 and the connecting portion 2123 may be equal to the minimum distance between the first via structure 2126 and the connecting portion 2123.

[0083] For example, Figure 5 As shown, the orthographic projection of the second via structure 2127 on the base substrate 211 is outside the orthographic projection of the light shielding layer 213 on the base substrate 211 , that is, the light shielding layer 213 does not cover the second via structure 2127 .

[0084] For instance, in one example, a plurality of thin film transistors are arranged on the base substrate 211, portions of the light shading layer 213 corresponding to different thin film transistors are spaced apart from each other, and portions of the light shading layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are an integral structure, that is, in addition to covering the first channel region 2124 and the second channel region 2125, the light shading layer 213 also covers the portion between the first channel region 2124 and the second channel region 2125.

[0085] For example, Figure 5 As shown, the first branch portion 2121 and the second branch portion 2122 both extend along the first direction X, the connecting portion 2123 extends along the second direction Y intersecting the first direction X, the first branch portion 2121, the second branch portion 2122 and the connecting portion 2123 are arranged to form an opening area, and the shading layer 213 covers at least a portion of the opening area.

[0086] For example, in one example, the first direction X and the second direction Y are perpendicular.

[0087] For example, Figure 5 As shown, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in a second direction Y, and the orthographic projection of the gate line 2128 on the base substrate 211 and the orthographic projection of the first channel region 2124 on the base substrate 211 and the orthographic projection of the second channel region 2125 on the base substrate 211 all overlap.

[0088] For example, Figure 5 As shown, there is a gap between the light shielding layer 213 and the connecting portion 2123 in the first direction X, that is, the lower edge of the light shielding layer 213 is located above the upper edge of the connecting portion 2123 .

[0089] For example, Figure 6 A schematic diagram of a stacked structure of another array substrate provided for at least one embodiment of the present disclosure. In one example, a plurality of thin film transistors are arranged on the base substrate 211, and portions of the light shielding layer 213 corresponding to different thin film transistors are spaced apart from each other. Portions of the light shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are respectively the first sub-light shielding portion 213a and the second sub-light shielding portion 213b, and the first sub-light shielding portion 213a and the second sub-light shielding portion 213b are spaced apart from each other. Figure 6 It can be seen from the figure that the distance between the side of the second sub-light-shielding portion 213b farthest from the connecting portion 2123 and the connecting portion 2123 is greater than the distance between the side of the first sub-light-shielding portion 213a farthest from the connecting portion 2123 and the connecting portion 2123.

[0090] For example, Figure 6 As shown, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126. Figure 6 In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0091] For example, Figure 6 As shown, the first sub-light shielding portion 213a covers the orthographic projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light shielding portion 213b covers the orthographic projection of the second channel region 2125 on the base substrate 211, but does not cover the orthographic projection of the second via structure 2127 on the base substrate 211. The array substrate 21 can reduce leakage current and improve the retention capacity of pixel capacitance by designing the first sub-light shielding portion 213a to cover the orthographic projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and designing the second sub-light shielding portion 213b to cover the orthographic projection of the second channel region 2125 on the base substrate 211, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0092] For example, Figure 6 As shown, the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the first sub-light shielding portion 213a on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located outside the orthographic projection of the second sub-light shielding portion 213b on the base substrate 211.

[0093] For example, Figure 7 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure, Figure 8 for Figure 7 The schematic diagram of the cross-sectional structure of the array substrate in FIG. Figure 7 and Figure 8The array substrate 21 includes a base substrate 211 and a light shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to a first via structure 2126, that is, the first branch portion 2121 has a first via structure 2126 on one side away from the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127 on the base substrate 211. The array substrate 21 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.

[0094] For example, combined with Figure 7 In the first direction X, the second via structure 2127 is further away from the connecting portion 2123 than the first via structure 2126. Figure 7 In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0095] For example, combined with Figure 7 and Figure 8The array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211. The first metal layer 214 includes a gate line 2128 extending in the second direction Y. The gate line 2128 is in a long strip shape. The gate line 2128 includes a first gate 2128a and a second gate 2128b. The orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0096] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0097] For example, Figure 8 As shown, a first insulating layer 219 is disposed between the light shielding layer 213 and the semiconductor layer 212 , a gate insulating layer 217 is disposed between the first insulating layer 219 and the first metal layer 214 , and an interlayer insulating layer 218 is disposed on a side of the first metal layer 214 away from the base substrate 211 .

[0098] For example, Figure 7 and Figure 8 As shown, the orthographic projection of the side of the light shielding layer 213 away from the connection portion 2123 on the base substrate 211 includes a first portion 213c located on the side of the first via structure 2124 away from the connection portion 2123 and a second portion 213d located on the side of the second via structure 2127 away from the connection portion 2123, and the upper edge of the first portion 213c and the upper edge of the second portion 213d are not on the same straight line, that is, the plane shape of the light shielding layer 213 is stepped. In the first direction X, the distance between the first portion 213c and the connection portion 2123 is greater than the distance between the second portion 213d and the connection portion 2123. The orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the light shielding layer 213 on the base substrate 211. It should be noted that, in this example, the material of the light-shielding layer 213 is a non-conductive light-shielding material. When the material of the light-shielding layer 213 is a non-conductive light-shielding material, even if the interlayer insulating layer 218 is etched to over-etch the light-shielding layer 213, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.

[0099] For example, Fig. 9A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure is shown. Fig.10 for Fig. 9 The schematic diagram of the cross-sectional structure of the array substrate shown in FIG. Fig. 9 and Fig.10 The array substrate 21 includes a base substrate 211 and a light shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to a first via structure 2126, that is, the first branch portion 2121 has a first via structure 2126 on one side away from the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connecting portion 2123 on the base substrate 211. The orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127 on the base substrate 211. The array substrate 21 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125, the first via structure 2126 and the second via structure 2127, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.

[0100] For example, combined with Fig. 9 , the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2124 and the connecting portion 2123, that is, Fig. 9In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2124 corresponding to the end of the first branch portion 2121 are flush.

[0101] For example, combined with Fig. 9 and Fig.10 The array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211. The first metal layer 214 includes a gate line 2128 extending in the second direction Y. The gate line 2128 is in a long strip shape. The gate line 2128 includes a first gate 2128a and a second gate 2128b. The orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211. For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0102] For example, Fig.10 As shown, a first insulating layer 219 is disposed between the light shielding layer 213 and the semiconductor layer 212 , a gate insulating layer 217 is disposed between the first insulating layer 219 and the first metal layer 214 , and an interlayer insulating layer 218 is disposed on a side of the first metal layer 214 away from the base substrate 211 .

[0103] For example, combined with Fig. 9 and Fig.10 In one example, the material of the light shielding layer 213 includes a non-conductive light shielding material, and the orthographic projections of the first via structure 2126 and the second via structure 2127 on the base substrate 211 are both located within the orthographic projection of the light shielding layer 213 on the base substrate 211 .

[0104] For example, combined with Fig. 9 and Fig.10The light-shielding layer 213 is an integral structure, and the orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projection of the first channel region 2124 on the base substrate 211, the orthographic projection of the second channel region 2125 on the base substrate 211, the orthographic projection of the first via structure 2126 on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211, as well as covers the gap between the first channel region 2124 and the second channel region 2125, and covers the gap between the first via structure 2126 and the second via structure 2127.

[0105] For example, Fig.11 A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure is shown. Fig.12 for Fig.11 The schematic diagram of the cross-sectional structure of the array substrate shown in FIG. Fig.11 and Fig.12The array substrate 21 includes a base substrate 211 and a light shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122. The first branch portion 2121 includes a first channel region 2124, and the second branch portion 2122 includes a second channel region 2125. The end of the first branch portion 2121 away from the connecting portion 2123 corresponds to a first via structure 2126, that is, the first branch portion 2121 has a first via structure 2126 on one side away from the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The portions of the light shielding layer 213 corresponding to different thin film transistors are spaced apart from each other, and the portions of the light shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are respectively the first sub-light shielding portion 213a and the second sub-light shielding portion 213b, and the first sub-light shielding portion 213a and the second sub-light shielding portion 213b are spaced apart from each other. The first sub-light shielding portion 213a covers the orthographic projections of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light shielding portion 213b covers the orthographic projections of the second channel region 2125 and the second via structure 2127 on the base substrate 211. The array substrate 21 is designed such that the first sub-light-shielding portion 213a is designed such that the orthographic projection of the first sub-light-shielding portion 213a on the base substrate 211 covers the orthographic projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, and the second sub-light-shielding portion 213b is designed such that the orthographic projection of the second sub-light-shielding portion 213b on the base substrate 211 covers the orthographic projection of the second channel region 2125 and the second via structure 2127 on the base substrate 211. This design can reduce leakage current and enhance the retention capacity of pixel capacitance, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel to be subsequently formed.

[0106] For example, combined with Fig.11 , the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126, that is, Fig.11In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X. The length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are flush.

[0107] For example, combined with Fig.11 and Fig.12 The array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211. The first metal layer 214 includes a gate line 2128 extending in the second direction Y. The gate line 2128 is in a long strip shape. The gate line 2128 includes a first gate 2128a and a second gate 2128b. The orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0108] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0109] For example, Fig.12 As shown, a first insulating layer 219 is disposed between the light shielding layer 213 and the semiconductor layer 212 , a gate insulating layer 217 is disposed between the first insulating layer 219 and the first metal layer 214 , and an interlayer insulating layer 218 is disposed on a side of the first metal layer 214 away from the base substrate 211 .

[0110] For example, Fig.11 and Fig.12As shown, the orthographic projection of the side of the first sub-light shielding portion 213a away from the connecting portion 2123 on the base substrate 211 includes a first portion 213c located on the side of the first via structure 2126 away from the connecting portion 2123, and the orthographic projection of the side of the second sub-light shielding portion 213b away from the connecting portion 2123 on the base substrate 211 includes a second portion 213d located on the side of the second via structure 2127 away from the connecting portion 2123, that is, the plane shapes of the first sub-light shielding portion 213a and the second sub-light shielding portion 213b are both long strips, and the length of the first sub-light shielding portion 213a is equal to the length of the second sub-light shielding portion 213b. In the first direction X, the distance between the first portion 213c and the connecting portion 2123 is equal to the distance between the second portion 213d and the connecting portion 2123. The orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the light shielding layer 213 on the base substrate 211. It should be noted that, in this example, the material of the light-shielding layer 213 is a non-conductive light-shielding material. Even if the interlayer insulating layer 218 is etched to over-etch the light-shielding layer 213, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.

[0111] For example, a plurality of thin film transistors are arranged on the array substrate 21, and portions of the light shielding layer 213 corresponding to different thin film transistors are spaced apart from each other. Fig.11 and Fig.12 The parts of the light shielding layer 213 corresponding to the first channel region 2124 and the second channel region 2125 of the same thin film transistor are respectively the first sub-light shielding portion 213a and the second sub-light shielding portion 213b, and the first sub-light shielding portion 213a and the second sub-light shielding portion 213b are spaced from each other, the orthographic projection of the first channel region 2124 on the base substrate 211 is completely located within the orthographic projection of the first sub-light shielding portion 213a on the base substrate 211, and the orthographic projection of the second channel region 2125 on the base substrate 211 is completely located within the orthographic projection of the second sub-light shielding portion 213b on the base substrate 211. The orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the first sub-light shielding portion 213a on the base substrate 211, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the second sub-light shielding portion 213b on the base substrate 211.

[0112] For example, Fig.13 A schematic diagram of a planar structure of another array substrate provided in at least one embodiment of the present disclosure is shown. Fig.14 for Fig.13 The cross-sectional structure diagram of the array substrate is shown in FIG. Fig.13As shown, the array substrate 21 includes a base substrate 211 and a light shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211. The semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122, the first branch portion 2121 includes a first channel region 2124, the second branch portion 2122 includes a second channel region 2125, and the end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the first branch portion 2121 has a first via structure 2126 on one side away from the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the base substrate 211. The end of the second branch portion 2122 away from the connection portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connection portion 2123 on the base substrate 211. The orthographic projection of the light shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125 and the first via structure 2126 on the base substrate 311. The array substrate 21 can reduce the leakage current phenomenon and improve the retention capacity of the pixel capacitance by setting the light shielding layer 213 to cover the entire area of ​​the first channel region 2124, the second channel region 2125 and the first via structure 2126, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0113] For example, Fig.13 As shown, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2124 and the connecting portion 2123. Fig.13 In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2124 corresponding to the end of the first branch portion 2121 are flush.

[0114] For example, Fig.13As shown, the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in the second direction Y, the gate line 2128 is in a long strip shape, the gate line 2128 includes a first gate 2128a and a second gate 2128b, the orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.

[0115] For example, the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure, the first gate 2128a and the second gate 2128b are part of the gate line 2128, the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124, and the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.

[0116] For example, Fig.14 As shown, a first insulating layer 219 is disposed between the light shielding layer 213 and the semiconductor layer 212 , a gate insulating layer 217 is disposed between the first insulating layer 219 and the first metal layer 214 , and an interlayer insulating layer 218 is disposed on a side of the first metal layer 214 away from the base substrate 211 .

[0117] For example, combined with Fig.13 and Fig.14 In one example, the material of the light shielding layer 213 includes a non-conductive light shielding material or a conductive light shielding material, and the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the light shielding layer 213 on the base substrate 211 .

[0118] For example, combined with Fig.13 and Fig.14 The light-shielding layer 213 is an integral structure, and the orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projection of the first channel region 2124 on the base substrate 211, the orthographic projection of the second channel region 2125 on the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211, as well as covers the gap between the first channel region 2124 and the second channel region 2125. The planar shape of the light-shielding layer 213 is stepped.

[0119] For example, Fig.15A schematic diagram of a stacked structure of another array substrate provided for at least one embodiment of the present disclosure, in one example, a plurality of thin film transistors are arranged on the base substrate 211, portions of the light-shielding layer 213 corresponding to different thin film transistors are spaced apart from each other, and the light-shielding layer 213 only corresponds to the first channel region 2124 of the same thin film transistor, that is, the orthographic projection of the light-shielding layer 213 on the base substrate 211 only covers the orthographic projection of the first channel region 2124 on the base substrate 211, and does not cover the orthographic projection of the second channel region 2125 on the base substrate 211.

[0120] For example, Fig.15 As shown, the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is farther away from the connecting portion 2123 than the first via structure 2126. Fig.15 In the plan view shown, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.

[0121] For example, Fig.15 As shown, the array substrate 21 can reduce leakage current and enhance the retention capacity of pixel capacitance by designing the shading layer 213 to cover the positive projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel formed subsequently.

[0122] For example, Fig.16 A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure, Fig.16 The array substrate and Figure 5 The difference of the array substrate shown is that a touch signal line 220 extending along the first direction X is provided between the first branch portion 2121 and the second branch portion 2122 . This design can save space for placing the wiring and make the array substrate thinner and lighter. Fig.16 The structure of the array substrate shown can be seen in Figure 5 The description of the array substrate will not be repeated here.

[0123] For example, Fig.17A schematic diagram of a stacked structure of another array substrate provided in at least one embodiment of the present disclosure, Fig.17 The array substrate and Fig.11 The difference of the array substrate shown is that a touch signal line 220 extending along the first direction X is provided between the first branch portion 2121 and the second branch portion 2122 . This design can save space for wiring placement and make the array substrate thinner and lighter. Fig.17 The structure of the array substrate shown can be seen in Fig.11 The description of the array substrate will not be repeated here.

[0124] For example, for the display panel, a black matrix can be further arranged on an opposing substrate arranged opposite to the array substrate, and the length of the light-shielding layer that blocks the spacing area on the lower side of the gate line in the first direction X can be reduced, so that the edges of the light-shielding layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0125] At least one embodiment of the present disclosure provides a display panel, which includes a first substrate and a second substrate arranged oppositely, wherein the first substrate includes a substrate substrate and a semiconductor layer and a light shielding layer stacked on the substrate substrate; the second substrate includes a black matrix; the semiconductor layer includes a first branch portion and a second branch portion arranged oppositely, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion away from the substrate substrate, and the orthographic projection of the first via structure on the substrate substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the substrate substrate; the orthographic projection of the light shielding layer on the substrate substrate is located within the orthographic projection of the black matrix on the substrate substrate, and at least covers the orthographic projection of the first channel region and the first via structure on the substrate substrate. The display panel can reduce the leakage current of the display panel formed subsequently by adjusting the design of the light shielding layer to improve the retention capacity of the pixel capacitor, thereby improving the problem of flickering at low frequency, and can also ensure the aperture ratio of the display panel formed subsequently, and make the edges of the light shielding layer shrink to the area covered by the black matrix, so as to further improve the aperture ratio of the display panel.

[0126] For example, Fig.18 is a schematic cross-sectional structure diagram of a display panel provided in at least one embodiment of the present disclosure, Fig.19 A schematic diagram of a planar structure of a display panel provided in at least one embodiment of the present disclosure is provided. Fig. 20 A schematic cross-sectional structure diagram of a first substrate provided in at least one embodiment of the present disclosure, combined with Fig.18 , Fig.19 and Fig. 20As shown, the display panel 30 includes a first substrate 31 and a second substrate 32 arranged oppositely, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged oppositely, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, the first branch portion 3121 includes a first channel region 3121a, the second branch portion 3122 includes a second channel region 3122a, the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first branch portion 3121 has a first via structure 314 on a side away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located at the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311. 11, the orthographic projection of the shading layer 313 on the substrate 311 is within the orthographic projection of the black matrix 321 on the substrate 311, and at least covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 314 on the substrate 311. The display panel 30 sets the black matrix 321 to cover the entire area of ​​the shading layer 313, and sets the shading layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314. This can reduce the leakage current phenomenon of the display panel formed subsequently, enhance the retention capacity of the pixel capacitance, thereby improving the flicker problem under low frequency, and can also ensure the aperture ratio of the display panel.

[0127] It should be noted that the semiconductor layer is in a state during the process of manufacturing the display panel. There are other subsequent processes to conduct part of the semiconductor area. That is, after forming the gate and gate line mentioned later, there is a heavy doping step to make the part of the semiconductor layer outside the area covered by the gate into a conductor, so that the gate can block the channel area. Therefore, the channel area corresponding to the semiconductor layer is located below the gate.

[0128] It should also be noted that although Fig.19 In the illustrated embodiment, the light shielding layer 313 covers the second channel region 3122 a , but in other examples, the light shielding layer 313 may not cover the second channel region 3122 a .

[0129] For example, in one example, the first substrate 31 is an array substrate, and the second substrate 32 is an opposing substrate arranged opposite to the array substrate, and the opposing substrate is, for example, a color filter substrate. Other structures on the color filter substrate can refer to conventional designs and will not be described here.

[0130] For example, combined with Fig.19 , the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, Fig.19 In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the minimum distance between the second via structure 315 and the connecting portion 3123 is greater than the minimum distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0131] For example, combined with Fig.19 and Fig. 20 The first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0132] For example, combined with Fig.19 and Fig. 20 , the orthographic projection of the first gate 3161a on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, so that the black matrix 321 completely covers the first gate 3161a and the second gate 3161b. Moreover, the black matrix 321 covers the entire gate line 3161.

[0133] It should be noted that in Fig.19 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0134] For example, Fig. 20 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0135] For example, combined with Fig.19 and Fig. 20 In one example, the material of the light-shielding layer 313 includes a conductive metal with light-shielding properties, the orthographic projection of the black matrix 321 on the base substrate 311 and the orthographic projection of the light-shielding layer 313 on the base substrate 311 both cover the orthographic projection of the first via structure 314 on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the light-shielding layer 313 on the base substrate 311.

[0136] It should be noted that if the second via structure 315 is blocked by the light-shielding layer 313, the light-shielding layer 313 needs to be blocked by the black matrix 321. Taking into account the alignment fluctuations in the process, when the light-shielding layer 313 is added here, the alignment fluctuations of the multi-layer structure will lead to the need to design a wider black matrix, thereby sacrificing the pixel aperture ratio of the subsequently formed display panel. Based on the yield of the display panel, there is a risk of over-etching the light-shielding layer 313 when etching the interlayer insulating layer 318. Moreover, when the material of the light-shielding layer 313 is a conductive metal with light-shielding properties, over-etching the interlayer insulating layer 318 will cause a short circuit between the first source-drain electrode and the second source-drain electrode of the thin-film transistor, thereby causing the thin-film transistor to lose its switching function.

[0137] It should also be noted that when the material of the light-shielding layer 313 is not a conductive material with light-shielding properties, that is, when the material of the light-shielding layer 313 is an insulating material with light-shielding properties, the light-shielding layer 313 can also cover the second via structure 315, so that even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin-film transistor.

[0138] For example, in one example of the present disclosure, Fig.19 and Fig. 20 The light shielding layer 313 covers the first via structure 314, which is helpful to reduce the leakage current I off The effect is quite significant. When the shielding area of ​​the light shielding layer 313 on the first channel region 3121a changes, the corresponding leakage current I offThe data are as follows: Taking the conventional design as the benchmark (100%), the data obtained from the experimental item is compared with the data obtained from the conventional design. It can be concluded that when the shielding area of ​​the light shielding layer 313 to the first channel region 3121a is increased, the leakage current I off The improvement effect is obvious, but the adjustment of the blocking area of ​​the second channel region 3122a by the shading layer 313 has little effect on the characteristics of the thin film transistor. Therefore, under the premise of not affecting the aperture ratio of the display panel formed subsequently, the blocking area of ​​the first channel region 3121a by the shading layer 313 is increased as much as possible, and the shading layer 313 blocks the first via structure 314, and reduces the blocking area of ​​the second channel region 3122a by the shading layer 313, which can reduce the impact on the aperture ratio of the display panel formed subsequently.

[0139] For example, in one example of the present disclosure, in order to ensure that the first via structure 314 does not leak light, the black matrix 321 needs to completely cover the first via structure 314, and make the distance between the first via structure 314 and the edge of the black matrix 321 adjacent to the first via structure 314 in the first direction X be 1.15 microns. Therefore, in order to ensure that the light-shielding layer 313 does not affect the aperture ratio of the display panel formed subsequently, in the first direction X, the upper edge of the right side portion of the light-shielding layer 313 corresponding to the first via structure is flush with the upper edge of the first via structure 314.

[0140] For example, Fig.19As shown, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns, the light shielding layer 313 completely shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314. On the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 6.15 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns. In order not to affect the aperture ratio of the display panel formed subsequently, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, the light transmittance is 34% under 6500 nit illumination; and the light transmittance is 31% under 20000 nit illumination.

[0141] For example, based on the above Fig.19 and Fig. 20 When the display panel is designed based on the numerical values ​​in the embodiment shown, 10 sets of experimental data on low-frequency flicker are obtained, namely: -35.82, -33.53, -36.55, -36.45, -35.78, -38.12, -36.21, -36.45, -35.72 and -37.41, so that the average flicker value can be obtained as -36.204. Correspondingly, based on Figure 1 When designing the display panel based on the numerical values ​​of the conventional design in, 10 sets of experimental data on low-frequency flicker are made, namely: -28.12, -26.58, -26.09, -28.22, -27.35, -29.2, -27.63, -28.54, -27.86 and -29.51, so that the average flicker value can be obtained as -27.91. It can be concluded from the above experimental data that by optimizing the design of the shading layer 313, the flicker degree of the display screen of the display panel can be effectively improved to meet the control benchmark for the display panel.

[0142] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 5.5 microns, the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 5.5 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns. In order not to affect the aperture ratio of the display panel formed subsequently, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the gap above the gate line 3161. For example, when the display panel is designed based on the above numerical values, the light transmittance is 49% under 6500 nit illumination; and the light transmittance is 41% under 20000 nit illumination.

[0143] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 5 microns, the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 5 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns. In order not to affect the aperture ratio of the display panel, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121, and the distance from the lower edge of the light shielding layer 313 to the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light shielding layer 313 is relatively long, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the gap above the gate line 3161. For example, when the display panel is designed based on the above numerical values, the light transmittance is 57% under 6500nit illumination; and the light transmittance is 48% under 20000nit illumination.

[0144] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 4.5 microns, the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, so on the upper side of the gate line 3161, the length of the light shielding layer 313 shielding the first branch portion 3121 is 4.5 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns. In order not to affect the aperture ratio of the display panel, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 is designed to be flush with the lower edge of the black matrix 321, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 to the gate line 3161 is 1.4 microns. In the second direction Y, the length of the light shielding layer 313 is relatively long, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the gap above the gate line 3161. For example, when the display panel is designed based on the above numerical values, the light transmittance is 64% under 6500nit illumination; and the light transmittance is 61% under 20000nit illumination.

[0145] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns, the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 6.15 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 0.7 microns. In order not to affect the aperture ratio of the display panel, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 0.7 microns. In the second direction Y, the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, under the condition of 6500 nit illumination, the light transmittance is 36%; under the condition of 20000 nit illumination, the light transmittance is 35%.

[0146] For example, in another example, in the first direction X, the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns, the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 6.15 microns. In the first direction X, on the lower side of the gate line 3161, the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 0 microns. In order not to affect the aperture ratio of the display panel, in the first direction X, the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 0 micrometers. In the second direction Y, the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 micrometers, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 micrometers. In addition, the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161. For example, when the display panel is designed based on the above numerical values, the light transmittance is 39% under 6500 nit illumination; and the light transmittance is 32% under 20000 nit illumination.

[0147] Based on the analysis of the above experimental data, it can be concluded that the channel region corresponding to the two gates of the thin film transistor is shielded by a whole shading layer or a shading layer with a larger area and spaced apart, and the shading layer increases the shielding area on one side of the first source and drain electrode connected to the pixel electrode, that is, when the first via structure in the above interlayer insulating layer is blocked, the leakage current of the thin film transistor included in the display panel can be reduced, and the length of the shading layer on the lower side of the gate line in the first direction X that shields the spacing area is reduced, so that the edges of the shading layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0148] For example, a plurality of thin film transistors may be disposed on the first substrate 31, and portions of the light shielding layer 313 corresponding to different thin film transistors may be spaced apart from each other, for example, Fig.19As shown, the portion of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor is an integral structure. The light shielding layer 313 is designed as an integral structure so that the area covered by the light shielding layer 313 on one side of the first via structure 314 is increased, thereby reducing the leakage current of the thin film transistor.

[0149] For example, Fig.19 As shown, the first branch portion 3121 and the second branch portion 3122 both extend along the first direction X, and the connecting portion 3123 extends along the second direction Y intersecting the first direction X. The first branch portion 3121, the second branch portion 3122 and the connecting portion 3123 are arranged to form an opening area, and the shading layer 313 covers at least part of the opening area, so that the shading layer 313 can be arranged to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314, so as to reduce the leakage current of the thin film transistor, and enhance the retention capacity of the pixel capacitance, improve the flicker problem under low frequency, and in addition, the aperture ratio of the display panel can be guaranteed.

[0150] For example, in one example, the first direction X and the second direction Y are perpendicular.

[0151] For example, Fig.19 As shown, the orthographic projections of the two side edges of the gate line 3161 in the second direction Y on the substrate substrate 311 and the orthographic projections of the corresponding two side edges of the black matrix 321 in the second direction Y on the substrate substrate 311 overlap respectively, that is, the orthographic projections of the edge lines on both sides of the gate line 3161 in the second direction Y on the substrate substrate 311 and the orthographic projections of the edge lines on both sides of the black matrix 321 in the second direction Y on the substrate substrate 311 coincide with each other, so that it can be ensured that the gate line 3161 can be shrunk into the area covered by the black matrix 321, thereby further improving the aperture ratio of the display panel.

[0152] For example, Fig.19 As shown, in one example, in the first direction X, there is a gap between the light shielding layer 313 and the connecting portion 3123, that is, there is a gap between the black matrix 321 and the connecting portion 3123. In this way, while reducing the leakage current of the thin film transistor included in the display panel, it is also possible to improve the flicker problem of the display panel at low frequencies and increase the aperture ratio of the display panel.

[0153] For example, Fig.19As shown, in one example, the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the substrate substrate 311 overlaps with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the substrate substrate 311, that is, the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the substrate substrate 311 and the orthographic projection of the portion of the black matrix 321 corresponding to the first branch portion 3121 on the substrate substrate 311 overlaps. The orthographic projection of the edge close to the connecting portion 3123 on the base substrate 311 is flush, that is, the orthographic projection of the edge line of the portion of the light shading layer 313 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the base substrate 311 coincides with the orthographic projection of the edge line of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the base substrate 311. This ensures that the edge of the light shading layer 313 can be completely retracted into the area covered by the black matrix 321 to ensure the aperture ratio of the display panel.

[0154] For example, in other examples, in the second direction Y, the leftmost edge of the light-shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located within the orthographic projection of the leftmost edge of the black matrix 321 on the base substrate 311; the rightmost edge of the light-shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located within the orthographic projection of the rightmost edge of the black matrix 321 on the base substrate 311.

[0155] For example, Fig.19 As shown, the bottom edge of the partial light-shielding layer 313 corresponding to the first branch portion 3121 located at the lower side of the gate line 3161 in the first direction X and the edge of the partial black matrix 321 corresponding to the first branch portion 3121 located at the lower side of the gate line 3161 in the first direction X, which is closest to the connecting portion 3123, overlap in their orthographic projections on the base substrate 311, that is, at least part of the black matrix 321 is also flush with the edge of the light-shielding layer 313.

[0156] For example, Fig.21 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure, Fig. 22 for Fig.21 A schematic diagram of the cross-sectional structure of the first substrate in FIG. Fig.18 , Fig.21 and Fig. 22The first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122. The first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first The side of the branch portion 3121 away from the base substrate 311 has a first via structure 314, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311, and the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and The orthographic projection of the second via structure 315 on the substrate substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the substrate substrate 311, the orthographic projection of the light shielding layer 313 on the substrate substrate 311 is located within the orthographic projection of the black matrix 321 on the substrate substrate 311, and the orthographic projection of the light shielding layer 313 on the substrate substrate 311 covers the orthographic projections of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315 on the substrate substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of ​​the light shielding layer 313, and setting the light shielding layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.

[0157] For example, combined with Fig.21 In the first direction X, the second via structure 315 is further away from the connecting portion 3123 than the first via structure 314. Fig.21In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0158] For example, combined with Fig.21 and Fig. 22 The first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate line 3161 extending in the second direction Y. The gate line 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311. The orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0159] It should be noted that in Fig.21 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0160] For example, Fig. 22 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0161] For example, Fig.21 and Fig. 22As shown, the orthographic projection of the edge of the light shielding layer 313 away from the connection portion 3123 on the base substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123 and a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123. The upper edge of the first portion 313c and the upper edge of the second portion 313d are not on the same straight line, that is, the plane shape of the light shielding layer 313 is step-shaped, and the plane shape of the black matrix 321 is grid-shaped. Although Fig.21 The plane shape of the black matrix 321 shown is a rectangle, and the plane shape of the light shielding layer 313 corresponding to the black matrix 321 is also stepped, and in the first direction X, the distance between the first portion 313c and the connecting portion 3123 is smaller than the distance between the second portion 313d and the connecting portion 3123. The second portion 313d and the orthographic projection of the edge of the black matrix 321 located on the upper side of the second via structure 315 on the base substrate 311 overlap, that is, the orthographic projection of the second portion 313d and the upper edge of the left side of the black matrix 321 corresponding to the second via structure 315 on the base substrate 311 coincides, and the orthographic projection of the first portion 313c and the edge of the black matrix 321 located on the upper side of the first via structure 314 on the base substrate 311 are spaced. The orthographic projection of the black matrix 321 on the base substrate 311 and the orthographic projection of the light shielding layer 313 on the base substrate 311 both cover the orthographic projection of the second via structure 315 on the base substrate 311, that is, the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the light shielding layer 313 on the base substrate 311. It should be noted that, in this example, the material of the light shielding layer 313 is a non-conductive light shielding material. When the material of the light shielding layer 313 is a non-conductive light shielding material, even if the interlayer insulating layer 318 is etched to over-etch the light shielding layer 313, there will be no problem of short circuit between the first source-drain electrode and the second source-drain electrode of the thin film transistor.

[0162] For example, Fig.23 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.24 for Fig.23 A schematic diagram of the cross-sectional structure of the first substrate in FIG. Fig.18 , Fig.23 and Fig.24The first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, the first branch portion 3121 includes a first channel region 3121a, the second branch portion 3122 includes a second channel region 3122a, the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, and the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other, and the portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced apart from each other. The first sub-light shielding portion 313a covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and the second sub-light shielding portion 313b covers the orthographic projection of the second channel region 3122a on the base substrate 311, but does not cover the orthographic projection of the second via structure 315 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of ​​the light-shielding layer 313 and the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designing the first sub-light-shielding portion 313a to cover the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and designing the second sub-light-shielding portion 313b to cover the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.

[0163] For example, combined with Fig.23 , the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, Fig.23In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.

[0164] For example, combined with Fig.23 and Fig.24 The first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0165] It should be noted that in Fig.23 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0166] For example, Fig.23 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0167] For example, Fig.23 and Fig.24As shown, the orthographic projection of the side of the first sub-light shielding portion 313a away from the connecting portion 3123 on the substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connecting portion 3123, and the orthographic projection of the side of the second sub-light shielding portion 313b away from the connecting portion 3123 on the substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connecting portion 3123, that is, the plane shapes of the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are both long strips, and the length of the first sub-light shielding portion 313a is less than the length of the second sub-light shielding portion 313b. In the first direction X, the distance between the first portion 313c and the connecting portion 3123 is less than the distance between the second portion 313d and the connecting portion 3123. The orthographic projections of the edge of the second portion 313d and the portion of the black matrix 321 located on the upper side of the second via structure 315 on the substrate substrate 311 overlap, that is, the orthographic projections of the second portion 313d and the portion of the black matrix 321 located on the upper side of the second via structure 315 on the substrate substrate 311 coincide, and the orthographic projections of the edge of the first portion 313c and the portion of the black matrix 321 located on the upper side of the first via structure 314 on the substrate substrate 311 are spaced. The orthographic projection of the black matrix 321 on the substrate substrate 311 covers the orthographic projection of the second via structure 315 on the substrate substrate 311, and the orthographic projection of the light shielding layer 313 on the substrate substrate 311 does not cover the orthographic projection of the second via structure 315 on the substrate substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate substrate 311 is outside the orthographic projection of the light shielding layer 313 on the substrate substrate 311. It should be noted that, in this example, the material of the light-shielding layer 313 is a non-conductive light-shielding material or a light-shielding conductive material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin-film transistor.

[0168] For example, a plurality of thin film transistors are disposed on the first substrate 31, and portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other. Fig.23 and Fig.24The parts of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced from each other, the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311. The orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311.

[0169] For example, Fig.23 and Fig.24 As shown, the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315 , and the maximum distance between the second via structure 315 and the connecting portion 3123 is greater than the maximum distance between the first via structure 314 and the connecting portion 3123 .

[0170] For example, Fig.25 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.26 for Fig.25 A schematic diagram of the cross-sectional structure of the first substrate in FIG. Fig.18 , Fig.25 and Fig.26The first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are oppositely arranged, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, wherein the first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a, and the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, and the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315. The orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and covers the orthographic projections of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of ​​the light-shielding layer 313, and setting the light-shielding layer 313 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.

[0171] For example, in Fig.25 In the planar structural schematic diagram shown, the orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection area of ​​the light-shielding layer 313 on the base substrate 311 is smaller than the orthographic projection area of ​​the black matrix 321 on the base substrate 311. Of course, the embodiments of the present disclosure are not limited to this, and the portion of the black matrix covering the lower left corner of the connecting portion 3123 is not considered. The planar shape of the light-shielding layer 313 and the planar shape of the portion of the black matrix 321 corresponding to the light-shielding layer may also be the same.

[0172] For example, combined with Fig.25 , the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, that is, Fig.25In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.

[0173] For example, combined with Fig.25 and Fig.26 The first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.

[0174] It should be noted that in Fig.25 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0175] For example, Fig.26 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0176] For example, combined with Fig.25 and Fig.26In one example, the material of the light-shielding layer 313 includes a non-conductive light-shielding material, the orthographic projection of the black matrix 321 on the base substrate 311 covers the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311, and the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311 are both located within the orthographic projection of the light-shielding layer 313 on the base substrate 311.

[0177] For example, combined with Fig.25 and Fig.26 The light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second channel region 3122a on the base substrate 311, the orthographic projection of the first via structure 314 on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a, and covers the gap between the first via structure 314 and the second via structure 315.

[0178] For example, Fig. 27 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.28 for Fig. 27 A schematic diagram of the cross-sectional structure of the first substrate in FIG. Fig.18 , Fig. 27 and Fig.28The first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311 . The second substrate 32 includes a black matrix 321, the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, the first branch portion 3121 includes a first channel region 3121a, the second branch portion 3122 includes a second channel region 3122a, the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on a side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311, and the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other, and the portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced apart from each other. The first sub-light shielding portion 313a covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and the second sub-light shielding portion 313b covers the orthographic projection of the second channel region 3122a and the second via structure 315 on the base substrate 311. The display panel 30 sets the black matrix 321 to cover the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, but does not cover the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designs the first sub-light-shielding portion 313a so that the orthographic projection of the first sub-light-shielding portion 313a on the substrate 311 covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the substrate 311, and designs the second sub-light-shielding portion 313b so that the orthographic projection of the second sub-light-shielding portion 313b on the substrate 311 covers the orthographic projection of the second channel region 3122a and the second via structure 315 on the substrate 311. This design can reduce leakage current and improve the retention capacity of pixel capacitance, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.

[0179] For example, combined with Fig. 27 , the second via structure 315 corresponds to the end of the second branch portion 3122 away from the connecting portion 3123, and the minimum distance between the second via structure 315 and the connecting portion 3123 is equal to the minimum distance between the first via structure 314 and the connecting portion 3123, that is, Fig. 27In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X. The length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.

[0180] For example, combined with Fig. 27 and Fig.28 The first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311. The first metal layer 316 includes a gate 3161 extending in the second direction Y. The gate 3161 is in a long strip shape. The gate line 3161 includes a first gate 3161a and a second gate 3161b. The orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311. The orthographic projection of the gate line 3161 on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, that is, the gate line 3161 is also contracted to within the range defined by the black matrix 321, thereby not reducing the aperture ratio of the display panel.

[0181] It should be noted that in Fig. 27 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0182] For example, Fig.28 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0183] For example, Fig. 27 and Fig.28As shown, the orthographic projection of the edge of the first sub-light shielding portion 313a away from the connection portion 3123 on the substrate substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123, and the orthographic projection of the edge of the second sub-light shielding portion 313b away from the connection portion 3123 on the substrate substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123, and the upper edge of the first portion 313c and the upper edge of the second portion 313d are on the same straight line, that is, the plane shapes of the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are both long strips, and the length of the first sub-light shielding portion 313a in the first direction X is equal to the length of the second sub-light shielding portion 313b in the first direction X. In the first direction X, the distance between the first portion 313c and the connection portion 3123 is equal to the distance between the second portion 313d and the connection portion 3123. The second portion 313d overlaps with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the second via structure 315 on the substrate 311, that is, the second portion 313d coincides with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the second via structure 315 on the substrate 311, and the first portion 313c coincides with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the first via structure 314 on the substrate 311. The orthographic projection of the black matrix 321 on the substrate 311 and the orthographic projection of the light shielding layer 313 on the substrate 311 both cover the orthographic projection of the second via structure 315 on the substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate 311 is located within the orthographic projection of the light shielding layer 313 on the substrate 311. It should be noted that, in this example, the material of the light-shielding layer 313 is a non-conductive light-shielding material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.

[0184] For example, a plurality of thin film transistors are disposed on the first substrate 31, and portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other. Fig. 27 and Fig.28The parts of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced from each other, the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311. The orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311.

[0185] For example, Fig.29 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.30 for Fig.29 The cross-sectional structure diagram of the first substrate shown in FIG. Fig.18 , Fig.29 and Fig.30As shown, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, wherein the first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311. The end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the base substrate 311. The orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 2126 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 3121a, the second channel region 3122a and the first via structure 314, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.

[0186] For example, Fig.29 As shown, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123. Fig.29 In the plan view shown, the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 2124 corresponding to the end of the first branch portion 3121 are flush.

[0187] For example, Fig.29 and 30As shown, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0188] For example, the first gate 3161a, the second gate 3161b and the gate line 3161 are an integrated linear structure, the first gate 3161a and the second gate 3161b are part of the gate line 3161, the first gate 3161a is the part of the gate line 3161 corresponding to the first channel region 3121a, and the second gate 3161b is the part of the gate line 3161 corresponding to the second channel region 3122a.

[0189] It should be noted that in Fig.29 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0190] For example, Fig.30 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0191] For example, combined with Fig.29 and Fig.30 In one example, the material of the light shielding layer 313 includes a non-conductive light shielding material or a conductive light shielding material, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the light shielding layer 313 on the base substrate 311 .

[0192] For example, combined with Fig.29 and Fig.30The light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a. The planar shape of the light-shielding layer 313 is stepped.

[0193] For example, Fig.31 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.32 for Fig.31 The cross-sectional structure diagram of the first substrate shown in FIG. Fig.18 , Fig.31 and Fig.32 As shown, the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311. The second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, wherein the first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a. The end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311. The end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the base substrate 311. The orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311. The orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a and the first via structure 2126 on the base substrate 311. The display panel 30 can reduce leakage current and enhance the retention capacity of the pixel capacitor by setting the light-shielding layer 213 to cover the entire area of ​​the first channel region 3121a and the first via structure 314, but not covering the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.

[0194] For example, Fig.31 As shown, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123 .

[0195] For example, Fig.31 and 32 As shown, the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.

[0196] It should be noted that in Fig.31 In the embodiment shown, the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions. Fig.19 The data lines are not shown in the figure. In actual products, the black matrix 321 also covers the data lines. When touch signal lines are also provided on the display panel, the black matrix also covers the touch signal lines.

[0197] For example, Fig.32 As shown, a first insulating layer 319 is provided between the light shielding layer 313 and the semiconductor layer 312 , a gate insulating layer 317 is provided between the first insulating layer 319 and the first metal layer 316 , and an interlayer insulating layer 318 is provided on a side of the first metal layer 316 away from the base substrate 311 .

[0198] For example, combined with Fig.31 and Fig.32 In one example, the material of the light shielding layer 313 includes a non-conductive light shielding material or a conductive light shielding material, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the light shielding layer 313 on the base substrate 311 .

[0199] For example, Fig.33 A schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure is shown. Fig.33 The display panel and Fig.19The difference of the display panel shown is that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122 , which can save space for wiring placement and make the display panel thinner and lighter. Fig.33 The structure of the display panel shown can be seen in Fig.19 The relevant description of the display panel shown is not repeated here.

[0200] For example, in Fig.33 In the structure shown, the black matrix 321 also covers the touch signal line 320 .

[0201] For example, Fig.34 A schematic diagram of a stacked structure of another display panel provided in at least one embodiment of the present disclosure, Fig.34 The display panel and Fig. 27 The difference of the display panel shown is that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122 , which can save space for wiring placement and make the display panel thinner and lighter. Fig.34 The structure of the display panel shown can be seen in Fig. 27 The relevant description of the display panel shown is not repeated here.

[0202] For example, in Fig.34 In the structure shown, the black matrix 321 also covers the touch signal line 320 .

[0203] For example, Fig.35 A block diagram of a display panel provided in at least one embodiment of the present disclosure, such as Fig.35 As shown, the display panel 30 includes the array substrate 21 in any of the above embodiments, that is, the first substrate 31. In one example, the display panel 30 also includes a liquid crystal layer sandwiched between the first substrate 31 and the second substrate 32. Other circuit structures included in the display panel can refer to conventional designs, and the embodiments of the present disclosure are not limited to this.

[0204] At least one embodiment of the present disclosure further provides a display device, for example, Fig.36 A block diagram of a display device provided in at least one embodiment of the present disclosure, such as Fig.36 As shown, the display device 500 includes any of the display panels 30 described above, and the display panel 30 includes the array substrate provided by any of the above embodiments.

[0205] For example, the display device 500 may be a display device with a display function. For example, the display device 500 may be a display, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function and a touch function.

[0206] The array substrate, display panel and display device provided by at least one embodiment of the present disclosure have at least one of the following beneficial technical effects:

[0207] (1) The array substrate provided in at least one embodiment of the present disclosure can reduce the leakage current of the display panel by adjusting the design of the light-shielding layer. The light-shielding layer is designed to shield the first via structure, thereby improving the retention capacity of the pixel capacitor, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.

[0208] (2) In the display panel provided by at least one embodiment of the present disclosure, the light-shielding layer is designed as an integral piece, and the light-shielding layer completely blocks the gap between the first branch portion and the second branch portion, that is, the light-shielding layer fully blocks the gap above the gate line, thereby reducing the leakage current of the thin film transistor without affecting the aperture ratio.

[0209] (3) In the display panel provided by at least one embodiment of the present disclosure, the edges of the light shielding layer are shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

[0210] There are a few points to note:

[0211] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0212] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0213] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0214] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate, the semiconductor layer comprising a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion comprising a first channel region, the second branch portion comprising a second channel region, a first via structure being provided on a side of the first branch portion away from the base substrate, and an orthographic projection of the first via structure on the base substrate is located within an orthographic projection of an end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.

2. The array substrate according to claim 1, wherein: The second branch portion has a second via structure on the side away from the base substrate, and the orthographic projection of the second via structure on the base substrate is located within the orthographic projection of the end of the second branch portion away from the connecting portion on the base substrate, and the minimum distance between the second via structure and the connecting portion is greater than or equal to the minimum distance between the first via structure and the connecting portion.

3. The array substrate according to claim 2, wherein: The orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light shielding layer on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: A plurality of thin film transistors are arranged on the base substrate, portions of the light shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

5. The array substrate according to claim 4, wherein: The first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the shading layer covers at least a portion of the opening area.

6. The array substrate according to claim 5 further includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

7. The array substrate according to claim 4, wherein: There is a gap between the light shielding layer and the connecting portion in the first direction.

8. The array substrate according to any one of claims 1 to 3, wherein: A plurality of thin film transistors are arranged on the base substrate, and portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other. Portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively a first sub-light-shielding portion and a second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

9. The array substrate according to claim 8, wherein: The orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light shielding portion on the base substrate.

10. A display panel, comprising a first substrate and a second substrate arranged opposite to each other, wherein: The first substrate includes a base substrate and a semiconductor layer and a light shielding layer stacked on the base substrate; The second substrate includes a black matrix; The semiconductor layer includes a first branch portion and a second branch portion that are arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion that is away from the substrate, and an orthographic projection of the first via structure on the substrate is located within an orthographic projection of an end of the first branch portion that is away from the connecting portion on the substrate; The orthographic projection of the light shielding layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate, and at least covers the orthographic projections of the first channel region and the first via structure on the base substrate.

11. The display panel according to claim 10, wherein: An end of the second branch portion away from the connecting portion corresponds to a second via structure, and the second via structure is further away from the connecting portion than the first via structure.

12. The display panel according to claim 11, wherein: The material of the light-shielding layer includes a conductive metal, the orthographic projection of the black matrix on the base substrate covers the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light-shielding layer on the base substrate.

13. The display panel according to any one of claims 10 to 12, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.

14. The display panel according to claim 13, wherein: The first branch portion and the second branch portion both extend along a first direction, the connecting portion extends along a second direction intersecting the first direction, the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area, and the shading layer covers at least a portion of the opening area.

15. The display panel according to claim 14, wherein: The first substrate also includes a first metal layer arranged on a side of the semiconductor layer away from the base substrate, the first metal layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.

16. The display panel according to claim 15, wherein: The orthographic projection of the first gate on the base substrate is within the orthographic projection of the black matrix on the base substrate, and the orthographic projection of the second gate on the base substrate is within the orthographic projection of the black matrix on the base substrate.

17. The display panel according to claim 16, wherein: There is a gap between the light shielding layer and the connecting portion in the first direction.

18. The display panel according to any one of claims 14 to 17, wherein: The orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion close to the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion close to the connecting portion on the base substrate.

19. The display panel according to claim 11, wherein: The orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion farthest from the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion farthest from the connecting portion on the base substrate.

20. The display panel according to claim 19, wherein: The orthographic projection of the edge of the light-shielding layer away from the connecting portion on the base substrate includes a first part located on the side of the first via structure away from the connecting portion and a second part located on the side of the second via structure away from the connecting portion, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the edge of the black matrix farthest from the second via structure on the base substrate.

21. The display panel according to claim 19 or 20, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are respectively the first sub-light-shielding portion and the second sub-light-shielding portion, and the first sub-light-shielding portion and the second sub-light-shielding portion are spaced apart from each other.

22. The display panel according to claim 21, wherein: The orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light shielding portion on the base substrate.

23. The display panel according to claim 10, wherein: An end of the second branch portion away from the connecting portion corresponds to a second via structure, and a maximum distance between the second via structure and the connecting portion is equal to a maximum distance between the first via structure and the connecting portion.

24. The display panel according to claim 23, wherein: The material of the light shielding layer includes a non-conductive light shielding material, and the orthographic projection of the black matrix on the base substrate and the orthographic projection of the light shielding layer on the base substrate both cover the orthographic projection of the second via structure on the base substrate.

25. The display panel according to claim 23 or 24, wherein: A plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure or a structure spaced apart from each other.

26. A display device, comprising the array substrate according to any one of claims 1 to 9, or the display panel according to any one of claims 10 to 25.

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