A kind of κ-Ga 2 O 3 / Al 2 O 3 Negative capacitance transistor with composite ferroelectric layer and preparation method thereof

Abstract

The present invention discloses a negative capacitance transistor with a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a preparation method thereof. The negative capacitance transistor of the present invention includes a substrate, a GaN buffer layer, a UID-GaN channel layer, and Al arranged in sequence from bottom to top. 0.25 Ga 0.75 N barrier layer, and a source electrode, a drain electrode, and a gate arranged on the Al 0.25 Ga 0.75 N barrier layer, and a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer arranged between the gate and the Al 0.25 Ga 0.75 N barrier layer. The negative capacitance transistor of the present invention can achieve the combination of volatile and non-volatile storage, thereby improving the stability of the system and the data preservation reliability after power-off while ensuring the high-speed data processing ability, and providing efficient data management support for the application of the full reservoir.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a negative capacitance transistor with a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a preparation method thereof. Background Art

[0002] With the continuous evolution of semiconductor technology, the size of transistors continues to shrink, approaching the physical limit. However, as the integration density of devices increases, the power consumption problem becomes more prominent. Although the performance can be improved to a certain extent by using high dielectric constant materials, improving current driving capability and optimizing device structure, these technical means still cannot effectively solve the problem of excessive power consumption. This is because the subthreshold swing (SS) of traditional metal oxide semiconductor field effect transistors is limited by Boltzmann statistics and can only reach a minimum of 60 mV / dec, which greatly limits the switching speed and energy efficiency of the device. Therefore, how to break through this bottleneck and develop new low-power devices with lower SS has become a key technical challenge to achieve higher performance and low-power integrated circuits, and is also an important research direction for the future semiconductor industry.

[0003] The negative capacitance effect generated by ferroelectric materials when polarization is reversed can amplify the surface potential of the channel material, thereby effectively reducing the subthreshold swing (SS) of the device and breaking through the Boltzmann limit, making it an ideal choice for building low-power transistors in the post-Moore era. However, in traditional preparation methods, there are a large number of interface states at the interface because the ferroelectric dielectric layer and the channel layer are not epitaxial. This is because non-epitaxial growth causes a large number of dangling bonds to be generated at the interface. These defects will increase leakage current and reduce electron mobility when used as transistor devices, ultimately affecting the overall performance of the device.

[0004] In order to overcome the above problems and realize the construction of low-power negative capacitance transistors, the present invention adopts epitaxial κ-Ga2O3 material on the substrate to greatly reduce the interface state density. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a method for preparing the same. The present invention forms a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer with high interface quality by epitaxially growing a ferroelectric dielectric material film and combining it with oxygen interface compensation, thereby improving device performance. In the negative capacitance transistor of the present invention, the composite ferroelectric dielectric layer produces a negative capacitance effect during the polarization reversal process, thereby reducing device power consumption and enabling the transistor to break through the subthreshold swing limit. Oxygen plasma compensation can effectively improve the interface quality between the ferroelectric layer and the channel material and between the ferroelectric layer and alumina, reduce the impact of defect capture on ferroelectric performance, and further enhance the stability and overall performance of the transistor. The present invention solves the problem in the prior art of using ferroelectric dielectric materials to prepare negative capacitance transistors, which is caused by the ferroelectric hysteresis effect and low interface quality of the ferroelectric material, thereby affecting device performance.

[0006] To achieve the above purpose, the technical solution designed by the present invention is as follows:

[0007] The present invention provides a negative capacitance transistor with a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, wherein the negative capacitance transistor comprises a substrate, a GaN buffer layer, a UID-GaN channel layer, an Al2O3 composite ferroelectric dielectric layer, and a GaN buffer layer. 0.25 Ga 0.75 N barrier layer, and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer, and the source electrode arranged in the source electrode region, the drain electrode arranged in the drain electrode region and the gate arranged in the gate region; the UID-GaN channel layer and the Al 0.25 Ga 0.75 The contact surface of the N barrier layer forms a two-dimensional electron gas channel 2DEG;

[0008] The negative capacitance transistor further includes a gate and an Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer between the N barrier layers; the κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer comprises a plurality of layers arranged in sequence from bottom to top on the Al 0.25 Ga 0.75 The κ-Ga2O3 ferroelectric layer and the Al2O3 insulating layer on the surface of the N barrier layer are made of κ-Ga2O3 and the Al2O3 insulating layer is made of Al2O3.

[0009] Furthermore, the negative capacitance transistor further comprises SiN x The insulating layer, the SiN xThe insulating layer is disposed on the surface of the negative capacitance transistor except the gate region.

[0010] Furthermore, the Al 0.25 Ga 0.75 The interface between the N barrier layer and the κ-Ga2O3 ferroelectric layer is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer and the Al2O3 insulating layer is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.9×10 13 ~2.5×10 13 cm -2 .

[0011] Furthermore, the thickness of the κ-Ga2O3 ferroelectric layer is 50-100 nm, and the thickness of the Al2O3 insulating layer is 30-50 nm;

[0012] The substrate is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate, the thickness of the GaN buffer layer is 4-4.5 μm, the thickness of the UID-GaN channel layer is 300-350 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer is 200~250 nm, and the SiN x The thickness of the insulating layer is 100~150 nm.

[0013] Furthermore, the thickness of the κ-Ga2O3 ferroelectric layer is 50 nm, and the thickness of the Al2O3 insulating layer is 30 nm;

[0014] The substrate is a silicon substrate, the thickness of the GaN buffer layer is 4 μm, the thickness of the UID-GaN channel layer is 300 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer is 200 nm, and the SiN x The thickness of the insulating layer is 100 nm.

[0015] Furthermore, the source electrode and the drain electrode are both Ti / Al / Ni / Au alloys, and the thicknesses of Ti, Al, Ni and Au are 20~30, 120~150, 50~60 and 80~100 nm respectively; the gate is a Ni / Au alloy, and the thicknesses of Ni and Au are 50~60 and 80~100 nm respectively; the distance between the gate and the source electrode is 6~12 μm, and the distance between the gate and the drain electrode is 6~12 μm.

[0016] The present invention also provides a method for preparing the negative capacitance transistor, comprising the following steps:

[0017] (1) Clean the substrate; deposit the GaN buffer layer, UID-GaN channel layer and Al 0.25 Ga 0.75 N barrier layer;

[0018] (2) Using photolithography technology on Al 0.25 Ga 0.75 The surface of the N barrier layer defines the source electrode region and the drain electrode region. The source electrode and the drain electrode are formed by electron beam evaporation deposition of Ti, Al, Ni, and Au metal layers. 0.25 Ga 0.75 The N barrier layer forms an ohmic contact;

[0019] (3) Plasma enhanced chemical vapor deposition technology is used to deposit SiN on the surface of the epitaxial wafer x Insulation layer;

[0020] (4) Using photolithography technology on SiN x The gate region is defined on the surface of the insulating layer, and SiN is etched vertically downward in the gate region. x Insulation layer until Al leaks out 0.25 Ga 0.75 The surface of the N barrier layer;

[0021] (5) sequentially growing a κ-Ga2O3 ferroelectric layer and an Al2O3 insulating layer on the surface of the epitaxial wafer;

[0022] (6) Use plasma enhanced etching process to etch the Al2O3 insulating layer and κ-Ga2O3 ferroelectric layer outside the gate area until reaching the SiN x The surface of the insulation layer;

[0023] (7) The Al2O3 insulating layer in the gate region is photolithographically processed and developed to form a gate window, and Ni and Au metal layers are deposited in the gate window to form a gate, thereby obtaining a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer.

[0024] Furthermore, in the step (4), after defining the gate region, oxygen plasma treatment is used to remove residual glue;

[0025] In the step (5), after depositing the κ-Ga2O3 ferroelectric layer, the κ-Ga2O3 ferroelectric layer is treated with oxygen plasma;

[0026] The conditions of the oxygen plasma treatment are: radio frequency power of 100-500 W and treatment time of 60 s.

[0027] Furthermore, the method further comprises a side etching step, which is arranged between step (2) and step (3). Specifically, the side etching step comprises defining a non-effective working area at the outer edges of the source electrode and the drain electrode, respectively, and etching downward 200 nm along the non-effective working area to form a step notch structure;

[0028] In the step (3), SiN is deposited on the surface of the epitaxial wafer and in the step-notch structure by plasma enhanced chemical vapor deposition technology. x Insulation layer.

[0029] Furthermore, the method further includes a needle window step, which is arranged after step (7). Specifically, the needle window step comprises: photolithography and development on the surface of the source electrode and the surface of the drain electrode to form a needle window, etching SiN on the needle window on the surface of the source electrode. x The insulating layer forms the source electrode pinning area, and SiN is etched in the pinning window on the drain electrode surface. x The insulating layer forms a drain electrode pinning region.

[0030] Principle of the present invention:

[0031] 1. The present invention adopts a method of epitaxially growing κ-Ga2O3 material on an epitaxial wafer to significantly reduce the interface state density. The reasons for using κ-Ga2O3 as a ferroelectric layer are as follows:

[0032] (1) κ-Ga2O3 has excellent remanent polarization strength. The theoretical remanent polarization strength of κ-Ga2O3 is 23 μC / cm², and the experimentally measured remanent polarization strength is 2 μC / cm², which is significantly higher than that of general two-dimensional slip ferroelectric materials (such as Cd3Cl6, which has a remanent polarization strength of 0.3~0.4 μC / cm² at room temperature);

[0033] (2) κ-Ga2O3 also has a relatively small coercive electric field. Its theoretical coercive electric field is 2.27 MV / cm, while the coercive electric field of perovskite materials such as AlScN is 5 MV / cm. Therefore, the required voltage and power consumption are much lower than those of materials such as AlScN. Therefore, in comparison, κ-Ga2O3 has significant advantages in reducing device power consumption and improving switching performance due to its excellent coercive electric field and residual polarization strength, making it an ideal choice in the field of negative capacitance transistors.

[0034] (3) κ-Ga2O3 has a bandgap of 4.85 eV and a relatively high dielectric constant of 32. It exhibits excellent radiation resistance, good thermal stability, and excellent ultraviolet absorption ability. It has become the preferred material in the field of solar-blind ultraviolet detection and is widely used in various application scenarios such as space communications, fire monitoring, meteorological monitoring, and environmental pollution monitoring.

[0035] 2. The reasons for selecting aluminum oxide as the material for forming a composite ferroelectric dielectric layer with gallium oxide are:

[0036] Aluminum oxide has a high dielectric constant and low leakage current density, which can effectively reduce the charge leakage of the dielectric layer and provide a reliable insulation environment for the device. In addition, aluminum oxide has good chemical stability and good chemical compatibility with gallium oxide. It can form a stable transition layer at the interface and reduce interface defects. Furthermore, the thermal expansion coefficient of aluminum oxide is close to that of gallium oxide, which helps to maintain the stability of the interface structure under high-temperature process conditions and reduce interface defects caused by thermal stress. Finally, aluminum oxide has a large bandgap width of 8.8 eV, which can form a deep barrier in the composite ferroelectric dielectric layer, effectively blocking carriers from crossing and improving device performance.

[0037] Beneficial effects of the present invention:

[0038] 1. Compared with traditional field-effect transistors, the negative capacitance transistor prepared by the present invention can achieve a subthreshold swing lower than the theoretical limit of 60 mV / dec, and when the voltage scanning speed is reduced to 0.003 V / s, the measured subthreshold swing is as low as 11 mV / dec, so the subthreshold swing is related to the voltage scanning rate.

[0039] 2. In the present invention, oxygen plasma compensates the oxide surface, which can further effectively compensate the interface state and more fully reflect the regulation of the ferroelectric layer on the channel electrons. This process will not cause damage to the surface of the channel material.

[0040] 3. The method of reducing leakage of the present invention is applicable to any planar structure transistor, SiN x Can effectively isolate the gate through Al 0.25 Ga 0.75 The N barrier layer directly transmits the current to the source electrode, effectively reducing gate leakage, while aluminum oxide has a good effect in alleviating the leakage phenomenon caused by the crystal structure of the multi-rotation domains of κ-Ga2O3.

[0041] 4. The ferroelectric dielectric material κ-Ga2O3 in the negative capacitance transistor of the present invention is used to produce a negative capacitance effect when the polarization is reversed, so that the transistor device breaks through the subthreshold swing limit. Compared with other non-epitaxially grown ferroelectric dielectric layers, the epitaxially grown κ-Ga2O3 has less interface state density, thereby promoting the electrons in the ferroelectric polarization regulation channel.

[0042] 5. The κ-Ga2O3 prepared by the present invention can be prepared on a variety of substrates to achieve diversified detection forms and meet different detection needs. The device prepared on the sapphire substrate works in the Rayleigh mode with a resonant frequency of 1.96 GHZ and a phase velocity of υ pis 3138 m / s, and the electromechanical coupling coefficient k eff 2 The device fabricated on a silicon carbide substrate operates in the Cecilia mode with a resonant frequency of 3.31 GHz. p It is 6640 m / s.

[0043] 6. The negative capacitance transistor prepared by the present invention has multiple modulation modes of electrical signals and dual plasticity (long-term plasticity and short-term plasticity at the same time). Due to the wide bandgap characteristics and ferroelectric polarization effect of κ-Ga2O3, the transistor has multiple modulation modes of electrical signals and has good radiation resistance to short-wavelength light. The transistor of the present invention can realize the combination of volatile and non-volatile storage, thereby ensuring high-speed data processing capabilities while improving the stability of the system and the reliability of data preservation after power failure, providing efficient data management support for full reserve pool applications, reducing migration delays and power consumption, and enhancing its robustness in extreme environments. Therefore, the device can provide efficient data management support for full reserve pool applications and is expected to be widely used in aerospace AI systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic structural diagram of a negative capacitance transistor of the present invention;

[0045] In the figure, 1, substrate; 2, GaN buffer layer; 3, UID-GaN channel layer; 4, Al 0.25 Ga 0.75 N barrier layer; 5, source electrode; 6, drain electrode; 7, gate; 8, composite ferroelectric dielectric layer; 9, κ-Ga2O3 ferroelectric layer; 10, Al2O3 insulating layer; 11, SiN x Insulation layer;

[0046] Figure 2 In order to deposit GaN buffer layer, UID-GaN channel layer and Al 0.25 Ga 0.75 N barrier layer step diagram;

[0047] Figure 3 A diagram showing the steps for preparing source and drain electrodes;

[0048] Figure 4 Figure 1 is a side etching step diagram;

[0049] Figure 5 For deposition of SiN x Insulation layer step diagram;

[0050] Figure 6 A diagram showing the steps for defining the gate region;

[0051] Figure 7The diagram is a step diagram for epitaxial growth of κ-Ga2O3 ferroelectric layer and Al2O3 insulating layer;

[0052] Figure 8 A diagram showing the steps of etching the composite ferroelectric layer outside the gate region;

[0053] Fig. 9 A diagram showing the steps for preparing a gate;

[0054] Fig.10 This is a step-by-step diagram for the acupuncture window;

[0055] Fig.11 An optical microscope image of a negative capacitance transistor device of the present invention;

[0056] Fig.12 This is the X-ray diffraction (XRD) result of the κ-Ga2O3 ferroelectric layer;

[0057] Fig.13 This is the atomic force microscopy (AFM) result of the κ-Ga2O3 ferroelectric layer;

[0058] Fig.14 This is the piezoelectric force microscopy (PFM) result of the κ-Ga2O3 ferroelectric layer;

[0059] Fig.15 This is the polarization intensity result diagram of the κ-Ga2O3 ferroelectric layer under the PUND test;

[0060] Fig.16 It is a transfer curve diagram of the oxide dielectric layer of the negative capacitance transistor of the present invention before being treated by oxygen plasma;

[0061] Fig.17 It is a transfer curve diagram of the negative capacitance transistor of the present invention after the oxide dielectric layer is treated by oxygen plasma;

[0062] Fig.18 A graph showing the transfer characteristics of a negative capacitance transistor according to the present invention;

[0063] Fig.19 This is a graph showing the subthreshold swing results of the negative capacitance transistor of the present invention;

[0064] Fig. 20 is an output characteristic curve diagram of the negative capacitance transistor of the present invention;

[0065] Fig.21 This is a graph showing the effects of small pulses and large pulses on the conductivity plasticity of the negative capacitance transistor of the present invention. DETAILED DESCRIPTION

[0066] The present invention is further described in detail below in conjunction with specific embodiments so that those skilled in the art can understand.

[0067] Example 1

[0068] This embodiment provides a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric layer, combined with Figure 1 As shown, the negative capacitance transistor includes a substrate 1, a GaN buffer layer 2, a UID-GaN channel layer 3, an Al 0.25 Ga 0.75 N barrier layer 4, and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer 4, the source electrode 5 arranged in the source electrode region, the drain electrode 6 arranged in the drain electrode region and the gate 7 arranged in the gate region, and the gate 7 and the Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer 8 between the N barrier layers 4 and the SiN x The insulating layer 11, the κ-Ga2O3 / Al2O3 composite ferroelectric layer 8 includes an Al 0.25 Ga 0.75 The surface of the N barrier layer 4 is provided with a κ-Ga2O3 ferroelectric layer 9 and an Al2O3 insulating layer 10 in sequence from bottom to top.

[0069] UID-GaN channel layer 3 and Al 0.25 Ga 0.75 The contact surface of the N barrier layer 4 forms a two-dimensional electron gas channel 2DEG; Al 0.25 Ga 0.75 The interface between the N barrier layer 4 and the κ-Ga2O3 ferroelectric layer 9 is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer 9 and the Al2O3 insulating layer 10 is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.90×10 13 cm -2 .

[0070] In the negative capacitance transistor with the κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer of this embodiment:

[0071] (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 50-100 nm, and the thickness of the Al2O3 insulating layer 10 is 30-50 nm;

[0072] Preferably, the thickness of the κ-Ga2O3 ferroelectric layer 9 is 50 nm, and the thickness of the Al2O3 insulating layer 10 is 30 nm;

[0073] (2) The substrate 1 is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate;

[0074] Preferably, the substrate 1 is a silicon substrate;

[0075] (3) The thickness of the GaN buffer layer 2 is 4~4.5 μm, the thickness of the UID-GaN channel layer 3 is 300~350 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 200-250 nm, and the SiN x The thickness of the insulating layer 11 is 100-150 nm;

[0076] Preferably, the thickness of the GaN buffer layer 2 is 4 μm, the thickness of the UID-GaN channel layer 3 is 300 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 200 nm, and the SiN x The thickness of the insulating layer 11 is 100 nm;

[0077] (4) The source electrode 5 and the drain electrode 6 are both Ti / Al / Ni / Au alloys, and the thicknesses of Ti, Al, Ni and Au are 20~30, 120~150, 50~60 and 80~100 nm respectively; the gate 7 is Ni / Au alloy, and the thicknesses of Ni and Au are 50~60 and 80~100 nm respectively; the distance between the gate 7 and the source electrode 5 is 6~12 μm, and the distance between the gate 7 and the drain electrode 6 is 6~12 μm;

[0078] Preferably, in the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni and Au are 20, 120, 50 and 100 nm respectively; in the gate 7, the thicknesses of Ni and Au are 50 and 100 nm respectively; the distance between the gate 7 and the source electrode 5 is 6 μm, and the distance between the gate 7 and the drain electrode 6 is 10 μm.

[0079] Example 2

[0080] This embodiment provides a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer. The negative capacitance transistor of this embodiment is the same as that of embodiment 1. The only difference is that the transistor of this embodiment lacks SiN x Insulating layer 11.

[0081] Al 0.25 Ga 0.75 The interface between the N barrier layer 4 and the κ-Ga2O3 ferroelectric layer 9 is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer 9 and the Al2O3 insulating layer 10 is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 2.5×10 13 cm -2 .

[0082] Example 3

[0083] This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, combined with Figure 2~Figure 10 As shown, the specific steps include:

[0084] 1. If Figure 2 As shown, the substrate 1 is cleaned; a GaN buffer layer 2, a UID-GaN channel layer 3 and an Al 0.25 Ga 0.75 N barrier layer 4, the specific steps are as follows:

[0085] (1) A silicon substrate 1 with a (111) crystal plane (a silicon carbide substrate or a sapphire substrate may also be selected) is selected to reduce the lattice mismatch with GaN, and the silicon substrate 1 is cleaned using a Piranha solution (H2SO4+H2O2) or HF acid.

[0086] (2) A GaN buffer layer 2 is prepared on a silicon substrate 1. The GaN buffer layer 2 is deposited by metal organic chemical vapor deposition (MOCVD) technology at 1050°C under hydrogen or nitrogen protection using ammonia (NH3) as a nitrogen source and triethylgallium (TEGa) as a gallium source. The deposition thickness is 4 μm.

[0087] (3) A UID-GaN channel layer 3 is prepared on the GaN buffer layer 2. The UID-GaN channel layer 3 is grown by MOCVD. The MOCVD technology is also used for deposition. The growth temperature is 1050°C~1100°C and the deposition thickness is 300 nm.

[0088] (4) Preparation of Al on UID-GaN channel layer 3 0.25 Ga 0.75 N barrier layer 4, Al was grown by MOCVD at 1050°C using triethylaluminum (TEAl) and triethylgallium (TEGa) as metal sources and NH3 as nitrogen source. 0.25 Ga 0.75 The N barrier layer 4 is deposited to a thickness of 200 nm.

[0089] 2. If Figure 3 As shown in Al 0.25 Ga 0.75Photolithography is performed on the N barrier layer 4 to define the source electrode region and the drain electrode region. After exposure, oxygen plasma is used to remove the residual glue. Subsequently, Ti, Al, Ni, and Au metal layers are deposited in sequence by electron beam evaporation with thicknesses of 20 nm, 120 nm, 50 nm, and 100 nm, respectively, to form the source electrode 5 and the drain electrode 6. After the metal deposition is completed, annealing is performed at 840°C in a nitrogen atmosphere for 1 min. The source electrode 5 and the drain electrode 6 are bonded to the Al 0.25 Ga 0.75 The N barrier layer 4 forms a high-quality ohmic contact.

[0090] 3. If Figure 4 As shown in FIG. 1 , the outer edges of the source electrode 5 and the drain electrode 6 define the ineffective working area and the effective working area, respectively. Using photolithography technology, the photoresist covers the effective working area, and the photoresist in the ineffective working area falls off after exposure. Subsequently, the plasma enhanced etching (RIE) process is used to etch Al2O3 downward along the ineffective working area. 0.25 Ga 0.75 The N barrier layer 4 material is 200 nm. Since the effective working area is protected by photoresist, the effective working area remains intact, while the material in the ineffective working area is partially etched. In this way, the devices are effectively isolated from each other, forming a step gap structure, which successfully prevents current crosstalk between current devices.

[0091] 4. If Figure 5 As shown, a 100 nm SiN layer is deposited on the surface of the epitaxial wafer by a plasma enhanced chemical vapor deposition (PECVD) method in an atmosphere of silane (SiH4) and ammonia (NH3) through a radio frequency plasma reaction. x Thin film, forming SiN x Insulating layer 11.

[0092] 5. If Figure 6 As shown, the SiN x The gate region is defined on the surface of the insulating layer 11, and oxygen plasma is used to remove the residual glue (the conditions of oxygen plasma treatment: the RF power range is 100~500 W, and the duration of plasma treatment is fixed at 60 s). Subsequently, a plasma enhanced etching (RIE) process is used to etch the SiN in the gate region in a mixed atmosphere of fluorine-based gas (such as SF6 or CHF3) and oxygen. x The insulating layer 11 is anisotropically etched until the Al 0.25 Ga 0.75 The surface of the N barrier layer 4 is cleaned with acetone to remove the remaining photoresist.

[0093] 6. If Figure 7As shown, a Mist-CVD method (PLD or MOCVD can also be used) is then used to epitaxially grow a 50 nm κ-Ga2O3 film on the surface of the epitaxial wafer. The temperature is set to 700°C, and a precursor solution is prepared by dissolving gallium chloride (GaCl3) in deionized water or an alcohol solution (such as methanol, ethanol). The epitaxial growth is completed in an oxygen atmosphere to form a κ-Ga2O3 ferroelectric layer 9. The κ-Ga2O3 ferroelectric layer 9 is treated with oxygen plasma (the conditions for oxygen plasma treatment: the RF power range is 100~500 W, and the duration of plasma treatment is fixed at 60 s.); then, an atomic layer deposition (ALD) process is used to alternately introduce trimethylaluminum (TMA) and water vapor to react on the surface of the κ-Ga2O3 ferroelectric layer 9, and a 30 nm Al2O3 film is deposited layer by layer to form an Al2O3 insulating layer 10.

[0094] 7. If Figure 8 As shown, the region outside the gate region is subjected to photolithography technology, and after exposure, the κ-Ga2O3 ferroelectric layer 9, the Al2O3 insulating layer 10 and the SiN x The insulating layer 11 is then removed by oxygen plasma, and then the Al2O3 insulating layer 10 and the κ-Ga2O3 ferroelectric layer 9 are etched away by RIE process, leaving the SiN x Insulating layer 11.

[0095] 8. If Fig. 9 As shown, a gate 7 window is formed on the Al2O3 insulating layer 10 by photolithography and development, and then the residual glue is removed by oxygen plasma. Subsequently, Ni and Au electrodes are deposited in the gate 7 window by electron beam evaporation, with thicknesses of 50 nm and 100 nm, respectively, as the gate 7. After the preparation is completed, metal stripping is performed using acetone solution to remove excess metal, and the gate 7 is completed (the distance between the gate 7 and the source electrode 5 is 6 μm, and the distance between the gate 7 and the drain electrode 6 is 10 μm).

[0096] 9. If Fig.10 As shown, the surface of the source electrode 5 and the surface of the drain electrode 6 are photolithographically etched and developed to form a pinning window, and then the residual glue is removed by oxygen plasma. Subsequently, SiN is etched in the pinning window on the surface of the source electrode 5 by RIE etching. x The insulating layer 11 forms the source electrode 5 pinning area, and SiN is etched in the pinning window on the surface of the drain electrode 6. x The insulating layer 11 forms the puncture area of ​​the drain electrode 6, and a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer can be obtained. The minimum subthreshold swing of the transistor is 11 mV / dec.

[0097] Example 4

[0098] This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer. The preparation steps are the same as those in Embodiment 3, except that:

[0099] (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 100 nm, and the thickness of the Al2O3 insulating layer 10 is 50 nm;

[0100] (2) The thickness of the GaN buffer layer 2 is 4.5 μm, the thickness of the UID-GaN channel layer 3 is 350 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 250 nm, and the SiN x The thickness of the insulating layer 11 is 150 nm;

[0101] (3) In the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni and Au are 30, 150, 60 and 80 nm, respectively; in the gate 7, the thicknesses of Ni and Au are 60 and 80 nm, respectively; the distance between the gate 7 and the source electrode 5 is 12 μm, and the distance between the gate 7 and the drain electrode 6 is 6 μm.

[0102] Example 5

[0103] This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer. The preparation steps are the same as those in Embodiment 3, except that:

[0104] (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 80 nm, and the thickness of the Al2O3 insulating layer 10 is 40 nm;

[0105] (2) The thickness of the GaN buffer layer 2 is 4.2 μm, the thickness of the UID-GaN channel layer 3 is 320 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 230 nm, and the SiN x The thickness of the insulating layer 11 is 120 nm;

[0106] (3) In the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni and Au are 25, 130, 55 and 90 nm, respectively; in the gate 7, the thicknesses of Ni and Au are 55 and 90 nm, respectively; the distance between the gate 7 and the source electrode 5 is 10 μm, and the distance between the gate 7 and the drain electrode 6 is 12 μm.

[0107] Example 6

[0108] Performance testing of negative capacitance transistors with κ-Ga2O3 / Al2O3 composite ferroelectric layers

[0109] Fig.11 This is an optical microscope image of the negative capacitance transistor device of Example 1, which has a top-gate structure.

[0110] Fig.12 This is the XRD diagram of the 50 nm κ-Ga2O3 ferroelectric layer prepared in Example 1. It can be seen that the prepared κ-Ga2O3 is a single phase. Fig.13 This is an AFM image of the 50 nm κ-Ga2O3 ferroelectric layer prepared in Example 1. The κ-Ga2O3 film has a flat and uniform surface with a roughness of 9.1 nm, and the growth mode is island growth.

[0111] Fig.14 The piezoelectric force microscopy image of a 50 nm κ-Ga2O3 ferroelectric layer shows that the film has an obvious phase reversal phenomenon and exhibits a certain amplitude response.

[0112] Fig.15 The polarization intensity result of 50 nm κ-Ga2O3 ferroelectric layer measured by PUND shows that the material has 2 μC / cm 2 The residual polarization intensity.

[0113] Example 7

[0114] Effect of oxygen plasma treatment on the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention

[0115] Fig.16 is a transfer curve diagram of the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention before being treated by oxygen plasma, Fig.17 The transfer curve diagram of the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention after being treated with oxygen plasma; the results show that the hysteresis of the transfer curve before the treatment is clockwise, representing a defect capture mechanism, while the hysteresis of the transfer curve after the treatment is counterclockwise, representing an iron-deficient polarization reversal mechanism. After the oxide dielectric layer of the negative capacitance transistor of the present invention is treated with oxygen plasma, the concentration of the acceptor interface state is reduced, and the potential barrier close to the semiconductor surface will be further reduced, so the defect capture mechanism will become a secondary factor, and the ferroelectric polarization induced channel formation will become a major factor, making the performance of the negative capacitance transistor more excellent.

[0116] Example 8

[0117] Subthreshold swing detection of negative capacitance transistors with κ-Ga2O3 / Al2O3 composite ferroelectric layers

[0118] Fig.18 is a transfer characteristic result diagram of the negative capacitance transistor of Example 1, Fig.19The subthreshold swing result diagram of the negative capacitance transistor of Example 1. The results show that the transfer curve of the transistor has a counterclockwise hysteresis phenomenon, and the subthreshold swing breaks through the Boltzmann limit and decreases to below 60 mV / dec. At the same time, the subthreshold swing is also affected by the voltage scan rate. Specifically, when the scan rate is 0.003 V / s, the minimum subthreshold swing measured is 11 mV / dec.

[0119] Fig. 20 : is an output characteristic curve diagram of the negative capacitance transistor of Example 1. From the output curve, it can be seen that the ferroelectric polarization reversal of κ-Ga2O3 has an obvious modulation effect on the channel conductance.

[0120] Fig.21 The effects of small and large pulses on the conductivity plasticity of the negative capacitance transistor of Example 1 are shown. When the pulse voltage is close to the coercive voltage of κ-Ga2O3, the transistor can maintain conductivity after the pulse is removed, showing non-volatile storage characteristics; and when the pulse voltage is much lower than the coercive voltage, the transistor will "forget" the conductivity after the pulse is removed, showing volatile storage characteristics.

[0121] Although the above embodiments have been described in detail, they are only a part of the embodiments of the present invention, not all of them. People can also obtain other embodiments based on this embodiment without creativity, and these embodiments all belong to the protection scope of the present invention.

Claims

1. A negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, the negative capacitance transistor comprising a substrate (1), a GaN buffer layer (2), a UID-GaN channel layer (3), an Al 0.25 Ga 0.75 N barrier layer (4), and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer (4), and the source electrode (5) arranged in the source electrode region, the drain electrode (6) arranged in the drain electrode region and the gate (7) arranged in the gate region; the UID-GaN channel layer (3) and the Al 0.25 Ga 0.75 The contact surface of the N barrier layer (4) forms a two-dimensional electron gas channel 2DEG; Features: The negative capacitance transistor further includes a gate (7) and an Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer (8) is disposed between the N barrier layers (4); the κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer (8) comprises: 0.25 Ga 0.75 A κ-Ga2O3 ferroelectric layer (9) and an Al2O3 insulating layer (10) are provided on the surface of an N barrier layer (4), wherein the material of the κ-Ga2O3 ferroelectric layer (9) is κ-Ga2O3, and the material of the Al2O3 insulating layer (10) is Al2O3.

2. The negative capacitance transistor according to claim 1, characterized in that: The negative capacitance transistor further comprises SiN x The insulating layer (11), the SiN x An insulating layer (11) is arranged on the surface of the negative capacitance transistor except the gate region.

3. The negative capacitance transistor according to claim 1, characterized in that: The Al 0.25 Ga 0.75 The interface where the N barrier layer (4) and the κ-Ga2O3 ferroelectric layer (9) are in contact is a first oxygen compensation interface, and the interface where the κ-Ga2O3 ferroelectric layer (9) and the Al2O3 insulating layer (10) are in contact is a second oxygen compensation interface, and the defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.9×10 13 ~2.5×10 13 cm -2 .

4. The negative capacitance transistor according to claim 2, characterized in that: The κ-Ga2O3 ferroelectric layer (9) has a thickness of 50-100 nm, and the Al2O3 insulating layer (10) has a thickness of 30-50 nm; The substrate (1) is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate, the thickness of the GaN buffer layer (2) is 4-4.5 μm, the thickness of the UID-GaN channel layer (3) is 300-350 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer (4) is 200~250 nm, and the SiN x The thickness of the insulating layer (11) is 100-150 nm.

5. The negative capacitance transistor according to claim 4, characterized in that: The κ-Ga2O3 ferroelectric layer (9) has a thickness of 50 nm, and the Al2O3 insulating layer (10) has a thickness of 30 nm; The substrate (1) is a silicon substrate, the GaN buffer layer (2) has a thickness of 4 μm, the UID-GaN channel layer (3) has a thickness of 300 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer (4) is 200 nm, and the SiN x The thickness of the insulating layer (11) is 100 nm.

6. The negative capacitance transistor according to claim 1, characterized in that: The source electrode (5) and the drain electrode (6) are both Ti / Al / Ni / Au alloys, with the thicknesses of Ti, Al, Ni and Au being 20-30, 120-150, 50-60 and 80-100 nm respectively; the gate (7) is a Ni / Au alloy, with the thicknesses of Ni and Au being 50-60 and 80-100 nm respectively; the distance between the gate (7) and the source electrode (5) is 6-12 μm, and the distance between the gate (7) and the drain electrode (6) is 6-12 μm.

7. A method for preparing a negative capacitance transistor according to any one of claims 2 to 6, characterized in that: The following steps are involved: 1) cleaning the substrate (1); depositing a GaN buffer layer (2), a UID-GaN channel layer (3) and an Al 0.25 Ga 0.75 N barrier layer (4); 2) Using photolithography technology on Al 0.25 Ga 0.75 The surface of the N barrier layer (4) defines a source electrode region and a drain electrode region. Ti, Al, Ni, and Au metal layers are deposited by electron beam evaporation to form a source electrode (5) and a drain electrode (6). The source electrode (5) and the drain electrode (6) are connected to Al 0.25 Ga 0.75 The N barrier layer (4) forms an ohmic contact; 3) Plasma enhanced chemical vapor deposition technology is used to deposit SiN on the surface of the epitaxial wafer x Insulating layer (11); 4) Using photolithography technology on SiN x The surface of the insulating layer (11) defines a gate region, and SiN is etched vertically downward in the gate region. x Insulation layer (11) until Al leaks out 0.25 Ga 0.75 a surface of the N barrier layer (4); 5) sequentially growing a κ-Ga2O3 ferroelectric layer (9) and an Al2O3 insulating layer (10) on the surface of the epitaxial wafer; 6) Use plasma enhanced etching process to etch the Al2O3 insulating layer (10) and κ-Ga2O3 ferroelectric layer (9) outside the gate area until reaching the SiN x a surface of the insulating layer (11); 7) Photolithography and development are performed on the Al2O3 insulating layer (10) in the gate region to form a gate (7) window, and Ni and Au metal layers are deposited in the gate (7) window to form a gate (7), thereby obtaining a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer.

8. The preparation method according to claim 7, characterized in that: In the step 4), after defining the gate region, oxygen plasma treatment is used to remove residual glue; In the step 5), after depositing the κ-Ga2O3 ferroelectric layer (9), the κ-Ga2O3 ferroelectric layer (9) is treated with oxygen plasma; The conditions of the oxygen plasma treatment are: radio frequency power of 100-500 W and treatment time of 60 s.

9. The preparation method according to claim 7, characterized in that: The method further comprises a side etching step, wherein the side etching step is arranged between step 2) and step 3), and the side etching step specifically comprises defining a non-effective working area at the outer edges of the source electrode (5) and the drain electrode (6), respectively, and etching downwards by 200 nm along the non-effective working area to form a step notch structure; In the step 3), SiN is deposited on the surface of the epitaxial wafer and in the step-notch structure by plasma enhanced chemical vapor deposition technology. x Insulating layer (11).

10. The preparation method according to claim 7, characterized in that: The invention also includes a needle-piercing window step, which is arranged after step 7). Specifically, the needle-piercing window step comprises: photolithography and development are respectively performed on the surface of the source electrode (5) and the surface of the drain electrode (6) to form a needle-piercing window, and SiN is etched in the needle-piercing window on the surface of the source electrode (5). x The insulating layer (11) forms a pinning area for the source electrode (5), and SiN is etched in the pinning window on the surface of the drain electrode (6). x The insulating layer (11) forms a drain electrode (6) puncture area.

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