A double-gate enhancement-mode gallium nitride radio frequency power transistor
By introducing a dual-gate structure of RF gate and DC gate into GaN HEMT devices, the circuit complexity and performance deficiencies caused by the depletion-mode nature of GaN HEMT devices are solved, achieving high transconductance, positive threshold voltage and high cutoff frequency, thus improving RF performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI UNIV
- Filing Date
- 2024-09-24
- Publication Date
- 2026-06-19
AI Technical Summary
Existing GaN HEMT devices are typically depletion-mode, requiring negative voltage turn-off, which leads to high circuit complexity and cost. Furthermore, conventional p-GaN gate HEMT devices have insufficient transconductance and cutoff frequency, making it difficult for them to gain a competitive advantage in 5G communications.
A dual-gate enhancement gallium nitride (GaN) RF power transistor is designed, combining an RF gate and a DC gate. The RF gate is used to input the RF signal, and the DC gate controls the switch. A two-dimensional electron gas is generated through piezoelectric polarization and spontaneous polarization effects to achieve a positive threshold voltage and high transconductance.
It improves the transconductance, cutoff frequency, and breakdown voltage of transistors, simplifies circuit design, reduces the switching ratio, and improves RF performance.
Smart Images
Figure CN119230604B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of transistors, and in particular to a dual-gate enhancement-mode gallium nitride radio frequency power transistor. Background Technology
[0002] With the advent of the 5G era, communication methods and radio frequency (RF) technologies have been greatly improved, thus placing increasingly stringent demands on RF devices. GaN HEMT devices (gallium nitride high electron mobility transistors) generate two-dimensional electron gases with high mobility and saturation carrier velocity, making them widely used in high-frequency, high-speed, and high-power applications. Therefore, GaN HEMT devices play an indispensable role in power amplifiers and RF switches in RF front-end applications.
[0003] For RF power amplifiers, enhancement-mode devices with a positive threshold voltage can utilize unipolar biased designs, significantly saving space, improving operational safety, and simplifying circuit design. While conventional GaN HEMT devices offer excellent power amplification capabilities, their two-dimensional electron gas is spontaneously generated, making them typically depletion-mode devices. Therefore, GaN HEMT devices often require a negative gate voltage for turn-off in practical applications, undoubtedly increasing circuit complexity and manufacturing costs. Although p-GaN gate HEMT devices are currently the most mature and promising enhancement-mode GaN n-FET devices, the presence of the p-GaN cap layer results in significantly lower transconductance, cutoff frequency, and maximum oscillation frequency compared to conventional GaN HEMT devices. Furthermore, the negative threshold voltage of conventional GaN HEMTs prevents them from gaining a competitive advantage in practical 5G communication applications. Summary of the Invention
[0004] The purpose of this application is to provide a dual-gate enhancement gallium nitride RF power transistor with high turn-on and cut-off frequencies and a positive threshold voltage, thereby improving the RF performance of the RF power transistor.
[0005] To achieve the above objectives, this application provides the following solution:
[0006] In a first aspect, this application provides a dual-gate enhancement-type gallium nitride radio frequency power transistor, comprising: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a source, a radio frequency gate, a DC gate, and a drain;
[0007] The substrate, the buffer layer, the GaN channel layer, and the AlGaN barrier layer are stacked sequentially from bottom to top;
[0008] The p-GaN cap layer is disposed on the upper surface of the AlGaN barrier layer; the DC gate is disposed on the upper surface of the p-GaN cap layer;
[0009] The source and the drain are respectively located at both ends of the upper surface of the AlGaN barrier layer;
[0010] The radio frequency gate is disposed on the upper surface of the AlGaN barrier layer and located between the source and the p-GaN cap layer.
[0011] Optionally, the distance between the RF gate and the source is smaller than the distance between the RF gate and the drain;
[0012] The distance between the DC gate and the drain is less than the distance between the DC gate and the source.
[0013] Optionally, at the interface between the AlGaN barrier layer and the GaN channel layer, a two-dimensional electron gas is generated on the side near the GaN channel layer through piezoelectric polarization and spontaneous polarization effects.
[0014] Optionally, the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a self-supporting gallium nitride substrate.
[0015] Optionally, the buffer layer is a gallium nitride layer doped with iron or carbon, an AlGaN superlattice structure, or a GaN superlattice structure.
[0016] Optionally, the materials of the source and the drain include T, Al, Ni and Au.
[0017] Optionally, the material of the radio frequency gate includes Ni and Au.
[0018] Optionally, the thickness of the substrate is 1 mm;
[0019] The thickness of the buffer layer is 4 μm;
[0020] The thickness of the GaN channel layer is 100 nm;
[0021] The thickness of the AlGaN barrier layer is 20 nm;
[0022] The thickness of the p-GaN cap layer is 70 nm.
[0023] Optionally, the length of the source electrode is 5 μm;
[0024] The length of the radio frequency gate is 0.5 μm;
[0025] The length of the DC gate is 2 μm;
[0026] The length of the drain electrode is 5 μm.
[0027] According to the specific embodiments provided in this application, the following technical effects are disclosed:
[0028] This application provides a dual-gate enhancement-mode gallium nitride (GaN) radio frequency (RF) power transistor, which adds an RF gate and a DC gate to a conventional p-GaN gate HEMT. The RF gate is a Schottky gate structure near the source side, whose main function is to input RF signals. Due to its low parasitic capacitance and high channel carrier mobility, the transistor device has high transconductance and cutoff frequency. The DC gate is a p-GaN gate structure near the drain side, and its contact can be ohmic, Schottky, or dielectric isolation (MIS), etc. Due to the presence of the p-GaN cap layer, the DC gate can obtain a positive threshold voltage, thereby controlling the switching of the transistor device. In addition, the DC gate can also increase transconductance, improve power-added efficiency, and filter power supply noise. Therefore, the dual-gate combination of the RF gate and DC gate can simultaneously obtain several excellent electrical characteristics such as high cutoff frequency, positive threshold voltage, large breakdown voltage, and low on / off ratio, thus improving the electrical characteristics of the GaN HEMT device. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 A schematic diagram of a dual-gate enhancement-mode gallium nitride radio frequency power transistor provided in this application embodiment;
[0031] Figure 2 This is a structural schematic diagram of a cross-section 1 of a transistor provided in an embodiment of this application;
[0032] Figure 3 This is a structural schematic diagram of cross-section 2 of the transistor provided in an embodiment of this application;
[0033] Figure 4 This is a structural schematic diagram of cross-section 3 of the transistor provided in an embodiment of this application;
[0034] Figure 5 This is a structural schematic diagram of cross-section 4 of the transistor provided in an embodiment of this application.
[0035] Figure label:
[0036] Substrate—1; Buffer layer—2; GaN channel layer—3; AlGaN barrier layer—4; p-GaN cap layer—5; Source—6; RF gate—7; DC gate—8; Drain—9. Detailed Implementation
[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0039] Example
[0040] This embodiment provides a dual-gate enhancement-mode gallium nitride (GaN) radio frequency power transistor, such as Figures 1 to 5 As shown, it includes a substrate 1, a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, a p-GaN cap layer 5, a source 6, an RF gate 7, a DC gate 8, and a drain 9.
[0041] The structure comprises a substrate 1, a buffer layer 2, a GaN channel layer 3, and an AlGaN barrier layer 4, stacked sequentially from top to bottom. The substrate 1 is located at the bottom of the entire structure, providing support, and may be, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, or a self-supporting gallium nitride substrate. The buffer layer 2 is located above the substrate 1 and may be, but is not limited to, a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure. The GaN channel layer 3 is located above the buffer layer 2. The AlGaN barrier layer 4 is located above the GaN channel layer 3, and at its interface with the GaN channel layer 3, a two-dimensional electron gas 2DEG10 is generated on the side closer to the GaN channel layer 3 through piezoelectric polarization and spontaneous polarization effects.
[0042] The p-GaN cap layer 5 is located on the upper surface of the AlGaN barrier layer 4. A DC gate 8 is disposed above the p-GaN cap layer 5.
[0043] The upper surface of the AlGaN barrier layer 4 has a source 6 and a drain 9 at both ends. The radio frequency gate 7 is disposed on the upper surface of the AlGaN barrier layer 4 and is located between the source and the p-GaN cap layer.
[0044] The RF gate 7 is a Schottky gate structure located near the source side, meaning the distance between the RF gate and the source is less than the distance between the RF gate and the drain. Its main function is to input RF signals. The DC gate 8 is a pGaN gate structure located near the drain side, meaning the distance between the DC gate and the drain is less than the distance between the DC gate and the source. It functions to control device switching and filter power supply noise. The pGaN contact can be an ohmic contact, a Schottky contact, or a dielectric layer isolation (MIS) connection. The dual-gate combination of the RF gate and the DC gate can simultaneously achieve several excellent electrical characteristics, including a high cutoff frequency, a positive threshold voltage, a large breakdown voltage, and a low on / off ratio.
[0045] As an optional implementation, the thickness of the substrate is 1 mm.
[0046] As an optional implementation, the thickness of the buffer layer is 4 μm.
[0047] As an optional implementation, the thickness of the GaN channel layer is 100 nm.
[0048] As an optional implementation, the thickness of the AlGaN barrier layer is 20 nm.
[0049] As an optional implementation, the thickness of the p-GaN cap layer is 70 nm.
[0050] As an optional implementation, the length of the source electrode is 5 μm.
[0051] As an optional implementation, the length of the radio frequency gate is 0.5 μm.
[0052] As an optional implementation, the length of the DC gate is 2µm.
[0053] As an optional implementation, the length of the drain electrode is 5 μm.
[0054] As an optional implementation, the materials of the source and the drain include T, Al, Ni and Au.
[0055] As an optional implementation, the material of the radio frequency gate includes Ni and Au.
[0056] The material types and dimensions of the structures described above are merely examples and are not intended to limit the scope of this embodiment. The material types and dimensions can be adjusted according to actual needs.
[0057] The dual-gate enhancement-mode gallium nitride (GaN) RF power transistor (HMT) design in this embodiment is based on a conventional p-GaN gate HEMT. A conventional RF gate is added to the left of the p-GaN gate, utilizing the high transconductance and large saturation current of the RF gate for RF signal input. The p-GaN gate primarily functions to control device switching and filter power supply noise. The pGaN contact can be of various types, including ohmic contact, Schottky contact, and dielectric isolation (MIS). This combination simultaneously achieves several excellent electrical characteristics, such as high cutoff frequency, positive threshold voltage, large breakdown voltage, and low on / off ratio.
[0058] To obtain the aforementioned dual-gate enhancement-mode gallium nitride (GaN) RF power transistor structure, the following fabrication process is proposed:
[0059] Step (1): Select an epitaxial wafer with a pre-formed substrate 1, buffer layer 2, GaN channel layer 3, AlGaN barrier layer 4, and p-GaN cap layer 5. The substrate 1, buffer layer 2, GaN channel layer 3, AlGaN barrier layer 4, and p-GaN cap layer 5 of the epitaxial wafer are as follows: Figure 1 The positional relationships are shown.
[0060] Step (2): If the DC gate 8 uses a MIS gate contact, a dielectric layer can be deposited over the entire surface, including but not limited to aluminum oxide (Al2O3), silicon oxide (SiO2), and silicon nitride (SixN). y )wait.
[0061] Step (3): Mesa isolation step: ICP-RIE dry etching of AlGaN / GaN to the buffer layer to form electrical isolation.
[0062] Step (4): Deposit metal (e.g., Ti / Ni, TiN / Ni) on the DC gate 8, and use the gate metal as a hard mask to etch the p-GaN cap layer 5, exposing the contact area of the source and drain, leaving only the p-GaN cap layer 5 in the DC gate 8 region.
[0063] Step (5): Perform surface treatment (acid treatment: HCl, BOE) on the device after the mesa isolation is completed to remove surface oxides and reduce the surface trap state density.
[0064] Step (6): Using electron beam evaporation or magnetron sputtering, evaporate ohmic contact metal (e.g., Ti / Al / Ti / Au or Ti / Al / Ni / Au) on the source and drain electrode region windows (dielectric layer openings), and rapidly anneal to form source 6 and drain 9.
[0065] Step (7): Using electron beam evaporation or magnetron sputtering, evaporate the Schottky contact metal (e.g., Ni / Au or Ti / Au) on the gate region window to form the RF gate 7.
[0066] This application also provides an application scenario in which the aforementioned dual-gate enhancement-mode gallium nitride (GaN) RF power transistor is used. Specifically, the dual-gate enhancement-mode GaN RF power transistor provided in this embodiment can be used in a Class D switching amplifier to amplify signals while controlling switching. The DC gate performs the function of an enhancement-mode switching device, and the RF gate performs the function of signal amplification.
[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0068] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A dual-gate enhancement-mode gallium nitride (GaN) radio frequency power transistor, characterized in that, include: Substrate, buffer layer, GaN channel layer, AlGaN barrier layer, p-GaN cap layer, source, RF gate, DC gate and drain; The substrate, the buffer layer, the GaN channel layer, and the AlGaN barrier layer are stacked sequentially from bottom to top; The p-GaN cap layer is disposed on the upper surface of the AlGaN barrier layer; The DC gate is disposed on the upper surface of the p-GaN cap layer; The source and the drain are respectively located at both ends of the upper surface of the AlGaN barrier layer; The radio frequency gate is disposed on the upper surface of the AlGaN barrier layer and located between the source and the p-GaN cap layer; the radio frequency gate and the source are spaced apart and independently disposed; The radio frequency gate is a Schottky gate structure located near the source side. Its main function is to input radio frequency signals. The radio frequency gate can improve the transconductance and cutoff frequency of transistor devices. The DC gate is a p-GaN gate structure located near the drain side. Due to the presence of the p-GaN cap layer, the DC gate obtains a positive threshold voltage, thereby controlling the switching of the transistor device. The DC gate also plays a role in increasing transconductance, improving power-added efficiency, and filtering power supply noise. The dual-gate combination of RF gate and DC gate can improve transconductance and cutoff frequency, and has a positive threshold voltage.
2. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, The distance between the RF gate and the source is smaller than the distance between the RF gate and the drain; The distance between the DC gate and the drain is less than the distance between the DC gate and the source.
3. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, At the interface between the AlGaN barrier layer and the GaN channel layer, a two-dimensional electron gas is generated on the side near the GaN channel layer through piezoelectric polarization and spontaneous polarization effects.
4. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, The substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a self-supporting gallium nitride substrate.
5. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, The buffer layer is a gallium nitride layer doped with iron or carbon, an AlGaN superlattice structure, or a GaN superlattice structure.
6. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, The materials of the source and the drain include Ti, Al, Ni and Au.
7. The double-recessed enhancement-mode gallium nitride RF power transistor of claim 1, wherein, The materials of the radio frequency gate include Ni and Au.
8. The dual-gate enhancement-mode gallium nitride RF power transistor according to claim 1, characterized in that, The thickness of the substrate is 1 mm; The thickness of the buffer layer is 4 μm; The thickness of the GaN channel layer is 100 nm; The thickness of the AlGaN barrier layer is 20 nm; The thickness of the p-GaN cap layer is 70 nm.
9. The dual-gate enhancement-mode gallium nitride RF power transistor according to claim 1, characterized in that, The length of the source electrode is 5 μm; The length of the radio frequency gate is 0.5 μm; The length of the DC gate is 2 μm; The length of the drain electrode is 5 μm.