A low voltage diode and a method for preparing the same

Abstract

A low-voltage diode disclosed in the present invention comprises an N+ single crystal, an epitaxial N-layer, an N-region, an N-region, a P+ region, a dielectric layer and polysilicon formed on the surface of the N+ single crystal, a first metal layer arranged above the polysilicon and a second metal layer arranged below the N+ single crystal. A low-voltage diode of the present invention can obtain a lower, more stable and consistent breakdown voltage and a lower leakage current through a new structure and process design under the condition that the chip area remains unchanged.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and mainly relates to a low-voltage diode and a preparation method thereof. Background Art

[0002] Figure 3 The structure diagram of a low-voltage diode of conventional process is shown. Above the N+ single crystal wafer 112 is the P+ region 113. 111 and 115 are metal regions, representing the cathode and anode of the diode respectively. 114a and 114b are dielectric layers, which mainly serve the isolation and protection functions.

[0003] Figure 2 Curve a in the middle shows an IV characteristic curve of a low-voltage diode of a conventional process. When 115 is at a high potential and 111 is grounded, the current flows from the P+ region 113 through the N+ single crystal 112, showing the forward conduction characteristic of the diode. When 111 is at a high potential and 115 is grounded, the current flows from the N+ single crystal 112 through the P+ region 113, showing the low-voltage breakdown characteristic of the diode. The breakdown voltage of the diode is determined by the NP junction formed by the N+ single crystal 112 and the P+ region 113. The product parameters that can be obtained with this structure are: VRWM=3.3V, VBR(IT=5mA)=5.0~6.0V, IR(VR=3.3V)≤10μA.

[0004] A conventional low-voltage diode is formed by front-side photolithography on an N+ single crystal wafer 112 at 0.001-0.005Ω.cm, followed by 5E15-1E16cm-2, 50-100KeV boron implantation, and 1000-1100℃ / 60-120min / N2 boron drive to form a P+ region 113. The breakdown voltage of the NP junction formed by the heavily doped N+ single crystal wafer 112 and the high-concentration P+ region 113 can be 5-6V, but since the junction depth of the PN junction is relatively deep, generally 3-5μm, and the concentrations on both sides are very high, the corresponding leakage current is very large, generally 5-10μA. Since the resistivity tolerance of the N+ single crystal wafer 112 is ±20%, the corresponding breakdown voltage accuracy can be 10%, and the voltage range is relatively wide. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a new technical solution, which can provide a low-voltage diode. Under the condition of unchanged chip area, a lower breakdown voltage and lower leakage current can be obtained through a new structure and process design.

[0006] To achieve the above objectives, on the one hand, a low-voltage diode of the present invention includes an N+ single crystal wafer, an epitaxial N-- layer, an N-region, an N-region, a P+ region, a dielectric layer and polycrystalline silicon formed on the surface of the N+ single crystal wafer, a first metal layer arranged above the polycrystalline silicon and a second metal layer arranged below the N+ single crystal wafer.

[0007] On the other hand, the technical solution adopted by the present invention is a method for preparing a low-voltage diode, comprising the following steps:

[0008] Step 01, prepare N+ single crystal wafer and grow N-- layer;

[0009] Step 02, grow a field oxide layer, perform front-side photolithography, and form an N-region pattern;

[0010] Step 03: Phosphorus implantation, advancement, forming an N-region;

[0011] Step 04: Photolithography on the front side to form the P+ region implantation pattern;

[0012] Step 05, depositing undoped polysilicon;

[0013] Step 06: implant boron on the front side and push forward to form a P+ region;

[0014] Step 07: Deposit a dielectric layer on the front side, perform photolithography on the front side, and form a contact hole area;

[0015] Step 08: Evaporate metal on the front side, perform photolithography on the front side, and perform alloying to form a metal area;

[0016] Step 09: Thin the back side and evaporate metal on the back side to form a metal area.

[0017] In some embodiments, the crystal orientation of the N+ single crystal in step 01 is <111> The impurity is arsenic, the resistivity is 0.002~0.006Ω·cm, the resistivity of the N-- region is 0.01~0.1Ω·cm, and the thickness is 5~10μm.

[0018] In some embodiments, the thickness of the field oxide layer in step 02 is 6000-8000Å.

[0019] In some embodiments, the phosphorus implantation dose in step 03 is 2E15-5E15cm -2 , the energy is 40~100KeV, the temperature conditions for phosphorus advancement are 1000~1100℃, and the time is 60~180min to form an N-region.

[0020] In some embodiments, the thickness of the undoped polysilicon in step 05 is 0.5-0.8 μm.

[0021] In some embodiments, the boron implantation dose in step 06 is 4E15-8E15cm -2 , the energy is 40~120KeV, the temperature conditions of boron advancement are 900~1050℃, the time is 30~120min, and a P+ region is formed.

[0022] In some embodiments, the dielectric layer in step 07 is tetraethoxysilane TEOS, and has a thickness of 5000-10000Å.

[0023] In some embodiments, the metal evaporated on the front side in step 08 is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 2-5 μm, and the alloy temperature is 360-430° C. for 25-45 min.

[0024] In some embodiments, the back surface in step 09 is thinned to a thickness of 150-200 μm, and the back surface evaporated metal is Ti / Ni / Ag with a thickness of 0.1-0.3 μm / 0.2-0.5 μm / 1.0-1.5 μm.

[0025] The advantages of the present invention are:

[0026] 1. The present invention provides a new technical solution, which can provide a low-voltage diode. Under the condition of unchanged chip area, a lower, more stable and consistent breakdown voltage and lower leakage current can be obtained through new structure and process design.

[0027] 2. Different from the conventional structure, the processing material of the low-voltage diode of the present invention is introduced into the N-- region 102 epitaxially on the N+ single crystal 101, and the NP junction between the N-- region 102 and the P+ region 104 is established. The resistivity of the N-- region is 0.01-0.1Ω·cm, and the corresponding impurity concentration is low, which reduces the leakage current of the corresponding NP junction, and the leakage current can be controlled within 2μA. In addition, by depositing undoped polysilicon 107, front boron implantation, and advancement, a P+ region 104 with a shallow junction depth that can be stably controlled is formed, and the breakdown voltage is controlled by forming an NP junction between the N- region 103a, 103b and the P+ region 104. The impurity concentration tolerance of the N- region 103a, 103b and the P+ region 104 is 5%. By controlling the junction depth of the P+ region to 0.6-0.8μm, the corresponding breakdown voltage can be within the range of 4.8-5.4V, the breakdown voltage accuracy can be 5%, and the breakdown voltage is more stable and consistent. The product parameters that can be obtained by the structure of the present invention can be: VRWM=3.3V, VBR(IT=5mA)=4.8~5.4V, IR(VR=3.3V)≤2μA. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly understand the purpose and advantages of the present invention, the following will be described in detail with reference to the accompanying drawings, in which:

[0029] Figure 1 The figure is a structural diagram of a low voltage diode of the present invention.

[0030] Figure 2 The IV characteristic curve diagram of a low voltage diode of the present invention and a low voltage diode of a conventional process is shown in FIG.

[0031] Figure 3 This is a structural diagram of a low-voltage diode using conventional technology.

[0032] Figure 4 This is the first step of the process of a low voltage diode of the present invention, namely preparing an N+ single crystal wafer 101 and epitaxially growing an N-- layer 102.

[0033] Figure 5 This is the second step of the process of the low voltage diode of the present invention, namely growing field oxide layers 105a, 105b, 105c, and performing front-side photolithography to form N-region 103a, 103b patterns 118a, 118b.

[0034] Figure 6 This is the third step of the process of the low voltage diode of the present invention, namely, phosphorus implantation and advancement to form N-regions 103a and 103b.

[0035] Figure 7 This is the fourth step of the low voltage diode process of the present invention, namely, front side photolithography to form a P+ region injection region pattern 117.

[0036] Figure 8 This is the fifth step of the low voltage diode process of the present invention, namely, depositing undoped polysilicon 107.

[0037] Fig. 9 This is the sixth step of the low voltage diode process of the present invention, namely, front boron implantation and advancement to form a P+ region 104 .

[0038] Fig.10 This is the seventh step of the process of a low voltage diode of the present invention, namely, depositing dielectric layers 108a and 108b on the front side, and performing photolithography on the front side to form a contact hole area 116.

[0039] Fig.11 This is the eighth step of the low voltage diode process of the present invention, namely, evaporating metal from the front side, photolithography from the front side, alloying, and forming the metal region 109 .

[0040] Fig.12 This is the ninth step of the process of a low voltage diode of the present invention, namely, thinning the back side and evaporating metal on the back side to form a metal region 110 . DETAILED DESCRIPTION

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and implementation modes. A detailed description is given by taking the 3.3V voltage level as an example.

[0042] This implementation case uses a 3.3V voltage level for detailed explanation.

[0043] Figures 4 to 12 A process for manufacturing a low voltage diode of the present invention is provided.

[0044] First, the crystal orientation of the N+ single crystal wafer 101 is <111> The impurity is arsenic, and the resistivity is 0.003-0.006Ω.cm. The N-- layer 102 is epitaxially grown, and the resistivity of the N-- layer 102 is 0.05-0.1Ω.cm, and the thickness is 5-8μm.

[0045] Grow field oxide layers 105a, 105b, 105c, with a thickness of 6000~7000Å. Photolithography is performed on the front side to form N-regions 103a, 103b patterns 118a, 118b. Phosphorus implantation dose is 2E15~4E15cm -2 The energy is 40~60KeV, the temperature condition of phosphorus advancement is 1000~1050℃, and the time is 60~120min to form N-regions 103a and 103b.

[0046] The front side is photolithographically processed to form a P+ region implantation region pattern 117. Undoped polysilicon 107 is deposited. The thickness of the undoped polysilicon is 0.5-0.7 μm.

[0047] Boron is implanted on the front side and pushed forward to form P+ region 104. The boron implantation dose is 4E15~6E15cm -2 The energy is 40~80KeV, the temperature condition of boron propulsion is 950~1050℃, and the time is 60~120min.

[0048] Dielectric layers 108a and 108b are deposited on the front side, and photolithography is performed on the front side to form a contact hole region 116. The dielectric layers 108a and 108b are made of tetraethoxysilane TEOS, and have a thickness of 5000-8000Å.

[0049] The metal is evaporated on the front side, and the front side is photolithographically processed and alloyed to form the metal area 109. The metal evaporated on the front side is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 3-5 μm. The temperature of the alloy is 400-430°C, and the time is 25-45 minutes.

[0050] The back side is thinned and metal is evaporated on the back side to form a metal region 110. The back side is thinned to a thickness of 180-200 μm, and the evaporated metal on the back side is Ti / Ni / Ag with a thickness of 0.1 μm / 0.2 μm / 1.0 μm.

[0051] Figure 1What is shown is a structural diagram of a semiconductor structure of the present invention, in which an N-- region 102 is epitaxially grown on an N+ single crystal wafer 101, and above the N-- region 102 are N- region 103a, N- region 103b, and P+ region 104, and above the P+ region 104 and dielectric layers 106a and 106b is polysilicon 107, 110 and 109 are metal regions, representing the cathode and anode of the structure, respectively, and 105a, 105b, 106a, and 106b are dielectric layers, which mainly serve the function of isolation and protection.

[0052] Figure 2 The curve b in the middle shows an IV characteristic curve of a low voltage diode of the present invention. When 109 is at a high potential and 110 is grounded, the current flows from the polysilicon 107 through the P+ region 104, the N-- region 102, and the N+ region 101, showing the forward conduction characteristic of the diode. When 110 is at a high potential and 109 is grounded, the current flows from the N+ region 101 through the N-- region 102, the N-- regions 103a and 103b, the P+ region 104, and the polysilicon 107, showing the low voltage breakdown characteristic of the diode.

[0053] Figures 4 to 12 The invention discloses a process flow of a low-voltage diode. Figure 4 The N-- layer 102 is epitaxially grown on the N+ single crystal wafer 101.

[0054] Figure 5 Field oxide layers 105a, 105b, 105c are grown, and front-side photolithography is performed to form N-region 103a, 103b patterns 118a, 118b. Figure 6 Phosphorus is implanted and pushed forward to form N-regions 103a, 103b, dielectric layers 106a, 106b, Figure 7 The front side is photolithographically processed to form a P+ region implantation region 117 . Figure 8 is to deposit polysilicon 107, Fig. 9 It is the front boron implantation, advancing, forming the P+ region 104, Fig.10 The dielectric layers 108a and 108b are deposited, and the front side is photolithographically formed to form the contact hole region 116. Fig.11 The metal is evaporated on the front side, and then lithography and alloying are performed on the front side to form the metal area 109. Fig.12 The back side is thinned and metal is evaporated on the back side to form a metal region 110 .

[0055] Different from the conventional structure, the processing material of the low-voltage diode of the present invention is introduced into the epitaxial N--region 102 on the N+ single crystal 101, and the NP junction between the N--region 102 and the P+ region 104 is established. The resistivity of the N--region is 0.01-0.1Ω.cm, and the corresponding impurity concentration is low, which reduces the leakage current of the corresponding NP junction, and the leakage current can be controlled within 2μA. In addition, by depositing undoped polysilicon 107, front boron implantation, and advancement, a P+ region 104 with a shallow junction depth that can be stably controlled is formed, and the breakdown voltage is controlled by forming an NP junction between the N-region 103a, 103b and the P+ region 104. The impurity concentration tolerance of the N-region 103a, 103b and the P+ region 104 is 5%. By controlling the junction depth of the P+ region to 0.6-0.8μm, the corresponding breakdown voltage can be within the range of 4.8-5.4V, the breakdown voltage accuracy can be 5%, and the breakdown voltage is more stable and consistent. The product parameters that can be obtained by the structure of the present invention can be: VRWM=3.3V, VBR(IT=5mA)=4.8~5.4V, IR(VR=3.3V)≤2μA.

[0056] Finally, it should be noted that: technicians in this industry should understand that the present invention is not limited to the above-mentioned implementation cases. The above-mentioned embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which shall fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for preparing a low voltage diode, characterized in that: The following steps are involved: Step 01, prepare an N+ single crystal wafer, and grow an epitaxial N-- layer, wherein the resistivity of the N-- layer is 0.01-0.1Ω·cm; Step 02, grow a field oxide layer, perform front-side photolithography, and form a first pattern in the N-region and a second pattern in the N-region; Step 03: Phosphorus implantation, advancement, forming a first N-region and a second N-region; Step 04: Photolithography on the front side to form the P+ region injection area pattern; Step 05, depositing undoped polysilicon; Step 06: implant boron on the front side and push forward to form a P+ region, wherein the impurity concentration tolerance between the first N-region, the second N-region and the P+ region is 5%, and the junction depth of the P+ region is 0.6-0.8 μm; Step 07: Deposit a dielectric layer on the front side, perform photolithography on the front side, and form a contact hole area; Step 08: Evaporate metal on the front side, perform photolithography on the front side, and perform alloying to form a metal area; Step 09: Thin the back side and evaporate metal on the back side to form a metal area.

2. The preparation method according to claim 1, characterized in that: The crystal orientation of the N+ single crystal in step 01 is <111> The impurity is arsenic, the resistivity is 0.002~0.006Ω·cm, and the thickness is 5~10μm.

3. The preparation method according to claim 1, characterized in that: The thickness of the field oxide layer in step 02 is 6000-8000Å.

4. The preparation method according to claim 1, characterized in that: The phosphorus implantation dosage in step 03 is 2E15~5E15cm -2 The energy is 40~100KeV, the temperature condition of phosphorus propulsion is 1000~1100℃, and the time is 60~180min.

5. The preparation method according to claim 1, characterized in that: The thickness of the undoped polysilicon in step 05 is 0.5-0.8 μm.

6. The preparation method according to claim 1, characterized in that: The boron implantation dose in step 06 is 4E15~8E15cm -2 The energy is 40~120KeV, the temperature conditions of boron propulsion are 900~1050℃, and the time is 30~120min.

7. The preparation method according to claim 1, characterized in that: The dielectric layer in step 07 is tetraethoxysilane TEOS, and has a thickness of 5000-10000Å.

8. The preparation method according to claim 1, characterized in that: The metal evaporated on the front side in step 08 is aluminum or aluminum copper or aluminum silicon copper, with a thickness of 2-5 μm, an alloy temperature of 360-430° C., and a time of 25-45 min.

9. The preparation method according to claim 1, characterized in that: The back surface in step 09 is thinned to a thickness of 150-200 μm, and the evaporated metal on the back surface is Ti / Ni / Ag with a thickness of 0.1-0.3 μm / 0.2-0.5 μm / 1.0-1.5 μm.

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