Buck converter and control circuit and control method thereof

Abstract

The invention provides a buck converter and a control circuit and a control method thereof, and the control circuit comprises a turn-off control unit which samples an output voltage to obtain a feedback signal, carries out the error amplification of the feedback signal and a first reference voltage to obtain a compensation voltage, and generates a turn-off control signal according to an inductive current, the compensation voltage and a minimum conduction time signal; an underclocking control unit which generates an underclocking control signal based on a comparison result of the compensation voltage and the second reference voltage; the conduction control unit is used for generating a fixed-frequency control signal according to the clock signal and the first driving signal, and generating a conduction control signal according to the fixed-frequency control signal and the underclocking control signal; and the driving unit receives the turn-on control signal and the turn-off control signal to generate a first driving signal to control the turn-on or turn-off of the first switching tube. According to the invention, the frequency reduction control unit is arranged to realize constant-voltage output based on whether the output feedback control is inserted into the frequency reduction control in the fixed-frequency control mode or not.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to a buck converter and a control circuit and a control method thereof. Background Art

[0002] Switching power supply is a kind of power supply that uses modern power electronics technology to control the time ratio of the switch tube to be turned on and off to maintain a stable output voltage. Switching power supply is widely used in industrial automation control, military equipment, scientific research equipment, LED (Light Emitting Diode) lighting, industrial control equipment, communication equipment, power equipment, instrumentation, medical equipment and semiconductor refrigeration and heating. Among them, the buck converter has the characteristics of simple control and low cost, and is widely used in the power supply circuits of various electronic equipment.

[0003] In order to meet different application scenarios, buck converters with wide input range are widely used. However, in practical applications, due to the limitation of minimum duty cycle, when the input voltage is high, the output voltage will increase as the input voltage increases. That is, due to the limitation of minimum duty cycle, buck converters cannot achieve a wider input voltage range.

[0004] In order to solve the above problems, the present disclosure provides a buck converter with a wide range of input voltage and a control circuit and a control method thereof. Summary of the invention

[0005] In view of the above problems, an object of the present disclosure is to provide a buck converter and a control circuit and a control method thereof, so as to realize a switching power supply with a wide input range.

[0006] According to a first aspect of the present disclosure, a control circuit of a buck converter is provided, comprising:

[0007] a shutdown control unit, sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and the first reference voltage to obtain a compensation voltage, generating a minimum on-time signal based on the first drive signal, and generating a shutdown control signal according to the inductor current, the compensation voltage and the minimum on-time signal;

[0008] A frequency reduction control unit, which generates a frequency reduction control signal based on a comparison result between the compensation voltage and the second reference voltage;

[0009] a conduction control unit, which generates a fixed-frequency control signal according to the clock signal and the first drive signal, and generates a conduction control signal according to the fixed-frequency control signal and the reduced-frequency control signal; and

[0010] The driving unit receives the on-control signal and the off-control signal, generates a first driving signal, and controls the first switch tube to be on or off.

[0011] Optionally, the conduction control unit generates a fixed-frequency control signal according to the clock signal and the first drive signal, and generates a conduction control signal according to the fixed-frequency control signal, the frequency reduction control signal and the shutdown control signal.

[0012] Optionally,

[0013] When the compensation voltage is greater than the second reference voltage, the frequency reduction control signal releases the shielding of the fixed frequency control signal, the control circuit of the buck converter operates in a fixed frequency mode, and the first switch tube is turned on when the effective edge of the clock signal arrives;

[0014] When the compensation voltage is less than the second reference voltage, the control circuit of the buck converter operates in a frequency reduction mode;

[0015] The switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

[0016] Optionally, a turn-off time of the first switch tube in the frequency reduction mode is greater than a turn-off time of the first switch tube in the fixed frequency mode.

[0017] Optionally, in the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage is less than the second reference voltage, the frequency reduction control signal shields the fixed frequency control signal to extend the turn-off time of the first switch tube, and when the compensation voltage is equal to the second reference voltage, the frequency reduction control signal is unshielded and the first switch tube is turned on.

[0018] Optionally, after the first switch tube is turned on for a minimum on-time and when a current sampling signal representing the inductor current reaches a compensation voltage, the first switch tube is turned off.

[0019] Optionally, the frequency reduction control unit outputs the frequency reduction control signal in an invalid state to release the shielding of the fixed frequency control signal when the compensation voltage is greater than or equal to the second reference voltage, and outputs the frequency reduction control signal in a valid state to shield the fixed frequency control signal when the compensation voltage is less than the second reference voltage.

[0020] Optionally, the second reference voltage is a constant voltage or a ramp signal.

[0021] Optionally, the conduction control unit generates the fixed frequency control signal in a valid state when the effective edge of the clock signal arrives, and resets the fixed frequency control signal after the first drive signal jumps to the valid state and lasts for a first time.

[0022] And the conduction control signal in the effective state is generated according to the fixed-frequency control signal in the effective state and the reduced-frequency control signal in the invalid state, otherwise the conduction control signal in the invalid state is generated.

[0023] Optionally, the conduction control unit generates the fixed frequency control signal in a valid state when the effective edge of the clock signal arrives, and resets the fixed frequency control signal after the first drive signal jumps to the valid state and lasts for a first time.

[0024] And the conduction control signal of the effective state is generated according to the fixed frequency control signal of the effective state, the frequency reduction control signal of the invalid state and the shutdown control signal of the invalid state, otherwise the conduction control signal of the invalid state is generated.

[0025] Optionally, the shutdown control unit generates a shutdown control signal in a valid state when the current sampling signal reaches the compensation voltage and the minimum on-time signal is in an invalid state, otherwise it generates a shutdown control signal in an invalid state.

[0026] The minimum on-time signal is an inverted signal of the first driving signal after the rising edge is delayed.

[0027] Optionally, the driving unit generates a first driving signal of an invalid state according to an off control signal of a valid state and an on control signal of an invalid state, and generates a first driving signal of a valid state according to an on control signal of a valid state and an off control signal of an invalid state, and keeps the first driving signal at a previous level unchanged according to the on control signal of an invalid state and an off control signal of an invalid state.

[0028] Optionally, the shutdown control unit includes:

[0029] A current sampling unit, sampling the inductor current to obtain the current sampling signal;

[0030] A voltage sampling unit, sampling the output voltage to obtain the feedback signal;

[0031] a minimum on-time signal generating unit, which delays and inverts the rising edge of the first driving signal to generate the minimum on-time signal;

[0032] a first operational amplifier, wherein a first input terminal of the first operational amplifier receives the first reference voltage, a second input terminal of the first operational amplifier receives the feedback signal, and an output terminal of the first operational amplifier outputs the compensation voltage;

[0033] A first comparator, wherein a first input terminal of the first comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the first comparator receives the compensation voltage, and an output terminal of the first comparator outputs an intermediate signal;

[0034] A first NOT gate, an input terminal of which receives the minimum on-time signal; and

[0035] A first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the first comparator to receive the intermediate signal, a second input terminal of the first AND gate is connected to an output terminal of the first NOT gate, and an output terminal of the first AND gate outputs the shutdown control signal.

[0036] Optionally, the conduction control unit includes:

[0037] A monostable unit, outputting a delay signal in which the first driving signal is delayed by a first time;

[0038] A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the fixed-frequency control signal; and

[0039] A second AND gate, wherein the first input terminal of the second AND gate is connected to the output terminal of the trigger to receive the fixed frequency control signal, the second input terminal of the second AND gate receives the reduced frequency control signal, and the output terminal of the second AND gate outputs the conduction control signal.

[0040] Optionally, the conduction control unit includes:

[0041] A monostable unit, outputting a delay signal in which the first driving signal is delayed by a first time;

[0042] A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the fixed-frequency control signal;

[0043] a second NOT gate, an input terminal of the second NOT gate receiving the shutdown control signal; and

[0044] A third AND gate, wherein the first input terminal of the third AND gate is connected to the output terminal of the second NOT gate, the second input terminal of the third AND gate is connected to the output terminal of the trigger to receive the fixed frequency control signal, the third input terminal of the third AND gate receives the reduced frequency control signal, and the output terminal of the third AND gate outputs the conduction control signal.

[0045] Optionally, the driving unit comprises:

[0046] A latch, wherein the R end of the latch receives the shutdown control signal, the S end of the latch receives the conduction control signal, the first output end of the latch outputs the first drive signal, and the second output end of the latch outputs the second drive signal, wherein the second drive signal is an inverted signal of the first drive signal.

[0047] Optionally, the frequency reduction control unit includes:

[0048] A second comparator, wherein a first input terminal of the second comparator receives the compensation voltage, a second input terminal of the second comparator receives the fixed value voltage, and an output terminal of the second comparator outputs the frequency reduction control signal.

[0049] Optionally, the frequency reduction control unit includes:

[0050] a ramp signal generating unit, comprising a switch, a current source, a capacitor, and a second operational amplifier, wherein a first end of the switch is connected to a first end of the current source and a first end of the capacitor and provides an intermediate voltage, a second end of the switch is connected to a second end of the current source and a second end of the capacitor and is grounded, a control of the switch receives a first drive signal, a first input end of the second operational amplifier receives a third reference voltage, a second input end of the second operational amplifier receives the intermediate voltage, and an output end of the second operational amplifier outputs a ramp signal; and

[0051] A third comparator, wherein a first input terminal of the third comparator receives the compensation voltage, a second input terminal of the third comparator receives the ramp signal, and an output terminal of the third comparator outputs the frequency reduction control signal.

[0052] According to a second aspect of the present disclosure, a buck converter is provided, comprising:

[0053] A first capacitor, receiving an input voltage;

[0054] The second capacitor outputs the output voltage;

[0055] inductance;

[0056] A control circuit as described above;

[0057] a first switch tube, wherein a first end of the first switch tube is connected to a first end of the first capacitor, a second end of the first switch tube is connected to a first end of the second capacitor via the inductor, and a control end of the first switch tube is connected to a control circuit to receive a first drive signal; and

[0058] A second switch tube, wherein the first end of the second switch tube is connected to the second end of the first switch tube and the inductor, the second end of the second switch tube is connected to the second end of the second capacitor and the second end of the first capacitor and is grounded, and the control end of the second switch tube is connected to the control circuit to receive an inverted signal of the first drive signal.

[0059] According to a third aspect of the present disclosure, a control method for a buck converter is provided, comprising:

[0060] Sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference voltage to obtain a compensation voltage, generating a minimum on-time signal based on the first drive signal, and generating a shutdown control signal according to the inductor current, the compensation voltage and the minimum on-time signal;

[0061] generating a frequency reduction control signal based on a comparison result between the compensation voltage and the second reference voltage;

[0062] generating a fixed-frequency control signal according to the clock signal and the first driving signal, and generating a conduction control signal according to the fixed-frequency control signal and the reduced-frequency control signal; and

[0063] A first driving signal is generated according to the on-control signal and the off-control signal to control the first switch tube to be on or off.

[0064] Optionally, it also includes:

[0065] A conduction control signal is generated according to the fixed-frequency control signal, the reduced-frequency control signal and the shutdown control signal.

[0066] Optionally, when the compensation voltage is greater than the second reference voltage, the frequency reduction control signal releases the shielding of the fixed frequency control signal, the control circuit of the buck converter operates in a fixed frequency mode, and the first switch tube is turned on when the effective edge of the clock signal arrives;

[0067] When the compensation voltage is less than the second reference voltage, the control circuit of the buck converter operates in a frequency reduction mode;

[0068] The switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

[0069] Optionally, it also includes:

[0070] The turn-off time of the first switch tube in the frequency reduction mode is greater than the turn-off time of the first switch tube in the fixed frequency mode.

[0071] Optionally, in the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage is less than the second reference voltage, the frequency reduction control signal shields the fixed frequency control signal to extend the turn-off time of the first switch tube, and when the compensation voltage is equal to the second reference voltage, the frequency reduction control signal is unshielded and the first switch tube is turned on.

[0072] Optionally, after the first switch tube is turned on for a minimum on-time and when a current sampling signal representing the inductor current reaches a compensation voltage, the first switch tube is turned off.

[0073] The buck converter and its control circuit and control method provided by the present disclosure are configured to output a frequency reduction control signal based on output feedback to control whether to insert the frequency reduction control in the fixed frequency control mode to achieve constant voltage output. In the frequency reduction control mode, the present disclosure shields the fixed frequency control signal by generating a frequency reduction control signal to delay the triggering of the conduction control signal, so as to increase the off time in the switching cycle so as to reduce the switching frequency to achieve constant voltage output under high input. In this way, the buck converter can achieve constant voltage output even in a high input range, and realize constant voltage application with a wider input voltage range.

[0074] In addition, the present disclosure uses a fixed frequency combined with a reduced frequency control method, which is not limited by the minimum on-time limit, which can avoid reducing the stability of the power supply due to process limitations, and does not require the replacement of higher performance components. In addition, the present disclosure can ensure the minimum on-time, thereby preventing the buck converter from being triggered by mistake.

[0075] Furthermore, the frequency reduction control unit of the present disclosure compares the compensation voltage with the ramp signal to control whether to enter the frequency reduction mode, thereby avoiding subharmonic oscillation when there is a slight disturbance in the output feedback (compensation voltage), thereby ensuring the stability of the buck converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0077] Figure 1 A schematic diagram showing the structure of a buck converter provided by an embodiment of the present disclosure is shown;

[0078] Figure 2 A schematic diagram showing a control circuit of a buck converter provided by an embodiment of the present disclosure is shown;

[0079] Figure 3 A schematic diagram showing a control circuit of another buck converter provided by an embodiment of the present disclosure;

[0080] Figure 4A waveform diagram showing another control circuit of a buck converter provided by an embodiment of the present disclosure;

[0081] Figure 5 A schematic diagram showing another control circuit of a buck converter provided by an embodiment of the present disclosure is shown;

[0082] Figure 6 A schematic flow chart showing a control method of a buck converter provided by an embodiment of the present disclosure;

[0083] Figure 7 A flow chart showing another control method for a buck converter provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0084] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0085] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.

[0086] Figure 1 A schematic structural diagram of a buck converter provided in an embodiment of the present disclosure is shown. Figure 2 A schematic diagram of a control circuit of a buck converter provided by an embodiment of the present disclosure is shown. Figure 3 A schematic diagram of a control circuit of another buck converter provided by an embodiment of the present disclosure is shown. Figure 4 A waveform diagram of a control circuit of another buck converter provided in an embodiment of the present disclosure is shown.

[0087] like Figure 1 As shown, the buck converter includes a first switch tube Q1, a second switch tube Q2, a first capacitor C1, a second capacitor C2, an inductor Lm, and a control circuit 100.

[0088] The two ends of the first capacitor C1 receive the input voltage Vin, the first end of the first capacitor C1 is connected to the first end of the first switch tube Q1, and the second end of the first capacitor C1 is grounded. The second end of the first switch tube Q1 is connected to the first end of the inductor Lm, and the control end of the first switch tube Q1 is connected to the control circuit 100. The second end of the inductor Lm is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 is grounded, and the two ends of the second capacitor C2 output the output voltage Vout. The first end of the second switch tube Q2 is connected to the second end of the first switch tube Q1 and the first end of the inductor Lm, the second end of the second switch tube Q2 is grounded, and the control end of the second switch tube Q2 is connected to the control circuit 100.

[0089] The control circuit 100 receives the output voltage Vout, and is connected to the connection node of the first switch tube Q1 and the inductor Lm to receive the inductor current IL, and is used to provide a first drive signal to the first switch tube Q1 to control the first switch tube Q1 to be turned on or off, and to provide a second drive signal to the second switch tube Q2 to control the second switch tube Q2 to be turned on or off, thereby realizing the constant voltage output of the buck converter. The first drive signal and the second drive signal are mutually inverted signals. The control circuit 100 realizes constant voltage output by controlling the first switch tube Q1 and the second switch tube Q2 to be turned on alternately to achieve synchronous control.

[0090] Furthermore, in each switching cycle of the buck converter disclosed in the present invention, the control circuit 100 is used to control the first switch tube Q1 to be turned on and the second switch tube Q2 to be turned off, thereby causing the current IL of the inductor Lm to increase. When the inductor current IL reaches a preset value, the control circuit 100 controls the first switch tube Q1 to be turned off and the second switch tube Q2 to be turned on, and the buck converter enters the freewheeling stage. The buck converter achieves a constant output through the above control.

[0091] Furthermore, the output voltage Vout of the buck converter is Vin*Ton / (Ton+Toff), where Vin is the input voltage, Ton is the on-time of the first switch tube Q1, and Toff is the off-time of the first switch tube Q1. To ensure the circuit safety and stability of the buck converter, the on-time of the first switch tube Q1 should be limited by the minimum on-time. Under the constant frequency control mode, the value of Ton+Toff is constant, and when Ton is reduced to the minimum on-time, it cannot be reduced any further. To ensure the constant voltage output, the range of the input voltage Vin of the buck converter is limited. When the input voltage Vin is higher, the output voltage Vout will increase as the input voltage Vin increases.

[0092] In order to solve the above problems, the control circuit 100 in the buck converter of the present application determines whether to delay turning on the first switch Q1 through frequency reduction control based on output feedback on the basis of fixed frequency control, so that the buck converter can still maintain a constant voltage output when the input voltage increases.

[0093] It should be noted that the first end of the first switch tube Q1 and the second switch tube Q2 is, for example, a drain end of a transistor, the second end of the first switch tube Q1 and the second switch tube Q2 is, for example, a source end of a transistor, and the control end of the first switch tube Q1 and the second switch tube Q2 is, for example, a gate end of a transistor. In other embodiments, the first end of the first switch tube Q1 and the second switch tube Q2 may also be a source end of a transistor, and the second end of the first switch tube Q1 and the second switch tube Q2 may also be a drain end of a transistor.

[0094] like Figure 2As shown, the control circuit 300 of the buck converter includes a turn-on control unit 312 , a turn-off control unit 111 , a driving unit 113 and a frequency reduction control unit 120 .

[0095] like Figure 3 As shown, the control circuit 100 of the buck converter includes a turn-on control unit 112 , a turn-off control unit 111 , a driving unit 113 and a frequency reduction control unit 120 .

[0096] The shutdown control unit 111 samples the output voltage Vout of the buck converter to obtain a feedback signal Vfb, performs error amplification on the feedback signal Vfb and the first reference voltage Vref1 to obtain a compensation voltage COMP, generates a minimum on-time signal HSonn based on the first drive signal VGH, and generates a shutdown control signal Vgr according to the inductor current IL, the compensation voltage COMP and the minimum on-time signal HSonn.

[0097] The frequency reduction control unit 120 generates a frequency reduction control signal DOVP based on a comparison result between the compensation voltage COMP and the second reference voltage Vref2 .

[0098] The conduction control unit 312 generates a fixed frequency control signal SET according to the first driving signal VGH and the clock signal CLK, and generates a conduction control signal Vgs according to the fixed frequency control signal SET and the reduced frequency control signal DOVP.

[0099] In other embodiments, the conduction control unit 112 generates a fixed frequency control signal SET according to the first driving signal VGH and the clock signal CLK, and generates a conduction control signal Vgs according to the fixed frequency control signal SET, the reduced frequency control signal DOVP, and the shutdown control signal Vgr.

[0100] The driving unit 113 receives the on-control signal Vgs and the off-control signal Vgr, generates a first driving signal VGH, and controls the first switch tube Q1 to be on or off.

[0101] Further, when the compensation voltage COMP is greater than the second reference voltage Vref2, the frequency reduction control signal DOVP releases the shielding of the fixed frequency control signal SET, and the control circuit of the buck converter operates in the fixed frequency mode, and turns on the first switch tube when the effective edge of the clock signal CLK arrives. When the compensation voltage COMP is less than the second reference voltage Vref2, the control circuit of the buck converter operates in the frequency reduction mode.

[0102] Furthermore, the switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

[0103] Furthermore, the turn-off time of the first switch tube in the frequency reduction mode is greater than the turn-off time of the first switch tube in the fixed frequency mode.

[0104] Further, in the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage COMP is less than the second reference voltage Vref2, the frequency reduction control signal DOVP shields the fixed frequency control signal SET to extend the off time of the first switch tube, and when the compensation voltage COMP is equal to the second reference voltage Vref2, the frequency reduction control signal DOVP is unshielded and the first switch tube is turned on. After the first switch tube is turned on for the minimum on time and when the current sampling signal VIL representing the inductor current reaches the compensation voltage COMP, the first switch tube is turned off.

[0105] That is, the control circuit 100 of the present disclosure realizes constant voltage output by configuring the frequency reduction control unit 120 to output the frequency reduction control signal DOVP to control whether the switch control unit 110 inserts the frequency reduction control in the fixed frequency control mode.

[0106] Exemplarily, the frequency reduction control unit 120 outputs an invalid state (exemplarily a high level) frequency reduction control signal DOVP to release the shielding of the fixed frequency control signal SET when the compensation voltage COMP is greater than or equal to the second reference voltage Vref2, and outputs a valid state (exemplarily a low level) frequency reduction control signal DOVP to shield the fixed frequency control signal SET when the compensation voltage COMP is less than the second reference voltage Vref2.

[0107] In this embodiment, the second reference voltage Vref2 is a fixed voltage, which is related to the target voltage, the output feedback coefficient, and the first reference voltage Vref1. The frequency reduction control signal DOVP is a comparison result between the compensation voltage COMP and the reference voltage Vref2, and is used to indicate whether the output voltage Vout is greater than the target voltage. When the output voltage Vout rises, the compensation voltage COMP drops.

[0108] Specifically, the frequency reduction control unit 120 includes a second comparator CMP2. A first input terminal (exemplarily a positive input terminal) of the second comparator CMP2 receives the compensation voltage COMP, a second input terminal (exemplarily a negative input terminal) of the second comparator CMP2 receives a second reference voltage Vref2 (here, a constant voltage), and an output terminal of the second comparator CMP2 outputs a frequency reduction control signal DOVP.

[0109] Exemplarily, the shutdown control unit 111 generates a shutdown control signal Vgr in a valid state (exemplarily a high level) when the current sampling signal VIL reaches the compensation voltage COMP and the minimum on-time signal HSonn is in an invalid state (exemplarily a low level), and generates a shutdown control signal Vgr in an invalid state (exemplarily a low level) when the current sampling signal VIL does not reach the compensation voltage COMP or the minimum on-time signal HSonn is in a valid state (exemplarily a high level). The minimum on-time signal HSonn is an inverted signal of the signal VGHdelay of the minimum on-time delay of the rising edge of the first drive signal VGH.

[0110] Specifically, the shutdown control unit 111 includes a current sampling unit 1111, a voltage sampling unit 1112, a minimum on-time signal generating unit 1113, a first operational amplifier OP1, a first comparator CMP1, a first NOT gate NOT1, and a first AND gate AND1. The current sampling unit 1111 is connected to the second end of the first switch tube Q1 of the buck converter and the first end of the inductor Lm to sample the inductor current IL and obtain a current sampling signal VIL. The current sampling unit 1111, for example, includes a sampling resistor. The voltage sampling unit 1112 samples the output voltage Vout of the buck converter and obtains a feedback signal Vfb. The voltage sampling unit 1112, for example, includes a voltage divider network, and the voltage divider coefficient is, for example, the output feedback coefficient referred to above. The minimum on-time signal generating unit 1113 includes, for example, a delay unit Delay1 and a third NOT gate NOT3, the input end of the delay unit Delay1 receives the first drive signal VGH, the output end of the delay unit Delay1 is connected to the input end of the third NOT gate NOT3, and the output end of the third NOT gate NOT3 outputs the minimum on-time signal HSonmIn. The delay unit Delay1 is used to delay the minimum on-time of the rising edge of the first drive signal VGH, and the delay of the falling edge of the first drive signal VGH can be ignored (the delay of the falling edge is used to generate the pulse width of the signal VGHdelay). The first input end (exemplarily the positive input end) of the first operational amplifier OP1 receives the first reference voltage Vref1, the second input end (exemplarily the reverse input end) of the first operational amplifier OP1 receives the feedback signal Vfb, and the output end of the first operational amplifier OP1 outputs the compensation voltage COMP. The compensation voltage COMP is, for example, the difference voltage between the first reference voltage Vref1 and the feedback signal Vfb or the amplified value of the difference voltage. The first input terminal (exemplarily the positive input terminal) of the first comparator CMP1 is connected to the current sampling unit 1111 to receive the current sampling signal VIL, the second input terminal (exemplarily the reverse input terminal) of the first comparator CMP1 receives the compensation voltage COMP, and the output terminal of the first comparator CMP1 outputs the intermediate signal Reset. The intermediate signal Reset is the comparison result between the current sampling signal VIL and the compensation voltage COMP to indicate whether the inductor current IL reaches the preset value. The input terminal of the first NOT gate NOT1 receives the minimum on-time signal Hsonmin. The first input terminal of the first AND gate AND1 is connected to the output terminal of the first comparator CMP1 to receive the intermediate signal Reset, the second input terminal of the first AND gate AND1 is connected to the output terminal of the first NOT gate NOT1, and the output terminal of the first AND gate AND1 outputs the shutdown control signal Vgr.

[0111] like Figure 2As shown, the conduction control unit 312 generates a fixed-frequency control signal SET according to the clock signal CLK and the minimum conduction time signal Hsonmin, and generates a conduction control signal Vgs according to the fixed-frequency control signal SET and the reduced-frequency control signal DOVP.

[0112] Exemplarily, the conduction control unit 312 generates a fixed frequency control signal SET in an effective state (exemplarily a high level) at an effective edge (exemplarily a rising edge) of the clock signal CLK, and resets the fixed frequency control signal SET after the first drive signal VGH jumps to the effective state and lasts for a first time. And the conduction control unit 312 also generates a conduction control signal Vgs in an effective state (exemplarily a high level) according to the fixed frequency control signal SET in an effective state (exemplarily a high level) and the down-frequency control signal DOVP in an invalid state (exemplarily a high level), and generates a conduction control signal Vgs in an invalid state (exemplarily a low level) according to the fixed frequency control signal SET in an invalid state (exemplarily a low level) or the down-frequency control signal DOVP in an effective state (exemplarily a low level). It should be noted that in the initial state, before the first valid edge of the clock signal CLK arrives, the first switch tube Q1 is in the off state, and the first drive signal VGH is in an invalid state (exemplarily a low level). When the first edge of the clock signal CLK arrives, the first drive signal VGH is in a valid state (exemplarily a high level), and the conduction control signal Vgs is in an invalid state (exemplarily a low level).

[0113] Specifically, the conduction control unit 312 includes a monostable unit 1121, a trigger D1, and a second AND gate AND2. The monostable unit 1121 receives the first drive signal VGH and outputs a delay signal in which the first drive signal VGH is delayed by a first time (for example, 10ns). The D terminal of the trigger Q1 receives a power supply voltage VCC, the clock terminal CLK of the trigger Q1 receives the clock signal CLK, the reset terminal RST of the trigger Q1 receives the delay signal, and the output terminal Q of the trigger D1 outputs a fixed frequency control signal SET. The trigger D1 is triggered at the effective edge (exemplarily the rising edge) of the clock signal CLK so that the output terminal Q follows the output of the D terminal, and resets the fixed frequency control signal SET outputted by the output terminal Q when the rising edge of the delay signal at the reset terminal RST arrives. A first input terminal of the second AND gate AND2 is connected to the output terminal of the trigger D1 to receive the fixed frequency control signal SET, a second input terminal of the second AND gate AND2 is connected to the output terminal of the second comparator CMP2 in the frequency reduction control unit 120 to receive the frequency reduction control signal DOVP, and an output terminal of the second AND gate AND2 outputs a conduction control signal Vgs.

[0114] In other embodiments, Figure 3As shown, the conduction control unit 112 generates a fixed frequency control signal SET according to the clock signal CLK and the minimum conduction time signal Hsonmin, and generates a conduction control signal Vgs according to the fixed frequency control signal SET, the shutdown control signal Vgr, and the frequency reduction control signal DOVP.

[0115] Exemplarily, the conduction control unit 112 generates a fixed frequency control signal SET in an effective state (exemplarily a high level) at an effective edge (exemplarily a rising edge) of the clock signal CLK, and resets the fixed frequency control signal SET after the first drive signal VGH jumps to the effective state and lasts for a first time. And the conduction control unit 112 also generates a conduction control signal Vgs in an effective state (exemplarily a high level) according to the fixed frequency control signal SET in an effective state (exemplarily a high level), the frequency reduction control signal DOVP in an invalid state (exemplarily a high level), and the shutdown control signal Vgr in an invalid state (exemplarily a low level), and generates a conduction control signal Vgs in an invalid state (exemplarily a low level) according to the fixed frequency control signal SET in an invalid state (exemplarily a low level) or the frequency reduction control signal DOVP in an effective state (exemplarily a low level) or the shutdown control signal Vgr in an effective state (exemplarily a high level). It should be noted that in the initial state, before the first valid edge of the clock signal CLK arrives, the first switch tube Q1 is in the off state, and the first drive signal VGH is in an invalid state (exemplarily a low level). When the first edge of the clock signal CLK arrives, the first drive signal VGH is in a valid state (exemplarily a high level), and the conduction control signal Vgs is in an invalid state (exemplarily a low level).

[0116] Specifically, the conduction control unit 112 includes a monostable unit 1121, a trigger D1, a second NOT gate NOT2 and a third AND gate AND3. The monostable unit 1121 receives a first drive signal VGH and outputs a delay signal of the first drive signal VGH delayed by a first time (for example, 10ns). The D terminal of the trigger Q1 receives a power supply voltage VCC, the clock terminal CLK of the trigger Q1 receives a clock signal CLK, the reset terminal RST of the trigger Q1 receives the delay signal, and the output terminal Q of the trigger D1 outputs a fixed frequency control signal SET. Among them, the trigger D1 is triggered at the effective edge (exemplarily the rising edge) of the clock signal CLK so that the output terminal Q follows the output of the D terminal, and resets the fixed frequency control signal SET output by the output terminal Q when the rising edge of the delay signal of the reset terminal RST arrives. The input terminal of the second NOT gate NOT2 is connected to the output terminal of the first AND gate AND1 in the shutdown control unit 111 to receive the shutdown control signal Vgr. A first input terminal of the third AND gate AND3 is connected to an output terminal of the second NOT gate NOT2, a second input terminal of the third AND gate AND3 is connected to an output terminal of the trigger D1 to receive a fixed frequency control signal SET, a third input terminal of the third AND gate AND3 is connected to an output terminal of the second comparator CMP2 in the frequency reduction control unit 120 to receive a frequency reduction control signal DOVP, and an output terminal of the third AND gate AND3 outputs a conduction control signal Vgs.

[0117] The driving unit 113 is connected to the on-control unit 111 and the off-control unit 112, and generates a first driving signal VGH to drive the control end of the first switch tube Q1 according to the on-control signal Vgs and the off-control signal Vgr. In addition, the driving unit 113 also generates a second driving signal VGL that is inverted with the first driving signal VGH to synchronously control the controller of the second switch tube Q2.

[0118] Exemplarily, the driving unit 113 generates a first driving signal VGH in an invalid state (exemplarily at a low level) and a second driving signal VGL in a valid state (exemplarily at a high level) according to a shutdown control signal Vgr in a valid state (exemplarily at a high level) and an on-control signal Vgs in an invalid state (exemplarily at a low level), and generates a second driving signal VGL in an invalid state (exemplarily at a low level) and a first driving signal VGH in a valid state (exemplarily at a high level) according to the on-control signal Vgs in a valid state (exemplarily at a high level) and the shutdown control signal Vgr in an invalid state (exemplarily at a low level), and maintains the previous level state of the first driving signal VGH and the second driving signal VGL according to the on-control signal Vgs in a valid state (exemplarily at a high level) and the off-control signal Vgr in an invalid state (exemplarily at a low level).

[0119] Specifically, the driving unit 113 includes a latch RS1. The R terminal of the latch RS1 is connected to the output terminal of the first AND gate AND1 to receive the shutdown control signal Vgr, the S terminal of the latch RS1 is connected to the output terminal of the third AND gate AND3 to receive the conduction control signal Vgs, the first output terminal Q of the latch RS1 outputs the first drive signal VGH, and the second output terminal of the latch RS1 outputs the first drive signal VGH. The second drive signal VGL is output. When one of the S terminal and the R terminal is at a low level, the first output terminal Q of the latch RS1 follows the S terminal output. The second output terminal Q of the latch RS1 follows the S terminal output. The level state is opposite to the level state of the first output terminal Q. When both the S terminal and the R terminal of the output terminal of the latch RS1 are at low level, the previous level state remains unchanged.

[0120] Combination Figure 4 , several switching cycles of the buck converter are expanded.

[0121] Among them, T0-T8 works in fixed frequency mode, and T8-T13 works in reduced frequency mode.

[0122] The fixed frequency mode includes 4 switching cycles (T0-T2 is a switching cycle, T2-T4 is a switching cycle, T4-T6 is a switching cycle, and T6-T8 is a switching cycle), among which the on-time of the first switch tube in the first two switching cycles is greater than the minimum on-time Hsonmin, and the on-time of the first switch tube in the last two switching cycles is equal to the minimum on-time.

[0123] The frequency reduction mode includes 2 switching cycles (T8-T11 is one switching cycle, and T11-T13 is one switching cycle).

[0124] The fixed frequency mode is described by taking the switching period T0-T2 as an example. When the compensation voltage COMP is greater than the reference voltage Vref2, the frequency reduction control unit 120 outputs the frequency reduction control signal DOVP in an invalid state (exemplarily a high level), and the fixed frequency control signal SET is unshielded.

[0125] At time T0, the rising edge of the clock signal CLK arrives, and the conduction control unit 112 outputs a fixed-frequency control signal SET in a valid state (exemplarily a high level). The current sampling signal VIL does not reach the compensation voltage COMP (indicating that the inductor current IL has not reached the preset value), and the shutdown control unit 111 outputs a shutdown control signal Vgr in an invalid state (exemplarily a low level). The compensation voltage COMP is greater than the second reference voltage Vref2 (indicating that the output voltage Vout is equal to the target voltage), and the frequency reduction control unit 120 outputs a frequency reduction control signal DOVP in an invalid state (exemplarily a high level). Then, the S terminal of the latch RS1 is high level, the R terminal is low level, and the output terminal Q outputs a first drive signal VGH in a valid state (exemplarily a high level) and a second drive signal VGL in an invalid state (exemplarily a low level). The control circuit 100 controls the first switch tube Q1 to turn on and the second switch tube Q2 to turn off based on a fixed frequency method, and the inductor current IL rises linearly.

[0126] The time period between T0 and T1 is the fixed frequency conduction state. It should be noted that the T4-T5 stage and the T6-T7 stage of other switching cycles are the critical states of fixed frequency conduction, that is, the conduction time of the first switch tube Q1 has dropped to equal to the minimum conduction time Hsonmin. Between T0 and T1, the fixed frequency control signal SET is reset to an invalid state (exemplarily a low level) by the first drive signal VGH. Then the S terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0127] At time T1, the conduction control unit 112 outputs a fixed-frequency control signal SET in an invalid state (exemplarily a low level). The current sampling signal VIL reaches the compensation voltage COMP (indicating that the inductor current IL reaches the preset value) and the minimum on-time signal HSonmIn is in an invalid state (exemplarily a low level), and the shutdown control unit 111 outputs a shutdown control signal Vgr in a valid state (exemplarily a high level). Then, the S terminal of the latch RS1 is at a low level, the R terminal is at a high level, and the output terminal Q outputs a second drive signal VGL in a valid state (exemplarily a high level) and a first drive signal VGH in an invalid state (exemplarily a low level) to keep the first switch tube Q1 turned off. The control circuit 100 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on based on the frequency reduction method, and the inductor current IL rises linearly.

[0128] Between T1 and T2, the current sampling signal VIL decreases, and the shutdown control signal Vgr is in an invalid state (illustratively a low level). Thus, the R terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0129] At time T2, the next switching cycle begins. When the rising edge of the clock signal CLK arrives, the conduction control unit 112 outputs the fixed frequency control signal SET in the valid state (exemplarily high level). The frequency reduction control unit 120 outputs the frequency reduction control signal DOVP in the invalid state (exemplarily high level), and the shutdown control unit 111 outputs the invalid state (exemplarily low level) based on the inductor current IL being lower than the preset value, and then the latch RS1 outputs the first drive signal VGH in the valid state (exemplarily high level) and the second drive signal VGL in the invalid state (exemplarily low level) to turn on the first switch tube Q1.

[0130] The switching cycle of T8-T11 is taken as an example to illustrate the frequency reduction mode.

[0131] At time T8, the rising edge of the clock signal CLK arrives, and the conduction control unit 112 outputs a fixed-frequency control signal SET in a valid state (exemplarily a high level). The current sampling signal VIL does not reach the compensation voltage COMP (indicating that the inductor current IL has not reached the preset value), and the shutdown control unit 111 outputs a shutdown control signal Vgr in an invalid state (exemplarily a low level). The compensation voltage COMP is greater than the second reference voltage Vref2 (indicating that the output voltage Vout is equal to the target voltage), and the frequency reduction control unit 120 outputs a frequency reduction control signal DOVP in an invalid state (exemplarily a high level). Then, the S terminal of the latch RS1 is high level, the R terminal is low level, and the output terminal Q outputs a first drive signal VGH in a valid state (exemplarily a high level) and a second drive signal VGL in an invalid state (exemplarily a low level). The control circuit 100 controls the first switch tube Q1 to turn on and the second switch tube Q2 to turn off based on a fixed frequency method, and the inductor current IL rises linearly.

[0132] Between T8 and T9, the compensation voltage COMP is less than the reference voltage Vref2, and the frequency reduction control unit 120 outputs a frequency reduction control signal DOVP in a valid state (exemplarily a low level) and shields the fixed frequency control signal SET, thus entering the frequency reduction mode.

[0133] The T8-T9 stage is the frequency reduction conduction stage, and the conduction time of the first switch tube Q1 is equal to the minimum conduction time Hsonmin. Between T8 and T9, the frequency reduction control signal DOVP shields the fixed frequency control signal SET to output the conduction control signal Vgs in an invalid state (exemplarily a low level). Then, the S terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0134] At time T9, the on-time of the first switch tube Q1 reaches the minimum on-time Hsonmin. The on-control unit 112 keeps outputting the on-control signal Vgs in an invalid state (exemplarily a low level). The current sampling signal VIL reaches the compensation voltage COMP (indicating that the inductor current IL reaches the preset value) and the minimum on-time signal Hsonmin is in an invalid state (exemplarily a low level), and the off-control unit 111 outputs the off-control signal Vgr in an effective state (exemplarily a high level). Then, the S terminal of the latch RS1 is at a low level, the R terminal is at a high level, and the output terminal Q outputs the second drive signal VGL in an effective state (exemplarily a high level) and the first drive signal VGH in an invalid state (exemplarily a low level) to keep the first switch tube Q1 turned off. The control circuit 100 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on based on the frequency reduction method, and the inductor current IL rises linearly.

[0135] Between T9 and T10, HSonmIn becomes valid (exemplarily high level), and the shutdown control signal Vgr becomes invalid (exemplarily low level). Then, the R terminal of the latch RS1 is low level, and the output of the latch RS1 remains unchanged.

[0136] At time T10, the rising edge of the clock signal CLK arrives, and the conduction control unit 112 outputs the fixed frequency control signal SET in a valid state (exemplarily a high level). At this stage, the frequency reduction control unit 120 outputs the frequency reduction control signal DOVP in a valid state (exemplarily a low level), shields the fixed frequency control signal SET to generate the conduction control signal Vgs in an invalid state (exemplarily a low level). The first switch tube remains turned off.

[0137] At time T11, the next cycle is entered. The shutdown control unit 111 outputs the shutdown control signal Vgr in an invalid state (exemplarily a low level) based on HSonm in a valid state (exemplarily a high level). The compensation voltage COMP is equal to the second reference voltage Vref2 (indicating that the output voltage Vout is higher than the target voltage), and the frequency reduction control signal DOVP is in an invalid state (exemplarily a high level). Since the first drive signal VGH remains in an invalid state between T10-T11, the fixed frequency control signal SET remains in a valid state, and then outputs the conduction control signal Vgs in a valid state. Then the latch RS1 keeps outputting the first drive signal VGH in a valid state (exemplarily a high level) and the second drive signal VGL in an invalid state (exemplarily a low level). Afterwards, the fixed frequency control signal SET is reset after the first time.

[0138] Figure 5 A schematic diagram of another control circuit of a buck converter provided in an embodiment of the present disclosure is shown.

[0139] Compared with the control circuit 100, the control circuit 200 of the buck converter only changes the structure of the frequency reduction control unit. The frequency reduction control unit 220 includes a ramp signal generating unit 221 and a third comparator CMP3. This embodiment can ensure that the buck converter is still in a stable state when the output capacitance is small.

[0140] In addition, the frequency reduction control unit 220 in this embodiment may also replace the frequency reduction control unit 120 in the control circuit 300 to obtain a new control circuit.

[0141] The ramp signal generating unit 221 generates a ramp signal to avoid subharmonic oscillation when the compensation voltage COMP has a slight disturbance, so that the generated frequency reduction control signal will not mistakenly shield the fixed frequency control signal, thereby ensuring the stability of the frequency reduction converter.

[0142] Exemplarily, the ramp signal generating unit 221 includes a switch S1, a current source Ir, a capacitor Cr, and a second operational amplifier OP2. The first end of the switch S1 is connected to the first end of the current source Ir and the first end of the capacitor Cr and provides an intermediate voltage RAMP. The second end of the switch S1 is connected to the second end of the current source Ir and the second end of the capacitor Cr and is grounded. The control of the switch S1 receives the first drive signal VGH. The first input end (positive input end) of the second operational amplifier OP2 receives the third reference voltage Vref3, the second input end (reverse input end) of the second operational amplifier OP2 receives the intermediate voltage RAMP, and the output end of the second operational amplifier OP2 outputs the ramp signal Vref4. The first input end (positive input end) of the third comparator CMP3 receives the compensation voltage COMP, the second input end (reverse input end) of the third comparator CMP3 receives the ramp signal Vref4, and the output end of the third comparator CMP3 outputs the frequency reduction control signal DOVP.

[0143] When the first switch tube Q1 is turned off, the capacitor Cr is charged, and the intermediate voltage Ramp rises linearly. Since the third reference voltage Vref3 is a constant reference, Vref4=Vref3-Ramp, the ramp signal Vref4 is a changing value with a certain slope.

[0144] Figure 6 A flow chart of a control method for a buck converter provided in an embodiment of the present disclosure is shown. Figure 7 A flow chart showing another control method for a buck converter provided in an embodiment of the present disclosure is shown.

[0145] like Figure 6 , Figure 7 As shown, the control method includes:

[0146] Step S100: sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and the first reference voltage to obtain a compensation voltage, generating a minimum on-time signal based on the first drive signal, and generating a shutdown control signal according to the inductor current, the compensation voltage and the minimum on-time signal.

[0147] Step S200: generating a frequency reduction control signal based on a comparison result between the compensation voltage and the second reference voltage.

[0148] Step S300: Generate a fixed frequency control signal according to the clock signal and the first drive signal, and generate a conduction control signal according to the fixed frequency control signal and the frequency reduction control signal. In an alternative embodiment, this step is: generate a fixed frequency control signal according to the clock signal and the first drive signal, and generate a conduction control signal according to the fixed frequency control signal, the frequency reduction control signal, and the shutdown control signal.

[0149] Step S400: Generate a first driving signal according to the on-control signal and the off-control signal to control the first switch tube to be on or off.

[0150] Furthermore, it also includes:

[0151] When the compensation voltage is greater than the second reference voltage, the frequency reduction control signal releases the shielding of the fixed frequency control signal, the control circuit of the buck converter operates in a fixed frequency mode, and the first switch tube is turned on when the effective edge of the clock signal arrives;

[0152] When the compensation voltage is less than the second reference voltage, the control circuit of the buck converter operates in a frequency reduction mode.

[0153] In the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage is less than the second reference voltage, the frequency reduction control signal shields the fixed frequency control signal to extend the turn-off time of the first switch tube, and when the compensation voltage is equal to the second reference voltage, the frequency reduction control signal is unshielded and the first switch tube is turned on. And after the first switch tube is turned on for the minimum on time and when the current sampling signal representing the inductor current reaches the compensation voltage, the first switch tube is turned off.

[0154] Furthermore, a switching frequency of the first switch tube in the frequency reduction mode is lower than a switching frequency of the first switch tube in the fixed frequency mode.

[0155] Further, a turn-off time of the first switch tube in the frequency reduction mode is greater than a turn-off time of the first switch tube in the fixed frequency mode.

[0156] like Figure 7 As shown, another control method includes the following steps:

[0157] Step S110: when the first edge of the clock signal arrives, output a fixed-frequency control signal in a valid state;

[0158] Step S120: determining whether the compensation voltage reaches the reference voltage.

[0159] If step S130 is executed: the first switch is turned on, that is, when the compensation voltage is equal to or greater than the reference signal, an invalid down-frequency control signal is output, and then an effective on-control signal is output to turn on the first switch at a constant frequency.

[0160] Otherwise, step S140 is executed: wait for the compensation voltage to be equal to the reference voltage to turn on the first switch tube. That is, when the compensation voltage is less than the reference signal, a frequency reduction control signal of a valid state is output, and then an invalid state conduction control signal is output, so that the first switch tube is kept off by frequency reduction control until the compensation voltage is equal to the reference voltage to turn on the first switch tube.

[0161] Step S210: After the first switch tube is turned on for the minimum on-time, whether the current sampling signal reaches the compensation voltage.

[0162] If step S220 is executed: the first switch tube is turned off, that is, when the current sampling signal reaches the compensation voltage, which indicates that the inductor current reaches the preset value, a valid shutdown control signal is output to turn off the first switch tube.

[0163] Otherwise, execute step S230: keep the first switch on until the inductor current reaches a preset value. That is, when the current sampling signal does not reach the compensation voltage, indicating that the inductor current does not reach the preset value, an invalid shutdown control signal is output to keep the first switch on until the inductor current reaches the preset value.

[0164] The control circuit of the buck converter provided in the present invention can start the frequency reduction control based on the output feedback when the input voltage increases, and shield the fixed frequency start under the frequency reduction control, so as to extend the off time of the first switch tube by delaying the turn-on of the first switch tube until the output voltage reaches the target voltage, and then control the buck converter by the fixed frequency control method to achieve constant voltage output.

[0165] Furthermore, the buck converter and its control circuit and control method provided by the present disclosure realize constant voltage output by setting a frequency reduction control unit to output a frequency reduction control signal based on output feedback, thereby controlling whether the switch control unit inserts the frequency reduction control in the fixed frequency control mode. Thus, the buck converter can realize constant voltage output even in a high input range, and realize constant voltage application in a wider input voltage range.

[0166] Furthermore, the present disclosure uses a fixed frequency combined with a reduced frequency control method, which is not limited by the minimum on-time limit, and can avoid reducing the stability of the power supply due to process limitations, and does not need to replace higher performance components. In addition, the present disclosure can ensure the minimum on-time, thereby preventing the buck converter from being triggered by mistake.

[0167] Furthermore, the frequency reduction control unit of the present disclosure compares the compensation voltage with the ramp signal to control whether to enter the frequency reduction mode, thereby avoiding subharmonic oscillation when there is a slight disturbance in the output feedback (compensation voltage), thereby ensuring the stability of the buck converter.

[0168] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a buck converter, wherein: include: a shutdown control unit, sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and the first reference voltage to obtain a compensation voltage, generating a minimum on-time signal based on the first drive signal, and generating a shutdown control signal according to the inductor current, the compensation voltage and the minimum on-time signal; A frequency reduction control unit, which generates a frequency reduction control signal based on a comparison result between the compensation voltage and the second reference voltage; A conduction control unit, which generates a fixed-frequency control signal according to the clock signal and the first drive signal, and generates a conduction control signal according to the fixed-frequency control signal and the frequency reduction control signal; as well as The driving unit receives the on-control signal and the off-control signal, generates a first driving signal, and controls the first switch tube to be on or off.

2. The control circuit of the buck converter according to claim 1, wherein: The conduction control unit generates a fixed-frequency control signal according to the clock signal and the first driving signal, and generates a conduction control signal according to the fixed-frequency control signal, the frequency reduction control signal and the shutdown control signal.

3. The control circuit of the buck converter according to claim 1 or 2, wherein: When the compensation voltage is greater than the second reference voltage, the frequency reduction control signal releases the shielding of the fixed frequency control signal, the control circuit of the buck converter operates in a fixed frequency mode, and the first switch tube is turned on when the effective edge of the clock signal arrives; When the compensation voltage is less than the second reference voltage, the control circuit of the buck converter operates in a frequency reduction mode; The switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

4. The control circuit of the buck converter according to claim 3, wherein: The turn-off time of the first switch tube in the frequency reduction mode is greater than the turn-off time of the first switch tube in the fixed frequency mode.

5. The control circuit of the buck converter according to claim 4, wherein: In the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage is less than the second reference voltage, the frequency reduction control signal shields the fixed frequency control signal to extend the turn-off time of the first switch tube, and when the compensation voltage is equal to the second reference voltage, the frequency reduction control signal is unshielded and the first switch tube is turned on.

6. The control circuit of the buck converter according to claim 5, wherein: After the first switch tube is turned on for a minimum on-time and when the current sampling signal representing the inductor current reaches a compensation voltage, the first switch tube is turned off.

7. The control circuit of the buck converter according to claim 4, wherein: The frequency reduction control unit outputs the frequency reduction control signal in an invalid state to release the shielding of the fixed frequency control signal when the compensation voltage is greater than or equal to the second reference voltage, and outputs the frequency reduction control signal in a valid state to shield the fixed frequency control signal when the compensation voltage is less than the second reference voltage.

8. The control circuit of the buck converter according to claim 1 or 2, wherein: The second reference voltage is a constant voltage or a ramp signal.

9. The control circuit of the buck converter according to claim 1, wherein: The conduction control unit generates the fixed frequency control signal in a valid state when the effective edge of the clock signal arrives, and resets the fixed frequency control signal after the first drive signal jumps to the valid state and lasts for a first time. And the conduction control signal in the effective state is generated according to the fixed-frequency control signal in the effective state and the reduced-frequency control signal in the invalid state, otherwise the conduction control signal in the invalid state is generated.

10. The control circuit of the buck converter according to claim 2, wherein: The conduction control unit generates the fixed frequency control signal in a valid state when the effective edge of the clock signal arrives, and resets the fixed frequency control signal after the first drive signal jumps to the valid state and lasts for a first time. And the conduction control signal of the effective state is generated according to the fixed frequency control signal of the effective state, the frequency reduction control signal of the invalid state and the shutdown control signal of the invalid state, otherwise the conduction control signal of the invalid state is generated.

11. The control circuit of the buck converter according to claim 1 or 2, wherein: The shutdown control unit generates a shutdown control signal in a valid state when the current sampling signal reaches the compensation voltage and the minimum on-time signal is in an invalid state, otherwise generates a shutdown control signal in an invalid state, The minimum on-time signal is an inverted signal of the first driving signal after the rising edge is delayed.

12. The control circuit of the buck converter according to claim 1 or 2, wherein: The driving unit generates a first driving signal of an invalid state according to an off control signal of an effective state and an on control signal of an invalid state, generates a first driving signal of an effective state according to an on control signal of an effective state and an off control signal of an invalid state, and keeps a previous level state of the first driving signal unchanged according to an on control signal of an invalid state and an off control signal of an invalid state.

13. The control circuit of the buck converter according to claim 11, wherein: The shutdown control unit comprises: A current sampling unit, sampling the inductor current to obtain the current sampling signal; A voltage sampling unit, sampling the output voltage to obtain the feedback signal; a minimum on-time signal generating unit, which delays and inverts the rising edge of the first driving signal to generate the minimum on-time signal; a first operational amplifier, wherein a first input terminal of the first operational amplifier receives the first reference voltage, a second input terminal of the first operational amplifier receives the feedback signal, and an output terminal of the first operational amplifier outputs the compensation voltage; A first comparator, wherein a first input terminal of the first comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the first comparator receives the compensation voltage, and an output terminal of the first comparator outputs an intermediate signal; A first NOT gate, an input terminal of which receives the minimum on-time signal; and A first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the first comparator to receive the intermediate signal, a second input terminal of the first AND gate is connected to an output terminal of the first NOT gate, and an output terminal of the first AND gate outputs the shutdown control signal.

14. The control circuit of the buck converter according to claim 9, wherein: The conduction control unit comprises: A monostable unit, outputting a delay signal in which the first driving signal is delayed by a first time; A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the fixed-frequency control signal; and A second AND gate, wherein the first input terminal of the second AND gate is connected to the output terminal of the trigger to receive the fixed frequency control signal, the second input terminal of the second AND gate receives the reduced frequency control signal, and the output terminal of the second AND gate outputs the conduction control signal.

15. The control circuit of the buck converter according to claim 10, wherein: The conduction control unit comprises: A monostable unit, outputting a delay signal in which the first driving signal is delayed by a first time; A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the fixed-frequency control signal; a second NOT gate, an input terminal of the second NOT gate receiving the shutdown control signal; and A third AND gate, wherein the first input terminal of the third AND gate is connected to the output terminal of the second NOT gate, the second input terminal of the third AND gate is connected to the output terminal of the trigger to receive the fixed frequency control signal, the third input terminal of the third AND gate receives the reduced frequency control signal, and the output terminal of the third AND gate outputs the conduction control signal.

16. The control circuit of the buck converter according to claim 12, wherein: The driving unit comprises: A latch, wherein the R end of the latch receives the shutdown control signal, the S end of the latch receives the conduction control signal, the first output end of the latch outputs the first drive signal, and the second output end of the latch outputs the second drive signal, wherein the second drive signal is an inverted signal of the first drive signal.

17. The control circuit of the buck converter according to claim 8, wherein: The frequency reduction control unit comprises: A second comparator, wherein a first input terminal of the second comparator receives the compensation voltage, a second input terminal of the second comparator receives the fixed value voltage, and an output terminal of the second comparator outputs the frequency reduction control signal.

18. The control circuit of the buck converter according to claim 8, wherein: The frequency reduction control unit comprises: a ramp signal generating unit, comprising a switch, a current source, a capacitor, and a second operational amplifier, wherein a first end of the switch is connected to a first end of the current source and a first end of the capacitor and provides an intermediate voltage, a second end of the switch is connected to a second end of the current source and a second end of the capacitor and is grounded, a control of the switch receives a first drive signal, a first input end of the second operational amplifier receives a third reference voltage, a second input end of the second operational amplifier receives the intermediate voltage, and an output end of the second operational amplifier outputs a ramp signal; and A third comparator, wherein a first input terminal of the third comparator receives the compensation voltage, a second input terminal of the third comparator receives the ramp signal, and an output terminal of the third comparator outputs the frequency reduction control signal.

19. A buck converter, wherein: include: A first capacitor, receiving an input voltage; The second capacitor outputs the output voltage; inductance; A control circuit as described in any one of claims 1 to 18 above; a first switch tube, wherein a first end of the first switch tube is connected to a first end of the first capacitor, a second end of the first switch tube is connected to a first end of the second capacitor via the inductor, and a control end of the first switch tube is connected to a control circuit to receive a first drive signal; as well as A second switch tube, wherein the first end of the second switch tube is connected to the second end of the first switch tube and the inductor, the second end of the second switch tube is connected to the second end of the second capacitor and the second end of the first capacitor and is grounded, and the control end of the second switch tube is connected to the control circuit to receive an inverted signal of the first drive signal.

20. A control method for a buck converter, wherein: include: Sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference voltage to obtain a compensation voltage, generating a minimum on-time signal based on the first drive signal, and generating a shutdown control signal according to the inductor current, the compensation voltage and the minimum on-time signal; generating a frequency reduction control signal based on a comparison result between the compensation voltage and the second reference voltage; Generate a fixed-frequency control signal according to the clock signal and the first drive signal, and generate a conduction control signal according to the fixed-frequency control signal and the reduced-frequency control signal; as well as A first driving signal is generated according to the on-control signal and the off-control signal to control the first switch tube to be on or off.

21. The control method of the buck converter according to claim 20, wherein: Also includes: A conduction control signal is generated according to the fixed-frequency control signal, the reduced-frequency control signal and the shutdown control signal.

22. The control method of the buck converter according to claim 20 or 21, wherein: When the compensation voltage is greater than the second reference voltage, the frequency reduction control signal releases the shielding of the fixed frequency control signal, the control circuit of the buck converter operates in a fixed frequency mode, and the first switch tube is turned on when the effective edge of the clock signal arrives; When the compensation voltage is less than the second reference voltage, the control circuit of the buck converter operates in a frequency reduction mode; The switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

23. The control method of the buck converter according to claim 22, wherein: Also includes: The turn-off time of the first switch tube in the frequency reduction mode is greater than the turn-off time of the first switch tube in the fixed frequency mode.

24. The control method of the buck converter according to claim 23, wherein: In the frequency reduction mode, after the first switch tube is turned off, when the compensation voltage is less than the second reference voltage, the frequency reduction control signal shields the fixed frequency control signal to extend the turn-off time of the first switch tube, and when the compensation voltage is equal to the second reference voltage, the frequency reduction control signal is unshielded and the first switch tube is turned on.

25. The control method of the buck converter according to claim 24, wherein: After the first switch tube is turned on for a minimum on-time and when the current sampling signal representing the inductor current reaches a compensation voltage, the first switch tube is turned off.

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