High-voltage level shifting circuits, gate driver chips, intelligent power modules and devices

Abstract

This application provides a high-voltage level shifting circuit, a gate driver chip, a smart power module, and a device. The high-voltage level shifting circuit includes: a dual-pulse shaping circuit for shaping and inverting a received first pulse signal and a second pulse signal to obtain a first inverted pulse signal and a second inverted pulse signal; and a common-mode noise filtering circuit electrically connected to the dual-pulse shaping circuit for filtering noise signals from the first inverted pulse signal and the second inverted pulse signal to obtain and output a reset signal and a set signal, respectively. The common-mode noise filtering circuit includes: a first switching transistor, a second switching transistor, a first current limiting circuit, and a second current limiting circuit. The solution of this application can eliminate dV / dt noise and will not interfere with subsequent circuits.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a high-voltage level shifting circuit, a gate driver chip, a smart power module, and a device. Background Technology

[0002] Intelligent Power Module (IPM) integrates high-side gate driver chip, over-temperature, over-current and under-voltage protection circuits, fault handling circuits, and driven power devices. Thanks to its advantages such as high switching frequency, low switching loss, and strong noise immunity, it has strong application potential in the field of power electronics and has a wide range of applications, especially suitable for variable frequency motors and inverter power supplies.

[0003] Traditional high-side gate driver chips are mainly composed of high-voltage dual-pulse triggered level shifter circuits, pulse filters, RS latches, and gate driver circuits. When integrated into intelligent power modules (IPMs) and applied in high-voltage, high-speed environments, their weak dV / dt noise immunity can cause power transistors to turn on incorrectly, resulting in shoot-through of the upper and lower bridge power transistors and causing serious damage to the system. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] This application provides a high-voltage level shifting circuit, which includes:

[0006] A dual-pulse shaping circuit is used to shape and invert the received first pulse signal and second pulse signal respectively to obtain a first inverted pulse signal and a second inverted pulse signal.

[0007] The common-mode noise filtering circuit is electrically connected to the dual-pulse shaping circuit. It is used to filter out noise signals in the first and second inverted pulse signals to obtain and output reset and set signals, respectively.

[0008] The common-mode noise filtering circuit includes:

[0009] The first switching transistor has its gate connected to a dual-pulse shaping circuit and a floating power supply. It is used to receive a second inverted pulse signal and control the first switching transistor to turn on or off through the second inverted pulse signal.

[0010] The second switching transistor has its gate connected to a dual-pulse shaping circuit and a floating power supply. It is used to receive a first inverted pulse signal and control the second switching transistor to turn on or off through the first inverted pulse signal. The input terminal of the first switching transistor is connected to the gate of the second switching transistor, and the input terminal of the second switching transistor is connected to the gate of the first switching transistor.

[0011] The first current limiting circuit has one end connected to the output terminal of the first switching transistor and the other end connected to the floating ground terminal. The output terminal of the first switching transistor is used to output a reset signal.

[0012] The second current limiting circuit has one end connected to the output terminal of the second switching transistor and the other end connected to the floating ground terminal. The output terminal of the first switching transistor is used to output a set signal.

[0013] In one embodiment, the dual-pulse shaping circuit includes:

[0014] A first pulse shaping circuit is used to shape and invert the received first pulse signal, and output a first inverted pulse signal. The first pulse shaping circuit includes:

[0015] The first input switch transistor has its gate used to receive the first pulse signal.

[0016] The first current-limiting resistor has one end connected to the input terminal of the first input switch transistor and the other end connected to the gate of the second switch transistor, and is used to output the first inverted pulse signal to the second switch transistor.

[0017] The first current mirror circuit is coupled between the output terminal and the gate of the first input switch.

[0018] Since the dual-pulse shaping circuit includes a current mirror circuit, it can improve the circuit's noise immunity and provide a negative feedback loop. When the first pulse signal is an effective signal, the pulse signal is momentarily set low to drive the first input switch transistor to turn on and off with a narrow pulse, thereby reducing power consumption.

[0019] In one embodiment, the first current mirror circuit includes:

[0020] The first NPN transistor has its collector connected to the gate of the first input switch transistor and its emitter connected to ground.

[0021] The second NPN transistor has its collector connected to the output terminal of the first input switch, its emitter connected to ground, and its base electrically connected to the base of the first NPN transistor. The base of the second NPN transistor is also electrically connected to the output terminal of the first input switch.

[0022] By using two NPN transistors to form a current mirror circuit, the circuit's ability to resist noise signal interference is enhanced, and the structure is simple and low in cost.

[0023] In one embodiment, the dual-pulse shaping circuit includes:

[0024] The second pulse shaping circuit is used to shape the received second pulse signal and output the shaped second inverted pulse signal. The second pulse shaping circuit includes:

[0025] The gate of the second input switch is used to receive the second pulse signal;

[0026] The second current-limiting resistor has one end connected to the input terminal of the second input switch transistor and the other end connected to the gate of the first switch transistor, and is used to output a second inverted pulse signal to the first switch transistor.

[0027] The second current mirror circuit is coupled between the output terminal and the gate of the second input switch.

[0028] By setting up this current mirror circuit, the circuit's ability to resist noise interference can be improved, and a negative feedback loop can be provided. When the second pulse signal is an effective signal, the pulse signal is momentarily set low, and the second input switch is turned on and off with a narrow pulse, thereby reducing power consumption.

[0029] In one embodiment, the second current mirror circuit includes:

[0030] The collector of the third NPN transistor is connected to the gate of the second input switch, and the emitter of the third NPN transistor is connected to the ground terminal.

[0031] The fourth NPN transistor has its collector connected to the output terminal of the second input switch, its emitter connected to ground, its base electrically connected to the base of the third NPN transistor, and its base also electrically connected to the output terminal of the second input switch.

[0032] By using two NPN transistors to form a current mirror circuit, the circuit's ability to resist noise signal interference is enhanced, and the structure is simple and low in cost.

[0033] In one embodiment, it also includes:

[0034] A first input resistor, one end of which is connected to a floating power supply, and the other end of which is connected to a first current-limiting resistor; and

[0035] The second input resistor has one end connected to the floating power supply and the other end connected to the second current-limiting resistor.

[0036] The first and second input resistors serve as current limiting protection and voltage divider, thereby ensuring the normal output of the reset and set signals generated by the circuit.

[0037] In one embodiment, the system further includes a voltage regulator circuit, wherein the first input resistor and the second input resistor are connected in parallel with a voltage regulator circuit, wherein each voltage regulator circuit includes at least two diodes connected in series, and the negative terminal of one diode is electrically connected to a floating power supply.

[0038] By connecting at least two diodes in series, the voltage regulation value of the voltage regulator circuit can be improved, and it can also provide reverse current limiting protection.

[0039] Another aspect of this application provides a gate driver chip, comprising:

[0040] A pulse generation circuit is used to encode the rising edge and falling edge of the received PWM pulse width modulation signal into a first pulse signal and a second pulse signal, respectively.

[0041] The aforementioned high-voltage level shifting circuit is electrically connected to the pulse generation circuit and is used to receive the first pulse signal and the second pulse signal.

[0042] In one embodiment, it also includes:

[0043] The noise cancellation circuit, electrically connected to the high-voltage level shift circuit, is used to receive and filter out differential-mode noise in the set and reset signals.

[0044] The noise cancellation circuit can filter out differential noise in the signal, thereby improving the problem of differential noise interfering with subsequent circuits and causing false triggering.

[0045] In one embodiment, it also includes:

[0046] The trigger circuit is electrically connected to the noise cancellation circuit. It is used to receive the signal output by the noise cancellation circuit, process the signal output by the noise cancellation circuit to obtain the target drive signal, and output the target drive signal as a latch signal when a noise signal appears in the signal output by the noise cancellation circuit.

[0047] A latch, electrically connected to a trigger circuit, is used to receive a target drive signal and process it to obtain a switching signal, which drives the device to be driven to turn on or off.

[0048] A driving circuit is connected to the gate of the target switching transistor and is used to drive the target switching transistor to turn on or off. The driving circuit includes a device to be driven, and the output of the latch is connected to the gate of the device to be driven.

[0049] The trigger circuit of this application can improve the noise signal caused by the negative voltage of VS and the narrow pulse width of the input signal, which can cause false triggering of the driven device, and output a clean drive signal. This solves the problem that the drive may be latched up due to false triggering of the device, which can cause serious damage to the system.

[0050] In one embodiment, the pulse generation circuit includes:

[0051] The filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it.

[0052] A low-voltage level shifting circuit is used to process PWM pulse width modulation signals to obtain level shifted signals;

[0053] A narrow pulse generation circuit is used to encode the rising and falling edges of a low-voltage level shift signal into a first pulse signal and a second pulse signal, respectively.

[0054] The signal is filtered and shaped by a filtering and shaping circuit to obtain a clean signal. A low-voltage level shifting circuit transfers the signal from the low-voltage region to the working voltage region. A narrow pulse generation circuit can precisely control the triggering time of the signal to achieve high-precision timing control.

[0055] In another aspect, this application also provides an intelligent power module, including the aforementioned gate driver chip.

[0056] In another aspect, this application provides an apparatus comprising the aforementioned high-voltage level shifting circuit, or the aforementioned gate driver chip, or the aforementioned smart power module.

[0057] With the high-voltage level shifting circuit, gate driver chip, intelligent power module and device of this application, when dV / dt noise is applied to the floating power supply voltage, both the first and second switching transistors are in the off state, and the common-mode noise filtering circuit maintains the output of low-level reset and set signals. Therefore, dV / dt noise can be eliminated and will not interfere with the subsequent circuits. This effectively improves the problem that the power transistors are mistakenly turned on due to dV / dt noise, resulting in shoot-through of the upper and lower bridge power transistors and serious damage to the system. Attached Figure Description

[0058] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0059] Figure 1 A circuit diagram of a high-side gate driver chip in the related art is shown;

[0060] Figure 2 A schematic diagram of the structure of an intelligent power module (IPM) is shown;

[0061] Figure 3 A schematic diagram of the circuit structure of a high-voltage dual-pulse triggered level shifting circuit in the related art is shown;

[0062] Figure 4 It shows Figure 3 Timing diagram of medium and high voltage dual-pulse triggered level shift circuit;

[0063] Figure 5 A schematic diagram of the circuit structure of a high-voltage level shifting circuit in one embodiment of this application is shown;

[0064] Figure 6 It shows Figure 5 Timing diagram of medium and high voltage level shifting circuit;

[0065] Figure 7 It shows Figure 2 A schematic diagram showing a false trigger caused by the overlap of the VS negative overshoot and the RESET signal in the middle structure;

[0066] Figure 8 This shows the result when the first pulse signal SET = 0 and the second pulse signal RESET = 1. Figure 5 A schematic diagram of the working state of a medium-to-high voltage level shifting circuit;

[0067] Figure 9A This diagram illustrates the timing when a negative overshoot of the VS signal overlaps with the RESET signal.

[0068] Figure 9B The timing diagram shows the case where the VS negative overshoot and the RESET signal do not overlap.

[0069] Figure 10 A schematic diagram of the trigger circuit in one embodiment of this application is shown;

[0070] Figure 11 A schematic diagram of the structure of a pulse modulator in one embodiment of this application is shown;

[0071] Figure 12 A timing diagram of an edge-triggered circuit for receiving a reset signal in a trigger circuit according to one embodiment of this application is shown.

[0072] Figure 13 A schematic diagram of the structure of a high-voltage gate driver chip in one embodiment of this application is shown. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of this application, and not all of the embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.

[0074] High-voltage gate driver chips are mainly classified into low-side, high-side, single-channel, dual-channel, isolated, half-bridge, and full-bridge power driver chips. They integrate low-voltage signal transmission logic control circuits for more precise processing of front-end input signals. Simultaneously, to drive high-power downstream devices, they are also equipped with high-voltage output drive circuits. The core function of this circuit product is to convert front-end microprocessor (MCU) signals into switching transistor drive control signals. In normal operation, the high-voltage gate driver chip not only processes input signals to drive power switching transistors but also transmits various operating status signals to an external microprocessor (MCU) for monitoring circuit operation. Intelligent power modules (IPMs) integrate high-voltage gate driver chips, over-temperature, over-current, and under-voltage protection circuits, fault handling circuits, and driven power devices. Benefiting from their high switching frequency, low switching losses, and strong noise immunity, they have strong application potential in the current power electronics field and a wide range of application scenarios, especially suitable for variable frequency motors and inverter power supplies. Figure 1 As shown, traditional high-side gate driver chips are mainly composed of a high-voltage dual-pulse triggered level shifter circuit, a pulse filter, an RS latch, and a gate driver circuit. When integrated into an intelligent power module (IPM) and applied in high-voltage, high-speed environments, they often suffer from problems such as false turn-off and false turn-on. For example, high-side gate driver chips have weak dV / dt noise immunity; high dV / dt noise may cause the power transistors to turn on incorrectly, resulting in shoot-through of the upper and lower bridge power transistors, which can severely damage the system.

[0075] Below, we will combine Figures 2 to 4 The causes of dV / dt noise are explained, including, for example... Figure 2 As shown, the intelligent power module includes a high-side gate driver chip (HVIC) and a low-side gate driver chip (LVIC). They receive control signals from a microcontroller (MCU) or other control unit, amplify and process the signals through internal circuitry, and ultimately output sufficient voltage and current to drive the gate of the power devices, enabling their turn-on and turn-off. Specifically, the high-side gate driver chip (HVIC) outputs a high-voltage drive output (HO) to control the high-side power transistor IGBT1. The low-side gate driver chip (LVIC) outputs a low-voltage drive output (LO) to control the low-side power transistor IGBT2.

[0076] Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power transistor IGBT1 and the low-side power transistor IGBT2 is Vs at the high-side floating ground VS terminal. Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are alternately turned on. When the high-side power transistor IGBT1 is on and the low-side power transistor IGBT2 is off, the high-side floating ground VS terminal Vs is approximately equal to the bus voltage VH, that is, Vs is at a high potential. When the high-side power transistor IGBT1 is off and the low-side power transistor IGBT2 is on, the high-side floating ground VS terminal Vs is approximately equal to the ground voltage GND. Optionally, a load (not shown in the attached figure) is connected between the voltage Vs at the high-side floating ground VS terminal and the ground voltage. Optionally, the high-side floating power supply voltage VB (also known as the operating voltage VB) is bootstrap connected to the power supply voltage VCC through a bootstrap diode D1. Optionally, the high-side floating power supply voltage VB is bootstrap connected to the high-side floating ground Vs terminal through a bootstrap capacitor C1.

[0077] There are two main causes of dV / dt noise: First, when the high-side power transistor IGBT1 is turned on and the low-side power transistor IGBT2 is turned off, the VS potential rises, generating dVS / dt noise. The magnitude of this noise is mainly related to the switching speed of the power transistors and the DC VH voltage. Specifically, the faster the low-side power transistor IGBT2 turns off, the stronger the dVS / dt noise signal. Second, when driving an inductive load, if IGBT2 turns off too quickly, the energy on the load inductor L_load is not completely depleted. In this case, the load inductor L_load will form a freewheeling circuit with the body diode D3 of IGBT1. Because the diode's turn-on speed is very fast, the VS voltage changes instantaneously, resulting in significant dV / dt noise. Since the VB and VS terminals are connected through the bootstrap capacitor C1, the dV / dt noise is coupled to the high-voltage floating power supply inside the chip through the bootstrap capacitor, thus generating the same dV / dt noise in VB. Figure 3As shown, the power supply for the integrated high-voltage level shift circuit is this floating voltage. This high-voltage level shift circuit mainly consists of an HVNLDMOS transistor connected in series with resistors. Due to manufacturing process limitations, the HVNLDMOS transistor has parasitic capacitances C1 and C2 at its drain and source terminals. This causes dV / dt noise to generate significant displacement currents IC1 and IC2 through the parasitic capacitances at the drain terminals of the HVNLDMOS transistor. These displacement currents pass through the drain resistors R4 and R5 of the high-voltage level shift circuit, resulting in voltage drops VR4 and VR5 across the drain resistors. Since VSD = VB - VR4 and VRD = VB - VR5, and generally R4 = R5, VSD = VRD. The larger the dV / dt noise, the smaller VSD or VRD. The circuit timing is as follows: Figure 4 As shown, if the voltage drop exceeds the logic input threshold of the subsequent module, the RS flip-flop will output an abnormal drive signal, causing the high-side power transistor IGBT1 to erroneously turn on or off, affecting the normal logic function of the chip. Therefore, the high-voltage level shift circuit, as the bridging part between the high-side floating power supply and the low-side low-voltage circuit, determines the reliability of the chip through its dV / dt noise immunity. In addition, dV / dt noise and VS negative voltage overshoot can also interfere with the low-side GND and VCC through the parasitic capacitance, parasitic diodes, and parasitic transistors inside the chip, thus affecting the SET and RESET signals. When the interfering signal meets the turn-on condition of HVNLDMOS (the first input switch and the second input switch), i.e., VSET-VGND>Vth or VRESET-GND>Vth, a false trigger signal will be introduced, causing the IGBT1 on the upper bridge to erroneously turn on or off.

[0078] To address the aforementioned technical problems, this application provides a high-voltage level shifting circuit, comprising: a dual-pulse shaping circuit for shaping and inverting a received first pulse signal and a second pulse signal respectively to obtain a first inverted pulse signal and a second inverted pulse signal; and a common-mode noise filtering circuit electrically connected to the dual-pulse shaping circuit for filtering out noise signals in the first inverted pulse signal and the second inverted pulse signal to obtain and output a reset signal and a set signal respectively. The common-mode noise filtering circuit includes: a first switching transistor, the gate of which is connected to a dual-pulse shaping circuit and a floating power supply, for receiving a second inverted pulse signal and controlling the first switching transistor to turn on or off via the second inverted pulse signal; a second switching transistor, the gate of which is connected to the dual-pulse shaping circuit and a floating power supply, for receiving a first inverted pulse signal and controlling the second switching transistor to turn on or off via the first inverted pulse signal, wherein the input terminal of the first switching transistor is connected to the gate of the second switching transistor, and the input terminal of the second switching transistor is connected to the gate of the first switching transistor; a first current limiting circuit, one end of which is connected to the output terminal of the first switching transistor and the other end of which is connected to a floating ground terminal, the output terminal of the first switching transistor being used to output a reset signal; and a second current limiting circuit, one end of which is connected to the output terminal of the second switching transistor and the other end of which is connected to a floating ground terminal, the output terminal of the first switching transistor being used to output a set signal.

[0079] With the high-voltage level shifting circuit of this application, when dV / dt noise is applied to the floating power supply voltage, both the first and second switching transistors are in the off state. The common-mode noise filtering circuit maintains the output of low-level reset and set signals. Therefore, dV / dt noise can be eliminated, and it will not interfere with the subsequent circuits. This effectively improves the problem that the power transistors are mistakenly turned on due to dV / dt noise, which leads to the shoot-through of the upper and lower bridge power transistors and causes serious damage to the system.

[0080] Below, we will refer to Figure 5 and Figure 6 The structure of the high-voltage level shifting circuit of this application is described. It is worth mentioning that, without conflict, the technical features of the various embodiments of this application can be combined with each other.

[0081] First, such as Figure 5 As shown, the high-voltage level shifting circuit of this application includes: a dual-pulse shaping circuit 510, used to shape and invert the received first pulse signal SET and second pulse signal RESET respectively to obtain a first inverted pulse signal SET' and a second inverted pulse signal RESET'.

[0082] Optionally, the dual-pulse shaping circuit 510 is electrically connected to the preceding pulse generation circuit. The pulse generation circuit encodes the rising and falling edges of the received PWM pulse width modulation signal into a first pulse signal SET and a second pulse signal RESET, respectively. Optionally, both the first and second pulse signals are square wave signals. Optionally, the high-level portions of the first pulse signal SET and the second pulse signal RESET do not overlap in timing to prevent the RS latch from entering an unknown state.

[0083] The dual-pulse shaping circuit 510 includes a first pulse shaping circuit and a second pulse shaping circuit. The two pulse shaping circuits have basically the same structure. They are used to receive the first pulse signal SET and the second pulse signal RESET, respectively, and shape them.

[0084] In one example, a first pulse shaping circuit is used to shape and invert the received first pulse signal, outputting a first inverted pulse signal SET'. The first pulse shaping circuit includes a first input switch NM1, the gate of which receives the first pulse signal SET and controls the first input switch NM1 to be turned on or off based on the first pulse signal SET. Optionally, the first input switch NM1 can be any suitable switch, such as an NMOS or PMOS. For example, the first input switch NM1 is a high-voltage N-type LDMOS device.

[0085] In one example, the first pulse shaping circuit further includes a first current-limiting resistor R2. One end of the first current-limiting resistor R2 is connected to the input terminal of the first input switch NM1 (for example, if the first input switch is a high-voltage N-type LDMOS device, then the input terminal can refer to the drain terminal of the LDMOS device), and the other end is connected to the gate of the second switch PM2, for outputting a first inverted pulse signal SET' to the second switch. Optionally, the number of first current-limiting resistors R2 can be one or more, which is not specifically limited here. The first current-limiting resistor R2 can limit the current in the branch, preventing excessive current from burning out the switch and other devices. Furthermore, the first current-limiting resistor R2 can limit the current within a predetermined safe range, and it can also be used as a voltage divider resistor.

[0086] In one example, the first pulse shaping circuit further includes a first current mirror circuit 511. The first current mirror circuit 511 is coupled between the output terminal and the gate of the first input switch NM1. That is, one end of the first current mirror is connected to the source terminal of the first input switch NM1, and the other end is connected to the gate to receive the first pulse signal SET. By setting this current mirror circuit, the circuit's noise immunity can be improved. Furthermore, by utilizing the characteristics of the current mirror, a negative feedback loop can be provided to facilitate monitoring the on or off state of NM1. When the first pulse signal SET is a valid signal, the pulse signal is momentarily set low to drive the first input switch NM1 to turn on and off with a narrow pulse, thereby reducing power consumption.

[0087] In one example, a diode (e.g., a reverse Zener diode or a forward diode, not shown) can be connected in series between the source of the first input switch NM1 and the base of the first NPN transistor to increase the NPN threshold voltage, so that it is turned on when the effective signal of the first pulse signal SET is high, and turned off when there is noise signal in order to filter out interference signals.

[0088] In one example, the first current mirror circuit 511 can be any suitable circuit structure. For example, the first current mirror circuit 511 includes a first NPN transistor Q1 and a second NPN transistor Q2. The collector of the first NPN transistor Q1 is connected to the gate of the first input switch NM1, and the emitter of the first NPN transistor Q1 is connected to ground. The collector of the second NPN transistor Q2 is connected to the output terminal (e.g., the source terminal) of the first input switch NM1, the emitter of the second NPN transistor Q2 is connected to ground, and the base of the second NPN transistor Q2 is electrically connected to the base of the first NPN transistor Q1. The base of the second NPN transistor Q2 is also electrically connected to the output terminal (e.g., the source terminal) of the first input switch NM1. By using two NPN transistors to form a current mirror circuit, the circuit's anti-signal interference capability is enhanced, and the structure is simple and low-cost.

[0089] In one example, the second pulse shaping circuit is used to shape the received second pulse signal RESET and output a shaped second inverted pulse signal RESET'. The second pulse shaping circuit includes a second input switch NM2, a second current-limiting resistor R3, and a second current mirror circuit 512. The gate of the second input switch NM2 receives the second pulse signal RESET. One end of the second current-limiting resistor R3 is connected to the input terminal of the second input switch, and the other end is connected to the gate of the first switch PM1, for outputting the second inverted pulse signal RESET' to the first switch PM1 to drive the first switch PM1 to turn on and off. Optionally, the number of second current-limiting resistors R3 can be one or more, without specific limitation. The second current-limiting resistor R3 can limit the current in the branch, preventing excessive current from burning out the switch and other devices. It can also limit the current within a predetermined safe range and can be used as a voltage divider resistor.

[0090] Optionally, the second current mirror circuit 512 is coupled between the output terminal and the gate of the second input switch NM2. That is, one end of the second current mirror circuit 512 is connected to the source terminal of the second input switch NM2, and the other end is connected to the gate to receive the second pulse signal RESET. By setting this current mirror circuit, the circuit's noise immunity can be improved. Furthermore, by utilizing the characteristics of the current mirror, a negative feedback loop can be provided to facilitate monitoring the on or off state of NM2. When the second pulse signal RESET is a valid signal, the pulse signal is momentarily set low to drive the second input switch NM2 to turn on and off with a narrow pulse, thereby reducing power consumption.

[0091] In one example, a diode (e.g., a reverse Zener diode or a forward diode, not shown) can be connected in series between the source of the second input switch NM1 and the base of the fourth NPN transistor to increase the NPN threshold voltage, so that it turns on when the effective signal of the second pulse signal RESET is high and turns off when there is noise signal in order to filter out interference signals.

[0092] In one example, the second current mirror circuit 512 can use any suitable circuit structure. For example, the second current mirror circuit 512 includes: a third NPN transistor Q3 and a fourth NPN transistor Q4. The collector of the third NPN transistor Q3 is connected to the gate of the second input switch NM2, and the emitter of the third NPN transistor Q3 is connected to ground. The collector of the fourth NPN transistor Q4 is connected to the output of the second input switch NM2, and the emitter of the fourth NPN transistor is connected to ground. The base of the fourth NPN transistor Q4 is electrically connected to the base of the third NPN transistor Q3, and the base of the fourth NPN transistor Q4 is also electrically connected to the output of the second input switch NM2. By using two NPN transistors to form a current mirror circuit, the circuit's noise signal interference immunity is enhanced, and the structure is simple and low-cost.

[0093] Furthermore, to improve the circuit's noise signal interference immunity, the high-voltage level shifting circuit of this application also includes a common-mode noise filtering circuit, which is electrically connected to the dual-pulse shaping circuit 510. This circuit filters out noise signals from the first and second inverted pulse signals to obtain and output a reset signal and a set signal, respectively. The common-mode noise filtering circuit includes a first switching transistor PM1, whose gate is connected to the dual-pulse shaping circuit 510 and a floating power supply (i.e., the high-side floating power supply VB terminal). This floating power supply receives the second inverted pulse signal RESET' and controls the first switching transistor PM1 to turn on or off, thereby outputting a set signal SD.

[0094] The common-mode noise filtering circuit 520 further includes: a second switch PM2, the gate of which is connected to the dual-pulse shaping circuit 510 and the floating power supply, for receiving the first inverted pulse signal SET', and controlling the second switch PM2 to be turned on or off (sometimes referred to as off in this document) through the first inverted pulse signal SET', wherein the input terminal (e.g., its source terminal) of the first switch PM1 is connected to the gate of the second switch PM2, and the input terminal (e.g., its source terminal) of the second switch PM2 is connected to the gate of the first switch PM1.

[0095] The common-mode noise filtering circuit 520 also includes a first current limiting circuit, one end of which is connected to the output terminal of the first switching transistor PM1 (e.g., the drain terminal of the first switching transistor PM1), and the other end is connected to the floating ground terminal (also referred to as the high-side floating ground Vs terminal in this article). The output terminal of the first switching transistor PM1 is used to output the reset signal RD. The first current limiting circuit can limit the current in the branch to prevent the current from being too large and burning out the switching transistor and other devices. The first current limiting circuit can also be used as part of a voltage divider circuit.

[0096] The first current limiting circuit can adopt any suitable circuit structure that can play a current limiting protection role. Optionally, the first current limiting circuit may include at least one first resistor R6. When there are multiple first current limiting resistors, the multiple first resistors R6 are connected in series or in parallel.

[0097] The common-mode noise filtering circuit 520 also includes a second current-limiting circuit, one end of which is connected to the output terminal of the second switching transistor PM2, and the other end is connected to the floating ground terminal. The output terminal of the first switching transistor PM1 is used to output the third set signal. The second current-limiting circuit can limit the current in the branch, preventing excessive current from burning out the switching transistor and other devices. The second current-limiting circuit can also be used as part of a voltage divider circuit.

[0098] The second current limiting circuit can adopt any suitable circuit structure that can play a current limiting protection role. Optionally, the second current limiting circuit may include at least one second resistor R7. When there are multiple second resistors, the multiple second current limiting resistors are connected in series or in parallel.

[0099] When dV / dt noise is applied to the floating power supply VB, both the first switch PM1 and the second switch PM2 are in the off state. The common-mode noise filtering circuit 520 maintains a low-level output reset signal RD and set signal SD. Therefore, it can eliminate dV / dt noise and will not interfere with the subsequent circuits. This effectively improves the problem of the power transistors being incorrectly turned on due to dV / dt noise, which causes the upper and lower bridge power transistors to shoot through and seriously damage the system.

[0100] Optionally, the first switch PM1 and the second switch PM2 can be the same type of switch, such as both being NMOS or PMOS. In the embodiments of this application, the first switch PM1 and the second switch PM2 are mainly PMOS.

[0101] In one example, the high-voltage level shifting circuit further includes: a first input resistor R4 and a second input resistor R5, one end of the first input resistor R4 being connected to a floating power supply and the other end being connected to a first current-limiting resistor R2, and one end of the second input resistor R5 being connected to a floating power supply and the other end being connected to a second current-limiting resistor R3.

[0102] Optionally, the first input resistor R4 and the second input resistor R5 can have the same resistance value, which can be achieved using one or more resistors. The first input resistor R4 and the second input resistor R5 can be used as voltage divider resistors. For example, the first input resistor R4 and the first current-limiting resistor R2 can form a voltage divider circuit, with the voltage divider node positioned between the first input resistor R4 and the first current-limiting resistor R2 to output a first inverted pulse signal SET'. This output is high-level when the branch containing the first input resistor R4 and the first current-limiting resistor R2 is conducting and low-level when it is off. Similarly, the second input resistor R5 and the second current-limiting resistor R3 can form a voltage divider circuit, with the voltage divider node positioned between the second input resistor R5 and the second current-limiting resistor R3 to output a second inverted pulse signal RESET'. This output is high-level when the branch containing the second input resistor R5 and the second current-limiting resistor R3 is conducting and low-level when it is off. Therefore, the first input resistor R4 and the second input resistor R5 can provide current limiting protection and voltage division, thereby ensuring the normal output of the reset signal and set signal generated by the circuit.

[0103] In one example, the high-voltage level shifting circuit of this application also includes a voltage regulator circuit. The first input resistor and the second input resistor are connected in parallel with a voltage regulator circuit 531 and 532, respectively. Each voltage regulator circuit includes at least two diodes connected in series. The negative terminal of one diode is electrically connected to a floating power supply. The diode operates under reverse bias conditions. When the reverse voltage is lower than the breakdown voltage of the diode (also known as the Zener voltage or the voltage regulation value), the voltage regulator circuit is almost non-conductive. Once the reverse voltage reaches or exceeds the voltage regulation value, the diode will enter the breakdown region. At this time, the current will increase significantly, but the voltage across the diode will remain almost unchanged. This stable voltage value is the voltage regulation value of the diode. By connecting at least two diodes in series, the voltage regulation value of the voltage regulator circuit can be improved, and it can also play a role in reverse current limiting protection.

[0104] For example, such as Figure 5 As shown, the first voltage regulator circuit 531, connected in parallel with the first input resistor R4, includes a first diode D1 and a second diode D2 connected in series. The anode of the first diode D1 is connected to the end where the first input resistor R4 and the first current-limiting resistor R2 are connected, and the cathode of the first diode D1 is connected to the anode of the second diode D2. The cathode of the second diode D2 is electrically connected to the floating power supply VB. The second voltage regulator circuit 52, connected in parallel with the second input resistor R5, includes a third diode D3 and a fourth diode D4 connected in series. The anode of the third diode D3 is connected to the end where the second input resistor R5 and the second current-limiting resistor R3 are connected, and the cathode of the fourth diode D4 is connected to the anode of the fourth diode D4. The cathode of the fourth diode D4 is electrically connected to the floating power supply VB.

[0105] The first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 can be Zener diodes or other suitable types of diodes.

[0106] It is worth noting that, in this application, the term "the connection state of component A and component B" includes not only the case where component A and component B are physically and directly connected, but also the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved through their coupling, such as indirect connection via resistors or diodes.

[0107] The first and second input switching transistors of this application can be high-voltage devices, such as transistors with a DMOS (Double-Diffused MOS) structure. However, transistors with other structures can also be used, such as HVMOS (High Voltage MOSFET), LDMOS (Lateral Diffusion MOSFET), IGBT (Insulated Gate Bipolar Transistor), SiC (Silicon Carbide)-JFET, SiC-MOSFET, etc. Other transistors not specifically designated as high-voltage devices can be MOSFETs with typical voltage ratings.

[0108] The following will combine Figure 6The timing diagram shown describes the working principle of the high-voltage level shift circuit of this application. In the absence of dV / dt noise, when the first pulse signal SET is high and the second pulse signal RESET is low, the first input switch NM1 is turned on and the second input switch NM2 is turned off. Therefore, the generated first inverted pulse signal SET' is high, which turns off the first switch PM1, and the generated second inverted pulse signal RESET' is low, which turns on the second switch PM2. When the first switch PM1 is turned off, the RD signal is set low, and when the second switch PM2 is turned on, the SD signal is set high, thereby ensuring normal signal output. When dV / dt noise is applied to VB, the same voltage drop is generated across the first input resistor R4 and the second input resistor R5. That is, the voltage applied to the source and gate terminals of the first switch PM1 is equal, and the voltage applied to the source and gate terminals of the second switch PM2 is equal. Therefore, the gate-source voltage VGS of the first switch PM1 is equal to zero, and the gate-source voltage VGS of the second switch PM2 is also equal to zero. Both the first switch PM1 and the second switch PM2 are in the cutoff region. The voltage across the first resistor R6 and the second resistor R7 is VS, which means that the low-level reset signal RD and set signal SD are output. Therefore, the dV / dt noise is eliminated and will not interfere with the subsequent circuits.

[0109] When interference noise is applied to the first pulse signal SET and the second pulse signal RESET, the NPN transistors with their sources connected in series, such as the first input switch NM1 and the second input switch NM2, increase the turn-on threshold of these transistors. Interference signals introduced by ground voltage GND and power supply voltage VCC are shielded at the source terminals of the first input switch NM1 and the second input switch NM2. Compared to the conventional structure, where the first input switch NM1 and the second input switch NM2 will turn on as long as the level of the first pulse signal VSET or the level of the second pulse signal RESET is greater than the threshold voltage Vth, the circuit structure of this invention requires the narrow pulse to meet a predetermined pulse width and amplitude to turn on the first input switch NM1 and the second input switch NM2. Since the pulse width and amplitude of noise signals are typically lower than those of normal signals in pulse signals, the noise signals cannot drive the first input switch NM1 and the second input switch NM2 to turn on, thus filtering out interference signals.

[0110] Although the high-voltage level shifting circuit in the aforementioned embodiments can improve the noise problem in pulse signals, since high-voltage gate driver chips are often used to drive inductive loads in many applications, a key characteristic of inductive loads is that the current cannot change abruptly. Therefore, IPM modules typically use 2, 4, or 6 power transistors to form half-bridge, full-bridge, or three-phase circuit drive structures to meet the driving requirements of various motors. Taking a half-bridge circuit structure as an example... Figure 7 As shown, under rapid turn-off changes, the current on the load inductor L_load cannot change abruptly, forcing the parasitic inductors L3 and L4 and the reverse recovery diode D2 of the power transistor IGBT2 to form a current freewheeling loop. A significant negative overshoot voltage is generated at the high-side floating ground VS terminal of the HVIC driver chip. The high-side floating power supply VB terminal is connected to the high-side floating ground VS terminal through an external bootstrap capacitor. Therefore, the voltage at the VB terminal follows the voltage change of VS. As the VS voltage decreases, this situation strongly interferes with the high-voltage level shifting circuit of the HVIC and subsequent logic module circuits, leading to false turn-on and false turn-off phenomena. When the negative overshoot voltage of VS reaches 15V, this causes the HVIC power supply voltage VB to also fall below 0V. When the VB voltage is less than the reference ground GND, it forces the parasitic diode between the high-voltage trap and the substrate to conduct, i.e., the parasitic diode from GND to VB, allowing current to flow through the substrate. This substrate current may cause latch-up in the high-side drive circuit, resulting in a short circuit between the upper and lower bridge IGBT1 and IGBT2, generating excessive power consumption and burning out the device. When the reset signal RD and set signal SD output from the high-voltage level shift circuit pass through the noise cancellation circuit to eliminate the common-mode noise and differential-mode noise of DV / DT, the signals RD' and SD' are obtained. However, as the input pulse width decreases and IGBT1 turns off faster, the negative overshoot of VS overlaps with the set signal RESET, which can still cause the set signal SD to be falsely triggered as a valid high-level signal, causing the latch RS_LATCH to latch incorrectly, resulting in false triggering. When the negative overshoot of VS occurs, VB will change with VS. If VB < 0, the parasitic diode of GND to VB will be forward turned on, charging the external capacitor connected to VB. If VB > 0, the parasitic diode of GND to VB will be turned off, and according to the diode characteristics, a reverse recovery current will be generated. Figure 8 This indicates the operating state of the high-voltage level shift circuit when the first pulse signal SET = 0 and the second pulse signal RESET = 1. The reverse recovery currents IRS and IRR flow to parasitic diodes D11 and D22, respectively. Without an edge-triggered circuit, the circuit timing diagram is as follows: Figure 9AAs shown, if the second pulse signal RESET is high-effective and overlaps with the negative voltage of VS, then IRS > IRR and VR4 > VR5. Since VSET’ = VB - VR4 and VRESET’ = VB - VR5, so VSET’ < VRESET’, which causes PM1 to turn off and PM2 to turn on, setting the reset signal RD output by the high-voltage level shift circuit to a low level and the set signal SD to a high level. Then, the set signal (RS_LATCH SET) input to the latch RS_LATCH is also at a high level, while the reset signal (RS_LATCH RESET) input to the latch RS_LATCH is at a low level, resulting in the RS_LATCH latching an error signal (for example, outputting a high-level signal, while actually according to the initial first and second pulse signals, at this time period, the RS_LATCH latch should output a low level and not trigger the IGBT1 to turn on), leading to a mis-triggering.

[0111] To solve the above technical problems, the present application provides a trigger circuit that can receive the set signal and reset signal output by the high-voltage level shift circuit, or receive the filtered set signal and reset signal output by the noise cancellation circuit, as Figure 9B As can be seen from the circuit timing diagram shown, by setting this trigger circuit, if RESET is high-effective (i.e., an effective high level) and does not overlap with the negative voltage of VS, then IRS ≈ IRR, VR4 ≈ VR5, VSET’ ≈ VRESET’, which causes PM1 to turn off and PM2 to turn off, setting RD to low and SD to low, thereby keeping the latch RS_LATCH latched and avoiding mis-triggering.

[0112] Specifically, the trigger circuit of the present application will be described below with reference to Figures 10 to 12 the following.

[0113] As an example, as Figure 10As shown, the trigger circuit of this application includes two edge-triggered circuits for processing the reset signal RD and the set signal SD, respectively. Each edge-triggered circuit includes: a first pulse modulator 1010, whose input terminal is used to receive a first drive signal and perform delay and noise filtering processing on the first drive signal to obtain a second drive signal RDB, wherein the first drive signal is either the reset signal RD or the set signal SD; a rising edge trigger DFF1, whose input terminal is used to receive the first drive signal and process the first drive signal to obtain a first output signal Q1, wherein the rising edge of the first drive signal triggers the rising edge trigger to make the first output signal Q1 high; and a falling edge trigger DFF1. 2. Its input terminal is connected to the first pulse modulator 1010, used to receive the second driving signal and process it to obtain the second output signal. The falling edge of the second driving signal RDB triggers the falling edge flip-flop DFF2 to make the second output signal Q2 high. The logic operation circuit 1030, electrically connected to the rising edge flip-flop DFF1 and the falling edge flip-flop DFF2, is used to perform operations on the received first output signal Q1 and second output signal Q2 to obtain the target driving signal RD' and send it to the latch, so that the latch outputs a switching signal to drive the driven device to turn on or off. When noise appears in the first output signal Q1, the target driving signal RD' outputs a latching signal to the latch, so that the latch latches and holds the signal. Through the triggering circuit of this application, the false triggering of the driven device caused by noise signals due to the negative voltage VS and the narrow pulse width of the input signal can be improved, resulting in a clean output driving signal. This solves the problem of latch-up effect caused by device false triggering, which can severely damage the system.

[0114] Since the edge-triggered circuits used to process the set signal and the reset signal have the same structure, the following explanation and illustration will mainly take the edge-triggered circuit used to process the reset signal as an example.

[0115] The first pulse modulator 1010 can be any suitable modulator, which can filter out signals with a certain noise width and play the role of pulse modulation.

[0116] In one example, the first pulse modulator 1010 can be implemented as follows: Figure 11The structure shown illustrates that the first pulse modulator 1010 includes a signal shaping circuit 1011 for receiving a first drive signal (i.e., the input terminal VIN receives, for example, a reset signal RD or a set signal SD), and shaping the first drive signal to obtain a square wave signal. For example, the signal shaping circuit 1011 may consist of at least two inverters INV connected in series. After the first drive signal passes through the inverters INV, a square wave signal is obtained, resulting in a relatively ideal square wave signal. By utilizing the oscillation characteristics of the inverters INV, the output signal of the inverters continuously switches between high and low levels, thereby generating a relatively ideal square wave signal. Optionally, the inverter can be a CMOS inverter, a TTL inverter, or other suitable inverters.

[0117] In one example, such as Figure 11 As shown, the first pulse modulator also includes a filter circuit 1012 and a Schmitt trigger SMIT. The filter circuit 1012 is connected to the signal shaping circuit 1011 and is used to filter the square wave signal to obtain the filtered signal. The Schmitt trigger SMIT is connected to the filter circuit 1012 and is used to filter out noise signals in the filtered signal and output a second drive signal.

[0118] For example, the filter circuit 1012 can be an RC filter circuit or other suitable circuits. Using the filter circuit 1012, the rising edge of the square wave signal output by the signal shaping circuit is slowed down, which helps to provide a stable input signal to the subsequent Schmitt trigger, reducing false triggering of the Schmitt trigger due to rapid signal changes. Furthermore, because noise signals and normal pulse signals have different pulse widths, they will behave differently when passing through an RC filter circuit. Noise signals are often narrower, so the voltage accumulated on the capacitor of the RC filter circuit may not be sufficient to trigger subsequent circuits (such as Schmitt triggers). Normal pulse signals, on the other hand, have a wider pulse width, allowing sufficient voltage to accumulate on the capacitor to trigger subsequent circuits. Thus, the RC charging circuit performs both filtering and shaping functions, removing noise signals and retaining normal pulse signals.

[0119] In a specific example, the filter circuit 1012 includes a charging resistor R1, a capacitor C1, and a switching module. One end of the charging resistor R1 and one end of the capacitor C1 are connected. The square wave signal output by the signal shaping circuit 1011 is used to control the switching module to turn on or off so that the power supply voltage VCC charges the capacitor C1 through the charging resistor R1 or the capacitor C1 discharges through the switching module. For example, the switching module includes a first switch P1 and a second switch N1. The gate of the first switch P1 is connected to a signal shaping circuit 1011 to receive a first drive signal. The gate of the second switch N1 is also connected to the signal shaping circuit 1011 to receive the first drive signal. The first switch P1 and the second switch N1 are connected in series between the power supply voltage VCC and the ground terminal GND. One end of the first switch P1 is connected to the power supply, and one end of the second switch N1 is connected to the ground terminal. The first switch P1 and the second switch N1 are connected via a charging resistor R1. The first switch P1 and the second switch N1 are different types of switches and do not conduct simultaneously. For example, the first switch is a PMOS and the second switch is an NMOS. Specifically, the source terminal of the first switch P1 is connected to the power supply voltage VCC, the drain terminal of the first switch P1 is connected to the drain terminal of the second switch N1 via the charging resistor R1, and the source terminal of the second switch N1 is connected to the ground terminal GND. Capacitor C1 and the second switch N1 are connected in parallel, and capacitor C1 is also connected to a Schmitt trigger SMIT. When the square wave signal output by the signal shaping circuit 1011 controls the first switch P1 to turn on and the second switch N1 to turn off, the power supply voltage VCC charges capacitor C1 through the charging resistor R1. When the voltage of capacitor C1 is higher than the first switching level of Schmitt trigger SMIT, Schmitt trigger SMIT outputs a high-level signal. When the voltage of capacitor C1 is lower than the second switching level, Schmitt trigger outputs a low-level signal. The first switching level is higher than the second switching level.

[0120] Specifically, the charging circuit in the RC filter circuit is utilized. When the first switch P1 is turned on, for example, when the signal shaping circuit 1011 outputs a low-level signal, the first switch P1 is turned on, and the voltage of the power supply VCC charges the capacitor C1 through the charging resistor R1, thereby changing the rising slope of the pulse signal and transforming the originally rapidly changing pulse signal into a slowly rising signal. If the normal input signal contains noise, the maximum voltage reached by the capacitor C1 will differ from the width of the noise signal due to the difference between the noise signal and the normal short pulse signal. When the input pulse signal arrives, the capacitor C1 is charged through the charging resistor R1. If the voltage across the capacitor C1 reaches the first flip-flop level of the subsequent Schmitt trigger, the signal is a normal pulse signal and will be received by the subsequent circuit. In this case, the RC circuit acts as a shaping circuit. If the voltage across the capacitor C1 does not reach the first flip-flop level of the subsequent Schmitt trigger, the signal is a noise signal and will not be received by the subsequent circuit. The circuit state will not change. Therefore, this circuit can filter out noise signals of a certain noise width, achieving the purpose of pulse modulation.

[0121] A Schmitt trigger (SMIT) can be composed of multiple electronic components, including but not limited to CMOS inverters, resistors, diodes, and transistors. For example, two CMOS inverters can be connected in series, and the voltage at the output terminal can be fed back to the input terminal through a voltage divider resistor, thereby forming a circuit with Schmitt triggering characteristics. Specifically, this application does not limit the structure of the Schmitt trigger.

[0122] The Schmitt trigger (SMIT) has two distinct threshold voltage levels (i.e., the first and second flip-flops mentioned earlier): the first flip-flop is the rising threshold (positive threshold), and the second flip-flop is the falling threshold (negative threshold). When the input signal exceeds the rising threshold, the output changes from low to high; when the input signal falls below the falling threshold, the output changes from high to low. This dual-threshold structure makes the Schmitt trigger more sensitive to changes in the input signal and provides some resistance to noise interference.

[0123] In one example, the first pulse modulator 1010 may further include an output inverter INV connected to a Schmitt trigger SMIT to invert the signal output by the Schmitt trigger SMIT, thereby outputting a signal with the same phase as the signal input to the first pulse modulator. However, due to the processing by the inverter and the RC filter circuit, the signal output from the first pulse modulator has a certain delay compared to the signal input to the first pulse modulator.

[0124] Furthermore, the rising edge flip-flop DFF1 of this application has its input terminal used to receive a first drive signal, such as a reset signal RD, and to process the first drive signal to obtain a first output signal Q1. The rising edge of the first drive signal triggers the rising edge flip-flop to make the first output signal Q1 high. This rising edge flip-flop DFF1 ensures that the input signal is read at the beginning of each clock cycle, thereby achieving precise timing control. That is, the triggering action occurs at the rising edge of the first drive signal (i.e., the instant from low to high level). Optionally, the rising edge flip-flop DFF1 can be any suitable flip-flop, such as a D flip-flop. The D flip-flop may include a clock input terminal (CLK) for receiving a clock signal and controlling the triggering timing. When the rising edge (or falling edge, depending on the type of flip-flop) of the clock signal arrives, the flip-flop updates its output according to the data state of the D terminal. The D flip-flop also includes a data input (D) terminal for receiving data to be stored. When the trigger edge of the clock signal arrives, the data at the D terminal is transmitted to the output terminal of the flip-flop. It also includes an output (Q) terminal for outputting the current state of the flip-flop. The state (0 or 1) of the flip-flop is updated based on the data at the D terminal when the trigger edge of the clock signal arrives and is maintained at the Q terminal output. It can also have a reset (R) port to force the output of the flip-flop to 0.

[0125] The rising edge flip-flop DFF1 can contain multiple NAND gates or other logic gates to implement the logic function of the flip-flop, without any specific limitations here.

[0126] Furthermore, the falling edge trigger DFF2 of this application has its input connected to the first pulse modulator 1010. It receives the second drive signal output by the first pulse modulator 1010 and processes it to obtain the second output signal Q2. The falling edge of the second drive signal triggers the falling edge trigger DFF2 to make the second output signal Q2 high. Before the falling edge of the clock signal arrives, the falling edge trigger is in a waiting state. However, when the falling edge of the clock signal arrives, the falling edge trigger updates its output state according to the current input signal (or internal state) and maintains this state until the next falling edge of the clock signal arrives.

[0127] The falling edge trigger DFF1 provides better noise immunity because the falling edge is typically steeper than the rising edge, making it easier to identify and process, thus reducing the likelihood of false triggering.

[0128] The falling edge trigger DFF1 can also be implemented based on a D flip-flop, which can also have a D terminal, a Q terminal, a CLK terminal, and an R terminal.

[0129] Furthermore, the trigger circuit of this application also includes a logic operation circuit 1030, which is electrically connected to a rising edge flip-flop DFF1 and a falling edge flip-flop DFF2. It is used to perform operations on the received first output signal Q1 and second output signal Q2 to obtain a target drive signal and send it to the latch, so that the latch outputs a switch signal to drive the device to be driven to turn on or off. When a noise signal appears in the first output signal, the target drive signal is output as a latch signal to the latch so that the latch latches and holds the signal.

[0130] Optionally, the logic operation circuit 1030 can be an AND gate or other suitable circuit. The logic operation circuit 1030 can comprehensively process the first output signal from the rising-edge flip-flop and the second output signal from the falling-edge flip-flop to generate a more stable and reliable target drive signal. For example, when there is high-level noise in the first input signal, and the second input signal is low, an AND gate will output a low level, thus preventing the noise signal from being output to the next stage circuit.

[0131] AND gates can be implemented in various ways, such as using CMOS logic, NMOS logic, PMOS logic, and diodes. Taking CMOS logic as an example, an AND gate is usually composed of a combination of PMOS and NMOS transistors, and the "AND" operation is achieved by controlling the conduction and cutoff of the transistors. No specific limitation is made here.

[0132] In one example, each edge-triggered circuit further includes a second pulse modulator 1020. The second pulse modulator 1020 is connected to the reset signal input terminal R of the rising edge trigger DFF1 and the falling edge trigger DFF2, and is used to process the target drive signal into a trigger reset signal to reset the rising edge trigger DFF1 and the falling edge trigger DFF2, so that the rising edge trigger DFF1 and the falling edge trigger DFF2 output a low-level signal. The second pulse modulator 1020 can realize the reset operation of the triggers, thereby ensuring that the circuit finally outputs the target drive signal corresponding to the input signal.

[0133] The second pulse modulator 1020 may adopt the same or different structure as the first pulse modulator 1010, and no specific limitation is made here.

[0134] Specifically, it will combine Figure 12The timing sequence of the edge-triggered circuit is described as follows: When a signal pulse arrives at the reset signal RD, the rising edge of the pulse triggers the rising edge flip-flop, causing the output terminal of the rising edge flip-flop to output the first output signal Q1. At this time, Q1 = D = VCC, and the rising edge flip-flop is stored in a high-level state. After the reset signal RD is delayed and filtered by the first pulse modulator PULSE MOD, the second output signal RDB is obtained. The falling edge of this pulse triggers the falling edge flip-flop DFF2, causing Q2 = D = VCC, and the falling edge flip-flop DFF2 is stored in a high-level state. Since both are at a high level, after passing through a logic operation circuit such as an AND gate, it remains at a high level. Therefore, the RD' signal output by the edge-triggered flip-flop is at a high level. After passing through the second pulse modulator, the flip-flop reset signal R is obtained, causing the rising edge flip-flop DFF1 and the falling edge flip-flop DFF2 to enter the reset state and output a low level. After passing through a logic operation circuit such as an AND gate, the RD' signal is set to a low level. The pulse width of the signal output by the pulse modulator (e.g., the first pulse modulator and the second pulse modulator) can be adjusted by adjusting the charging resistor R1 or the capacitor C1. When the pulse width is less than a certain value, it can be determined as a noise signal, so that the second output signal RDB does not respond to the noise signal, thus preventing the noise signal from being read in and avoiding false triggering.

[0135] In summary, the trigger circuit of this application can improve noise immunity and avoid false triggering.

[0136] Furthermore, such as Figure 13 As shown, this application also provides a gate driver chip, which includes a high-side gate driver chip (HVIC). The gate driver chip can be a PWM driver chip or a general-purpose driver chip. The PWM driver chip is a driver chip that can transmit three-phase pulse signals (U-phase, V-phase, and W-phase), while a general-purpose driver chip typically transmits only one pulse signal. Compared to a general-purpose driver chip, the PWM driver chip has two more signal input ports (hereinafter referred to as I / O ports) than a general-purpose chip.

[0137] The gate driver chip includes a pulse generation circuit 1310, which encodes the rising and falling edges of the received PWM pulse width modulation signal into a first pulse signal SET and a second pulse signal RESET, respectively. The pulse generation circuit 1310 may include a filtering and shaping circuit, a low-voltage level shifting circuit, and a narrow pulse generation circuit. The filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it; the low-voltage level shifting circuit processes the PWM pulse width modulation signal to obtain a level-shifted signal; and the narrow pulse generation circuit encodes the rising and falling edges of the level-shifted signal into the first pulse signal and the second pulse signal, respectively. The narrow pulse generation circuit enables precise control of the signal triggering time, achieving high-precision timing control.

[0138] Optionally, the filtering and shaping circuit may include a Schmitt trigger (SMIT) and an input signal filter (INPUTFILTER).

[0139] Specifically, such as Figure 13 The high-voltage gate driver chip circuit structure shown has three voltage domains: a low-voltage region, a working voltage region, and a high-voltage region. The low-voltage region power supply VDD is provided by the working voltage VCC through a linear load regulator REG, primarily for compatibility with the upstream drive capability. The high-voltage region power supply is provided by the working voltage VCC through a bootstrap boost circuit, primarily for compatibility with driving downstream loads. The output control signal directly drives the gate of the power transistor. To ensure normal circuit operation, both the high-voltage and working voltage regions require undervoltage protection circuits, namely HSUVLO and LSUVLO, respectively. The two circuits are identical in structure and parameters except for the device type. Because the devices in the high-voltage region are integrated in a high-voltage isolation island, they must be replaced with isolated devices.

[0140] HIN receives a PWM pulse width modulation signal from a controller such as an MCU. This input signal is at 3.3V CMOS level or 5V TTL level. After the signal is filtered and shaped by a Schmitt trigger (SMIT) and an input signal filter (INPUT FILTER), a clean signal HIN_PWM is obtained. This signal is then transferred from the low voltage region to the operating voltage region by a level shifting circuit (LS_L2H), and the LS_PWM signal (i.e., the level shifted signal) is output. The narrow pulse generation circuit (PULSE GEN) encodes the rising and falling edges of the high-side signal of the LS_PWM signal into two narrow pulse signals, namely the first pulse signal PWM1 and the second pulse signal PWM2.

[0141] Furthermore, such as Figure 13As shown, the high-voltage gate driver chip of this application also includes a high-voltage level shifting circuit 1320, which can be implemented as the high-voltage level shifting circuit in the aforementioned embodiment, thereby having the aforementioned high-voltage level shifting circuit's function of resisting noise signal interference.

[0142] The narrow pulse signals are used as the gate inputs of two high-voltage LDMOS transistors (such as the aforementioned first and second input switches) in the high-voltage level shifter circuit (LEVEL_SHIFTER). Two inverted narrow pulse signals are generated at the drain of the high-voltage LDMOS transistors. After passing through the common-mode noise filtering circuit, a reset signal RD and a set signal SD are generated. The high-voltage level shifter circuit 1320 shifts the signals from the operating voltage region to the high-voltage region.

[0143] In one example, a noise cancellation circuit 1330 is also included, with one end connected to a high-voltage level shift circuit 1320 and the other end connected to a trigger circuit. This circuit filters out noise from the reset signal RD and the set signal SD before outputting them to the trigger circuit 1340. After passing through the noise cancellation circuit, the differential-mode noise in the reset signal RD and the set signal SD is filtered out, resulting in the RD' and SD' signals.

[0144] In one example, the circuit also includes the edge triggering circuit (EDGE TRIGGER) from the aforementioned embodiments. The RD' and SD' signals pass through the edge triggering circuit (EDGE TRIGGER) to prevent false triggering caused by the negative VS voltage and the narrow pulse width HIN, thus obtaining clean signals.

[0145] In one example, a latch 1350 and a drive circuit 1360 are also included. The latch 1350 is electrically connected to a trigger circuit 1340 and is used to process the signal output by the trigger circuit 1340 to obtain a switching signal to drive the device under test to turn on or off. The drive circuit 1360 is connected to the gate of the target switching transistor (e.g., a high-side power transistor IGBT1) and is used to drive the target switching transistor to turn on or off. The drive circuit 1360 includes the device under test, and the output of the latch 1350 is connected to the gate of the device under test, which is a switching transistor. The signal output by the latch 1350 controls the switching transistor to turn on or off, thereby controlling the drive circuit 1360 to turn on or off. In a specific example, the latch 1350 restores the signal output by the trigger circuit 1340 to a normal floating voltage switching signal and outputs it to the drive circuit to control the drive circuit to turn on or off, obtaining a HO signal. The HO signal is output to the high-side power transistor IGBT1 through the driver circuit 1360, thereby realizing the turn-on / turn-off of the high-side power transistor IGBT1.

[0146] Optionally, latch 1350 can be an RS latch, which can be a low-level active flip-flop, and may include a first trigger terminal S, a second trigger terminal R, and a flip-flop output terminal Q. Optionally, the first trigger terminal S receives the aforementioned SD' signal and changes its level state. The second trigger terminal R receives the aforementioned RD' signal and changes its level state. The flip-flop output terminal Q outputs a control signal (i.e., a switching signal) for the drive circuit according to the level states of the first trigger terminal S and the second trigger terminal R.

[0147] Specifically, the structure of the drive circuit 1360 can be any suitable circuit, and no specific limitation is made here.

[0148] Since the gate driver chip of this application has the aforementioned high-voltage level shift circuit and / or the aforementioned edge triggering circuit, it has the same advantages as the aforementioned high-voltage level shift circuit and / or the aforementioned edge triggering circuit.

[0149] This application also provides a smart power module, including the aforementioned gate driver chip.

[0150] The gate driver chip in this application is a high-voltage gate driver chip, belonging to the high-side gate driver chip category, and is used in intelligent power modules (IPMs). Optionally, three single-channel high-side gate driver chips, one three-channel low-side gate driver chip, and six power transistors can be packaged together in an IPM for driving three-phase motors. It can be used in, for example, electric vehicles, home appliances, and industrial equipment.

[0151] by Figure 2 Taking a smart power module with a half-bridge circuit structure as an example, it includes a high-side gate driver chip HVIC and a low-side gate driver chip LVIC. The high-side gate driver chip HVIC outputs a high-voltage drive signal (HO) to control the high-side power transistor IGBT1. The low-side gate driver chip LVIC outputs a low-voltage drive signal (LO) to control the low-side power transistor IGBT2.

[0152] Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power transistor IGBT1 and the low-side power transistor IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power transistor IGBT1 and the low-side power transistor IGBT2 are turned on alternately.

[0153] The IPM of this application has the aforementioned gate driver chip, and therefore also has the advantages of the aforementioned gate driver chip.

[0154] Furthermore, this application also provides a device that may include the aforementioned trigger circuit, or the aforementioned gate driver chip, or the aforementioned smart power module.

[0155] The device can be any electronic product or device such as a household appliance (e.g., an inverter air conditioner), a television, a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television set, a VCD player, a DVD player, a GPS navigator, a camera, a camcorder, a voice recorder, an MP3 player, an MP4 player, or a PSP. Alternatively, the device can also be a vehicle or other transportation equipment.

[0156] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several vehicle systems, several of these vehicle systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0157] The above are merely specific embodiments or descriptions of specific embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A gate driver chip, characterized in that, include: A pulse generation circuit is used to encode the rising edge and falling edge of the received PWM pulse width modulation signal into a first pulse signal and a second pulse signal, respectively. A high-voltage level shifting circuit, which is electrically connected to the pulse generation circuit, is used to receive the first pulse signal and the second pulse signal; The high-voltage level shifting circuit includes: A dual-pulse shaping circuit is used to shape and invert the received first pulse signal and second pulse signal respectively to obtain a first inverted pulse signal and a second inverted pulse signal. A common-mode noise filtering circuit is electrically connected to the dual-pulse shaping circuit, used to filter out noise signals in the first inverted pulse signal and the second inverted pulse signal to obtain and output a reset signal and a set signal, respectively. The common-mode noise filtering circuit includes: The first switching transistor has its gate connected to the dual-pulse shaping circuit and the floating power supply. It is used to receive the second inverted pulse signal and control the first switching transistor to be turned on or off through the second inverted pulse signal. The second switch, whose gate is connected to the dual-pulse shaping circuit and the floating power supply, is used to receive the first inverted pulse signal and control the second switch to be turned on or off by the first inverted pulse signal. The input terminal of the first switch is connected to the gate of the second switch, and the input terminal of the second switch is connected to the gate of the first switch. The first current limiting circuit has one end connected to the output terminal of the first switching transistor and the other end connected to the floating ground terminal. The output terminal of the first switching transistor is used to output the reset signal. The second current limiting circuit has one end connected to the output terminal of the second switching transistor and the other end connected to the floating ground terminal. The output terminal of the second switching transistor is used to output the set signal. A noise cancellation circuit, electrically connected to the high-voltage level shifting circuit, is used to receive and filter out differential-mode noise in the set signal and the reset signal; A trigger circuit, electrically connected to the noise cancellation circuit, is used to receive the signal output by the noise cancellation circuit, process the signal output by the noise cancellation circuit to obtain a target driving signal, and when a noise signal appears in the signal output by the noise cancellation circuit, the target driving signal is output as a latch signal. The trigger circuit includes: A first pulse modulator is used to receive a first driving signal and perform delay and noise filtering on the first driving signal to obtain a second driving signal, wherein the first driving signal is a reset signal or a set signal. A rising edge trigger is used to receive the first drive signal and process the first drive signal to obtain a first output signal; A falling-edge trigger is used to receive the second drive signal and process it to obtain the second output signal; A logic operation circuit is used to receive the first output signal and the second output signal, and to perform operations on the first output signal and the second output signal to obtain a target driving signal; A latch, which is electrically connected to the trigger circuit, is used to receive the target drive signal and process it to obtain a switching signal, so as to drive the device to be driven to turn on or off. A driving circuit is connected to the gate of a target switching transistor and is used to drive the target switching transistor to turn on or off. The driving circuit includes the device to be driven, and the output terminal of the latch is connected to the gate of the device to be driven.

2. The gate driver chip as described in claim 1, characterized in that, The dual-pulse shaping circuit includes: A first pulse shaping circuit is used to shape and invert the received first pulse signal to output a first inverted pulse signal. The first pulse shaping circuit includes: The first input switch transistor has its gate used to receive the first pulse signal; The first current-limiting resistor has one end connected to the input terminal of the first input switch transistor and the other end connected to the gate of the second switch transistor, and is used to output the first inverted pulse signal to the second switch transistor. A first current mirror circuit is coupled between the output terminal and the gate of the first input switch.

3. The gate driver chip as described in claim 2, characterized in that, The first current mirror circuit includes: The first NPN transistor has its collector connected to the gate of the first input switch transistor and its emitter connected to ground. The second NPN transistor has its collector connected to the output terminal of the first input switch, its emitter connected to ground, and its base electrically connected to the base of the first NPN transistor. The base of the second NPN transistor is also electrically connected to the output terminal of the first input switch.

4. The gate driver chip as described in claim 2, characterized in that, The dual-pulse shaping circuit includes: A second pulse shaping circuit is used to shape the received second pulse signal and output a shaped second inverted pulse signal. The second pulse shaping circuit includes: The gate of the second input switch is used to receive the second pulse signal; The second current-limiting resistor has one end connected to the input terminal of the second input switch transistor and the other end connected to the gate of the first switch transistor, and is used to output the second inverted pulse signal to the first switch transistor. The second current mirror circuit is coupled between the output terminal and the gate of the second input switch.

5. The gate driver chip as described in claim 4, characterized in that, The second current mirror circuit includes: The collector of the third NPN transistor is connected to the gate of the second input switch transistor, and the emitter of the third NPN transistor is connected to the ground terminal. The fourth NPN transistor has its collector connected to the output terminal of the second input switch, its emitter connected to ground, its base electrically connected to the base of the third NPN transistor, and its base also electrically connected to the output terminal of the second input switch.

6. The gate driver chip as described in claim 4, characterized in that, Also includes: A first input resistor, one end of which is connected to the floating power supply, and the other end of which is connected to the other end of the first current-limiting resistor; as well as The second input resistor has one end connected to the floating power supply and the other end connected to the other end of the second current-limiting resistor.

7. The gate driver chip as described in claim 6, characterized in that, Also includes: A voltage regulator circuit, wherein the first input resistor and the second input resistor are respectively connected in parallel to one of the voltage regulator circuits, wherein each of the voltage regulator circuits includes at least two diodes connected in series, and the negative terminal of one of the diodes is electrically connected to the floating power supply.

8. The gate driver chip as described in claim 1, characterized in that, The pulse generation circuit includes: A filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it. A level shifting circuit is used to process the PWM pulse width modulation signal to obtain a level shifted signal; A narrow pulse generation circuit is used to encode the rising edge and falling edge of the level shift signal into the first pulse signal and the second pulse signal, respectively.

9. A smart power module, characterized in that, Includes the gate driver chip as described in any one of claims 1 to 8.

10. A device, characterized in that, It includes the gate driver chip as described in any one of claims 1 to 8, or the smart power module as described in claim 9.

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