Method and apparatus for complex zero equalizer

Abstract

Methods and apparatus for a complex zero equalizer are disclosed. An example circuit includes a driver circuit including a first input; and an equalizer circuit including a second input, a first output coupled to the first input, a transistor including a gate terminal, a drain terminal, and a source terminal, the gate terminal coupled to the second input and the drain terminal coupled to the first output, an inductor, and a second output coupled to the first output. The inductor includes a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to a source terminal of the transistor, a resistor coupled to the second inductor terminal, and a capacitor including a first terminal and a second terminal, the first terminal coupled to the source terminal and the first inductor terminal, the second terminal coupled to the second inductor terminal, and the first terminal coupled to the source terminal and the second inductor terminal. And the second terminal is coupled to the ground.

Description

Technical Field

[0001] The present disclosure relates generally to equalizers, and more particularly to methods and apparatus for complex-zero equalizers. Background Art

[0002] A broadband system is a system or device that operates over a wide frequency range. Broadband systems are used in a variety of fields, including telecommunications, radio and television broadcasting, radar systems, satellite communications, medical imaging, high-speed data acquisition, and more. Broadband systems are often used for high-speed data transmission because they enable the rapid transmission of large amounts of information. Therefore, broadband systems play a vital role in modern communications, where there is an increasing demand for faster data transmission. Summary of the invention

[0003] According to one aspect of the present application, a circuit is provided, comprising: a driver circuit comprising a first input; and an equalizer circuit comprising: a first output having a second input coupled to the first input; a transistor comprising a gate terminal, a drain terminal and a source terminal, the gate terminal being coupled to the second input, and the drain terminal being coupled to the first output; an inductor comprising a first inductor terminal and a second inductor terminal, the first inductor terminal being coupled to the source terminal of the transistor; a resistor coupled to the second inductor terminal; and a capacitor comprising a first terminal and a second terminal, the first terminal being coupled to the source terminal and the first inductor terminal, and the second terminal being coupled to ground.

[0004] According to another aspect of the present application, a system is provided, comprising: an input stage circuit, the input stage circuit comprising a first output; an equalizer circuit, the equalizer circuit comprising: a first transistor, the first transistor comprising a gate terminal coupled to the first output; a first inductor, the first inductor comprising a first inductor terminal, the first inductor terminal coupled to a first source terminal of the first transistor; a second transistor, the second transistor comprising a second drain terminal, the second drain terminal coupled to a second inductor terminal of the first inductor; a capacitor, the capacitor coupled to the first inductor terminal and coupled to the first source terminal of the first transistor; and a gain stage circuit, the gain stage circuit comprising a first input, the first input coupled to the first drain terminal of the first transistor.

[0005] According to another aspect of the present application, a method is provided, comprising: obtaining a modulated input signal at a first frequency; inducing a complex zero in a first frequency response of the modulated input signal at the first frequency; and based on the first frequency response, canceling the influence of a complex pole in a second frequency response of the modulated input signal at the first frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic illustration of an example communication channel showing the frequency response of the channel.

[0007] Figure 2 is a schematic illustration of an example transistor implementing the examples disclosed herein.

[0008] Figure 3 is a schematic illustration of a simplified vertical cavity surface emitting laser (VCSEL) model including a complex pole.

[0009] Figure 4 is a block diagram of an example VCSEL driver system including an example first complex zero continuous time linear equalizer (CTLE) for canceling Figure 3 The influence of the complex poles of the VCSEL model.

[0010] Figure 5 yes Figure 4 Offset Figure 3 An example of the impact of the complex poles of the VCSEL model. Schematic illustration of the first complex zero CTLE circuit.

[0011] Figure 6 is an example frequency response graph of an example optical frequency response across a VCSEL bias, an example conventional CTLE response, and an example complex-zero CTLE response.

[0012] Figure 7 is a schematic illustration of an example second complex-zero CTLE circuit.

[0013] Figure 8 yes Figure 3 Example first VCSEL group delay response diagram for three bias currents of the VCSEL, Figure 7 Example first CTLE response diagram of the second complex zero CTLE circuit, Figure 7 An example second CTLE response diagram of a second complex-zero CTLE circuit and Figure 7 0048 is a graphical representation of an example third response graph of a second complex-zero CTLE circuit.

[0014] Fig. 9 Yes Figure 7 An example system diagram of an example VCSEL driver of an example second complex-zero CTLE circuit.

[0015] Fig.10 is a comparison of example VCSEL, example conventional CTLE and Figure 7 An example first group delay response diagram of an example second complex zero CTLE circuit, and a comparison of an example conventional CTLE and Figure 7An example second group delay response graph of the group delay response and gain response of a VCSEL of an example second complex-zero CTLE circuit.

[0016] Fig.11 is a schematic illustration of an example third complex-zero CTLE circuit.

[0017] Fig. 12A , 12B and 12C is Figure 5 Schematic illustration of different applications of an example complex-zero CTLE circuit.

[0018] Fig.13 The flowchart of FIG. 1 represents a method for canceling the effects of complex poles in the frequency response of a broadband system. Figure 4 , Figure 5 , Figure 7 and Fig.11 Example operation of an example reset-zero CTLE circuit.

[0019] In general, the same reference numerals will be used throughout the various drawings and the accompanying written description to refer to the same or similar components. The drawings are not necessarily to scale. Instead, the thickness of a layer or region may be exaggerated in the drawings. Although the drawings show layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be imperceptible, blended, and / or irregular.

[0020] As used herein, unless otherwise indicated, the terms "above" or "over" describe the relationship of two parts relative to the earth. A first part is above a second part if at least a portion of the second part is between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As described above, a first part can be above or below a second part in one or more of the following situations: there are other parts in between, there are no other parts in between, the first part and the second part are in contact, or the first part and the second part are not in direct contact with each other.

[0021] Nevertheless, in the context of referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies during fabrication or manufacture, "above" is not with reference to the earth, but rather with reference to the underlying substrate on which the associated components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise stated or implied from the context, a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is "above" a second component within the semiconductor die when the first component is farther from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided during fabrication / manufacturing than the second component within the semiconductor die. Similarly, a first component (e.g., a semiconductor die) within an IC package is "above" a second component within the IC package during fabrication when the first component is farther from a printed circuit board (PCB) to which the IC package is to be mounted or attached, unless otherwise stated or implied from the context. It is understood that semiconductor devices are often used in a different orientation than they are during fabrication. Thus, when reference is made during use to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of the two components relative to the earth) will most likely be limited based on the context of use.

[0022] As used in this patent, recitation of any component (e.g., layer, film, region, area, or plate) as being on another component in any manner (e.g., positioned on, located on, arranged on, or formed on, etc.) indicates that the referenced component is either in contact with the other component, or that the referenced component is above the other component with one or more intermediate components located therebetween.

[0023] As used herein, reference to connection (e.g., attachment, coupling, connection, engagement) may include reference to intermediate members between the elements referenced by the connection and / or relative movement between such elements, unless otherwise indicated. Thus, reference to connection does not necessarily infer that two elements are directly connected and / or have a fixed relationship to each other. As used herein, a statement that any component is "in contact with" another component is defined to mean that there are no intermediate components between the two components.

[0024] Unless otherwise specifically stated, descriptors such as "first," "second," "third," and the like are used herein without importing or otherwise indicating any priority, physical order, arrangement in a list, and / or meaning of being ordered in any manner, but are merely used as labels and / or arbitrary names to distinguish elements so that the disclosed examples are easily understood. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims with a different descriptor, such as "second" or "third." In this case, it should be understood that such descriptors are only used to clearly identify these elements within the context of the discussion (e.g., within the claims), otherwise these elements may, for example, share the same name in such a discussion.

[0025] As used herein, "approximately" and "about" modify the subject matter / value thereof to recognize that there may be variations in real-world applications. For example, "approximately" and "approximately" may modify a dimension that may not be exact due to manufacturing tolerances and / or other real-world imperfections that would be understood by one of ordinary skill in the art. For example, "approximately" and "about" may indicate that such a dimension may be within a tolerance range of + / - 10%, unless otherwise indicated in the following description.

[0026] As used herein, the phrase "communicating with..." - including variations thereof - encompasses direct communication and / or indirect communication through one or more intermediate components, without requiring direct physical (e.g., wired) communication and / or constant communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0027] As used herein, an integrated circuit is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of a semiconductor-based laser diode, an ASIC, an FPGA, a chip, a microchip, a programmable circuit, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), and the like. DETAILED DESCRIPTION

[0028] Data can be transmitted in parallel or serially. In some examples, problems arise when data is transmitted at high frequencies. For example, in parallel transmission, there is capacitance between two parallel data lines (e.g., two wires extending parallel to each other). Capacitance includes reactance (e.g., resistance of a capacitor), which is a function of frequency. For example, as frequency increases, the reactance between capacitively coupled parallel lines decreases. In some examples, when reactance decreases, the capacitance between two parallel data lines acts as a short circuit between the lines at high frequencies. Therefore, at high frequencies, data on one parallel line may interfere with data on another parallel line, and when a receiver obtains the data, the data will be damaged. In some examples, one of the parallel lines may be a ground line or a ground plane. In such examples, there is capacitive coupling between the data line and the ground.

[0029] In some examples, this impairment is sometimes referred to as channel attenuation. Channel attenuation is the loss of signal strength or distortion of a signal when transmitting data. Channel attenuation can occur due to a variety of different factors other than impairment, such as electromagnetic interference (EMI), the distance between the transmitter and receiver, and even the characteristics of the channel. For example, at high frequencies, the amplitude or gain of the signal can be reduced due to the resistance and reactance characteristics of the channel. In some examples, the channel acts as a filter (e.g., a low-pass filter or a high-pass filter) due to its resistance and reactance, such as Figure 1 As shown in FIG. 1 and described in further detail below, in order to counteract the effects of channel fading, the transmitter and the receiver implement an equalizer (eg, a continuous time linear equalizer (CTLE)).

[0030] Figure 1 Illustrated is a schematic diagram of an example communication channel 100 showing the frequency response of the channel. Figure 1 The example communication channel 100 includes an example resistor-capacitor (RC) filter 102 and an example frequency response graph 104. The example RC filter 102 includes an example resistor (R) 106 and an example capacitor (C) 108. The example frequency response graph 104 includes a first gain line 110 and a second gain line 112.

[0031] exist Figure 1 , an example resistor (R) 106 depicts the resistance of the communication channel 100. For example, a wire, a trace pad, etc. may have properties that act as a resistance to current flow.

[0032] exist Figure 1, an example capacitor (C) 108 depicts the capacitance of the communication channel 100 relative to ground. For example, inherent capacitance may exist between closely spaced conductors, such as traces on a printed circuitry board (PCB) or wires in a cable.

[0033] exist Figure 1 , the example first gain line 110 illustrates the input signal (V IN ) when passing through the example RC filter 102. The gain of a signal refers to the amplification or multiplication factor by which the amplitude of the signal is increased or decreased. The gain represents the output signal (V OUT ) amplitude and input signal (V IN ) ratio.

[0034] exist Figure 1 , the example second gain line 112 represents the input signal (V IN For example, the second gain line 112 illustrates the gain of the input signal (V IN ). In some examples, the equalizer achieves the desired gain of the input signal, thereby equalizing the transmitter. In some examples, once the receiver obtains the signal from the transmitter, the equalizer can be used to equalize the input signal at the receiver.

[0035] As mentioned above, a capacitor (e.g., C 108) has a reactance (X c ), which is a function of frequency. The capacitive reactance (X) of the example capacitor (C) 108 c ) will affect the channel output (V OUT ). For example, the inherent capacitance of the communication channel 100 (shown as C 108) can cause the output signal to decrease, depending on the frequency of the transmitted signal. Capacitive reactance is measured by the following equation 1, where X c is the capacitive reactance, f is the frequency (Hz), and C is the capacitance (farads).

[0036]

[0037] In Equation 1, C is a constant. Therefore, in the example operation of the example RC filter 102, the capacitive reactance (X c ) will vary based on the frequency. In the example first operation, when the input signal with a low frequency (V IN ) is applied to the RC filter 102, X c will be high, and the communication channel 100 will treat the input signal (V IN ) is passed to the output terminal. In the second example operation, when the input signal (V IN) is applied to the RC filter 102 and includes high frequencies, X C will be low, and capacitor (C) 108 will act as a short circuit to ground. Therefore, most of the input signal (V IN ) will be shorted to ground, and the communication channel 100 will not pass the high frequency input signal (V IN ) is passed to the output terminal.

[0038] The example frequency response graph 104 illustrates the example first and second operations of the RC filter 102 described above. At low frequencies, the capacitor 108 effectively behaves as an open circuit. Therefore, at lower frequencies, the first gain line 110 is high. Therefore, the example RC filter 102 passes most, if not all, of the input signal (V IN ) is passed to the output terminal (V OUT ). In the example second operation, the first gain line 110 is reduced at higher frequencies. Therefore, the higher the frequency, the higher the gain passed to the output terminal (V OUT ) input signal (V IN ) the less.

[0039] Therefore, it is desirable to implement an equalizer, such as a CTLE, before the gain stage in a transmitter or receiver to ensure that at higher frequencies, most of the input signal (V IN ) will be passed to the output (V OUT ). For example, an equalizer is located between an input stage and an output stage of a transmitter or a receiver to equalize an input signal and provide the equalized input signal to the output stage.

[0040] In some examples, the equalizer can compensate for the attenuation of the channel at higher frequencies. Figure 1 104, channel attenuation occurs between a first frequency (e.g., a cutoff frequency) at which the first gain line 110 begins to decrease and a second frequency at which the first gain line 110 is zero. The equalizer increases the gain of the input signal applied at any frequency between the cutoff frequency and the second frequency. For example, if the cutoff frequency is 1 GHz, the second frequency is 10 GHz, and the input signal is 5 GHz, the equalizer increases the gain of the input signal to compensate for the attenuation that the 5 GHz signal will experience when passing through the channel. Therefore, due to the boost in certain input frequencies, the input signal will not have a gain as depicted by the first gain line 110, but will have a gain as depicted by the second gain line 112.

[0041] One type of equalizer is the continuous time linear equalizer (CTLE). CTLEs are used in communication systems to compensate for channel distortion and improve overall signal quality. While CTLEs provide benefits, CTLEs also create some issues that should be considered. One of the issues CTLEs create is that the equalization range is limited. For example, within a certain frequency range (e.g., bandwidth), CTLEs can effectively compensate for frequency-related losses and distortions. However, beyond this bandwidth, CTLE equalization performance may degrade, limiting its effectiveness in compensating for channel impairments or frequency deviations. For example, in broadband systems (e.g., optical transmitters, shunt-peaking systems, package interfaces, etc.), equalization is limited by in-band complex pole pairs and high-order amplitude roll-off.

[0042] A complex pole pair refers to a pole in a transfer function that represents the relationship between the input signal and the output signal in a broadband system and has both a real part and an imaginary part. The real part of the complex pole affects the decay or growth of the response (e.g., transfer function) over time, while the imaginary part determines the oscillatory or resonant behavior of the response (e.g., transfer function) at a specific frequency. For example, if the pole of the transfer function has a negative real part, the broadband system will exhibit decaying behavior, which means that the amplitude of the output signal will decrease over time or as the frequency increases. If the pole of the transfer function has a positive real part, the broadband system will exhibit growing behavior, which means that the amplitude of the output signal will increase over time or as the frequency increases. In some examples, a complex pole pair with a positive imaginary part can result in oscillatory or resonant behavior, while a complex pole pair with a negative imaginary part can result in a damped response.

[0043] An in-band complex pole pair is a pair of complex poles that exist within the bandwidth of the signal (e.g., the frequency range of interest). When complex poles exist within the bandwidth, they can affect the frequency response of a wideband system by introducing peaks or notches at specific frequencies. In some examples, the effect of the complex poles is beneficial. In some examples, the effect of the complex poles is detrimental because it can cause instability, excessive peaking, or unwanted resonances within the desired bandwidth.

[0044] Higher-order amplitude roll-off for a wideband system refers to the rate at which a wideband system attenuates or reduces the amplitude of higher frequency components in the frequency response. In a wideband system, amplitude roll-off characterizes how the gain or amplification changes as the frequency increases. Higher-order roll-off means that the system provides increasingly greater attenuation to higher frequencies, resulting in a steeper decrease in the amplitude response. Amplitude roll-off is usually specified in decibels per octave (dB / octave) or decibels per decade (dB / decade). These units represent the rate of change of attenuation as the frequency doubles (octave) or increases tenfold (decade). For example, a wideband system with a 6dB / octave roll-off means that the amplitude decreases by 6dB for every doubling of the frequency, while a wideband system with a 20dB / decade roll-off means that the amplitude decreases by 20dB for every tenfold increase in frequency. Higher-order amplitude roll-offs are often desired in wideband system design to achieve sharper equalization and to better compensate for higher frequency distortion or channel impairments. However, broadband systems (e.g., optical transmitters, parallel peaking systems, package interfaces, etc.) may be limited by higher-order amplitude roll-off. For example, if the roll-off is too aggressive, it may attenuate or suppress the desired signal components within the broadband frequency range, resulting in loss of information or degradation of system performance.

[0045] As higher communication link data rates are desired, there is a greater demand for higher operating bandwidths. The examples disclosed herein provide a complex zero CTLE architecture that utilizes complex zero pairs to offset the effects of complex pole pairs and can perform second-order gain equalization. For example, a conventional CTLE uses a parallel RC network at the source of a common source amplifier to introduce a real zero in the amplitude response, while the examples disclosed herein use an inductor (L) in series with a resistor of the RC network. In the examples disclosed herein, the inductor (L) in series with a resistor of the RC network introduces a complex zero to the frequency response. Poles are points in the complex plane (e.g., the real and imaginary axes) at which the transfer function becomes infinite or undefined, while zeros are points at which the transfer function becomes zero. The presence of a complex zero pair in a transfer function (e.g., the response of a CTLE) allows for targeted shaping of the frequency response by attenuating or enhancing specific frequency components.

[0046] The examples disclosed herein implement a complex-zero CTLE architecture in any broadband system, such as vertical-cavity surface emitting laser (VCSEL)-based optical links, parallel peaking systems, and packaging interfaces. In the example VCSEL, the examples disclosed herein offset the effect of the complex pole pairs on the optical portion of the frequency response by generating a positive amplitude roll-off. For example, due to the presence of the complex pole pairs, the optical portion of the VCSEL frequency response includes a negative second-order (e.g., 40 dB / decade) roll-off. The example inductor (L) of the complex-zero CTLE architecture implements a positive (e.g., +40 dB / decade) amplitude roll-off to balance the negative (e.g., -40 dB / decade) roll-off of the VCSEL optical response. The following will be related to Figure 3 The VCSEL and the optical response of the VCSEL are described in further detail.

[0047] In some examples, conventional CTLEs include real zeros in the transfer function that are unable to equalize gain and group delay peaking introduced by complex pole pairs, such as gain and group delay peaking in the electro-optical frequency response of a VCSEL. As used herein, group delay is the amount of time it takes for a signal to pass through a circuit. Specifically, group delay is measured and plotted relative to frequency because signals at some frequencies may take longer to pass through a circuit than signals at other frequencies due to the reactance of certain components in the system. As used herein, group delay peaking is a phenomenon where certain frequencies in a communication system (e.g., a broadband system) experience an increase in group delay that cannot be equalized using a conventional real-zero equalizer. In addition, due to only a single real zero in the response, conventional CTLEs can only perform first-order gain equalization.

[0048] In some examples, conventional complex-zero equalization methods are used to equalize gain and group delay peaking introduced by complex pole pairs. For example, conventional complex-zero equalization methods include a low-pass path transfer function combined with a high-pass path transfer function to equalize gain and group delay peaking. However, such complex-zero equalizers are complex and involve multiple stages, which degrades energy efficiency and makes it difficult or even impossible to implement for higher data rates. Therefore, the examples disclosed herein improve and simplify conventional complex-zero equalization techniques.

[0049] Figure 2 is a schematic illustration of an example transistor 200 implementing the examples disclosed herein. Figure 2Example transistor 200 represents the structure and characteristics of an n-channel metal-oxide semiconductor (NMOS) transistor that can be used to implement an equalizer, an input stage, a gain stage, an output stage, and / or any other circuit of a broadband system, such as a vertical cavity surface emitting laser (VCSEL), a parallel peaking system, etc. Example transistor 200 includes a gate terminal 202, a drain terminal 204, and a source terminal 206. In some examples, gate terminal 202 is a control terminal. In some examples, drain terminal 204 and source terminal 206 are current terminals. Example transistor 200 is a gate terminal 202, a drain terminal 204, and a source terminal 206. In some examples, gate terminal 202 is a control terminal. In some examples, drain terminal 204 and source terminal 206 are current terminals. Example transistor 200 is a gate terminal 202, a drain terminal 204, and a source terminal 206. TH )208 operation. TH The value of 208 depends on the supply voltage level (e.g., VCC) at which transistor 200 is intended to operate. When the voltage level applied to example gate terminal 202 meets (e.g., is greater than) VCC of transistor 200, TH When the applied voltage level is at logic level high “1”, transistor 200 is said to be in the “on” state and a closed circuit is created between drain terminal 204 and source terminal 206, resulting in a drain-to-source current (I ds ) 210 flows between the drain terminal 204 and the source terminal 206 of the transistor 200 (eg, I ds =I ON ). When the voltage level applied to the example gate terminal 202 does not meet (eg, is less than) the V TH When the applied voltage level is at logic level low “0”, transistor 200 is said to be in the “off” state and an open circuit is created between drain terminal 204 and source terminal 206, resulting in a drain-to-source current (I ds )210 Stop (for example, I ds =I OFF ).

[0050] Although in Figure 2 Not shown, but another type of transistor is a p-channel metal-oxide semiconductor (PMOS) transistor. In the examples disclosed herein, a PMOS transistor is represented by a circle at its gate terminal. Relative to an NMOS transistor, the "on" and "off" states of a PMOS transistor are activated based on opposite inputs at its gate terminal. For example, when the voltage level applied to the gate terminal of a PMOS transistor meets (e.g., is greater than) the V THWhen the voltage level applied to the gate terminal of the PMOS transistor is at a logic high “1”, the PMOS transistor is said to be in the “off” state, while when the voltage level applied to the gate terminal of the PMOS transistor does not meet (e.g., is less than) the V TH When the applied voltage level is at a logic low “0”, the PMOS transistor is said to be in the “on” state.

[0051] Figure 3 3 is a schematic illustration of a simplified vertical cavity surface emitting laser (VCSEL) model 300. A VCSEL is a semiconductor laser in which the semiconductor emits light in a direction perpendicular to the surface of the VCSEL. The VCSEL can be directly modulated by an electrical signal (e.g., the current of the VCSEL can be changed using a modulation signal containing information to be transmitted), which makes the VCSEL useful for high-speed data communications, such as fiber optic communications. Optical fibers can be used to transmit light over long distances, thereby transmitting information. An example VCSEL includes an active region (e.g., a resonator) located between two semiconductors (e.g., two semiconductor Bragg reflectors). The VCSEL converts an electrical signal into an optical signal. For example, the electrical portion of the VCSEL provides current to the active region of the VCSEL and modulates it to generate light. The active region consists of a plurality of quantum wells, which are thin layers of semiconductor material that confine electrons and holes. Therefore, when current passes through the active region, the electrons and holes recombine, thereby releasing energy in the form of photons. The electrical portion of the VCSEL controls the current injected into the active region so as to modulate the VCSEL in a manner that achieves a desired output power. The optical portion of the VCSEL emits photons, allowing light to be emitted perpendicularly (eg, at right angles) from the surface of the VCSEL.

[0052] exist Figure 3 In FIG. 1 , the example simplified VCSEL model 300 includes an example electrical model 302 and an example optical model 304. The example electrical model 302 models the electrical parameters and characteristics of the electrical portion of the VCSEL. For example, the electrical model 302 models how the VCSEL affects the example modulated input current (I VCSEL ) 306. The example optical model 304 models the optical parameters and characteristics of the optical part of the VCSEL. For example, the optical model 304 models the example modulated input current (I VCSEL )306 How to affect the example light output (P out )308 gain modeling.

[0053] exist Figure 3 , the example electrical model 302 includes an example junction capacitor (C j )310、Example Junction Resistor (R j )312、Example Series Resistor (R s)314 and an example pad capacitor (C pad )316. Example Junction Capacitor (C j )310 and the example junction resistor (R j )312 are coupled in parallel. Example junction capacitor (C j ) 310 is coupled to an example series resistor (R s )314. Example series resistor (R s )314 is coupled to the modulation input current (I VCSEL )306 and an example pad capacitor (C pad )316.

[0054] exist Figure 3 In the example, the junction capacitor (C j )310 and an example junction resistor (R j ) 312 represents the junction resistance and capacitance. In some examples, the junction resistance and capacitance are the resistance and capacitance of the active region of the VCSEL. When a voltage is applied across the junction, it creates an electric field that drives the electrons and holes of the quantum well to flow toward the active region. Therefore, the junction resistance (R) of the VCSEL is j 312) and junction capacitance (C j 310) will affect the modulation input current (I VCSEL )306. For example, the modulated input current (I VCSEL )306 is diverted to the junction capacitor (C j )310, thereby creating a low impedance path at high frequencies. The actual amount of current available for electro-optical conversion is determined by the amount of current flowing to the example junction resistor (R j )312 current (I j )express.

[0055] exist Figure 3 In the example pad capacitor (C pad ) 316 represents the capacitance of a pad (e.g., electrical contact) on an active region (e.g., junction, PN junction, etc.). For example, electrical contacts are placed on p-type and n-type layers to modulate the input current (I VCSEL 306) provides a path for the VCSEL to flow into the pad capacitor (C pad ) 316 also represents parasitic capacitance (eg, unwanted capacitance), thereby modulating the input current (I VCSEL )306 will be diverted to the pad capacitor (C pad )316 and junction capacitor (C j )310, thereby creating a low impedance path at high frequencies.

[0056] exist Figure 3 In the example optical model 304, an example series inductor (L vl)318、Example Series Resistor (R vl )320 and the example series capacitor (C vl )322. Example series inductor (L vl )318、Example Series Resistor (R vl )320 and the example series capacitor (C vl )322 is η(I j -I TH ), where n represents the slope efficiency (e.g., the linearity of the VCSEL output), and I TH is the threshold current of the VCSEL. Example series inductor (L vl )318 and the example series resistor (R vl ) 320 and an example voltage source 324 are coupled in series. An example series resistor (R vl ) 320 is coupled to an example series capacitor (C vl )322. Figure 3 In the example, the series capacitor (C vl )322 voltage is used as output (P out )308.

[0057] In some examples, P out The gain of 308 can be measured by the following formula 2, where H VCSEL-E (s) is the frequency response of the electrical model 302, H VCSEL-O (s) is the frequency response of the optical model 304, η is the slope efficiency, L vl is the series inductor (L vl )318 is the inductance in henries (H), and C vl is the series capacitor (C vl )322 is the capacitance in farads (F).

[0058]

[0059] In some examples, the frequency response H of the optical model 304 is VCSEL-O (s) can be measured by the following formula 3, where s is a complex variable representing the imaginary part (j) multiplied by omega (ω) (for example, ω = 2πf), R vl is the series resistor (R vl )320 is the resistance in ohms (Ω).

[0060] H VCSEL-O (S) = s 2 +(R vl / L vl )s+1 / L vl C vl(Formula 3)

[0061] In some examples, the series inductor (L vl )318, Series resistor (R vl )320 and the series capacitor (C vl )322 The optical frequency response of VCSEL H VCSEL-O A complex pole pair is introduced in (s). Due to the existence of the complex pole pair, the optical frequency response H VCSEL-O (s) has a second-order (40 dB / decade) roll-off, in-band gain peaking (e.g., less than 3 dB), and group delay distortion (e.g., less than 10 picoseconds). The examples disclosed herein implement a complex-zero CTLE to balance the second-order roll-off, in-band gain peaking, and group delay distortion. For example, the complex-zero CTLE architecture reduces the gain variation and group delay distortion of the VCSEL frequency response while also correcting some of the second-order roll-off to extend the overall bandwidth of the VCSEL. The following will be related to Figure 6 The optical frequency response H is described in further detail VCSEL-O (s). The complex-zero CTLE architecture is not limited to VCSELs. For example, the complex-zero CTLE architecture can be extended to any system with similar problems (e.g., group delay distortion, gain variation, and second-order roll-off).

[0062] Figure 4 4 is a block diagram of an example VCSEL driver system 400, which includes an example first complex-zero CTLE circuit 404 for canceling the effect of complex poles of a VCSEL. In some examples, the first complex-zero CTLE circuit 404 is an equalizer circuit system, an equalizer circuit, etc. In some examples, the VCSEL driver system 400 is based on an input signal (V in )402 modulates the input to the VCSEL. For example, the VCSEL input current will be modulated by the driver circuit to achieve a target optical modulation amplitude (OMA). The OMA is the specific modulation value required that ensures that the signal received by the receiver is the same as the signal sent by the VCSEL. For example, laser modulation is defined between high (P1) and low (P0) output levels, representing 1 and 0 respectively, at a specified rate determined by the data rate of the link. The actual output power is the bias voltage applied to the laser output, while the receiver sensitivity is the minimum amount of received light that can accurately determine the modulation. Problems occur when the receiver cannot determine whether the light level is high or low at a given time. Therefore, the OMA is a value that, when met, determines that there is enough change from a high level to a low level that the receiver will be able to tell the difference between the two, whether the link is short or close to the maximum allowed link length.

[0063] exist Figure 4 In the example VCSEL driver system 400, an example first complex zero CTLE circuit 404, an example driver circuit 406, and an example laser diode 408. In some examples, the example laser diode 408 is a VCSEL and is composed of Figure 3 An example electrical model of 302 and Figure 3 An example optical model 304 of φ 200 is shown. In some examples, the driver circuit 406 is a drive circuit.

[0064] exist Figure 4 In the example, the input of the first complex zero CTLE circuit 404 is coupled to the input signal (V in ) 402, and the output of the first complex-zero CTLE circuit 404 is coupled to the input of the example driver circuit 406. The output of the example driver circuit 406 is coupled to the input of the example laser diode 408.

[0065] exist Figure 4 In the example, the driver circuit 406 is used to implement the input signal (V in ) 402, and also equalizes the frequency response of the VCSEL consisting of the electrical and optical parts to improve the link data rate. However, the example driver circuit 406 does not equalize the frequency response of the VCSEL. Therefore, the example VCSEL driver system 400 includes an example first complex zero CTLE circuit 404 for equalizing the frequency response of the VCSEL. Figure 5 The example first complex-zero CTLE circuit 404 is described in further detail.

[0066] Figure 5 is offset Figure 3 Schematic diagram of an example first complex-zero CTLE circuit 404 showing the effect of the complex pole of a VCSEL. The example first complex-zero CTLE circuit 404 includes an input (V in )502, output (V out )504, an example first transistor 506, an example first inductor 508, an example first resistor 510, an example first capacitor 512, and an example load impedance 514.

[0067] exist Figure 5In the example, the first transistor 506 is an NMOS transistor and includes a gate terminal (e.g., a control terminal, a base terminal, etc.), a drain terminal (e.g., a current terminal), and a source terminal (e.g., a current terminal). Additionally and / or alternatively, the first transistor 506 can be any type of transistor, such as a bipolar junction transistor (BJT), a field-effect transistor (FET), an insulated-gate bipolar transistor (IGBT), etc. The gate terminal of the first transistor 506 is coupled to the example input (V in ) 502. The drain terminal of the example first transistor 506 is coupled to the example load impedance 514. The source terminal of the example first transistor 506 is coupled to the first terminal of the example first inductor 508 and the first terminal of the example first capacitor 512. The example output (V out ) 504 is coupled to a drain terminal of an example first transistor 506. An example first inductor 508 is coupled between a source terminal of the example first transistor 506 and an example first resistor 510. For example, a second terminal of the first inductor 508 is coupled to the first resistor 510, and a first terminal of the first inductor 508 is coupled to the source terminal of the first transistor 506. The example first resistor 510 is coupled between the example first inductor 508 and ground. A first terminal of an example first capacitor 512 is coupled between the source terminal of the first transistor 506 and a first terminal of the first inductor 508, and a second terminal of the first capacitor 512 is coupled to ground.

[0068] exist Figure 5 In the example, the first transistor 506 is a common source amplifier, where the load impedance 514 acts as a bias network to ensure the desired operation of the first transistor 506. For example, the common source amplifier is used to amplify the input signal (e.g., V) based on the bias conditions set by the bias network. in 502). In some examples, an input signal (eg, V in 502) is applied to the gate terminal of the first transistor 506 to modulate the width of the channel between the first terminal and the drain terminal of the first transistor 506, thereby controlling the current passing through the first transistor 506. The changing drain current (I D ) will result in an amplified output at the drain terminal (V out ) 504. In some examples, the gain of the common source amplifier (eg, the first transistor 506) is determined by the output voltage (V out ) and input voltage (V inThe gain of the first transistor 506 is determined by the impedance (Z) of the first inductor 508, the first resistor 510 and the first capacitor 512 and the transconductance (g m ) influence. In some examples, the transconductance (g m ) is the drain current (I D ) changes with the input voltage at the gate terminal (V in ). In some examples, the gain of the first transistor 506 is affected by the load impedance 514. For example, a portion of the amplified output voltage drops across the load impedance 514, thereby reducing the output (V out )The voltage available at 504.

[0069] exist Figure 5 , an example first inductor 508, an example first resistor 510, and an example first capacitor 512 are implemented by the example first complex-zero CTLE circuit 404 to introduce a complex zero in the CTLE frequency response in order to equalize and / or eliminate the effects of the VCSEL frequency response (e.g., second-order roll-off, in-band gain peaking, and group delay distortion) and / or any similar effects present in the frequency response of any broadband system.

[0070] In a conventional CTLE, an RC network coupled to the source of a common-source amplifier is designed to provide a real zero in the amplitude response of the conventional CTLE. For example, in a CTLE with an RC network, a resistor provides source degeneration (e.g., negative feedback) to reduce the gain of the common-source amplifier. In order to change (e.g., increase and decrease) the gain of the common-source amplifier at certain frequencies, a capacitor is coupled in parallel with the resistor. The capacitor changes the impedance of the common-source amplifier, thereby changing the gain. For example, as described above, the capacitive reactance (X c ) is a function of frequency and indicates whether the capacitor is an open circuit or a closed circuit (e.g., a short circuit). For example, when the frequency is zero, the capacitive reactance is infinite, which means that the capacitor is an open circuit and the resistance / impedance in the common-source amplifier comes from the full resistance of the resistor. In this example, the gain of the common-source amplifier decreases. In some examples, as the frequency increases, the capacitive reactance decreases, which means that the capacitor acts like a short circuit (or begins to act like a short circuit) and the resistance / impedance in the common-source amplifier decreases. In this example, the gain of the common-source amplifier increases. Therefore, a capacitor coupled in parallel with a resistor introduces a zero point (e.g., a real zero point) in the frequency response of the common-source amplifier. However, as described above, a real zero point cannot balance the gain variation and group delay peaking introduced by a complex pole pair, such as the gain variation and group delay peaking in the electro-optical frequency response of a VCSEL.

[0071] exist Figure 5In the example, the example first inductor 508 coupled in series with the example first resistor 510 generates a complex zero to cancel out the complex pole of the VCSEL frequency response, wherein the complex pole causes second-order roll-off, in-band gain peaking, and group delay distortion in the VCSEL frequency response. For example, the first inductor 508 and the first resistor 510 form an LR circuit. In some examples, the frequency affects the LR circuit. For example, the first inductor 508 includes an inductive reactance (X L ), which is a function of frequency (e.g., X L =2πfL), where X L decreases, and when the frequency increases, X L The inductive reactance (X L ) and the resistance of the first resistor 510 combine to form an impedance (Z). The impedance (Z) in an LR circuit is the total opposition to the flow of current and is a complex quantity that includes both resistance and reactance. As the inductive reactance increases, the impedance (Z) also increases. This means that at higher frequencies, the first inductor 508 presents a greater opposition to the flow of current.

[0072] In some examples, the first inductor 508, the first resistor 510, and the first capacitor 512 work together to reduce the gain of the first complex-zero CTLE circuit 404 at a specific frequency and increase the gain of the first complex-zero CTLE circuit 404 at one or more specific frequencies. For example, the first inductor 508, the first resistor 510, and the first capacitor 512 are at given values ​​(e.g., resistance values, inductance values, and capacitance values) that enable the first complex-zero CTLE circuit 404 to output a specific gain at a specific frequency to cancel out the complex pole of the VCSEL. The gain of the example first complex-zero CTLE circuit 404 can be measured by the following formula 4, where g m is the transconductance of the first transistor 506, Z L is the impedance of the first inductor 508, s is a complex variable representing the imaginary part (j) multiplied by omega (ω) (e.g., ω=2πf), R is the resistance of the first resistor 510 in ohms (Ω), L is the inductance of the first inductor 508 in Henrys, and C is the capacitance of the first capacitor 512 in Farads.

[0073]

[0074] The following formula 5 illustrates how the first complex-zero CTLE circuit 404 generates a complex zero that cancels out the complex poles of the VCSEL. For example, formula 5 sets the complex zero portion of formula 4 (CTLE gain of the first complex-zero CTLE circuit 404) equal to formula 2 (frequency response H of the optical model 304) VCSEL-O(s)), where the value of the first inductor 508 (L) is equal to L vl The value of the first resistor 510 (R) is equal to the series resistor R vl The resistance of the first capacitor 512 (C) is equal to C vl of capacitance.

[0075] s 2 +(R / L)s+1 / LC=s 2 +(R vl / L vl )s+1 / L vl C vl (Formula 5)

[0076] In some examples, the first complex-zero CTLE circuit 404 achieves the same resonant frequency as the resonant frequency of the VCSEL (eg, by making 1 / LC equal to 1 / L). vl C vl ) and gain peaking identical to that of a VCSEL (e.g., by making R / L equal to R vl / L vl ), to achieve a complex zero at the frequency of the complex pole. In some examples, the transconductance (g) of the first transistor 506 is selected m ) value to push the complex pole of the VCSEL to a higher frequency. For example, the higher transconductance (g m ) value can achieve a positive second-order roll-off (e.g., +40dB / decade amplitude roll-off) to balance the negative second-order roll-off (e.g., -40dB / decade roll-off) of the VCSEL, thereby moving the complex pole from a lower frequency (e.g., a frequency within the frequency band) to a higher frequency (e.g., a frequency outside the frequency band). Figure 6 Examples of complex-zero CTLE frequency responses and VCSEL frequency responses are described in further detail.

[0077] Figure 6 is an example frequency response graph 600 depicting example optical VCSEL frequency responses 602 , 604 , an example conventional CTLE response 606 , and an example complex-zero CTLE response 608 across VCSEL bias.

[0078] exist Figure 6 , example optical VCSEL frequency responses 602 and 604 are VCSELs (e.g., Figure 3 The optical part of the simplified VCSEL model 300) (e.g., Figure 3The optical model 304 of FIG. 3 is a frequency response of the VCSEL at different bias voltages. For example, the optical VCSEL frequency response 602 is the frequency response of the VCSEL at a first VCSEL bias current, and the optical VCSEL frequency response 604 is the frequency response of the VCSEL at a second VCSEL bias current. In some examples, the optical VCSEL frequency responses 602, 604 are determined by the above formula 3, where H VCSEL-O (s) corresponds to a VCSEL (e.g., Figure 3 Optical VCSEL frequency responses 602, 604 of the simplified VCSEL model 300).

[0079] exist Figure 6 , example optical VCSEL frequency responses 602 and 604 are plotted over VCSEL bias current. For example, a VCSEL is driven by a bias current, where certain bias currents affect the VCSEL in different ways. For example, increasing the bias current of the VCSEL improves the resonant frequency, but also results in an increase in the damping factor. Therefore, the dependence of the resonant frequency and the damping factor on the bias current makes the frequency response of the VCSEL nonlinear. As used herein, the damping factor is a parameter that characterizes the amount of damping of a resonant peak in a frequency response. A high damping factor (e.g., ζ=1) results in a sharper or narrower resonant peak, indicating that the oscillation decays faster, while a low damping factor (e.g., ζ=0) results in a wider resonant peak, indicating that the oscillation decays slower.

[0080] exist Figure 6 In the VCSEL output (for example, Figure 3 P out 308) increases at a particular frequency. For example, the amplitude of the VCSEL output increases at a first frequency f1. In some examples, this increase or peak in amplitude is due to the optical portion of the VCSEL (e.g., Figure 3The optical model 304 of FIG. 304 is caused by a complex pole pair introduced by the optical model 304 of FIG. 304. In other words, the complex pole pair exists at a specific frequency (e.g., the first frequency f1), causing the optical VCSEL frequency response 602, 604 to peak at the specific frequency (e.g., the first frequency f1). In some examples, the amplitude (e.g., gain) of the VCSEL output decreases (e.g., decreases) according to a second-order roll-off (e.g., a 40 dB / decade slope) after the specific frequency (e.g., the first frequency f1). For example, the complex pole causes the amplitude of the VCSEL output to increase and then decrease, thereby limiting the bandwidth of the VCSEL. In some examples, if there is a real pole in the VCSEL instead of a complex pole, the optical VCSEL frequency response 602, 604 will be flat (e.g., not including a peak in amplitude) within the frequency band (e.g., at the first frequency f1) and then will roll off. In some examples, the group delay of the VCSEL output peaks at the frequency where the complex pole exists. For example, if the group delay is plotted over frequency, the group delay will increase at a first frequency (f1). In some examples, this peak in group delay and amplitude is undesirable and needs to be corrected by an equalizer (e.g., CTLE). For example, the goal of an equalizer is to flatten the amplitude of the VCSEL output at as high a frequency as possible.

[0081] exist Figure 6 , an example conventional CTLE response 606 is a frequency response of a prior CTLE without an inductor coupled to a resistor of an RC network. In some examples, the prior and / or conventional CTLE without an inductor introduces a real zero at a particular frequency. For example, the gain of the prior and / or conventional CTLE increases at a first frequency. In some examples, the increase in gain (e.g., the real zero) is combined with the gain of the VCSEL (e.g., added to the gain of the VCSEL) to flatten the frequency response of the VCSEL, thereby increasing the bandwidth of the VCSEL. However, the conventional CTLE does not cancel or offset the complex poles of the optical VCSEL frequency responses 602 and 604, nor does it implement a positive second order roll-off (e.g., +40 dB / decade amplitude roll-off) to balance the negative second order roll-off (e.g., -40 dB / decade roll-off) of the VCSEL.

[0082] exist Figure 6 , an example reset-zero CTLE response 608 is Figure 4 and Figure 5 The frequency response of the first complex-zero CTLE circuit 404 is shown in FIG. 6 . The example complex-zero CTLE response 608 depicts a “dip” (e.g., decrease) in the amplitude value at the first frequency (f1). In this example, the “dip” in the complex-zero CTLE response 608 is a complex zero and is expressed in brackets in the numerator of the above formula 4 (e.g., [s 2+(R / L)s+1 / LC]). Figure 6 , the example complex-zero CTLE response 608 increases at the second frequency (f2). This increase in the example complex-zero CTLE response 608 illustrates the positive second-order roll-off (e.g., +40 db / decade amplitude roll-off) provided by the example first complex-zero CTLE circuit 404 at the same frequency at which the VCSEL generates a negative second-order roll-off (e.g., -40 db / decade amplitude roll-off). Figure 6 In the scheme, the complex zero is placed at the same frequency (f1) as the complex pole, so that the gain of the VCSEL output and thus the bandwidth of the VCSEL will increase as desired.

[0083] Figure 7 is a schematic diagram of an example second complex-zero CTLE circuit 700. In some examples, the second complex-zero CTLE circuit 700 is an equalizer circuit system, an equalizer circuit, etc. Figure 7 In the example second complex zero CTLE circuit 700 is a reconfigurable CTLE, wherein the electrical components (eg, Figure 5 The values ​​of the first inductor 508, the first resistor 510, and the first capacitor 512 can be adjusted and / or tuned for a desired CTLE implementation. In some examples, Figure 4 and Figure 5 The first complex-zero CTLE circuit 404 is implemented by the second complex-zero CTLE circuit 700. In some examples, the second complex-zero CTLE circuit 700 facilitates the application of the first complex-zero CTLE circuit 404 in a wide range of VCSEL bias conditions and different VCSEL devices. For example, different VCSEL bias currents may result in different VCSEL frequency responses, thereby shifting the placement (e.g., frequency) of the complex pole pairs present in the VCSEL frequency response. Therefore, Figure 4 and Figure 5 The first complex zero CTLE circuit 404 is tuned and / or adjusted to accommodate the change in the placement of the complex pole pair. For example, the second complex zero CTLE circuit 700 can change the resonant frequency (ω) of the complex zero. n ) and a damping factor (ζ) so that the complex zero is moved to a position (e.g., frequency value) that accurately cancels the complex pole when the VCSEL bias current changes.

[0084] exist Figure 7 In the example second complex zero CTLE circuit 700, an example second transistor 702, an example second inductor (L1) 704, an example third transistor (R CTLE ) 706, an example second capacitor 708, an example second resistor (R C )710, an example first load 712, an example second load 714, an example fourth transistor (R2a )716, Example fifth transistor (R 2b )718, Example third inductor (L 2a )720, and an example fourth inductor (L 2b ).

[0085] exist Figure 7 In the example, the second transistor 702 is an NMOS transistor and can be composed of Figure 5 The first transistor 506 realizes or realizes Figure 5 The first transistor 506. Additionally and / or alternatively, the example second transistor 702 can be any type of transistor, such as a bipolar junction transistor (BJT), a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), etc. The example second transistor 702 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the second transistor 702 is coupled to the input (V in )(For example, V in 502). The drain terminal of the example second transistor 702 is coupled to the example first load 712 at the first node 701. The source terminal of the second transistor 702 is coupled to the example second inductor (L1) 704 and the example second capacitor 708 at the second node 703.

[0086] exist Figure 7 In the example, the third transistor (R CTLE ) 706 is an NMOS transistor and is used to implement Figure 5 An example of a first resistor 510. For example, a MOSFET (e.g., NMOS, PMOS, CMOS, etc.) can be used as a variable resistor. A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can act as a variable resistor by operating in its linear region (called a triode region or an ohmic region). In this region, the MOSFET behaves like a voltage-controlled resistor, and its resistance can be changed by changing the gate-source voltage (V GS ) to adjust. For example, increasing V GS will reduce the resistance and thus reduce V GS Additionally and / or alternatively, the example third transistor (R CTLE )706 can be any type of transistor, such as a bipolar junction transistor (BJT), a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), etc.

[0087] Example third transistor (R CTLE ) 706 includes a gate terminal, a drain terminal and a source terminal. The third transistor (R CTLE ) 706 has a gate terminal coupled to the first voltage input (VDAC1). The third transistor (RCTLE ) 706 has its source terminal coupled to ground. Example third transistor (R CTLE )706 has a drain terminal coupled to the example second inductor (L1) 704.

[0088] exist Figure 7 In some examples, the second capacitor 708 is a digitally controlled capacitor. In some examples, the second capacitor 708 is one or more digitally controlled capacitors. A digitally controlled capacitor is a capacitor that can be selectively turned on or off in discrete steps using a digital control signal. A digitally controlled capacitor, such as the example second capacitor 708, provides a means to digitally adjust the capacitance value in a circuit. The example second capacitor 708 is coupled to the example second resistor (R C )710.

[0089] exist Figure 7 In the example, the first load 712 is a first type load network of the example second complex zero CTLE circuit 700. The example first load 712 includes an example sixth transistor 724 and an example fifth inductor (L ser )726.

[0090] exist Figure 7 , the example sixth transistor 724 is a diode-connected PMOS transistor. A diode-connected PMOS transistor refers to a configuration in which the drain and gate terminals of the PMOS transistor are short-circuited together, thereby effectively producing diode-like behavior. For example, the sixth transistor 724 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the example sixth transistor 724 is coupled to the drain terminal of the example sixth transistor 724. In some examples, diode-connected PMOS transistors are used in the bias network because they always operate in the saturation region (e.g., fully turned-on state). For example, the voltage at the gate terminal (V G ) is always approximately equal to the voltage at the drain terminal (V D )(For example, V G =V D ), so the voltage between the gate and drain terminals (V DG ) is equal to zero (for example, V GD =0). In some examples, since the voltage between the gate and drain terminals is equal to zero, the gate-to-source voltage (V GS ) is equal to the drain-to-source voltage (V DS ). Therefore, the diode-connected PMOS transistor always operates in the saturation region because the drain-to-source voltage (V DS ) will always be less than the gate-to-source voltage minus the threshold voltage (V TH )(For example, V DS >V GS –VTH Additionally and / or alternatively, the example sixth transistor 724 may be any type of transistor, such as a bipolar junction transistor (BJT), a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or the like.

[0091] exist Figure 7 In the example, the fifth inductor (L ser ) 726 is a series peaking inductor. In some examples, the series peaking inductor is used to extend the bandwidth of the amplifier, thereby producing a resonant peak in the frequency response. Example fifth inductor (L ser ) 726 is coupled to the drain terminal of the example second transistor 702 at the first node 701 and is coupled to the drain terminal of the example sixth transistor 724 at the first node 701. The example fifth inductor (L ser ) 726 and the output of the example second complex-zero CTLE circuit 700 (eg, Figure 5 Vout 504) are coupled in series.

[0092] exist Figure 7 In the example, the second load 714 is a second type of load network of the example second complex zero CTLE circuit 700. For example, the second load 714 can be implemented as a replacement load relative to the first load 712. The example second load 714 includes an example seventh transistor 728, an example sixth inductor (L shunt )730, example third resistor (R L )732, an example eighth transistor 734, and an example ninth transistor 736.

[0093] exist Figure 7 , the example seventh transistor 728 and the example eighth transistor 734 are PMOS transistors. The example ninth transistor 736 is an example NMOS transistor. The example seventh transistor 728 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the example seventh transistor 728 is coupled to a bias voltage source. The source terminal of the example seventh transistor 728 is coupled to a supply voltage source (V DD The drain terminal of the example seventh transistor 728 is coupled to the example sixth inductor (L shunt ) 730, and coupled to an example third resistor (R L )732.

[0094] exist Figure 7In, the example eighth transistor 734 includes a gate terminal, a drain terminal, and a source terminal. The example ninth transistor 736 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the example eighth transistor 734 is shorted to the gate terminal of the example ninth transistor 736 at the third node 705. The drain terminal of the example eighth transistor 734 is coupled to the drain terminal of the example ninth transistor 736. The source terminal of the example eighth transistor 734 is coupled to the supply voltage source (VDD), and the source of the example ninth transistor 736 is coupled to ground. In Figure 7 , the configuration of the example eighth transistor 734 and the example ninth transistor 736 forms a complementary metal-oxide-semiconductor (CMOS) inverter. In some examples, the CMOS inverter is used to improve the gain of the common source amplifier (e.g., the gain of the second complex zero CTLE circuit 700). In this example, the shorted drain terminals of the eighth transistor 734 and the ninth transistor 736 are the output of the CMOS inverter, and thus the output of the second complex zero CTLE circuit 700. In this example, the shorted gate terminals of the eighth transistor 734 and the ninth transistor 736 are the input of the CMOS inverter.

[0095] exist Figure 7 In the example, the third resistor (R L )732 is a feedback resistor. For example, the third resistor (R L ) 732 provides resistive feedback to the CMOS inverter (eg, the configuration of the eighth transistor 734 and the ninth transistor 736). The third resistor (R L ) 732 is coupled to the drain terminal of the seventh transistor 728 and the drain terminal of the second transistor 702 at the first node 701, and the third resistor (R L ) 732 is coupled to the drain terminals of the eighth transistor 734 and the ninth transistor 736 (eg, the third resistor (R L )732 is coupled to the output of the CMOS inverter). Figure 7 In the example, the third resistor (R L )732 via the example sixth inductor (L shunt )730 provides resistive feedback to the CMOS inverter.

[0096] exist Figure 7 In the example, the sixth inductor (L shunt ) 730 is a parallel peaking inductor and is coupled to the gate terminals of the eighth transistor 734 and the ninth transistor 736 (eg, the sixth inductor (L shunt) 730 is coupled between the input of the CMOS inverter) and the drain terminals of the second transistor 702 and the seventh transistor 728. Parallel peaking is a bandwidth extension technique in which an inductor is implemented to extend the bandwidth of the frequency response.

[0097] exist Figure 7 In the example second complex-zero CTLE circuit 700, a first load 712 or a second load 714 can be implemented. In some examples, each load 712, 714 provides different boundaries for different applications of the second complex-zero CTLE circuit 700. For example, the first load 712 can provide a different bandwidth for the second complex-zero CTLE circuit 700 than the second load 714.

[0098] exist Figure 7 In the example second zero-reset CTLE circuit 700, the example fourth transistor (R 2a )716 and the example fifth transistor (R 2b ) 718 to tune the example coupled inductor network 738. Figure 7 In the example, the fourth transistor (R 2a )716 and the example fifth transistor (R 2b ) 718 is a voltage controlled resistor. In some examples, the fourth transistor (R 2a )716 and the fifth transistor (R 2b ) 718 is an NMOS transistor. Additionally or alternatively, the example fourth transistor (R 2a )716 and the example fifth transistor (R 2b )718 can be any type of transistor. Figure 7 In the example coupled inductor network 738, the example second inductor (L1) 704, the example third inductor (L 2a )720 and the example fourth inductor (L 2b )722.

[0099] exist Figure 7 In the example, the fourth transistor (R 2a ) 716 includes a gate terminal, a drain terminal, and a source terminal, and an example fifth transistor (R 2b ) 718 includes a gate terminal, a drain terminal, and a source terminal. The example second inductor (L1) 704 includes a first inductor terminal (p1) and a second inductor terminal (p2). The example third inductor (L 2a ) 720 includes a third inductor terminal (p3) and a fourth inductor terminal (p4). Example fourth inductor (L 2b )722 includes a fifth inductor terminal (p5) and a sixth inductor terminal (p6).

[0100] Example 4 transistor (R2a ) 716 has a gate terminal coupled to the second voltage input (VDAC2), and the fourth transistor (R 2a ) 716 has a drain terminal coupled to an example third inductor (L 2a ) 720 of the fourth inductor terminal (p4), and the example fourth transistor (R 2a ) 716 has its source terminal coupled to ground. Example fifth transistor (R 2b ) 718 has a gate terminal coupled to a third voltage input (VDAC3), and an example fifth transistor (R 2b ) 718 has a drain terminal coupled to the example fourth inductor (L 2b ) 722 of the sixth inductor terminal (p6), and the example fifth transistor (R 2b ) 718 has its source terminal coupled to ground. In this example, the third inductor (L 2a ) 720 has a third inductor terminal (p3) coupled to ground, and a fourth inductor (L 2b )722 has a fifth inductor terminal (p5) coupled to ground.

[0101] In some examples, the second voltage input (VDAC2) and the third voltage input (VDAC3) are control signals used to control the inductance of the second reset-zero CTLE circuit 700. For example, the second voltage input (VDAC) controls the fourth transistor (R 2a )716 is turned on and the third inductor (L 2a )720 inductive current, or the fourth transistor (R 2a )716 is turned off, so that the third inductor (L 2a ) 720 releases any stored energy. In some examples, the third voltage input (VDAC3) controls the fifth transistor (R 2b )718 is turned on and the fourth inductor (L 2b )722, or the fifth transistor (R 2a )716 is turned off, so that the fourth inductor (L 2b )722 releases any stored energy.

[0102] The example second complex-zero CTLE circuit 700 implements at least three tuning mechanisms to achieve a desired resonant frequency (ω n ) and damping factor (ζ). Additionally or alternatively, the example second complex-zero CTLE circuit 700 may implement any number of tuning mechanisms to achieve a desired resonant frequency (ω n) and a damping factor (ζ). An example first tuning mechanism of the example second complex-zero CTLE circuit 700 is to adjust the capacitance of the example second capacitor 708. For example, adjusting the capacitance of the second capacitor 708 can promote complex-zero over a wider frequency range.

[0103] For example, briefly go to Figure 8 , an example first VCSEL group delay response graph 800A, an example first CTLE response graph 800B, an example second CTLE response graph 800C, and an example third CTLE response graph 800D are shown. The example first VCSEL group delay response graph 800A depicts various first group delay responses 802 of a VCSEL based on an increase in the VCSEL bias current. For example, as the bias current of the VCSEL increases, the group delay distortion at the complex pole frequency decreases.

[0104] exist Figure 8 , an example first CTLE response graph 800B depicts a second group delay response 804 of the second complex-zero CTLE circuit 700 plotted against frequency. In the example first CTLE response graph 800B, the value of the second group delay response 804 varies based on how the capacitance of the example second capacitor 708 increases or decreases. For example, when the capacitance of the second capacitor 708 increases, the group delay of the second complex-zero CTLE circuit 700 decreases at lower frequencies. In some examples, when the capacitance of the second capacitor 708 decreases, the group delay of the second complex-zero CTLE circuit 700 decreases at higher frequencies.

[0105] Return to Figure 7 , the example second tuning mechanism of the example second complex zero CTLE circuit 700 includes adjusting the inductance of the example coupled inductor network 738. In some examples, when the VCSEL is biased by a low current, the fourth transistor (R 2a )716 and the fifth transistor (R 2b ) 718 adjusts the inductance of the coupled inductor network 738 (eg, tunes). For example, the second complex-zero CTLE circuit 700 is used to generate a low resonant frequency (ω n ) and a low damping factor (ζ) in order to balance the VCSEL output biased with a low VCSEL bias current (e.g., inserting a complex zero at the same frequency as the complex pole). In such an example, the fourth transistor (R 2a )716 and the fifth transistor (R 2b )718 is coupled to the third inductor (L 2a )720 and the fourth inductor (L 2b ) 722 (e.g., the two secondary coils of the coupled inductor network 738) to change the inductance value of the coupled inductor network 738. For example, switching the fourth transistor (R 2a)716 and the fifth transistor (R 2b ) 718 changes the effective inductance value in the second reset-zero CTLE circuit 700. In some examples, when the fourth transistor (R 2a )716 and / or the fifth transistor (R 2b )718 is turned on, the inductance of the primary coil (eg, the second inductor (L1) 704) decreases because some current flows through the third inductor (L 2a )720 and / or the fourth inductor (L 2b For example, when the fourth transistor (R 2a )716 is turned on, current will flow through the third inductor (L 2a ) 720, which affects (eg, reduces) the inductance of the second inductor (L1) 704. In some examples, when the fourth transistor (R 2a )716 and the fifth transistor (R 2b ) 718 is turned off, the inductance of the second inductor (L1) is higher. Therefore, the example second complex zero CTLE circuit 700 can be tuned and can be tuned at a lower resonant frequency (ω n ) to achieve a lower damping factor (ζ). Figure 8 C further details the tuning of the example coupled inductor network 738.

[0106] For example, a short turn Figure 8 C, shows an example second CTLE response graph 800C. The example second CTLE response graph 800C depicts a third group delay 806 of the second complex-zero CTLE circuit 700 plotted against frequency. In the example second CTLE response graph 800C, the value of the third group delay 806 is based on the example third transistor (R 2a )716 and the example fourth transistor (R 2b ) 718. In some examples, changing the inductance of a CTLE (eg, second complex-zero CTLE circuit 700) for low VCSEL bias current changes the resonant frequency (ω n ) and the damping factor (ζ). For example, as shown in the second CTLE response graph 800C, when the third transistor (R 2a )716 and the example fourth transistor (R 2b ) 718 are both operating in a high state (eg, when both transistors 716 and 718 are turned on due to VDAC2=1 and VDAC3=1), the resonant frequency (ω) of the third group delay 806 n ) is low, and the damping factor (ζ) is low. In some examples, when the fourth transistor (R 2b)718 operates in a high state (eg, VDAC3=1) and the third transistor (R 2a )716 operates in a low state (eg, VDAC2=0), the resonant frequency (ω) of the third group delay 806 n ) is less than the resonant frequency (ω) when both transistors 716, 718 are operated in the high state n ). In some examples, when the third transistor (R 2a )716 and the fourth transistor (R 2b )718 when operating in a low state (eg, VDAC2=0 and VDAC3=0), the resonant frequency (ω) of the third group delay 806 n ) is less than when both transistors 716, 718 are operating in a high state and when one transistor (e.g., R 2b 718) The resonant frequency (ω) when operating in the high state (eg, VDAC3 = 1) n ).

[0107] Back to Figure 7 The example third tuning mechanism of the example second complex zero CTLE circuit 700 includes adjusting the example third transistor (R CTLE ) 706. In the example third tuning mechanism, the example second complex-zero CTLE circuit 700 tunes (eg, adjusts, increases, decreases, etc.) the example third transistor (R CTLE )The resistor of 706 is used to adjust the peaking amount of the CTLE response.

[0108] For example, a short turn Figure 8 D, shows an example third CTLE response graph 800D. The example third CTLE response graph 800D depicts the fourth group delay 808 of the second complex-zero CTLE circuit 700 plotted against frequency. As shown in graph 800D, the fourth group delay 808 of the second complex-zero CTLE circuit 700 can be increased by increasing R CTLE For example, when the third transistor (R CTLE ) 706 increases, the fourth group delay 808 has a higher group delay value (e.g., picoseconds). Alternatively, when the example third transistor (R CTLE )706 decreases in resistance, the fourth group delay 808 has a lower group delay value (eg, picoseconds).

[0109] Back to Figure 7 , the tuning scheme of the example second complex-zero CTLE circuit 700 can equalize the frequency having a range from the first frequency (eg, ω n =18 GHz) to a second frequency (eg, ω n=28 GHz) and a wide range of VCSEL optical responses having a resonant frequency of ζ=0.35 and a damping factor ranging from a first damping factor (eg, ζ=0.55).

[0110] Figure 7 An example coupled inductor implementation 740 is included that includes an example coupled inductor network 738. In some examples, coupled inductor implementation 740 illustrates a layout of coupled inductor network 738 on a chip (eg, a microchip, a computer chip, an integrated circuit, a semiconductor material, etc.).

[0111] exist Figure 7 , an example coupled inductor implementation 740 includes a first inductor terminal (p1), a second inductor terminal (p2), a third inductor terminal (p3), a fourth inductor terminal (p4), a fifth inductor terminal (p5), and a sixth inductor terminal (p6). In some examples, the third inductor terminal (p3) is coupled to the fourth inductor terminal (p4) at a fourth node 707, and the fifth inductor terminal (p5) is coupled to the sixth inductor terminal (p6) at a fifth node 709.

[0112] exist Figure 7 In the example, the first inductor terminal (p1) is coupled to the example third transistor (R CTLE ) 706, and the example second inductor terminal (p2) is coupled to the source terminal of the example second transistor 702. In some examples, the third inductor terminal (p3) is grounded, and the fourth inductor terminal (p4) is coupled to the example fourth transistor (R 2a ) 716. In some examples, the fifth inductor terminal (p5) is grounded, and the sixth inductor terminal (p6) is coupled to the drain terminal of the fifth transistor (R 2b )The drain terminal of 718.

[0113] In some examples, the layout of coupled inductor implementation 740 is designed to maximize the secondary winding (third inductor (L 2a )720 and the fourth inductor (L 2b ) 722) overlaps the primary coil (second inductor (L1) 704) while there is no overlap between the two secondary coils. For example, 50% of the primary coil overlaps one of the secondary coils, and another 50% of the primary coil overlaps the other secondary coil. In some examples, such a layout ensures the highest primary to secondary coil coupling (e.g., coupling coefficient), thereby maximizing the tuning range of the second complex-zero CTLE circuit 700.

[0114] In some examples, the second complex zero CTLE circuit 700 is implemented by complementary metal oxide semiconductor (CMOS) technology. In some examples, CMOS technology provides the availability of more than five metal layers in an integrated circuit (IC) or chip. There are multiple metal layers in a CMOS system that provide interconnectivity between different components and circuit elements on the IC. These metal layers are also referred to as metal interconnect layers or metal wiring layers, allowing the wiring of electrical signals between transistors, resistors, capacitors and other components to be implemented. In some examples, the coupled inductor network 738 and / or coupled inductor implementation 740 can be implemented within the top two metal layers of the CMOS stack.

[0115] Fig. 9 Yes Figure 7 Example system diagram of an example VCSEL driver 900 of an example second zero-reset CTLE circuit 700. The example VCSEL driver 900 includes an example input stage 902, an example second zero-reset CTLE circuit 700 ( Figure 7 ), an example gain stage 904, an example output stage 906, and an example bias circuit 908.

[0116] exist Fig. 9 In the example second complex zero CTLE circuit 700, an example second transistor 702, an example second inductor (L1) 704, an example third transistor (R CTLE ) 706, an example second capacitor 708, an example first load 712, an example fourth transistor (R 2a )716, Example fifth transistor (R 2b )718, Example third inductor (L 2a )720, and an example fourth inductor (L 2b The example first load 712 includes an example sixth transistor 724 and an example fifth inductor (L ser )726.

[0117] exist Fig. 9 , the example input stage 902 is configured to receive an input voltage (V in ). The output of the example input stage 902 is coupled to the input of the example second complex-zero CTLE circuit 700, and provides an example first input 910 to the example second complex-zero CTLE circuit 700. The output of the example second complex-zero CTLE circuit 700 is coupled to the input of the example gain stage 904, and provides an example second input 912 to the example gain stage 904. The output of the example gain stage 904 is coupled to the input of the example output stage 906, and provides an example third input 914 to the example output stage 906. The output of the example output stage 906 is biased by the example VCSEL bias circuit 908, and provides an output signal (Vout )916.

[0118] exist Fig. 9 , the gate of the second transistor 702 is coupled to the example first input 910. The drain terminal of the example second transistor 702 is coupled to the example first load 712 at the first node 701. The source terminal of the second transistor 702 is coupled to the example second inductor (L1) 704 and the example second capacitor (C CTLE )708. The third transistor (R CTLE ) 706 has a gate terminal coupled to the first voltage input (VDAC1). The third transistor (R CTLE ) 706 has its source terminal coupled to ground. Example third transistor (R CTLE ) 706 is coupled to the drain terminal of the example second inductor (L1) 704. The gate terminal of the example sixth transistor 724 is coupled to the drain terminal of the example sixth transistor 724 at the first node 701. The example fifth inductor (L ser ) 726 is coupled to the drain terminal of the example second transistor 702 at the first node 701 and is coupled to the drain terminal of the example sixth transistor 724 at the first node 701. The example fifth inductor (L ser ) 726 is coupled to the input of the example gain stage 904 and provides the example second input 912 to the example gain stage 904. The example fourth transistor (R 2a ) 716 has a gate terminal coupled to the second voltage input (VDAC2), and the fourth transistor (R 2a ) 716 has a drain terminal coupled to an example third inductor (L 2a ) 720 of the fourth inductor terminal, and the example fourth transistor (R 2a ) 716 has its source terminal coupled to ground. Example fifth transistor (R 2b ) 718 has a gate terminal coupled to a third voltage input (VDAC3), and an example fifth transistor (R 2b ) 718 has a drain terminal coupled to the example fourth inductor (L 2b ) 722 of the sixth inductor terminal, and the example fifth transistor (R 2b ) The source terminal of 718 is coupled to ground.

[0119] The example VCSEL driver 900 includes an example input stage 902 for processing an input signal (Vin). The example input stage 902 can be implemented by any type of input stage circuit, such as a filter circuit, an amplifier circuit, an analog-to-digital converter circuit (ADC), a voltage divider circuit, a comparator circuit, and the like. In some examples, the input stage 902 includes multiple operations to ensure that the input signal meets the requirements of the VCSEL driver 900. For example, the input stage 902 amplifies, level shifts, and / or filters the input signal. In some examples, the input stage 902 converts the input signal to achieve current modulation of the VCSEL. For example, the input stage 902 can generate a controlled current waveform corresponding to a desired modulation scheme (e.g., on-off keying (OOK), pulse amplitude modulation (PAM), frequency modulation (FM), etc.). In some examples, the input stage 902 can be implemented by any type of input stage circuit.

[0120] The example VCSEL driver 900 includes an example second complex-zero CTLE circuit 700 to compensate for the frequency-dependent characteristics of the VCSEL and the optical transmission channel. For example, the second complex-zero CTLE circuit 700 mitigates the complex poles present in the VCSEL optical response, mitigates attenuation, and mitigates other frequency response changes to improve the signal quality at the output of the VCSEL driver. The example second complex-zero CTLE circuit 700 is reconfigurable and can be reconfigured to adapt to any type of VCSEL conditions. In some examples, the second complex-zero CTLE circuit 700 generates a complex zero at the same frequency at which the VCSEL generates a complex pole. In such an example, the second complex-zero CTLE circuit increases the bandwidth of the VCSEL to achieve a desired data rate.

[0121] The example VCSEL driver 900 includes an example gain stage 904 to amplify an example second input 912. In some examples, the gain stage 904 can be implemented by any type of gain stage circuit, such as a cherry-hooper gain circuit, a common emitter amplifier circuit, a common source amplifier circuit, an operational amplifier circuit, etc. In some examples, the gain stage 904 amplifies the second input 912 to a level sufficient to achieve the necessary drive current for the VCSEL. In some examples, the gain stage 904 provides amplification while maintaining low distortion and high linearity.

[0122] The example VCSEL driver 900 includes an example output stage 906 for sending a current modulation signal (eg, V out916). In some examples, the output stage 906 interfaces with the VCSEL and provides the final electrical drive to the laser diode of the VCSEL. In some examples, the output stage 906 may include an impedance matching network to maximize power transfer and ensure efficient operation. In some examples, the output stage 906 may also include protection circuits to protect the VCSEL and the VCSEL driver 900 from overcurrent, overvoltage, and other potential hazards. The example output stage 906 can be implemented by any output stage circuit, such as an impedance matching circuit, a current sink circuit, a push-pull circuit, an H-bridge circuit, and the like.

[0123] The example VCSEL driver 900 includes an example bias circuit 908 for generating a bias current that is applied to a laser diode to establish an operating point of the VCSEL. In some examples, the bias circuit 908 generates a bias current to set the operating point of a laser diode (e.g., a VCSEL diode) above its threshold current. For example, the threshold current is the minimum current required for the VCSEL diode to begin emitting light. By applying a bias current above the threshold current, the example bias circuit 908 can maintain the VCSEL diode in an active state. In some examples, the bias circuit 908 establishes the output power of the VCSEL. For example, the bias current directly affects the output power of the VCSEL (e.g., as Figure 8 800A). In some examples, the bias circuit 908 varies the bias current to control the output power of the VCSEL. The example bias circuit 908 can also provide temperature stability and reduce noise and distortion. In some examples, the bias circuit 908 can be implemented by a current source and / or any type of current bias circuit.

[0124] Fig.10 1002 and 1004. The example first group delay response graph 1002 compares an example first normalized group delay response 1006 of a VCSEL, an example second normalized group delay response 1008 of a conventional CTLE, and an example second normalized group delay response 1009 of a conventional CTLE. Figure 7 and Fig. 9 An example third normalized group delay response 1010 of the second complex-zero CTLE circuit 700 is shown.

[0125] Fig.10An example first group delay response graph 1002 is included to illustrate a comparison of the group delay distortion of a VCSEL and the group delay compensation provided by a conventional CTLE and a second example complex-zero CTLE circuit 700. For example, in the first group delay response graph 1002, a first normalized group delay response 1006 of the VCSEL illustrates a group delay distortion of 12 picoseconds at approximately 23 GHz. In some examples, 23 GHz corresponds to the frequency at which the VCSEL generates a complex pole pair. As shown in the example first group delay response graph 1002, the conventional CTLE only compensates for a portion of the VCSEL group delay distortion. For example, the second normalized group delay response graph 1008 illustrates that the group delay distortion of the conventional CTLE is approximately zero seconds, thereby canceling out only a portion of the VCSEL group delay distortion. In some examples, the second complex-zero CTLE circuit 700 compensates for all of the VCSEL group delay distortion by generating a negative group delay response at a frequency corresponding to the complex pole pair (e.g., approximately 23 GHz). For example, the third normalized group delay response 1010 illustrates that the complex-zero CTLE circuit 700 has a group delay of approximately negative 12 picoseconds at a frequency of 23 GHz. Thus, the example second complex-zero CTLE circuit 700 cancels the group delay distortion of the VCSEL and limits the group delay distortion of the VCSEL to less than 3 picoseconds.

[0126] Fig.10 An example second group delay response graph 1004 is included to compare the group delay and gain of a VCSEL implementing a conventional CTLE with the group delay and gain of a VCSEL implementing the example second complex-zero CTLE circuit 700. The example second group delay response graph 1004 includes a first group delay response 1012, a second group delay response 1014, a first gain response 1016, and a second gain response 1018.

[0127] exist Fig.10 , an example first group delay response 1012 corresponds to the group delay of a VCSEL implementing a conventional CTLE in a VCSEL driver. For example, the first group delay response 1012 illustrates the group delay response of the VCSEL in response to the second normalized group delay response 1008 of the conventional CTLE. For example, the first group delay response 1012 illustrates the extent to which the conventional CTLE cancels out the group delay distortion of the VCSEL.

[0128] exist Fig.10 , the example second group delay response 1014 corresponds to implementing Fig. 91002 ). For example, the second group delay response 1014 corresponds to the response of the VCSEL when the example second complex-zero CTLE circuit 700 generates a complex zero at the complex pole frequency. In some examples, the second group delay response 1014 illustrates the group delay response of the VCSEL in response to the third normalized group delay response 1010 of the second complex-zero CTLE circuit 700. For example, the negative group delay provided by the second complex-zero CTLE circuit 700 (as shown in the example third normalized group delay response 1010 in the example first group delay response graph 1002) is added to the positive group delay distortion provided by the VCSEL (as shown in the example first normalized group delay response 1006 in the example first group delay response graph 1002), thereby reducing the group delay distortion of the VCSEL.

[0129] exist Fig.10 , an example first gain response 1016 corresponds to the gain of a VCSEL implementing a conventional CTLE in a VCSEL driver. For example, the first gain response 1016 depicts the gain of a VCSEL with gain peaking (eg, having a gain peaking of approximately 2.5 dB in the frequency band).

[0130] exist Fig.10 , the example second gain response 1018 corresponds to implementing Fig. 9 1 and 2. The gain of a VCSEL of the example VCSEL driver 900 is shown in FIG. 1. For example, the second gain response 1018 depicts the gain of the VCSEL without gain peaking, so that the gain response is flatter.

[0131] In some examples, the first group delay response graph 1002 and the second group delay response graph 1004 illustrate improvements in a VCSEL when the VCSEL implements and / or receives an input signal from a VCSEL driver having the example second complex-zero CTLE circuit 700. For example, the second complex-zero CTLE circuit 700 achieves better VCSEL bandwidth, thereby achieving better data rates, relative to a conventional CTLE.

[0132] Fig.11 is a schematic illustration of an example third complex-zero CTLE circuit 1100. The example third complex-zero CTLE circuit 1100 includes an example tenth transistor 1102, an example eleventh transistor 1104, an example seventh inductor (L2) 1106, an example eighth inductor (L2) 1108, an example fourth resistor (R2) 1110, an example fifth resistor (R2) 1112, an example third capacitor (C2) 1114, an example fourth capacitor (C2) 1116, an example ninth inductor 1118, an example sixth resistor 1120, an example twelfth transistor 1124, and an example thirteenth transistor 1126.

[0133] exist Fig.11 , the example tenth transistor 1102 is a PMOS transistor and includes a gate terminal, a drain terminal, and a source terminal. The example eleventh transistor 1104 is an NMOS transistor and includes a gate terminal, a drain terminal, and a source terminal. The gate terminals of the example tenth transistor 1102 and the example eleventh transistor 1104 are connected to an input voltage (V in ). The drain terminal of the tenth transistor 1102 is coupled to the drain terminal of the eleventh transistor 1104. The source terminal of the example tenth transistor 1102 is coupled to the example seventh inductor 1106, and the source terminal of the example eleventh transistor 1104 is coupled to the example eighth inductor 1108. The example fourth resistor 1110 is coupled to the example seventh inductor 1106, and the example fifth resistor 1112 is coupled to the example eighth inductor 1108. In this example, the fourth resistor 1110 is coupled between the seventh inductor 1106 and the supply voltage, and the fifth resistor 1112 is coupled between the eighth inductor 1108 and ground. The example third capacitor 1114 is coupled to the example seventh inductor 1106 and the source terminal of the example tenth transistor 1102. The example fourth capacitor 1116 is coupled to the example eighth inductor 1108 and the source terminal of the example eleventh transistor 1104. In this example, the third capacitor 1114 is coupled between the supply voltage and the source terminal of the tenth transistor 1102 , and the fourth capacitor 1116 is coupled between the source terminal of the eleventh transistor 1104 and ground.

[0134] exist Fig.11 , the example twelfth transistor 1124 is a PMOS transistor and includes a gate terminal, a drain terminal, and a source terminal. The example thirteenth transistor 1126 is an NMOS transistor and includes a gate terminal, a drain terminal, and a source terminal. The example ninth inductor 1118 is coupled to the drain terminals of the example tenth transistor 1102 and the example eleventh transistor 1104, and is coupled to the gate terminals of the example twelfth transistor 1124 and the example thirteenth transistor 1126. The example sixth resistor 1120 is coupled to the drain terminals of the example tenth transistor 1102 and the example eleventh transistor 1104, and is coupled to the drain terminals of the example twelfth transistor 1124 and the example thirteenth transistor 1126. The drain terminals of the example twelfth transistor 1124 and the example thirteenth transistor 1126 are coupled together. The source terminal of the example twelfth transistor 1124 is coupled to the supply voltage, and the source terminal of the example thirteenth transistor 1126 is coupled to the ground.

[0135] In some examples, the tenth transistor 1102 and the eleventh transistor 1104 form a complementary implementation of the third complex zero CTLE circuit 1100. For example, the tenth transistor 1102, the seventh inductor (L2) 1106, the fourth resistor (R2) 1110, and the third capacitor (C2) 1114 are complementary to the eleventh transistor 1104, the eighth inductor (L2) 1108, the fifth resistor (R2) 1112, and the fourth capacitor (C2) 1116. In a complementary implementation (e.g., a complementary circuit), two types of devices are used: an NMOS transistor (e.g., the eleventh transistor 1104) and a PMOS transistor (e.g., the tenth transistor 1102), because the NMOS transistor (e.g., the eleventh transistor 1104) and the PMOS transistor (e.g., the tenth transistor 1102) have complementary characteristics. For example, the NMOS transistor is used to implement a low-side or ground connection switch in the circuit, and the PMOS transistor is used to implement a high-side or power connection switch in the circuit. In some examples, the complementary circuit of the third complex-zero CTLE circuit 1100 improves the linearity of the CTLE and improves the power consumption of the CTLE. For example, the complementary circuit reduces power consumption because the same bias current is reused between the PMOS transistor and the NMOS transistor to generate a double effective transconductance. In addition, the complementary circuit of the example third complex-zero CTLE circuit 1100 reduces the distortion of the CTLE at higher frequencies. For example, the third complex-zero CTLE circuit 1100 still outputs a desired signal at a higher input frequency (e.g., still generates a frequency response with complex zeros at the correct frequency).

[0136] In the example third complex zero point CTLE circuit 1100, the example seventh inductor (L2) 1106 and the example eighth inductor (L2) 1108 are magnetically coupled. For example, in a printed circuit board (PCB) or chip design, the seventh inductor (L2) 1106 and the eighth inductor (L2) 1108 are stacked on top of each other. In some examples, when two inductors are magnetically coupled, it means that there is a shared magnetic field between them. In some examples, when the magnetic field generated by one inductor (e.g., the seventh inductor 1106) intersects with the winding of another inductor (e.g., the eighth inductor 1108), magnetic coupling occurs, resulting in a mutual inductance effect. Mutual inductance refers to the induction of voltage in another inductor by a changing current in one inductor. In some examples, the mutual inductance between the coupled inductors (e.g., the seventh inductor 1106 and the eighth inductor 1108) affects the total inductance of the third complex zero point CTLE circuit 1100. For example, mutual inductance increases individual inductance and increases the effective inductance.

[0137] In some examples, when two inductors are magnetically coupled, they have a coupling coefficient (k). The coupling coefficient is a measure of the magnetic coupling between the inductors and ranges from 0 to 1. A value of 1 indicates complete coupling, i.e., all magnetic field lines of one inductor pass through the windings of the other inductor. A value of 0 indicates no coupling, i.e., the magnetic field of one inductor does not intersect the windings of the other inductor. In this example, by coupling the seventh inductor 1106 and the eighth inductor 1108, the area of ​​the third complex zero CTLE circuit 1100 is smaller than the area of ​​the uncoupled inductor. For example, in order to obtain a higher inductance, both the seventh inductor 1106 and the eighth inductor 1108 need to be doubled in size. However, coupled inductors do not have this problem because the seventh inductor 1106 and the eighth inductor 1108 are stacked together, which reduces the area required for the two inductors on the chip.

[0138] In some examples, the third complex-zero CTLE circuit 1100 can be used as a replacement equalizer for the example first complex-zero CTLE circuit 404 or the example second complex-zero CTLE circuit 700. For example, the third complex-zero CTLE circuit 1100 can be used when the user wants the equalizer to have energy efficiency (e.g., improved power consumption) and linearity (e.g., reduced noise distortion).

[0139] Fig. 12A , 12B and 12C is Figure 5 Schematic diagrams of different applications of the example first complex-zero CTLE circuit 404. For example, the first complex-zero CTLE circuit 404 can be widely applied to improve the bandwidth of various other broadband systems. Therefore, the example equalizer circuits disclosed herein (e.g., the first complex-zero CTLE circuit 404, the second complex-zero CTLE circuit 700, and the third complex-zero CTLE circuit 1100) can be coupled and / or applied to any bandwidth extension system to further improve the bandwidth of other data communication systems.

[0140] Fig. 12A is a schematic illustration of an example first broadband system 1200A and a corresponding example first broadband response graph 1202A. Fig. 12B is a schematic illustration of an example second broadband system 1200B and a corresponding example second broadband response graph 1202B. Fig. 12C is a schematic illustration of an example third broadband system 1200C and a corresponding example frequency response graph 1202C.

[0141] exist Fig. 12A In the example first broadband system 1200A, the example fourth complex-zero CTLE circuit 1204 is included. In some examples, the fourth complex-zero CTLE circuit 1204 is Figure 4 and Figure 5The example fourth complex-zero CTLE circuit 1204 includes an example first transistor 1206 , an example first inductor 1208 , an example first resistor 1210 , an example first capacitor 1212 , and an example load 1214 .

[0142] exist Fig. 12A In the example, the first transistor 1206 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the first transistor 1206 is coupled to the input terminal (V in ). The drain terminal of the example first transistor 1206 is coupled to the example load 1214. The source terminal of the example first transistor 1206 is coupled to a first terminal of an example first inductor 1208 and a first terminal of an example first capacitor 1212. The example first inductor 1208 is coupled between the source terminal of the example first transistor 1206 and the example first resistor 1210. For example, a second terminal of the first inductor 1208 is coupled to the first resistor 1210, and a first terminal of the first inductor 1208 is coupled to the source terminal of the first transistor 1206. The example first resistor 1210 is coupled between the example first inductor 1208 and ground. A first terminal of the example first capacitor 1212 is coupled between the source terminal of the first transistor 1206 and the first terminal of the first inductor 1208, and a second terminal of the first capacitor 1212 is coupled to ground.

[0143] exist Fig. 12A In the example first broadband system 1200A, the example fourteenth transistor 1216, the example ninth inductor (L sh )1218, Example 7 resistor (R L ) 1220, and an example fifth capacitor (C L ) 1222. The example fourteenth transistor 1216 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal of the example fourteenth transistor 1216 is coupled to the drain terminal of the example first transistor 1206 and the example load 1214. The drain terminal of the example fourteenth transistor 1216 is coupled to the example seventh resistor (R L ) 1220. The source terminal of the example fourteenth transistor 1216 is coupled to ground. The example seventh resistor (R L ) 1220 is coupled to the example ninth inductor (L sh ) 1218. Example fifth capacitor (C L )1222 coupled to the output (V out ). Output (V out ) is coupled to the drain terminal of the example fourteenth transistor 1216.

[0144] In this example, the example fourteenth transistor 1216, the example ninth inductor (Lsh )1218, Example 7 resistor (R L )1220 and the fifth capacitor (C L ) 1222 forms a parallel peaking circuit. In the parallel peaking circuit, the fourteenth transistor 1216 outputs the load. However, there is a certain resistance for outputting the load to the fourteenth transistor 1216, and the resistance is determined by the seventh resistor (R L ) 1220 indicates. The resistor (eg, the seventh resistor (R L )1220) limits the bandwidth of the system. Adding a shunt inductor (e.g., the ninth inductor (L sh )1218) to increase the bandwidth. For example, the ninth inductor (L sh )1218 provides an inductive reactance that boosts the output signal at high frequencies, which flattens the frequency response and thereby extends the bandwidth of the circuit.

[0145] For example, the first bandwidth response graph 1202A depicts a first bandwidth 1224, a second bandwidth 1226, a third bandwidth 1228, and a fourth bandwidth 1230. The example first bandwidth 1224, the second bandwidth 1226, the third bandwidth 1228, and the fourth bandwidth 1230 correspond to the gain of the example first broadband system 1200A plotted against frequency. For example, the first bandwidth 1224 corresponds to the case without the ninth inductor (L sh ) 1218 (eg, without bandwidth extension) for the first broadband system 1200A. The example second bandwidth 1226 corresponds to having a ninth inductor (L sh ) 1218 (e.g., with an extended bandwidth achieved by parallel peaking). In some examples, the bandwidth of the first broadband system 1200A that implements parallel peaking is greater than the bandwidth of the first broadband system 1200A that does not implement parallel peaking.

[0146] In some examples, adding an equalizer (e.g., CTLE) to the wideband system can further increase the bandwidth. For example, the third bandwidth 1228 corresponds to the gain of the first wideband system 1200A that implements both parallel peaking and a traditional CTLE. In some examples, the bandwidth of the first wideband system 1200A that implements both parallel peaking and a traditional CTLE is greater than the bandwidth of the first wideband system 1200A that implements only parallel peaking.

[0147] However, the example fourth complex-zero CTLE circuit 1204 provides greater bandwidth extension in the example first broadband system 1200A. For example, the fourth bandwidth 1230 corresponds to the gain of the first broadband system 1200A implementing both the fourth complex-zero CTLE circuit 1204 and parallel peaking. As shown in the example first bandwidth response graph 1202A, the fourth bandwidth 1230 of the first broadband system 1200A implementing both the fourth complex-zero CTLE circuit 1204 and parallel peaking is greater than the first bandwidth 1224, the second bandwidth 1226, and the third bandwidth 1228.

[0148] Fig. 12B 1202B is a schematic diagram of an example second broadband system 1200B, including an example fourth complex-zero CTLE circuit 1204 for equalizing the second order roll-off of the example second broadband system 1200B. In some examples, a broadband system with multiple real poles can effectively produce a higher order gain roll-off. As shown in the example second bandwidth response diagram 1202B, the example fourth complex-zero CTLE circuit 1204, when used in a multi-real pole system (e.g., the second broadband system 1200B), can perform second order gain equalization, thereby extending the bandwidth.

[0149] exist Fig. 12B In the example, the second broadband system 1200B has two stages, so that a second-order roll-off will occur. For example, the second broadband system 1200B includes an example fifteenth transistor 1232, an example sixteenth transistor 1234, an example eighth resistor (R L )1236、Example 9 Resistor (R L )1238, an example sixth capacitor 1240 and an example seventh capacitor 1242.

[0150] exist Fig. 12B , the example fifteenth transistor 1232 and the example sixteenth transistor 1234 are NMOS transistors and include a gate terminal, a drain terminal, and a source terminal. The gate terminal of the example fifteenth transistor 1232 is coupled to the drain terminal of the first transistor 1206 and is coupled to the load 1214. The drain terminal of the example fifteenth transistor 1232 is coupled to the eighth resistor 1236. The source terminal of the example fifteenth transistor 1232 is coupled to ground. The gate terminal of the example sixteenth transistor 1234 is coupled to the drain terminal of the example fifteenth transistor 1232 and is coupled to the eighth resistor 1236. The example sixth capacitor 1240 is coupled to the gate terminal of the example sixteenth transistor 1234. The drain terminal of the example sixteenth transistor 1234 is coupled to the ninth resistor 1238. The source terminal of the example sixteenth transistor 1234 is coupled to ground. The example seventh capacitor 1242 is coupled to the output (V out ), where the output (V out) is coupled to the drain terminal of the example sixteenth transistor 1234.

[0151] In some examples, the fifteenth transistor 1232, the eighth resistor 1236, and the sixth capacitor 1240 form a first stage of the second broadband system 1200B. In some examples, the sixteenth transistor 1234, the ninth resistor 1238, and the seventh capacitor 1242 form a second stage of the example second broadband system 1200B. In some examples, the second stage produces a second-order roll-off in the second broadband system 1200B. For example, in a second-order (e.g., two-stage) broadband system (e.g., the second broadband system 1200B), the gain of the output signal decreases by 40 dB for every ten-fold increase in frequency beyond the cutoff frequency (e.g., the frequency at which the gain response begins to significantly attenuate). The example fourth complex zero CTLE circuit 1204 compensates for this reduction in gain, thereby extending the bandwidth of the second broadband system 1200B.

[0152] For example, the second bandwidth response graph 1202B depicts a fifth bandwidth 1244, a sixth bandwidth 1246, and a seventh bandwidth 1248. The example fifth bandwidth 1244, the sixth bandwidth 1246, and the seventh bandwidth 1248 correspond to the gain of the example second broadband system 1200B plotted over frequency. For example, the fifth bandwidth 1244 corresponds to the gain of the second broadband system 1200B without any type of bandwidth extension (e.g., without the second stage). As shown in the second bandwidth response graph 1202B, the fifth bandwidth 1244 is less than 20 GHz. The example sixth bandwidth 1246 corresponds to the gain of the example second broadband system 1200B implementing a conventional CTLE. As shown in the example second bandwidth response graph 1202B, the sixth bandwidth 1246 is approximately 33 GHz. Therefore, the conventional CTLE extends the bandwidth of the example second broadband system 1200B. However, the example fourth complex-zero CTLE circuit 1204 extends the bandwidth of the example second broadband system 1200B to frequencies beyond the conventional CTLE extension bandwidth. For example, the seventh bandwidth 1248 corresponds to the gain of the second broadband system 1200B implementing the fourth complex-zero CTLE circuit 1204. As shown in the example second bandwidth response graph 1202B, the seventh bandwidth 1248 is approximately 45 GHz. Therefore, the example fourth complex-zero CTLE circuit 1204 extends the bandwidth of the example second broadband system 1200B to frequencies beyond those extended by conventional CTLEs.

[0153] Fig. 12C1 is a schematic diagram of an example third broadband system 1200C, including an example fourth complex zero CTLE circuit 1204, which is used to expand the bandwidth of the package interface. For example, the package interface is limited by the inductance of the bonding wire. As used herein, the bonding wire forms a connection from one device to another device in a semiconductor package. For example, when an integrated circuit (iC) or other semiconductor device is packaged, they usually require wire bonding to connect the internal circuit to the external leads or pads on the package. As used herein, the bonding wire inductance is the inductance associated with the wire used to interconnect electronic components (e.g., devices, integrated circuits, etc.). In some examples, the bonding wire inductance is a parasitic inductance and may have an impact on the performance of the higher frequency package interface. For example, the bonding wire inductance may limit the bandwidth of the system (e.g., the third broadband system 1200C).

[0154] exist Fig. 12C , the example third broadband system 1200C represents the packaging interface between the example driver 1250 and the example device 1252, which is composed of the example bonding wire (L BW )1256 connection. Fig. 12C , the example driver 1250 is composed of an example current source 1254 and an example driver resistor (R Dr )1258 modeling. Fig. 12C , the example device 1252 includes an input impedance, which is determined by the example device resistor (R De )1260 and the example device capacitor (C De )1262Modeling.

[0155] exist Fig. 12C In the example, the example current source 1254 is coupled to the drain terminal of the example first transistor 1206 and the example driver resistor 1258. In some examples, the current of the current source 1254 is determined by the driver input voltage (V C ) is determined. In some examples, the current source 1254 is connected via an example bonding wire (L BW )1256 provides current to the driver resistor 1258 and the example device 1252.

[0156] exist Fig. 12C In the example device resistor (R De )1260 and the example device capacitor (C De ) 1262 are coupled in parallel to form a parallel RC network. In some examples, the parallel RC network models the input impedance of device 1252. In some examples, at higher frequencies, the input impedance of device 1252 and the bond wire (L BW ) 1256 generates a complex pole in the frequency band of the third broadband system 1200C. For example, at a specific in-band frequency, the driver resistor (R Dr)1258, bonding wire (L BW )1256, device resistor (R De )1260 and device capacitor (C De ) 1262 may result in a complex pole in the frequency response of the third broadband system 1200C. The example fourth complex zero CTLE circuit 1204 introduces a complex zero at a specific in-band frequency to cancel the effect of the complex pole.

[0157] For example, frequency response graph 1202C depicts gain and group delay plotted over frequency for third broadband system 1200C. Example frequency response graph 1202C includes example first package response 1264 , example first CTLE package response 1266 , example second package response 1268 , and example second CTLE package response 1270 .

[0158] exist Fig. 12C , the example first package response 1264 depicts gain peaking at a particular frequency (e.g., about 20 GHz). In some examples, the gain peaking shown in the first package response 1264 is the location of a complex pole in the third broadband system 1200C. The example first CTLE package response 1266 depicts gain compensation at a particular frequency (e.g., about 20 GHz). For example, the fourth complex-zero CTLE circuit 1204 generates a complex zero at a particular frequency to improve the overall frequency response of the third broadband system 1200C.

[0159] exist Fig. 12C , an example second package response 1268 depicts group delay distortion at a particular frequency (e.g., approximately 20 GHz). In some examples, the group delay distortion (e.g., a peak in the group delay shown in the second package response 1268) is the frequency location of a complex pole in the third broadband system 1200C. An example second CTLE package response 1270 depicts group delay compensation at a particular frequency (e.g., approximately 20 GHz). For example, the fourth complex-zero CTLE circuit 1204 generates a complex zero at a particular frequency to improve the overall frequency response of the third broadband system 1200C.

[0160] Fig.13 The flowchart represents the method of canceling the effects of complex poles in the frequency response of a broadband system. Figure 4 and Figure 5 In some examples, the example operation 1300 of the example first zero-reset CTLE circuit 404 is as follows. Fig.13 The flowchart represents Figure 7 An example of a second zero-reset CTLE circuit 700 and Fig.11 Example operations 1300 of the example third complex-zero CTLE circuit 1100 are described below.

[0161] Fig.13The example operation of CTLE begins at block 1302, when the example first complex zero CTLE circuit 404 obtains a modulated input signal at a first frequency. For example, the gate terminal of the first transistor 506 obtains an input voltage (V in )502.

[0162] The example first complex-zero CTLE circuit 404 induces a complex-zero in a first frequency response at a first frequency of a modulated input signal (block 1304). For example, a first inductor 508, a first resistor 510, and a first capacitor 512 are implemented by the example first complex-zero CTLE circuit 404 to induce a complex-zero in a CTLE frequency response (e.g., a first frequency response) at a first frequency.

[0163] The example first complex-zero CTLE circuit 404 cancels the effects of a complex pole in a second frequency response at a first frequency of a modulated input signal based on the first frequency response, including gain peaking and group delay distortion (block 1306). For example, the first inductor 508, the first resistor 510, and the first capacitor 512 introduce a complex zero in the CTLE frequency response to equalize and / or cancel the effects of a broadband system frequency response (e.g., a VCSEL frequency response, a second frequency response, etc.) occurring at the first frequency.

[0164] The example first complex-zero CTLE circuit 404 extends the bandwidth of the second frequency response based on the complex zero in the first frequency response (1308). For example, the first inductor 508 of the first complex-zero CTLE circuit 404 implements a positive (e.g., +40 dB / decade) amplitude roll-off to balance the negative (e.g., -40 dB / decade) roll-off of the VCSEL optical response, thereby extending the bandwidth of the VCSEL optical response. Operation 1300 ends.

[0165] It will be appreciated from the foregoing that example systems, devices, articles, and methods for equalizing the negative effects of broadband systems at specific frequencies have been disclosed. For example, the examples disclosed herein include an equalizer that generates complex zeros at frequencies corresponding to complex poles introduced by the broadband system, wherein the complex zeros cancel out the complex poles. Relative to broadband systems that do not implement such an equalizer, an equalizer that implements the cancellation of complex poles enables broadband systems to operate efficiently and accurately at higher frequencies and larger bandwidths. The disclosed systems, devices, articles, and methods improve the efficiency of using broadband systems by reducing signal distortion and amplitude variations in the output of the broadband system when the broadband system operates at high frequencies. The disclosed systems, devices, articles, and methods are therefore dedicated to one or more improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

[0166] Example methods and apparatus for complex zero equalizers are disclosed herein. Further examples and combinations thereof include the following:

[0167] Example 1 includes a circuit comprising a driver circuit including a first input, and an equalizer circuit including a second input, a first output coupled to the first input, a transistor including a gate terminal, a drain terminal, and a source terminal, the gate terminal being coupled to the second input and the drain terminal being coupled to the first output, an inductor including a first inductor terminal and a second inductor terminal, the first inductor terminal being coupled to the source terminal of the transistor, a resistor coupled to the second inductor terminal, and a capacitor including a first terminal and a second terminal, the first terminal being coupled to the source terminal and the first inductor terminal, and the second terminal being coupled to ground.

[0168] Example 2 includes the circuit of Example 1, wherein the equalizer circuit further includes a load coupled to the drain terminal of the transistor and to the first output, the load comprising a series peaking inductor.

[0169] Example 3 includes the circuit of Example 1, wherein the equalizer circuit further comprises a load coupled to the drain terminal of the transistor and to the first output, the load comprising a shunt peaking inductor.

[0170] Example 4 includes the circuit of Example 1, wherein the equalizer circuit is a continuous-time linear equalizer circuit.

[0171] Example 5 includes the circuit of Example 1, wherein the transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

[0172] Example 6 includes the circuit of Example 1, wherein the driver circuit includes a second output configured to be coupled to a broadband system.

[0173] Example 7 includes the circuit of Example 6, wherein the broadband system is a vertical cavity surface emitting laser.

[0174] Example 8 includes the circuit of Example 1, wherein the driver circuit includes a second output configured to be coupled to a bandwidth extension system.

[0175] Example 9 includes the circuit of Example 1, wherein the transistor is a first transistor, the inductor is a first inductor, the resistor is a first resistor, and the capacitor is a first capacitor, the gate terminal is a first gate terminal, the drain terminal is a first drain terminal, and the source terminal is a first source terminal, the equalizer circuit further includes a second transistor including a second gate terminal, a second drain terminal, and a second source terminal, the second gate terminal being coupled to the second input and the second drain terminal being coupled to the first drain terminal of the first transistor and coupled to the first output, a second inductor including a third inductor terminal and a fourth inductor terminal, the third inductor terminal being coupled to the second source terminal, a second resistor being coupled to the fourth inductor terminal, and a second capacitor being coupled to the second source terminal and the third inductor terminal.

[0176] Example 10 includes the circuit of Example 9, wherein the first inductor and the second inductor are magnetically coupled.

[0177] Example 11 includes the circuit of Example 9, wherein the second transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

[0178] Example 12 includes a circuit that includes an input stage circuit including a first output, an equalizer circuit including a first transistor including a gate terminal coupled to the first output, a first inductor including a first inductor terminal coupled to a first source terminal of the first transistor, a second transistor including a second drain terminal coupled to a second inductor terminal of the first inductor, a capacitor coupled to the first inductor terminal and to the first source terminal of the first transistor, and a gain stage circuit including a first input coupled to the first drain terminal of the first transistor.

[0179] Example 13 includes the system of Example 12, wherein the equalizer circuit includes a third transistor, a second inductor including a third inductor terminal coupled to a third drain terminal of the third transistor and a fourth inductor terminal coupled to a third source terminal of the third transistor, a fourth transistor, and a third inductor including a fifth inductor terminal coupled to a fourth drain terminal of the fourth transistor and a sixth inductor terminal coupled to a fourth source terminal of the fourth transistor.

[0180] Example 14 includes the system of Example 13, wherein the second inductor and the third inductor are magnetically coupled to the first inductor.

[0181] Example 15 includes the system of Example 13, wherein the third transistor includes a third gate terminal configured to receive a first control signal, and the fourth transistor includes a fourth gate terminal configured to receive a second control signal.

[0182] Example 16 includes the system of Example 12, wherein the second transistor is a variable resistor.

[0183] Example 17 includes the system of Example 12, wherein the equalizer circuit further includes a third transistor comprising a third gate terminal coupled to the first drain terminal of the first transistor and a third drain terminal coupled to the first drain terminal of the first transistor, and a second inductor comprising a third inductor terminal coupled to the first drain terminal and the third drain terminal and a fourth inductor terminal coupled to the first input.

[0184] Example 18 includes the system of Example 17, wherein the second inductor is a series peaking inductor.

[0185] Example 19 includes the system of Example 17, wherein the third transistor is a diode-connected p-channel metal oxide semiconductor (PMOS) transistor.

[0186] Example 20 includes the system of Example 12, wherein the capacitor is a digitally controlled capacitor.

[0187] Example 21 includes the system of Example 12, further comprising an output stage circuit comprising a second input coupled to the second output of the gain stage circuit, and a third output configured to be coupled to a vertical cavity surface emitting laser.

[0188] Example 22 includes a method comprising obtaining a modulated input signal at a first frequency, inducing a complex zero in a first frequency response at the first frequency of the modulated input signal, and canceling an effect of a complex pole in a second frequency response at the first frequency of the modulated input signal based on the first frequency response.

[0189] Example 23 includes the method of Example 22, further comprising extending a bandwidth of the second frequency response based on complex zeros in the first frequency response.

[0190] Example 24 includes the method of Example 22, wherein the effects of the complex poles include gain peaking and group delay distortion.

[0191] Example 25 includes an apparatus comprising means for performing the method as described in any one or more of Examples 22-24.

[0192] Example 26 includes a machine-readable storage device including machine-readable instructions that, when executed, cause a computer to implement a method as described in any one or more of Examples 22-24.

[0193] Example 27 includes a computer program comprising instructions that, when executed by a computer, cause the computer to perform a method as described in any one or more of Examples 22-24.

[0194] The attached claims are hereby incorporated into this Detailed Description section by this reference. Although certain example systems, devices, articles, and methods are disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fairly fall within the scope of the claims of this patent.

Claims

1. A circuit comprising: a driver circuit comprising a first input; as well as An equalizer circuit, the equalizer circuit comprising: Second input; a first output coupled to the first input; a transistor comprising a gate terminal, a drain terminal, and a source terminal, the gate terminal coupled to the second input and the drain terminal coupled to the first output; an inductor comprising a first inductor terminal and a second inductor terminal, the first inductor terminal being coupled to a source terminal of the transistor; a resistor coupled to the second inductor terminal; and A capacitor includes a first terminal coupled to the source terminal and the first inductor terminal and a second terminal coupled to ground.

2. The circuit of claim 1, wherein: The equalizer circuit also includes a load coupled to the drain terminal of the transistor and to the first output, the load including a series peaking inductor.

3. The circuit of claim 1, wherein: The equalizer circuit also includes a load coupled to the drain terminal of the transistor and to the first output, the load including a shunt peaking inductor.

4. The circuit according to any one of claims 1 to 2, wherein: The equalizer circuit is a continuous time linear equalizer circuit.

5. The circuit according to any one of claims 1 to 2, wherein: The transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

6. The circuit as claimed in any one of claims 1 to 2, wherein: The driver circuit includes a second output configured to be coupled to a broadband system.

7. The circuit of claim 6, wherein: The broadband system is a vertical cavity surface emitting laser.

8. The circuit as claimed in any one of claims 1 and 2, wherein: The driver circuit includes a second output configured to be coupled to a bandwidth extension system.

9. The circuit as claimed in any one of claims 1, 2 and 7, wherein: The transistor is a first transistor, the inductor is a first inductor, the resistor is a first resistor, and the capacitor is a first capacitor, the gate terminal is a first gate terminal, the drain terminal is a first drain terminal, and the source terminal is a first source terminal, the equalizer circuit further comprising: a second transistor including a second gate terminal, a second drain terminal, and a second source terminal, the second gate terminal being coupled to the second input and the second drain terminal being coupled to the first drain terminal of the first transistor and to the first output; a second inductor including a third inductor terminal and a fourth inductor terminal, the third inductor terminal being coupled to the second source terminal; a second resistor coupled to the fourth inductor terminal; and A second capacitor is coupled to the second source terminal and the third inductor terminal.

10. The circuit of claim 9, wherein: The first inductor and the second inductor are magnetically coupled.

11. The circuit of claim 9, wherein: The second transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

12. A system comprising: an input stage circuit comprising a first output; An equalizer circuit, the equalizer circuit comprising: a first transistor including a gate terminal coupled to the first output; a first inductor including a first inductor terminal coupled to a first source terminal of the first transistor; a second transistor including a second drain terminal coupled to a second inductor terminal of the first inductor; a capacitor coupled to the first inductor terminal and to the first source terminal of the first transistor; and A gain stage circuit includes a first input coupled to a first drain terminal of the first transistor.

13. The system of claim 12, wherein: The equalizer circuit comprises: A third transistor; a second inductor comprising a third inductor terminal and a fourth inductor terminal, the third inductor terminal being coupled to a third drain terminal of the third transistor and the fourth inductor terminal being coupled to a third source terminal of the third transistor; a fourth transistor; and A third inductor includes a fifth inductor terminal and a sixth inductor terminal, the fifth inductor terminal is coupled to the fourth drain terminal of the fourth transistor, and the sixth inductor terminal is coupled to the fourth source terminal of the fourth transistor.

14. The system of claim 13, wherein: The second inductor and the third inductor are magnetically coupled to the first inductor.

15. The system of claim 13, wherein: The third transistor includes a third gate terminal configured to receive a first control signal, and the fourth transistor includes a fourth gate terminal configured to receive a second control signal.

16. The system of any one of claims 12 to 15, wherein: The second transistor is a variable resistor.

17. The system of claim 12, wherein: The equalizer circuit further comprises: a third transistor comprising a third gate terminal and a third drain terminal, the third gate terminal coupled to the first drain terminal of the first transistor, and the third drain terminal coupled to the first drain terminal of the first transistor; and A second inductor includes a third inductor terminal and a fourth inductor terminal, the third inductor terminal is coupled to the first drain terminal and the third drain terminal, and the fourth inductor terminal is coupled to the first input.

18. The system of claim 17, wherein: The second inductor is a series peaking inductor.

19. The system of claim 17, wherein: The third transistor is a diode-connected p-channel metal oxide semiconductor (PMOS) transistor.

20. The system of any one of claims 12-15, 18 and 19, wherein: The capacitor is a digitally controlled capacitor.

21. The system of any one of claims 12-15, 18 and 19, further comprising an output stage circuit, the output stage circuit comprising: a second input coupled to a second output of the gain stage circuit; as well as A third output is configured to be coupled to a vertical cavity surface emitting laser.

22. A method comprising: obtaining a modulated input signal at a first frequency; inducing complex zeros in a first frequency response at the first frequency of the modulated input signal; and Based on the first frequency response, an effect of a complex pole in a second frequency response at the first frequency of the modulated input signal is canceled.

23. The method of claim 22, further comprising extending a bandwidth of the second frequency response based on complex zeros in the first frequency response.

24. The method of any one of claims 22-23, wherein: The effects of the complex poles include gain peaking and group delay distortion.

25. An apparatus comprising means for performing the method of any one of claims 22-24.

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