An FPGA-based infrared imaging system and electronic device

Abstract

This application discloses an FPGA-based infrared imaging system and electronic device. The system includes an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit, and a CRT display. The infrared detector is used to acquire infrared signals and convert the acquired infrared signals into electrical signals. The infrared detector driving circuit is used to convert the electrical signals into raw 64-bit parallel binary digital signals. The FPGA processing system is used to process the raw 64-bit parallel binary digital signals in real time and output the processed infrared data stream. The interface driving circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal. The CRT display is used to display the composite synchronous video broadcast signal. This system has the advantages of good real-time performance, significant noise reduction effect, and ideal enhancement effect, which can effectively improve the quality of infrared images and provide better support for subsequent applications.

Description

Technical Field

[0001] This invention relates to the field of infrared imaging technology, and in particular to an FPGA-based infrared imaging system and electronic device. Background Technology

[0002] Infrared images have wide applications in many fields, such as military, security, medical, and industrial inspection. However, infrared images are often subject to various noise interferences during acquisition and transmission, which degrades image quality and readability, affecting subsequent analysis and processing. Furthermore, due to the inherent characteristics of infrared images, problems such as low contrast and insufficient detail exist, necessitating enhancement processing to improve image quality.

[0003] Common traditional infrared image denoising methods include mean filtering and median filtering. While mean filtering is simple, it can easily lead to blurred image edges; median filtering is effective at suppressing salt-and-pepper noise, but its effectiveness against other types of noise is limited. In addition, there are some denoising methods based on wavelet transform, but these methods often have high computational complexity and poor real-time performance. For infrared image enhancement, commonly used methods include histogram equalization. However, histogram equalization may lead to over-enhancement, causing unnatural phenomena in the image. Furthermore, some existing enhancement methods may not be ideal for enhancing image details and may fail to fully extract useful information from infrared images.

[0004] With the development of FPGA technology, its advantages such as strong parallel processing capabilities and good reconfigurability have provided a new approach for real-time processing of infrared images. However, directly applying traditional denoising and enhancement algorithms to FPGAs often faces problems such as high resource consumption, low efficiency, and poor adaptability. Moreover, different application scenarios have different requirements for the quality of infrared images, necessitating a denoising and enhancement algorithm that can be flexibly adjusted according to actual needs.

[0005] In practical applications, such as military reconnaissance, the quality of infrared images directly affects the effectiveness of target identification and monitoring. Excessive image noise or insufficient contrast can lead to misjudgments or missed detections. In the medical field, infrared images are used for disease diagnosis and monitoring, and high-quality images are crucial for accurate diagnosis. In industrial inspection, clear infrared images can help detect minute defects and anomalies.

[0006] There is currently no effective solution to the problem of insufficient precision in infrared image denoising processing in existing technologies. Summary of the Invention

[0007] The purpose of this application is to provide an FPGA-based infrared imaging system, electronic device, and readable storage medium. This system has the advantages of good real-time performance, significant noise reduction effect, and ideal enhancement effect, which can effectively improve the quality of infrared images.

[0008] To achieve the above objectives:

[0009] In a first aspect, embodiments of this application provide an FPGA-based infrared imaging system, the system comprising: an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit, and a CRT display. The infrared detector is used to acquire infrared signals and convert the acquired infrared signals into electrical signals; the infrared detector driving circuit is used to convert the electrical signals into raw 64-bit parallel digital signals; the FPGA processing system is used to process the raw 64-bit parallel digital signals in real time and output the processed infrared data stream; the interface driving circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal; and the CRT display is used to display the composite synchronous video broadcast signal.

[0010] Preferably, the FPGA processing circuit includes: processing the original 64-bit parallel digital signal input to the FPGA processing system sequentially using an infrared denoising and enhancement algorithm and an AGC algorithm to obtain a processed infrared data stream.

[0011] Preferably, the infrared denoising and enhancement algorithm includes a first module and a second module, wherein the first module includes:

[0012] The original 64-bit parallel binary digital signal is processed in the FPGA processing system for 3... 3. Open a window to obtain matrix X1. Wherein, data11-data33 are the original 64-bit parallel binary digital signals;

[0013] Multiplying matrix X1 by the boundary coefficients coefxx yields matrix X2.

[0014] ;

[0015] Specifically, the matrix X1 is multiplied by the boundary coefficients coefxx to obtain matrix X1'.

[0016] When the matrix X1' is at the image boundary, some pixel values ​​in the matrix... , , and If a pixel exceeds the boundary range, its boundary coefficient *coefxx* is set to 0, preventing it from participating in subsequent calculations. The boundary coefficients for the remaining pixel values ​​are set to values ​​between 0 and 1, resulting in matrix X2.

[0017]

[0018] Find the average value of matrix X2, and use the average value as the weak filter value;

[0019] The output data of the Digital Detail Enhancement Mode (DDE_mode) is used as the output data of the first module. The output data of the Digital Detail Enhancement Mode is divided into two types: when DDE_mode=0, the output data of the first module is data22, and when DDE_mode=1, the output data of the first module is the weak filter value.

[0020] Preferably, the second module includes:

[0021] Windowing is performed on the data output by the first module to obtain 5 5-pixel matrix x3

[0022] DATA00-DATA44 are

[0023] The 64-bit parallel binary digital signal after windowing processing has a window size of 5*5;

[0024] Multiplying matrix X3 by the boundary coefficients coefxx yields matrix X4. ;

[0025] Specifically, the matrix X3 is multiplied by the boundary coefficients coefxx to obtain the matrix.

[0026]

[0027] By setting DATAxx_plus=DATAxx*coefxx, where xx takes the values: 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 25, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, the resulting matrix will be transformed into matrix X4.

[0028] Multiplying matrix X4 by the threshold coefficient coefxx_2 yields matrix X5.

[0029]

[0030] Specifically, the matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix.

[0031]

[0032] By setting DATAxx_plus_x=DATAxx_plus*coefxx_2, where xx takes the values: 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, the resulting matrix will be transformed into matrix X5.

[0033] The matrix X5 multiplied by twice the threshold 2. Obtain matrix X6, where threshold is a preset value. Matrix X6 is:

[0034] ;

[0035] Specifically, the matrix X5 is multiplied by twice the threshold. 2. Obtain the matrix

[0036]

[0037] By setting DATAxx_plus_2x=DATAxx_plus_x threshold 2. The values ​​of xx are 00, 01, 02, 03, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44. The resulting matrix is ​​transformed into matrix X6.

[0038] Matrix X8 is obtained based on matrix X5.

[0039]

[0040] Matrix X7 is obtained based on matrix X6.

[0041]

[0042] The average value S_BF1 of matrix X7 and the average value S_BF_x1 of matrix X8 are calculated. Then, the parameter S_D1 is calculated based on the average value S_BF1 and the average value S_BF_x1, where the parameter S_D1 = (S_BF_x1 + 8192) - S_BF1. The range of the value of parameter S_D2 is determined based on the parameter S_D1.

[0043] Based on the value of parameter S_D2, calculate the values ​​of parameters S_RD_SD, S_RD_mean, and S_RB_BF;

[0044] Determine the sum of parameter S_RB_BF and parameter S_RD_SD and the magnitude of parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result;

[0045] Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2;

[0046] Calculate the variance of matrix X4, and determine whether the data output by the second module is DATA_OUT1 or DATA_OUT2 based on the variance.

[0047] Preferably, obtaining matrix X8 based on matrix X5 and obtaining matrix X7 based on matrix X6 includes:

[0048] Using the center pixel value data22 of matrix X5 and matrix X6 as a standard, a threshold is set, wherein the threshold can be 0, 8, 12, or 20; the threshold coefficient of pixels in the matrix whose pixel value is greater than data22+threshold or less than data22-threshold is set to 0, thus obtaining matrix X8 and matrix X7 respectively.

[0049] Preferably, determining the range of S_D2 based on the value of S_D1 includes:

[0050] If S_D1≥8192:

[0051] If S_D1 <= 8192 + 32, then S_D2 <= S_D1;

[0052] (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16;

[0053] (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32;

[0054] (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48;

[0055] Otherwise, S_D2 <= S_D1[63:4] + 7680 + 64;

[0056] If S_D1 < 8192:

[0057] If S_D1>=8192-32, then S_D2<=S_D1;

[0058] (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16;

[0059] (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32;

[0060] (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48;

[0061] else, S_D2 <= S_D1[63:4] + 7680 - 64;

[0062] Wherein, S_D1[63:1] represents the value after taking the 63rd to 1st character from the parameter S_D1, S_D1[63:2] represents the value after taking the 63rd to 2nd character from the parameter S_D1, S_D1[63:3] represents the value after taking the 63rd to 3rd character from the parameter S_D1, and S_D1[63:4] represents the value after taking the 63rd to 4th character from the parameter S_D1.

[0063] Preferably, the step of calculating the values ​​of parameters S_RD_SD, S_RD_mean, and S_RB_BF based on the range of S_D2 includes:

[0064] S_RD_SD= S_D2 Proportion_in;

[0065] S_RD_mean= {Proportion_in,7'd0}

[0066] S_RB_BF=S_BF_x1,

[0067] Wherein, Proportion_in is the image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros after the binary representation of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in is 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in is 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in is 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in is 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in is 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in is 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in is 280.

[0068] Preferably, the step of determining the sum of parameter S_RB_BF and parameter S_RD_SD and the magnitude of parameter S_RD_mean, and generating data DATA_OUT1 based on the determination result, includes:

[0069] If S_RB_B + S_RD_SD < S_RD_mean, then the generated data DATA_OUT1 is 0; if S_RB_B + S_RD_SD ≥ S_RD_mean, then the generated data DATA_OUT1 is S_RB_B + S_RD_SD - S_RD_mean. Preferably, the step of calculating the matrix variance using matrix X4 and determining whether the data output by the second module is DATA_OUT1 or DATA_OUT2 based on the variance includes:

[0070] If variance ≥ 300, it is determined to be an edge, and the data output by the second module is DATA_OUT1; if variance < 300, it is determined to be the background, and the data output by the second module is DATA_OUT2.

[0071] Secondly, embodiments of this application provide an electronic device including the aforementioned infrared imaging processing system.

[0072] The aforementioned FPGA-based infrared imaging system, electronic device, and computer-readable storage medium acquire infrared signals through an infrared detector and convert the acquired infrared signals into electrical signals. An infrared detector driving circuit converts the electrical signals into raw 64-bit parallel digital signals. An FPGA processing system processes the raw 64-bit parallel binary digital signals in real time and outputs the processed infrared data stream. An interface driving circuit converts the infrared data stream output by the FPGA into a composite synchronous video broadcast signal. A CRT display shows the composite synchronous video broadcast signal. The FPGA processing system uses infrared denoising and enhancement algorithms to preserve more details in the infrared image, resulting in better denoising and higher image quality.

[0073] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0074] The infrared denoising and enhancement algorithms preserve more details in the infrared image and make the background smoother. The entire FPGA-based infrared imaging system has the advantages of good real-time performance, significant denoising effect and ideal enhancement effect, which can effectively improve the quality of infrared images and provide better support for subsequent applications. Attached Figure Description

[0075] Figure 1 A flowchart of an infrared detector system based on FPGA design provided for an embodiment of the present invention;

[0076] Figure 2 This is a schematic diagram of the FPGA processing system flow.

[0077] Figure 3 A schematic diagram of the infrared denoising and enhancement algorithm provided in the embodiments of this application;

[0078] Figure 4 An internal framework diagram of the Ti60F100 chip provided in an embodiment of this application;

[0079] Figure 5 Before and after the execution of the infrared denoising and enhancement algorithm provided in the embodiments of this application;

[0080] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0081] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0082] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0083] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, this information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word “if” as used herein may be interpreted as “when…” or “in response to determination”. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0084] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0085] It should be noted that step designations such as S1 and S2 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0086] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0087] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0088] Figure 1 Here is the overall flowchart of the infrared detector system based on FPGA design; Figure 2 This is a schematic diagram of the FPGA processing system. (See attached diagram) Figure 1 The system includes: an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit, and a CRT display.

[0089] The infrared detector is used to collect infrared signals and convert the collected infrared signals into electrical signals;

[0090] The infrared detector used is a ceramic-encapsulated detector from Anhui Guangzhi, model VL0612VC. This detector is based on ceramic encapsulation technology, with a pixel size of 640x512 and a pixel pitch of 12μm. This solution is also compatible with 640x512 and 384x288 resolution infrared detectors from manufacturers such as IRay and Hikvision. This product is widely used in industrial temperature measurement, security, vehicle night vision, outdoor search and rescue, intelligent buildings, and fire protection.

[0091] The infrared detector driving circuit is used to convert the electrical signal into a raw 64-bit parallel digital signal;

[0092] Specifically, the conversion of electrical signals into digital signals is a crucial process in modern communication and signal processing. This process involves several key steps: Sampling: Sampling discretizes a continuous signal over time, that is, it collects instantaneous values ​​point-by-point on the original analog signal at specific time intervals. The sampling frequency is the number of samples collected per second. The higher the sampling frequency, the closer the resulting discrete signal is to the original analog signal, but it also requires more sophisticated circuitry and increases computational and storage costs. If the sampling frequency is too low, it may lead to information loss, and in severe cases, signal distortion, rendering the signal unusable. Quantization: Quantization converts the amplitude of the sampled signal into a certain discrete value, that is, it converts the continuous analog signal into a discrete digital signal. The more bits used for quantization, the smaller the quantization error and the better the quantization result. Encoding: Encoding converts the quantized signal into binary code, that is, it converts the discrete digital signal into a digital quantity. This process is achieved through parallel comparator circuits or successive approximation circuits, converting the quantized discrete signal into the corresponding original 64-bit parallel digital signal.

[0093] The FPGA processing system is used to process the original 64-bit parallel digital signal in real time and output the processed infrared data stream.

[0094] Specifically, see Figure 4 The FPGA solution chosen is the EileenTech Ti60F100 ultra-small 60K FPGA. EileenTech has unique expertise in low-power, small-size, high-performance FPGAs. The EileenTech Ti60F100 FPGA features 60K logic cells, high-speed I / O configurable for various protocols, and built-in SPI Flash and Hyper-RAM, all contained within a 5.5" FPGA with a mere 0.5mm pitch. In a 5.5mm miniature package, we solved the customer's product size and FPGA performance issues. The chip's internal frame diagram can be found here. Figure 4 .

[0095] The original 64-bit parallel digital signal input to the FPGA processing system is processed sequentially using infrared denoising and enhancement algorithms and AGC algorithms to obtain the processed infrared data stream.

[0096] The infrared denoising and enhancement algorithm includes a first module and a second module, as detailed in [link to relevant documentation]. Figure 3 The first module includes:

[0097] The original 64-bit parallel digital signal is processed in the FPGA processing system for 3... 3. Open a window to obtain matrix X1. Wherein, data11-data33 are the original 64-bit parallel digital signals;

[0098] Multiplying matrix X1 by the boundary coefficients coefxx yields matrix X2.

[0099] ,

[0100] Specifically, the matrix X1 is multiplied by the boundary coefficients coefxx to obtain the matrix

[0101] X1' When the matrix X1' is at the image boundary, some pixel values ​​in the matrix... , , and If a pixel exceeds the boundary range, its boundary coefficient *coefxx* is set to 0, preventing it from participating in subsequent calculations. The boundary coefficients for the remaining pixel values ​​are set to values ​​between 0 and 1, resulting in matrix X2. ;

[0102] Find the average value of matrix X2, and use the average value as the weak filter value;

[0103] The output data of the Digital Detail Enhancement Mode (DDE_mode) is used as the output data of the first module. The output data of the Digital Detail Enhancement Mode is divided into two types: when DDE_mode=0, the output data of the first module is data22, and when DDE_mode=1, the output data of the first module is the weak filter value.

[0104] The second module includes:

[0105] Windowing is performed on the data output by the first module to obtain 5 5-pixel matrix x 3,

[0106] ,

[0107] The pixel matrix X3 serves as the observation window, and the size of the observation window is 5. 5 pixels;

[0108] Multiplying matrix X3 by the boundary coefficients coefxx yields matrix X4.

[0109] ;

[0110] Specifically, the matrix X3 is multiplied by the boundary coefficients coefxx to obtain the matrix.

[0111]

[0112] By setting DATAxx_plus=DATAxx coefxx, where xx takes the values ​​00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 25, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, and the resulting matrix is ​​transformed into matrix X4.

[0113] Multiplying matrix X4 by the threshold coefficient coefxx_2 yields matrix X5.

[0114]

[0115] Specifically, the matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix.

[0116]

[0117] By setting DATAxx_plus_x=DATAxx_plus coefxx_2, where xx takes the values ​​00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, and the resulting matrix is ​​transformed into matrix X5;

[0118] The matrix X5 multiplied by twice the threshold 2. Obtain matrix X6, where the threshold is a preset value.

[0119] ;

[0120] Specifically, the matrix X5 is multiplied by twice the threshold. 2. Obtain the matrix

[0121]

[0122] By setting DATAxx_plus_2x=DATAxx_plus_x threshold 2. The values ​​of xx are 00, 01, 02, 03, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32.

[0123] 33, 34, 40, 41, 42, 43, 44, will result in the matrix X6;

[0124] Matrix X8 is obtained based on matrix X5.

[0125] ;

[0126] Matrix X7 is obtained based on matrix X6.

[0127]

[0128] The average value S_BF1 of matrix X7 and the average value S_BF_x1 of matrix X8 are obtained by dividing the sum of all elements in the matrix by the number of elements. Then, the parameter S_D1 is calculated, where the parameter S_D1 = (S_BF_x1 + 8192) - S_BF1. The value of parameter S_D2 is determined based on the parameter S_D1.

[0129] Specifically, determining the value of S_D2 based on the value of S_D1 includes:

[0130] If S_D1≥8192:

[0131] If S_D1 <= 8192 + 32, then S_D2 <= S_D1;

[0132] (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16;

[0133] (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32;

[0134] (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48;

[0135] Otherwise, S_D2 <= S_D1[63:4] + 7680 + 64;

[0136] If S_D1 < 8192:

[0137] If S_D1>=8192-32, then S_D2<=S_D1;

[0138] (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16;

[0139] (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32;

[0140] (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48;

[0141] else, S_D2 <= S_D1[63:4] + 7680 - 64;

[0142] Wherein, S_D1[63:1] represents the value after taking the 63rd to 1st character from S_D1, S_D1[63:2] represents the value after taking the 63rd to 2nd character from S_D1, S_D1[63:3] represents the value after taking the 63rd to 3rd character from S_D1, and S_D1[63:4] represents the value after taking the 63rd to 4th character from S_D1.

[0143] The calculation of the values ​​of parameters S_RD_SD, S_RD_mean, and S_RB_BF based on the S_D2 value includes:

[0144] S_RD_SD= S_D2 Proportion_in;

[0145] S_RD_mean= {Proportion_in,7'd0}

[0146] S_RB_BF=S_BF_x1,

[0147] Wherein, Proportion_in is the image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros to the binary representation of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in is 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in is 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in is 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in is 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in is 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in is 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in is 280. There are seven levels of DDE_LV, from 0 to 6.

[0148] Determine the sum of the parameter S_RB_BF and the parameter S_RD_SD and the magnitude of the parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result;

[0149] If S_RB_B + S_RD_SD < S_RD_mean, then the generated data DATA_OUT1 is 0; if S_RB_B + S_RD_SD ≥ S_RD_mean, then the generated data DATA_OUT1 is S_RB_B + S_RD_SD - S_RD_mean.

[0150] Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2;

[0151] The variance of matrix X4 is calculated, and based on this variance, it is determined whether the data output by the second module is DATA_OUT1 or DATA_OUT2. Finally, the image processed by the infrared denoising and enhancement algorithm is obtained. See the before-and-after effect diagrams of the infrared denoising and enhancement algorithm. Figure 5 ,from Figure 5 As can be seen, the image processed using infrared denoising and enhancement algorithms retains more image details, and the background is smoother.

[0152] Specifically, obtaining matrix X8 based on matrix X5 and obtaining matrix X7 based on matrix X6 includes:

[0153] Using the center pixel value data22 of matrices X5 and X6 as a standard, a threshold is set. Currently, in the FPGA program, levels 0-3 correspond to thresholds of 0, 8, 12, and 20, respectively. The threshold coefficient for pixels in the matrix whose pixel values ​​are greater than DATA22+threshold or less than DATA22-threshold is set to 0, resulting in matrices X8 and X7. The selection of the threshold is determined by comparing the final processing results after multiple FPGA system processing steps, and it changes with the increase of image levels.

[0154] Specifically, the step of calculating the matrix variance using matrix X4 and determining whether the data output by the second module is DATA_OUT1 or DATA_OUT2 based on the variance includes:

[0155] If the matrix variance ≥ 300, it is judged as an edge, and the data output by the second module is DATA_OUT1; if the matrix variance < 300, it is judged as background, and the data output by the second module is DATA_OUT2.

[0156] .

[0157] The interface driver circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal;

[0158] Specifically, composite synchronous video broadcast signals typically include video signals, synchronization signals, chroma signals, and luminance signals. FPGA logic is designed to generate the corresponding signals according to the format of the composite synchronous video broadcast signal. This includes encoding video data, generating synchronization signals, and modulating chroma and luminance signals. Timing control is performed to ensure that each signal output by the FPGA is generated at the correct time to meet the timing requirements of the composite synchronous video broadcast signal. High-precision clocks and counters are required. Level conversion is performed to convert the digital signals output by the FPGA into analog signals that meet the level requirements of the composite synchronous video broadcast signal. This requires the use of a DAC (digital-to-analog converter) and other analog circuitry. Testing and debugging are conducted using an oscilloscope and other testing equipment to check whether the signals output by the FPGA meet the specifications of the composite synchronous video broadcast signal. FPGA logic and circuit parameters are adjusted as needed until the output signals meet the requirements.

[0159] The CRT display is used to display the composite synchronous video broadcast signal.

[0160] Based on the same inventive concept as the foregoing embodiments, this invention also provides an electronic device, such as... Figure 6 As shown, the device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 6 The processor 310 shown in the diagram does not indicate that there is only one processor 310, but only indicates the positional relationship of the processor 310 relative to other devices. In practical applications, there can be one or more processors 310; similarly, Figure 6 The memory 311 shown in the diagram has the same meaning, that is, it is only used to indicate the positional relationship of memory 311 relative to other devices. In practical applications, there can be one or more memories 311. When the processor 310 runs the computer program, the fault diagnosis method of the above-mentioned engineering machinery control system is implemented.

[0161] The device may also include at least one network interface 312. The various components of the device are coupled together via a bus system 313. It is understood that the bus system 313 is used to implement communication between these components. In addition to a data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 6 The general designated all buses as Bus System 313.

[0162] The memory 311 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).

[0163] The memory 311 described in this embodiment of the invention is intended to include, but is not limited to, these and any other suitable types of memory. The memory 311 in this embodiment of the invention is used to store various types of data to support the operation of the device. Examples of this data include: any computer programs used to operate on the device, such as operating systems and applications; contact data; phonebook data; messages; pictures; videos, etc. The operating system includes various system programs, such as the framework layer, core library layer, driver layer, etc., used to implement various basic services and handle hardware-based tasks. Applications can include various applications, such as media players, browsers, etc., used to implement various application services. Here, the program implementing the method of this embodiment of the invention can be included in the application.

[0164] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a computer-readable storage medium storing a computer program. The computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc. When the computer program stored in the computer-readable storage medium is executed by a processor, it implements the fault diagnosis method of the above-mentioned engineering machinery control system.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0167] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An FPGA-based infrared imaging system, the system comprising: An infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit, and a CRT display are characterized by: The infrared detector is used to collect infrared signals and convert the collected infrared signals into electrical signals; The infrared detector driving circuit is used to convert the electrical signal into a raw 64-bit parallel binary digital signal; The FPGA processing system is used to process the original 64-bit parallel binary digital signal in real time and output the processed infrared data stream. The interface driver circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal; The CRT display is used to display the composite synchronous video broadcast signal; The FPGA processing system includes: The original 64-bit parallel binary digital signal input to the FPGA processing system is processed by infrared denoising and enhancement algorithm and AGC algorithm to obtain the processed infrared data stream. The infrared denoising and enhancement algorithm includes a first module and a second module. The first module is used to perform Digital Detail Exchange (DDE) processing on the original 64-bit parallel binary digital signal. The second module is used to determine whether the center value of the matrix is ​​the edge of the image or the background of the image, and output the corresponding data based on the determination result. The first module includes: The original 64-bit parallel binary digital signal is processed in the FPGA processing system for 3...

3. Open a window to obtain matrix X1. Wherein, data11-data33 are the original 64-bit parallel binary digital signals; Multiplying matrix X1 by the boundary coefficients coefxx yields matrix X2. Wherein, the boundary coefficient coefxx is a value between 0 and 1; Calculate the average value of the matrix X2, and use the average value as the weak filter value; The output data of the Digital Detail Enhancement Mode (DDE_mode) is used as the output data of the first module. The output data of the Digital Detail Enhancement Mode is divided into two types: when DDE_mode=0, the output data of the first module is the center pixel value data22 of the matrix X1 and the matrix X2; when DDE_mode=1, the output data of the first module is the weak filter value. The second module includes: Windowing is performed on the data output by the first module to obtain 5 5 matrix x 3, DATA00-DATA44 are The 64-bit parallel binary digital signal after windowing processing; Multiplying matrix X3 by the boundary coefficients coefxx yields matrix X4. ； Multiplying matrix X4 by the threshold coefficient coefxx_2 yields matrix X5. The matrix X5 multiplied by twice the threshold 2. Obtain matrix X6 Matrix X8 is obtained based on matrix X5. Matrix X7 is obtained based on matrix X6. Calculate the average value S_BF1 of matrix X7 and the average value S_BF_x1 of matrix X8, and calculate the parameter S_D1 based on the average value S_BF1 and the average value S_BF_x1, wherein the parameter S_D1 = (S_BF_x1+8192)-S_BF1, and determine the range of the value of S_D2 based on the value of S_D1; Based on the value of S_D2, the values ​​of parameters S_RD_SD, S_RD_mean, and S_RB_BF are calculated, specifically including: Determine the relative magnitude of the sum of the parameters S_RB_BF and S_RD_SD with the parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result; Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2; The variance of the matrix is ​​calculated using matrix X4, and the variance is used to determine whether the data output by the second module is DATA_OUT1 or DATA_OUT2.

2. The system according to claim 1, characterized in that, Based on the value of S_D2, the values ​​of parameters S_RD_SD, S_RD_mean, and S_RB_BF are calculated, specifically including: S_RD_SD= S_D2 Proportion_in S_RD_mean= {Proportion_in,7'd0} S_RB_BF=S_BF_x1 Wherein, Proportion_in is the image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros to the binary value of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in is 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in is 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in is 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in is 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in is 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in is 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in is 280.

3. The system according to claim 2, characterized in that, The step of determining the range of S_D2 values ​​based on the value of S_D1 includes: If S_D1≥8192: If S_D1 <= 8192 + 32, then S_D2 <= S_D1; (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16; (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32; (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48; Otherwise, S_D2 <= S_D1[63:4] + 7680 + 64; If S_D1 < 8192: If S_D1>=8192-32, then S_D2<=S_D1; (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16; (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32; (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48; Otherwise, S_D2 <= S_D1[63:4] + 7680 - 64; Wherein, S_D1[63:1] represents the value after taking the 63rd to 1st characters from the parameter S_D1, S_D1[63:2] represents the value after taking the 63rd to 2nd characters from the output parameter S_D1, S_D1[63:3] represents the value after taking the 63rd to 3rd characters from the parameter S_D1, and S_D1[63:4] represents the value after taking the 63rd to 4th characters from the parameter S_D1.

4. The system according to claim 2, characterized in that, The judgment involves determining the sum of parameter S_RB_BF and parameter S_RD_SD, the magnitude of parameter S_RD_mean, and generating data DATA_OUT1 based on the judgment result, including: If S_RB_B + S_RD_SD < S_RD_mean, then the generated data DATA_OUT1 takes the value of 0; if S_RB_B + S_RD_SD ≥ S_RD_mean, then the generated data DATA_OUT1 takes the value of S_RB_B + S_RD_SD - S_RD_mean.

5. An electronic device, characterized in that, Including the infrared imaging processing system as claimed in any one of claims 1-4.

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