Semiconductor structure and method of manufacturing the same, storage system

Abstract

The application provides a semiconductor structure, a manufacturing method thereof, and a storage system. The manufacturing method of the semiconductor structure includes: forming a plurality of virtual channel structures penetrating through a first stack structure, wherein the plurality of virtual channel structures are arranged along a first direction, and the first direction is perpendicular to a stacking direction of the first stack structure; and forming a gate gap structure penetrating through a part of the virtual channel structures, wherein the gate gap structure extends along the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for storage density in semiconductor structures such as three-dimensional semiconductor memory devices are becoming increasingly stringent. However, as the number of stacked layers in a semiconductor structure increases, the suspended dielectric layer is prone to bending during gate replacement processes. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the background section above or other deficiencies in the prior art.

[0004] This application provides a method for manufacturing a semiconductor structure. The method includes: forming a plurality of virtual channel structures through a first stacked structure, wherein the plurality of virtual channel structures are arranged along a first direction perpendicular to the stacking direction of the first stacked structure; and forming a gate gap structure through a portion of the virtual channel structures, wherein the gate gap structure extends along the first direction.

[0005] In one embodiment, the virtual channel structure includes a first support portion and a second support portion distributed adjacent to each other along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, forming a gate gap structure that penetrates a portion of the virtual channel structure, including: forming a gate gap structure that penetrates the first support portion, wherein the second support portion is in contact with the gate gap structure.

[0006] In one embodiment, the virtual channel structure includes a first support portion, a second support portion, and a third support portion distributed adjacent to each other along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, forming a gate gap structure that penetrates a portion of the virtual channel structure, including: forming a gate gap structure that penetrates the second support portion, wherein the first support portion and the third support portion are respectively in contact with both sides of the gate gap structure.

[0007] In one embodiment, the plurality of virtual channel structures include a first virtual channel structure and a second virtual channel structure that are adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and a gate gap structure extends through at least a portion of one of the first virtual channel structure and the second virtual channel structure.

[0008] In one embodiment, the first virtual channel structure includes a first support portion and a second support portion distributed adjacent to each other along a second direction, and the second virtual channel structure includes a third support portion and a fourth support portion distributed adjacent to each other along the second direction, wherein the second support portion and the third support portion are adjacent to each other and form a gate gap structure that penetrates a portion of the virtual channel structure, including: forming a gate gap structure that penetrates the second support portion and the third support portion, wherein the first support portion and the fourth support portion are respectively in contact with both sides of the gate gap structure.

[0009] In one embodiment, the method includes: forming a plurality of virtual channel structures through a first stacked structure and a channel structure through a second stacked structure and the first stacked structure, wherein the second stacked structure is located on the surface of the first stacked structure, and forming a gate gap structure through a portion of the virtual channel structure, including: forming a gate gap structure through the second stacked structure and through a portion of the virtual channel structure.

[0010] In one embodiment, forming a plurality of virtual channel structures penetrating a first stacked structure and a channel structure penetrating a second stacked structure and a first stacked structure includes: forming a plurality of virtual channel structures penetrating the first stacked structure and an initial first channel structure; forming a second stacked structure and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is connected to the initial first channel structure; removing the initial first channel structure through the second channel hole to form a channel hole; and forming a channel structure within the channel hole.

[0011] In one embodiment, forming a plurality of virtual channel structures and an initial first channel structure through the first stacked structure includes: forming a plurality of virtual channel holes and a first channel hole through the first stacked structure; filling the virtual channel holes and the first channel holes with sacrificial material to form an initial virtual channel structure and an initial first channel structure, respectively; and replacing the initial virtual channel structure with a virtual channel structure.

[0012] In one embodiment, replacing the initial virtual channel structure with a virtual channel structure includes: removing sacrificial material within the virtual channel aperture to form a gap; and forming a filling medium layer within the gap.

[0013] In one embodiment, the first stacked structure includes alternating stacked first dielectric layers and first sacrificial layers, and the second stacked structure includes alternating stacked second dielectric layers and second sacrificial layers, forming a gate gap structure that extends through the second stacked structure and through a portion of the virtual channel structure, including: forming a gate gap that extends through the second stacked structure and through a portion of the virtual channel structure; removing the first and second sacrificial layers through the gate gap to form a sacrificial gap; forming a gate layer within the sacrificial gap; and forming a gate gap structure within the gate gap.

[0014] In one embodiment, the method further includes: forming a top select gate structure on the surface of the second stacked structure; forming a top channel structure that extends through the top select gate structure and into the channel structure along the stacking direction; and forming an electrical contact structure connected to the top channel structure.

[0015] In one embodiment, the gate gap structure extends through a portion of the top select gate structure, the second stacked structure, and the virtual channel structure.

[0016] This application also provides a semiconductor structure. The semiconductor structure includes: a first stacked structure; a plurality of support structures extending through the first stacked structure, wherein the plurality of support structures are arranged along a first direction perpendicular to the stacking direction of the first stacked structure; and a gate gap structure extending through the first stacked structure along the first direction, wherein the gate gap structure contacts the support structures. In one embodiment, the support structures are located on at least one side of the gate gap structure.

[0017] In one embodiment, the plurality of support structures include a first support structure and a second support structure that are adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the first support structure and the second support structure are located on both sides of the gate gap structure, respectively.

[0018] In one embodiment, the material of the support structure includes oxides.

[0019] In one embodiment, the semiconductor structure further includes: a second stacked structure located on the surface of the first stacked structure, wherein a gate gap structure extends through the second stacked structure and the first stacked structure along the stacking direction; and a channel structure extending through the first stacked structure and the second stacked structure, comprising, from the outside to the inside, a barrier layer, a charge trapping layer, a tunneling layer and a channel layer.

[0020] Another aspect of this application provides a storage system including at least one three-dimensional memory, each three-dimensional memory including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the storage of data in the three-dimensional memory.

[0021] In one or more embodiments of this application, by providing a gate gap structure that extends through a portion of the virtual channel structure, the remaining portion of the virtual channel structure can be made to contact the gate gap structure. During the gate replacement process via the gate gap (which can be formed by filling the gate gap with dielectric material), the remaining portion of the virtual channel structure can serve as a support structure around the gate gap, reducing the bending phenomenon of the stacked structure. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0023] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0024] Figures 2 to 8 This is a process step diagram of manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0025] Figures 9 to 11 This is a schematic diagram showing the positional relationship between the virtual channel structure and the gate gap structure according to three embodiments of this application;

[0026] Figure 12 This is a schematic diagram of a semiconductor structure manufactured according to another exemplary embodiment of this application;

[0027] Figures 13 to 21 This is a process step diagram of manufacturing a semiconductor structure according to another exemplary embodiment of this application;

[0028] Figures 22 to 24 This is a schematic diagram showing the positional relationship between the virtual channel structure and the gate gap structure according to three other embodiments of this application;

[0029] Figure 25 This is a schematic diagram of a semiconductor structure manufactured according to another exemplary embodiment of this application;

[0030] Figure 26 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of this application;

[0031] Figures 27 to 29 This is a schematic diagram showing the positional relationship between the support structure and the gate gap structure according to three other embodiments of this application;

[0032] Figure 30 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0033] Figure 31A and Figure 31B This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0035] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first stacked structure discussed herein may also be referred to as the second stacked structure, and the first virtual channel structure may also be referred to as the second virtual channel structure, and vice versa.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0039] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0040] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0044] Figure 1 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of this application.

[0045] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a plurality of virtual channel structures penetrating a first stacked structure, wherein the plurality of virtual channel structures are arranged along a first direction, the first direction being perpendicular to the stacking direction of the first stacked structure; and S1200, forming a gate gap structure penetrating a portion of the virtual channel structures, wherein the gate gap structure extends along the first direction. Steps S1100 and S1200 will be described in detail below.

[0046] like Figure 5 As shown, multiple virtual channel structures 1200 can be formed through the first stacked structure 1100, wherein the multiple virtual channel structures 1200 are arranged along a first direction X, and the first direction X is perpendicular to the stacking direction Z of the first stacked structure 1100.

[0047] Specifically, such as Figure 2 As shown, a first dielectric layer 1110 and a first sacrificial layer 1120 can be alternately stacked to form a first stacked structure 1100. Exemplarily, a virtual channel via 1210 can be formed through the first stacked structure 1100. Figure 3 Then, a filling medium layer 100 is formed within the virtual channel hole 1200 to form the virtual channel structure 1200. Figure 5 ).

[0048] Exemplarily, the first stacked structure 1100 can be formed by sequentially stacking the first dielectric layer 1110 and the first sacrificial layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that the number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 are not limited to... Figure 2 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 as needed. Furthermore, the materials of the first dielectric layer 1110 and the first sacrificial layer 1120 may be selected from suitable materials known in the art; for example, the material of the first dielectric layer 1110 may include oxides such as silicon oxide, and the material of the first sacrificial layer 1120 may include nitrides such as silicon nitride.

[0049] For example, such as Figure 2 As shown, a first stacked structure 1100 can be formed on a substrate 1400. The substrate 1400 can be used to support the first stacked structure 1100 thereon and can be removed in subsequent processes. The material of the substrate 1400 includes at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 1400 can be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or it can be a multilayer structure such as including a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, multiple layers prepared of different materials can be sequentially formed to form the substrate 1400 by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0050] For example, in the process of forming the virtual channel hole 1210, a plurality of channel holes 1310 penetrating the first stacked structure 1100 may also be formed. Figure 3 Then, sacrificial material 200 can be filled into the channel hole 1310 to form the initial channel structure 1320. Figure 4 After forming the virtual channel structure 1200, the sacrificial material 200 within the channel hole 1310 can be removed, and then the channel structure 1300 can be formed within the channel hole 1310. Figure 7 ).

[0051] Exemplarily, the virtual channel holes 1210 and 1310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The virtual channel holes 1210 and 1310 may have a cylindrical or columnar shape extending along the stacking direction in the first stack structure 1100. Alternatively, the virtual channel holes 1210 and 1310 may extend into the substrate 1400.

[0052] During the formation of the virtual channel structure 1200, such as Figure 4 As shown, sacrificial material 200 can be filled into virtual channel holes 1210 and 1310 to form initial virtual channel structures 1220 and 1320, respectively. The sacrificial material 200 may include materials such as carbides, which have a low density to facilitate subsequent removal. Figure 5 As shown, a mask layer 300 can be formed on the surface of the initial channel structure 1320 to cover the initial channel structure 1320. Then, the sacrificial material 200 within the virtual channel aperture 1210 can be removed to form a gap (not shown), and a filling dielectric layer 100 can be formed within the gap to form the virtual channel structure 1200. It should be understood that during the formation of the filling dielectric layer 100, a filling dielectric layer 100 is also formed on the first stacked structure 1100. Figure 5 Subsequently, the filling medium layer 100 on the first stacked structure 1100 can be removed by a process such as mechanical grinding to form... Figure 6 The structure shown.

[0053] For example, in forming Figure 6 After the structure shown is completed, the sacrificial material 200 inside the channel hole 1310 can be removed, and then the channel structure 1300 can be formed inside the channel hole 1310. Figure 7 Forming the channel structure 1300 may include: forming a functional layer 1370 and a channel layer 1360 sequentially from the outside to the inside in the channel hole 1310; and forming a channel filling medium layer 1380 and a channel plug 1390.

[0054] The functional layer 1370 may include a barrier layer 1330 formed on the inner wall of the channel via 1310 to block the outflow of charge, a charge trapping layer 1340 formed on the surface of the barrier layer 1330 to store charge during operation of the semiconductor structure, and a tunneling layer 1350 formed on the surface of the charge trapping layer 1340.

[0055] In some embodiments, functional layer 1370 may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, functional layer 1370 may have a structure different from that of an ONO configuration. Channel layer 1360 may be formed on the surface of tunneling layer 1350 and is capable of transporting the required charge (electrons or holes).

[0056] For example, as an alternative, according to one embodiment of this application, a functional layer 1370 may be formed on the inner wall and bottom surface of the channel hole 1310, and a channel layer 1360 may be formed on the surface of the tunneling layer 1350 of the functional layer 1370 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0057] Furthermore, the channel structure 1300 also includes a channel plug 1390 formed at one end of the channel layer 1360 away from the substrate 1400 (which can be understood as the top of the channel structure 1300). Specifically, after forming the functional layer 1370 and the channel layer 1360, the channel hole 1310 can be filled with a channel-filling dielectric layer 1380. The channel-filling dielectric layer 1380 may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps can be formed in the channel-filling dielectric layer 1380 to reduce structural stress by controlling the channel filling process. Then, the channel plug 1390 is formed in the portion of the channel-filling dielectric layer 1380 located at the top of the channel hole 1310. The material of the channel plug 1390 can be selected from the same material as the channel layer 1360, such as N-type doped or P-type doped polysilicon. The channel plug 1390 is connected to the channel layer 1360.

[0058] In the exemplary embodiments of this application, such as Figure 8 As shown, a gate gap structure 1500 may be formed through a portion of the virtual channel structure 1200, wherein the gate gap structure 1500 extends along a first direction X. Exemplarily, as... Figures 9 to 11 The diagram shows the positional relationship between the virtual channel structure 1200 and the gate gap structure 1500 in the three embodiments shown.

[0059] In this application, multiple virtual channel structures 1200 can be arranged along a first direction X. For example... Figure 9 and Figure 10 As shown, the gate gap structure 1500 can penetrate a portion of a row of virtual channel structures 1200 arranged along the first direction X. Furthermore, the multiple virtual channel structures 1200 can also be distributed adjacently along a second direction Y, wherein the second direction Y can be perpendicular to the first direction X and the stacking direction Z. Figure 11As shown, the gate gap structure 1500 can penetrate a portion of each of the two rows of virtual channel structures 1200 arranged along the first direction X and adjacently distributed along the second direction Y.

[0060] Specifically, in one exemplary embodiment of this application, such as Figure 9 As shown, the maximum cross-sectional dimension of the virtual channel structure 1200 along the second direction Y can be greater than the maximum cross-sectional dimension of the channel structure 1300 along the second direction Y. The second direction Y can be perpendicular to the first direction X and the stacking direction Z. The virtual channel structure 1200 may include a first support portion (not shown) and a second support portion 1230 that are adjacently distributed along the second direction Y.

[0061] The gate gap structure 1500 forming a portion of the virtual channel structure 1200 may include: forming a gate gap structure 1500 through a first support portion, wherein a second support portion 1230 may contact the gate gap structure 1500.

[0062] In another exemplary embodiment of this application, such as Figure 10 As shown, the maximum cross-sectional dimension H1 of the virtual channel structure 1200 along the second direction Y can be greater than the maximum cross-sectional dimension H2 of the channel structure 1300 along the second direction Y. The virtual channel structure 1200 may include a first support portion 1230, a second support portion (not shown), and a third support portion 1240 that are adjacently distributed along the second direction Y.

[0063] The gate gap structure 1500 forming a portion of the virtual channel structure 1200 may include: forming a gate gap structure 1500 through a second support portion, wherein the first support portion 1230 and the third support portion 1240 may respectively contact the two sides of the gate gap structure 1500.

[0064] In another exemplary embodiment of this application, such as Figure 11 As shown, the maximum cross-sectional dimension of the virtual channel structure 1200 along the second direction Y can be the same as the maximum cross-sectional dimension of the channel structure 1300 along the second direction Y. Multiple virtual channel structures 1200 may include a first virtual channel structure 1200-1 and a second virtual channel structure 1200-2 distributed adjacently along the second direction Y. The gate gap structure 1500 may penetrate a portion of at least one of the first virtual channel structure 1200-1 and the second virtual channel structure 1200-2. For example, the gate gap structure 1500 may penetrate a portion of either the first virtual channel structure 1200-1 or the second virtual channel structure 1200-2 to form a similar Figure 9 or Figure 10 The structure shown.

[0065] Furthermore, the gate gap structure 1500 may extend through a portion of the first virtual channel structure 1200-1 and the second virtual channel structure 1200-2. Specifically, as shown... Figure 11 As shown, the first virtual channel structure 1200-1 may include a first support portion 1230 and a second support portion (not shown) that are adjacently distributed along the second direction Y. The second virtual channel structure 1200-2 may include a third support portion (not shown) and a fourth support portion 1240 that are adjacently distributed along the second direction Y.

[0066] The second support section can be adjacent to the third support section.

[0067] The gate gap structure 1500 forming a portion of the virtual channel structure 1200 may include: forming a gate gap structure 1500 that extends through a second support portion and a third support portion, wherein the first support portion 1230 and the fourth support portion 1260 may respectively contact the two sides of the gate gap structure 1500.

[0068] It should be understood that the manner in which the gate gap structure 1500 penetrates a portion of the virtual channel structure 1200, as described in this application, is merely an example and not an exhaustive description. In this application, the gate gap structure 1500 may penetrate any portion of the virtual channel structure 1200 that satisfies actual process requirements, such that the remaining portion of the virtual channel structure 1200 contacts the gate gap structure 1500. Thus, during a gate replacement process via the gate gap (which can be formed by filling the gate gap with dielectric material), the remaining portion of the virtual channel structure 1200 can serve as a support structure around the gate gap, reducing the bending phenomenon of the first stacked structure. Furthermore, by setting the remaining portion of the virtual channel structure 1200 to contact the gate gap structure 1500 (i.e., to contact the gate gap), the difficulty of forming the gate gap can also be reduced.

[0069] In the exemplary embodiments of this application, such as Figure 8 As shown, forming the gate gap structure 1500 may include: forming a gate gap (not shown) through the first stacked structure 1100; removing the first sacrificial layer 1120 through the gate gap to form a sacrificial gap (not shown); forming a gate layer 1130 within the sacrificial gap; and forming the gate gap structure 1500 within the gate gap.

[0070] Exemplarily, the gate gap can serve as a pathway for providing etchant. Exemplarily, the gate gap can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap may extend through a portion of the virtual channel structure 1200 along the stacking direction Z and may extend along a first direction X. As an alternative, such as Figure 8As shown, the gate gap can extend through a portion of the virtual channel structure 1200 along the stacking direction Z and extend to the substrate 1400. In other words, the gate gap structure 1500 can extend through a portion of the virtual channel structure 1200 along the stacking direction Z and extend to the substrate 1400.

[0071] It should be understood that the gate layer 1130 may include, for example, metal. The gate layer 1130 may function as the control gate for each memory cell, improving the control capability of the control gate. Exemplarily, the first sacrificial layer 1120 may be removed by a process such as wet etching to form a sacrificial gap.

[0072] In the exemplary embodiments of this application, such as Figure 8 As shown, forming the gate layer 1130 within the sacrificial gap may include sequentially forming a barrier layer 1140 and the gate layer 1130 within the sacrificial gap. The barrier layer 1140 may be located between the first dielectric layer 1110 and the gate layer 1130. In other words, the first dielectric layer 1110, the barrier layer 1140, and the gate layer 1130 are alternately stacked along the stacking direction Z of the first stacked structure 1100. It should be understood that the barrier layer 1140 may include, for example, aluminum oxide. The barrier layer 1140 can effectively prevent charge in the gate layer 1130 from diffusing into the first dielectric layer 1110. On the other hand, the barrier layer 1140 can increase the dielectric constant between the gate layer 1130 and the first dielectric layer 1110, thereby enhancing the controllability of the gate layer 1130. For example, the barrier layer 1140 and the gate layer 1130 may be sequentially formed within the sacrificial gap using deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0073] In an exemplary embodiment of this application, an insulating material 1510 and a dielectric material 1520 can be sequentially filled from the outside to the inside of the gate gap to form a gate gap structure 1500. By filling the inner wall of the gate gap with insulating material 1510, this application can disconnect adjacent gate layers 1130, avoiding subsequent electrical connections between gate layers 1130 of different levels.

[0074] Exemplarily, after filling the insulating material 1510, the remaining region of the gate gap 1510 can be filled with dielectric material 1520 to form a gate gap structure 1500. The gate gap structure 1500 can be used to divide the memory region to form multiple memory blocks. Specifically, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to fill the remaining region of the gate gap with dielectric material 1520 to form the gate gap structure 1500. The dielectric material 1520 can be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polysilicon; this application is not limited in this regard.

[0075] In the exemplary embodiments of this application, such as Figure 8 As shown, a top select gate structure 1600 may be formed on the surface of the first stacked structure 1100; a top channel structure 1700 may be formed that extends through the top select gate structure 1600 and into the channel structure 1300 along the stacking direction Z; and an electrical contact structure 1800 may be formed that is connected to the top channel structure 1700.

[0076] Exemplarily, the top select gate structure 1600 may include a multilayer structure sequentially stacked on the surfaces of the first stack structure 1100. A top channel structure 1700 may extend along the stacking direction Z through the top select gate structure 1600 and to a channel plug 1390 of the channel structure 1300. An electrical contact structure 1800 may be used to transmit electrical signals between the external environment and the channel structure 1300.

[0077] In another exemplary embodiment of this application, such as Figure 12 As shown, the gate gap structure 1500 can be formed after the top select gate structure 1600 is formed. Thus, the gate gap structure 1500 can extend through the top select gate structure 1600 and a portion of the virtual channel structure 1200.

[0078] It should be understood that this application does not limit the order in which the gate gap structure 1500 and the top select gate structure 1600 are formed. The order of the formation processes of the gate gap structure 1500 and the top select gate structure 1600 can be interchanged. In other words, the top select gate structure 1600 can be formed after the gate gap structure 1500 is formed; of course, the gate gap structure 1500 can also be formed after the top select gate structure 1600 is formed, and this application does not specifically limit this.

[0079] As the demand for semiconductor storage capacity continues to increase, the size of the storage stack is gradually increasing. In the exemplary embodiments of this application, multiple stacked structures can be provided, such as a first stacked structure and a second stacked structure.

[0080] For example, such as Figures 13 to 21 As shown, a method 1000 for manufacturing a semiconductor structure is described with the semiconductor structure comprising two stacked structures. It should be understood that the semiconductor structure may also include more stacked structures, and this application does not impose specific limitations on this.

[0081] like Figure 16 As shown, multiple virtual channel structures 1200 can be formed through the first stacked structure 1100, wherein the multiple virtual channel structures 1200 are arranged along a first direction X, and the first direction X is perpendicular to the stacking direction Z of the first stacked structure 1100.

[0082] Specifically, such as Figure 13 As shown, a first dielectric layer 1110 and a first sacrificial layer 1120 can be alternately stacked to form a first stacked structure 1100. Exemplarily, a virtual channel via 1210 can be formed through the first stacked structure 1100. Figure 14 Then, a filling medium layer 100 is formed within the virtual channel hole 1200 to form the virtual channel structure 1200. Figure 16 ).

[0083] For example, such as Figure 13 As shown, a first stacked structure 1100 can be formed on a substrate 1400. The substrate 1400 can be used to support the first stacked structure 1100 thereon and can be removed in subsequent processes.

[0084] For example, in the process of forming the virtual channel hole 1210, a plurality of first channel holes 1310 penetrating the first stacked structure 1100 may also be formed. Figure 14 Then, sacrificial material 200 can be filled into the first channel hole 1310 to form the initial first channel structure 1320. Figure 15 ).

[0085] During the formation of the virtual channel structure 1200, such as Figure 15 As shown, sacrificial material 200 can be filled into the virtual channel hole 1210 and the first channel hole 1310 to form the initial virtual channel structure 1220 and the initial first channel structure 1320, respectively. The sacrificial material 200 may include materials such as carbides, which have a low density to facilitate subsequent removal. Figure 16 As shown, a mask layer 300 can be formed on the surface of the initial first channel structure 1320 to cover the initial first channel structure 1320. Then, the sacrificial material 200 within the virtual channel aperture 1210 can be removed to form a gap (not shown), and a filling dielectric layer 100 can be formed within the gap to form the virtual channel structure 1200. It should be understood that during the formation of the filling dielectric layer 100, a filling dielectric layer 100 is also formed on the first stacked structure 1100. Figure 16Subsequently, the filling medium layer 100 on the first stacked structure 1100 can be removed by a process such as mechanical grinding to form... Figure 17 The structure shown.

[0086] For example, in forming Figure 17 After the structure shown, as Figure 18 As shown, a second stacked structure 2100 can be formed by alternately stacking a second dielectric layer 2110 and a second sacrificial layer 2120 on the surface of the first stacked structure 1100.

[0087] Exemplarily, the second stacked structure 2100 can be formed by sequentially stacking the second dielectric layer 2110 and the second sacrificial layer 2120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that the number and thickness of the second dielectric layer 2110 and the second sacrificial layer 2120 are not limited to... Figure 18 The quantities and thicknesses shown herein, without departing from the concept of this application, allow those skilled in the art to create any number and thickness of the second dielectric layer 2110 and the second sacrificial layer 2120 as needed. Furthermore, the materials of the second dielectric layer 2110 and the second sacrificial layer 2120 may be selected from suitable materials known in the art; for example, the material of the second dielectric layer 2110 may include oxides such as silicon oxide, and the material of the second sacrificial layer 2120 may include nitrides such as silicon nitride.

[0088] For example, such as Figure 19 As shown, a second channel hole 2210 can be formed through the second stacked structure 2100, wherein the second channel hole 2210 can be connected to the initial first channel structure 1320. Exemplarily, the initial first channel structure 1320 can be removed via the second channel hole 2210 to form the channel hole 2200. Figure 19 ); and forming a channel structure 2300 within the channel hole 2200. Figure 20 It should be understood that the channel hole 2200 may include a first channel hole 1310 and a second channel hole 2210.

[0089] like Figure 20 As shown, forming the channel structure 2300 may include: forming a functional layer 2370 and a channel layer 2360 sequentially from the outside to the inside of the channel hole 2200; and forming a channel filling dielectric layer 2380 and a channel plug 2390. It should be understood that the channel structure 2300 may penetrate the first stacked structure 1100 and the second stacked structure 2100 and extend to the substrate 1400.

[0090] In the exemplary embodiments of this application, such as Figure 21As shown, a gate gap structure 2500 may be formed through a portion of the virtual channel structure 1200, wherein the gate gap structure 2500 extends along a first direction X. Specifically, a gate gap structure 2500 may be formed through the second stacked structure 2100 and through a portion of the virtual channel structure 1200. For example, as... Figures 22 to 24 The diagram shows the positional relationship between the virtual channel structure 1200 and the gate gap structure 2500 in the three embodiments shown.

[0091] In this application, multiple virtual channel structures 1200 can be arranged along a first direction X. For example... Figure 22 and Figure 23 As shown, the gate gap structure 2500 can penetrate the second stacked structure 2100 and a portion of a row of virtual channel structures 1200 arranged along the first direction X. Furthermore, the plurality of virtual channel structures 1200 can also be distributed adjacently along the second direction Y, wherein the second direction Y can be perpendicular to the first direction X and the stacking direction Z. Figure 24 As shown, the gate gap structure 2500 can penetrate the second stacked structure 2100 and a portion of each of the two rows of virtual channel structures 1200 arranged along the first direction X and adjacently distributed along the second direction Y.

[0092] Specifically, in one exemplary embodiment of this application, such as Figure 22 As shown, the maximum cross-sectional dimension of the virtual channel structure 1200 along the second direction Y can be greater than the maximum cross-sectional dimension of the channel structure 2300 along the second direction Y. The second direction Y can be perpendicular to the first direction X and the stacking direction Z. The virtual channel structure 1200 may include a first support portion (not shown) and a second support portion 1230 that are adjacently distributed along the second direction Y.

[0093] The gate gap structure 2500 that forms through the second stacked structure 2100 and a portion of the virtual channel structure 1200 may include: forming a gate gap structure 2500 that forms through the second stacked structure 2100 and a first support portion, wherein the second support portion 1230 may contact the gate gap structure 2500.

[0094] In another exemplary embodiment of this application, such as Figure 23 As shown, the maximum cross-sectional dimension H1 of the virtual channel structure 1200 along the second direction Y can be greater than the maximum cross-sectional dimension H2 of the channel structure 2300 along the second direction Y. The virtual channel structure 1200 may include a first support portion 1230, a second support portion (not shown), and a third support portion 1240 that are adjacently distributed along the second direction Y.

[0095] The gate gap structure 2500 that forms a portion of the second stacked structure 2100 and the virtual channel structure 1200 may include: forming a gate gap structure 2500 that forms a portion of the second stacked structure 2100 and the second support portion, wherein the first support portion 1230 and the third support portion 1240 may respectively contact the two sides of the gate gap structure 2500.

[0096] In another exemplary embodiment of this application, such as Figure 24 As shown, the maximum cross-sectional dimension of the virtual channel structure 1200 along the second direction Y can be the same as the maximum cross-sectional dimension of the channel structure 2300 along the second direction Y. Multiple virtual channel structures 1200 may include a first virtual channel structure 1200-1 and a second virtual channel structure 1200-2 adjacently distributed along the second direction Y. The gate gap structure 2500 may penetrate a portion of at least one of the first virtual channel structure 1200-1 and the second virtual channel structure 1200-2. For example, the gate gap structure 2500 may penetrate the second stacked structure 2100 and a portion of the first virtual channel structure 1200-1 or the second virtual channel structure 1200-2 to form a similar Figure 22 or Figure 23 The structure shown.

[0097] Furthermore, the gate gap structure 2500 may extend through a portion of the first virtual channel structure 1200-1 and the second virtual channel structure 1200-2. Specifically, as shown... Figure 24 As shown, the first virtual channel structure 1200-1 may include a first support portion 1230 and a second support portion (not shown) that are adjacently distributed along the second direction Y. The second virtual channel structure 1200-2 may include a third support portion (not shown) and a fourth support portion 1240 that are adjacently distributed along the second direction Y.

[0098] The second support section can be adjacent to the third support section.

[0099] The gate gap structure 2500 that forms a portion of the second stacked structure 2100 and the virtual channel structure 1200 may include: forming a gate gap structure 2500 that forms a portion of the second stacked structure 2100, a second support portion, and a third support portion, wherein the first support portion 1230 and the fourth support portion 1260 may respectively contact the two sides of the gate gap structure 2500.

[0100] It should be understood that the manner in which the gate gap structure 2500 penetrates a portion of the virtual channel structure 1200, as described in this application, is merely an example and not an exhaustive description. In this application, the gate gap structure 2500 may penetrate any portion of the virtual channel structure 1200 that satisfies actual process requirements, such that the remaining portion of the virtual channel structure 1200 contacts the gate gap structure 2500. Thus, during a gate replacement process via the gate gap (which can be formed by filling the gate gap with dielectric material), the remaining portion of the virtual channel structure 1200 can serve as a support structure around the gate gap, reducing the bending phenomenon of the first stacked structure. Furthermore, by setting the remaining portion of the virtual channel structure 1200 to contact the gate gap structure 1500 (i.e., to contact the gate gap), the difficulty of forming the gate gap can also be reduced.

[0101] In the exemplary embodiments of this application, such as Figure 21 As shown, forming the gate gap structure 2500 may include: forming a gate gap (not shown) that extends through the second stacked structure 2100 and a portion of the virtual channel structure 1200; removing the first sacrificial layer 1120 and the second sacrificial layer 2120 via the gate gap to form a sacrificial gap (not shown); forming a gate layer 2130 within the sacrificial gap; and forming the gate gap structure 2500 within the gate gap.

[0102] Exemplarily, the gate gap can serve as a pathway for providing etchant. Exemplarily, the gate gap can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap may extend through the second stacked structure 2100 and a portion of the virtual channel structure 1200 along the stacking direction Z, and may extend along the first direction X. As an alternative, such as Figure 21 As shown, the gate gap can penetrate the second stacked structure 2100 and a portion of the virtual channel structure 1200 along the stacking direction Z, and extend to the substrate 1400. In other words, the gate gap structure 2500 can penetrate the second stacked structure 2100 and a portion of the virtual channel structure 1200 along the stacking direction Z, and extend to the substrate 1400.

[0103] It should be understood that the gate layer 2130 may include, for example, metal. The gate layer 2130 may function as the control gate for each memory cell, improving the control capability of the control gate. Exemplarily, the first sacrificial layer 1120 and the second sacrificial layer 2120 may be removed by a process such as wet etching to form a sacrificial gap.

[0104] In the exemplary embodiments of this application, such as Figure 21As shown, forming the gate layer 2130 within the sacrificial gap may include sequentially forming a barrier layer 2140 and the gate layer 2130 within the sacrificial gap. The barrier layer 2140 may be located between the first dielectric layer 1110 and the gate layer 2130, and between the second dielectric layer 2110 and the gate layer 2130. In other words, the first dielectric layer 1110 (or the second dielectric layer 2110), the barrier layer 2140, and the gate layer 2130 are alternately stacked along the stacking direction Z. It should be understood that the barrier layer 2140 may include, for example, aluminum oxide. The barrier layer 2140 can effectively prevent charge diffusion from the gate layer 2130 into the first dielectric layer 1110 and the second dielectric layer 2110. On the other hand, the barrier layer 2140 can increase the dielectric constant between the gate layer 2130 and the first dielectric layer 1110, and between the gate layer 2130 and the second dielectric layer 2110, thereby enhancing the controllability of the gate layer 2130. For example, the barrier layer 2140 and the gate layer 2130 may be sequentially formed within the sacrificial gap using deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0105] In an exemplary embodiment of this application, an insulating material 2510 and a dielectric material 2520 can be sequentially filled from the outside to the inside of the gate gap to form a gate gap structure 2500. By filling the inner wall of the gate gap with insulating material 2510, this application can disconnect adjacent gate layers 2130, avoiding subsequent electrical connections between gate layers 2130 of different levels.

[0106] Exemplarily, after filling the insulating material 2510, the remaining region of the gate gap 2510 can be filled with dielectric material 2520 to form a gate gap structure 2500. The gate gap structure 2500 can be used to divide the memory region to form multiple memory blocks. Specifically, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to fill the remaining region of the gate gap with dielectric material 2520 to form the gate gap structure 2500. The dielectric material 2520 can be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polysilicon; this application is not limited in this regard.

[0107] In the exemplary embodiments of this application, such as Figure 21 As shown, a top select gate structure 1600 may be formed on the surface of the second stacked structure 2100; a top channel structure 1700 may be formed that extends through the top select gate structure 1600 and into the channel structure 2300 along the stacking direction Z; and an electrical contact structure 1800 may be formed that is connected to the top channel structure 1700.

[0108] Exemplarily, the top select gate structure 1600 may include a multilayer structure sequentially stacked on the surfaces of the second stacked structure 2100. A top channel structure 1700 may extend along the stacking direction Z through the top select gate structure 1600 and to a channel plug 2390 of the channel structure 2300. An electrical contact structure 1800 may be used to transmit electrical signals between the external environment and the channel structure 2300.

[0109] In another exemplary embodiment of this application, such as Figure 25 As shown, the gate gap structure 2500 can be formed after the top select gate structure 1600 is formed. Thus, the gate gap structure 2500 can penetrate the top select gate structure 1600, the second stacked structure 2100, and a portion of the virtual channel structure 1200.

[0110] It should be understood that this application does not limit the order in which the gate gap structure 2500 and the top select gate structure 1600 are formed. The order of the formation processes of the gate gap structure 2500 and the top select gate structure 1600 can be interchanged. In other words, the top select gate structure 1600 can be formed after the gate gap structure 2500 is formed; of course, the gate gap structure 2500 can also be formed after the top select gate structure 1600 is formed, and this application does not specifically limit this.

[0111] Figure 26 This is a schematic diagram of the structure of a semiconductor structure 3000 according to an exemplary embodiment of this application.

[0112] The semiconductor structure 3000 may include a first stacked structure 3100, a plurality of support structures 3200 and a gate gap structure 3500.

[0113] The first stacked structure 3100 may include alternately stacked first dielectric layer 3110, barrier layer 3140, and gate layer 3130. It should be understood that the number and thickness of the first dielectric layer 3110, barrier layer 3140, and gate layer 3130 are not limited to... Figure 26 The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of this application. Any number and thickness of the first dielectric layer 3110, barrier layer 3140, and gate layer 3130 can be provided as needed. Furthermore, the materials of the first dielectric layer 3110, barrier layer 3140, and gate layer 3130 can be selected from suitable materials known in the art. For example, the material of the first dielectric layer 3110 may include oxides. The material of the barrier layer 3140 may include aluminum oxide, etc. The material of the gate layer 3130 may include metals and / or combinations of metal compounds.

[0114] Multiple support structures 3200 may penetrate the first stacked structure 3100. The multiple support structures 3200 may be arranged along a first direction X, which may be perpendicular to the stacking direction Z of the first stacked structure 3100. The material of the support structures 3200 may include oxides.

[0115] The gate gap structure 3500 can penetrate the first stacked structure 3100 and extend along the first direction X, wherein the gate gap structure 3500 can contact the support structure 3200. Exemplarily, the support structure 3200 can be located on at least one side of the gate gap structure 3500. By setting the gate gap structure 3500 to contact the support structure 3200, this application can ensure that the support structure 3200 has a supporting function during the fabrication of the semiconductor structure 3000, reducing the bending phenomenon of the first stacked structure and lowering the difficulty of forming the gate gap structure 3500. Exemplarily, the gate gap structure 3500 can sequentially include an insulating material 3510 and a dielectric material 3520 from the outside to the inside.

[0116] In an exemplary embodiment of this application, the semiconductor structure 3000 may further include a channel structure 3300 penetrating the first stacked structure. The channel structure 3300 includes, from the outside to the inside, a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer. In addition, the channel structure 3300 may also include a channel filling dielectric layer located inside the channel layer and a channel plug 3390 connected to the channel layer.

[0117] like Figures 27 to 29 The diagram shows the positional relationship between the support structure 3200 and the gate gap structure 3500 in three embodiments of this application.

[0118] In one exemplary embodiment of this application, such as Figure 27 As shown, the support structure 3200 may be located on one side of the gate gap structure 3500. In another exemplary embodiment of this application, as... Figure 28 or Figure 29 As shown, the support structure 3200 may be located on both sides of the gate gap structure 3500. Exemplarily, the plurality of support structures 3200 include a first support structure 3210 and a second support structure 3220 adjacently distributed along a second direction Y, wherein the second direction Y is perpendicular to the first direction X and the stacking direction Z. The first support structure 3210 and the second support structure 3220 may be located on both sides of the gate gap structure 3500, respectively.

[0119] In this application, the shapes of the multiple support structures 3200 can be arbitrarily formed to meet actual process requirements, and this application does not impose specific limitations on them. For example, the support structure 3200 may have a partially cylindrical or partially columnar shape extending along the stacking direction Z in the first stacked structure 1100. Furthermore, in actual processes, the curvature of the partially cylindrical shape can be arbitrarily adjusted according to requirements, that is, the degree of curvature of the partially cylindrical shape can be reasonably set according to requirements. Specifically, in the case of… Figure 28 In the illustrated embodiment, the first support structure 3210 and the second support structure 3220 have large curvatures, and the number of support structures in contact with the gate gap structure 3500 is small. In such... Figure 29 In the embodiment shown, the curvature of the first support structure 3210 and the second support structure 3220 is small, and the number of support structures in contact with the gate gap structure 3500 is large.

[0120] In the exemplary embodiments of this application, such as Figure 26 As shown, the semiconductor structure 3000 may further include a substrate 3400, a top select gate structure 3600, a top channel structure 3700, and an electrical contact structure 3800.

[0121] The first stacked structure 3100 may be located on the substrate 3400. The substrate 3400 may be used to support the first stacked structure 3100 thereon. The top select gate structure 3600 may include a multilayer structure sequentially stacked on the surfaces of the first stacked structure 3100. The top channel structure 3700 may extend along the stacking direction Z through the top select gate structure 3600 and into the channel plug 3390 of the channel structure 3300. The electrical contact structure 3800 may be used to transmit electrical signals between the outside world and the channel structure 3300.

[0122] In another exemplary embodiment of this application, the gate gap structure 3500 may penetrate the top selected gate structure 3600 and the first stacked structure 3100 and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200.

[0123] In another exemplary embodiment of this application, the semiconductor structure 3000 may further include a second stacked structure (not shown). The second stacked structure may be located on the surface of the first stacked structure 3100. A gate gap structure 3500 may extend through the second stacked structure and the first stacked structure 3100 along the stacking direction Z and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200. A channel structure 3300 may extend through the first stacked structure 3100 and the second stacked structure.

[0124] In another exemplary embodiment of this application, the gate gap structure 3500 may extend through the top selected gate structure 3600, the second stacked structure and the first stacked structure 3100 and along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200.

[0125] Since the content and structure described above regarding the method 1000 for manufacturing a semiconductor structure can be applied in whole or in part to the semiconductor structure 3000 described herein, related or similar content will not be repeated here.

[0126] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0127] Figure 30 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this application.

[0128] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 30 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0129] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0130] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 31AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 30 The host 18) is coupled to the memory card connector 24. In such a way... Figure 31B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 20 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0131] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple virtual channel structures are formed that penetrate the first stacked structure, wherein the multiple virtual channel structures are arranged along a first direction, the first direction being perpendicular to the stacking direction of the first stacked structure; and A gate gap structure is formed that extends through a portion of the virtual channel structure, wherein the gate gap structure extends along the first direction.

2. The method according to claim 1, characterized in that, The virtual channel structure includes a first support portion and a second support portion distributed adjacent to each other along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, forming a gate gap structure that penetrates a portion of the virtual channel structure, including: A gate gap structure is formed through the first support portion, wherein the second support portion is in contact with the gate gap structure.

3. The method according to claim 1, characterized in that, The virtual channel structure includes a first support portion, a second support portion, and a third support portion distributed adjacently along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, forming a gate gap structure that penetrates a portion of the virtual channel structure, including: A gate gap structure is formed that extends through the second support portion, wherein the first support portion and the third support portion are respectively in contact with both sides of the gate gap structure.

4. The method according to claim 1, characterized in that, The plurality of virtual channel structures include a first virtual channel structure and a second virtual channel structure that are adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the gate gap structure extends through a portion of at least one of the first virtual channel structure and the second virtual channel structure.

5. The method according to claim 4, characterized in that, The first virtual channel structure includes a first support portion and a second support portion distributed adjacent to each other along the second direction, and the second virtual channel structure includes a third support portion and a fourth support portion distributed adjacent to each other along the second direction, wherein the second support portion and the third support portion are adjacent to each other and form a gate gap structure penetrating a portion of the virtual channel structure, including: A gate gap structure is formed that extends through the second support portion and the third support portion, wherein the first support portion and the fourth support portion are respectively in contact with both sides of the gate gap structure.

6. The method according to claim 1, characterized in that, The method includes: A plurality of virtual channel structures are formed penetrating the first stacked structure and a channel structure penetrating the second stacked structure and the first stacked structure, wherein the second stacked structure is located on the surface of the first stacked structure and forms a gate gap structure penetrating a portion of the virtual channel structure, including: The gate gap structure is formed through the second stacked structure and through a portion of the virtual channel structure.

7. The method according to claim 6, characterized in that, Forming a plurality of virtual channel structures penetrating the first stacked structure and a channel structure penetrating the second stacked structure and the first stacked structure, including: Multiple virtual channel structures and an initial first channel structure are formed that penetrate the first stacked structure; The second stacked structure is formed, and a second channel hole is formed through the second stacked structure, wherein the second channel hole is connected to the initial first channel structure; The initial first channel structure is removed via the second channel aperture to form a channel aperture; and A channel structure is formed within the channel hole.

8. The method according to claim 7, characterized in that, Forming multiple virtual channel structures and an initial first channel structure that penetrate the first stacked structure, including: Multiple virtual channel holes and a first channel hole are formed that penetrate the first stacked structure; Sacrificial material is filled into the virtual channel hole and the first channel hole to form an initial virtual channel structure and the initial first channel structure, respectively; and Replace the initial virtual channel structure with the virtual channel structure.

9. The method according to claim 8, characterized in that, Replacing the initial virtual channel structure with the virtual channel structure includes: Remove the sacrificial material within the virtual channel hole to form a gap; and A filling medium layer is formed within the gap.

10. The method according to any one of claims 6-9, characterized in that, The first stacked structure includes alternating stacked first dielectric layers and first sacrificial layers, and the second stacked structure includes alternating stacked second dielectric layers and second sacrificial layers, forming the gate gap structure that extends through the second stacked structure and through a portion of the virtual channel structure, including: A gate gap is formed that extends through the second stacked structure and through a portion of the virtual channel structure; The first sacrificial layer and the second sacrificial layer are removed via the gate gap to form a sacrificial gap; A gate layer is formed within the sacrificial gap; and The gate gap structure is formed within the gate gap.

11. The method according to any one of claims 6-9, characterized in that, The method further includes: A top selection gate structure is formed on the surface of the second stacked structure; A top channel structure is formed that extends along the stacking direction through the top selected gate structure and into the channel structure; and An electrical contact structure is formed that connects to the top channel structure.

12. The method according to claim 11, characterized in that, The gate gap structure extends through the top selected gate structure, the second stacked structure, and a portion of the virtual channel structure.

13. A semiconductor structure, characterized in that, include: First layered structure; Multiple support structures penetrate the first stacked structure, wherein the multiple support structures are arranged along a first direction, the first direction being perpendicular to the stacking direction of the first stacked structure; as well as A gate gap structure extends through the first stacked structure and along the first direction, wherein the gate gap structure contacts the support structure.

14. The semiconductor structure according to claim 13, characterized in that, The support structure is located on at least one side of the gate gap structure.

15. The semiconductor structure according to claim 13, characterized in that, The plurality of support structures include a first support structure and a second support structure that are adjacent to each other along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the first support structure and the second support structure are respectively located on both sides of the gate gap structure.

16. The semiconductor structure according to claim 13, characterized in that, The material of the support structure includes oxides.

17. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure also includes: A second stacked structure is located on the surface of the first stacked structure, wherein the gate gap structure penetrates the second stacked structure and the first stacked structure along the stacking direction; and The channel structure extends through the first and second stacked structures and, from the outside in, includes a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer.

18. A storage system, characterized in that, include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as described in any one of claims 13 to 17; as well as A controller, coupled to the semiconductor structure, is used to control the storage of data in the three-dimensional memory.

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