Shift register, gate driving circuit and display device

Abstract

This disclosure provides a shift register, including: a display input reset circuit, an inverting circuit, at least one output circuit, and a first detection circuit. The display input reset circuit, the inverting circuit, and the output circuit are connected to a pull-up node, and the inverting circuit and the output circuit are connected to a pull-down node. The first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line. The first detection circuit is configured to control the acquisition of the voltage at the signal acquisition point in response to a signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line, so that an external first chip can adjust the effective level voltage provided by a third power supply terminal according to the detection voltage. The signal acquisition point includes at least one of a pull-down node and a signal output terminal. Embodiments of this disclosure also provide a gate driving circuit and a display device.

Description

Technical Field

[0001] This invention relates to the field of display, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. The pixel display device of AMOLED is Organic Light-Emitting Diode (OLED). AMOLED emits light by driving thin-film transistors to generate a driving current in a saturated state, which drives the light-emitting device to emit light. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a shift register, comprising: a display input reset circuit, an inverting circuit, at least one output circuit, and a first detection circuit, wherein the display input reset circuit, the inverting circuit, and the output circuit are connected to a pull-up node, and the inverting circuit and the output circuit are connected to a pull-down node;

[0004] The display input reset circuit is connected to the display signal input terminal, the reset signal terminal, and the second power supply terminal. It is configured to write an effective level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal, and to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the reset signal terminal.

[0005] The inverting circuit is connected to the second power supply terminal and the third power supply terminal, and is configured to invert the voltage of the pull-up node in response to the voltage provided by the second power supply terminal and the effective level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node.

[0006] The output circuit is connected to the pull-up node, the pull-down node, the corresponding signal output terminal, the corresponding output clock signal terminal, and the corresponding fourth power supply terminal. It is configured to write the signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node, and to write the voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node.

[0007] The first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line. It is configured to acquire the voltage at the signal acquisition point in response to the signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line, so that an external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal acquisition point includes at least one of the pull-down node and the signal output terminal.

[0008] In some embodiments, the first detection circuit includes at least one of a first detection sub-circuit and a second detection sub-circuit, and the acquisition control terminal includes either a first acquisition control terminal or a second acquisition control terminal.

[0009] The first detection sub-circuit is connected to the pull-down node, the first acquisition control terminal, and the first signal detection line. The first detection sub-circuit is configured to, in response to the control of the signal provided by the first acquisition control terminal, acquire the voltage at the pull-down node and output a first detection voltage corresponding to the voltage at the pull-down node to the first signal detection line.

[0010] The second detection sub-circuit is connected to the signal output terminal, the second acquisition control terminal, and the first signal detection line. The second detection sub-circuit is configured to, in response to the control of the signal provided by the second acquisition control terminal, acquire the voltage at the pull-down node and output a second detection voltage corresponding to the voltage at the signal output terminal to the first signal detection line.

[0011] In some embodiments, the first detection sub-circuit includes: a fifty-first transistor;

[0012] The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

[0013] In some embodiments, the first detection sub-circuit includes: a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor;

[0014] The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

[0015] The control electrode of the fifty-second transistor is connected to the pull-down node, and the first electrode of the fifty-second transistor is connected to the second electrode of the fifty-third transistor and the first electrode of the fifty-fourth transistor;

[0016] The control electrode of the fifty-third transistor is connected to the control terminal of the first switch, and the first electrode of the fifty-third transistor is connected to the control electrode of the fifty-second transistor.

[0017] The control electrode of the fifty-fourth transistor is connected to the control terminal of the second switch, and the second electrode of the fifty-fourth transistor is connected to the power supply terminal of the seventh power supply.

[0018] In some embodiments, the first detection sub-circuit further includes: a fifty-fifth transistor;

[0019] The second terminal of the fifty-second transistor is connected to the first terminal of the fifty-first transistor through the fifty-fifth transistor. The control terminal of the fifty-fifth transistor and the first terminal of the fifty-fifth transistor are both connected to the second terminal of the fifty-second transistor. The second terminal of the fifty-fifth transistor is connected to the first terminal of the fifty-first transistor.

[0020] Alternatively, the second terminal of the fifty-first transistor is connected to the first signal detection line through the fifty-fifth transistor, and both the control terminal and the first terminal of the fifty-fifth transistor are connected to the second terminal of the fifty-first transistor, and the second terminal of the fifty-fifth transistor is connected to the first signal detection line.

[0021] In some embodiments, the number of output circuits is m, the number of second detection sub-circuits is n, the number of second acquisition control terminals is n, the second detection sub-circuits and the second acquisition control terminals correspond one-to-one, and m and n are both positive integers and m≥n;

[0022] Different second detection sub-circuits correspond to different output circuits, and the second detection sub-circuit is connected to the signal output terminal of the corresponding output circuit.

[0023] In some embodiments, the second detection sub-circuit includes: a fifty-sixth transistor;

[0024] The control electrode of the fifty-sixth transistor is connected to the corresponding second acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

[0025] In some embodiments, it further includes: a step-down circuit;

[0026] The first detection circuit is connected to the first signal detection line through the step-down circuit. The step-down circuit is configured to step down the detection voltage output by the first detection circuit and output the step-down detection voltage to the first signal detection line.

[0027] In some embodiments, the step-down circuit includes: a first resistor and a second resistor;

[0028] The first end of the first resistor is connected to the first detection circuit, the second end of the first resistor is connected to the first signal detection line, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the ground terminal.

[0029] In some embodiments, the display input reset circuit includes:

[0030] The display input circuit is connected to the display signal input terminal and the pull-up node, and is configured to write a valid level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal;

[0031] The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the sensing reset signal input terminal.

[0032] The shift register further includes: a first voltage control circuit;

[0033] The first voltage control circuit is connected to the first power supply terminal, the pull-up node, and the first voltage control node. The first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node.

[0034] The shift register further includes at least one of a second leakage protection circuit and a display input leakage protection circuit;

[0035] The display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal.

[0036] The display input circuit is connected to the pull-up node via the display input leakage protection circuit. The display input circuit and the display input leakage protection circuit are connected to the display input leakage protection node. The display input leakage protection node is connected to the first voltage control node. The display input leakage protection node is connected to the display signal input terminal. The display input leakage protection circuit is configured to form a path between the display input leakage protection node and the pull-up node in response to the control of an effective level signal provided by the display signal input terminal, and to disconnect the circuit between the display input leakage protection node and the pull-up node in response to the control of an ineffective level signal provided by the display signal input terminal.

[0037] In some embodiments, the shift register further includes at least one of a pull-up noise reduction circuit and a global reset circuit;

[0038] The pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node, and the pull-down node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the effective level signal at the pull-down node.

[0039] The global reset circuit is connected to the global reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the global reset signal input terminal.

[0040] In some embodiments, it further includes: a first voltage control circuit;

[0041] The first voltage control circuit is connected to the first power supply terminal, the pull-up node, and the first voltage control node. The first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node.

[0042] The shift register circuit further includes at least one of a first leakage protection circuit and a third leakage protection circuit;

[0043] The global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal.

[0044] The pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the pull-down node.

[0045] In some embodiments, it also includes:

[0046] The second detection circuit is connected to the first voltage control node, the third acquisition control terminal, and the second signal detection line. It is configured to acquire the voltage at the first voltage control node in response to the signal provided by the third acquisition control terminal and output a third detection voltage corresponding to the voltage at the first voltage control node to the second signal detection line, so that the external first chip can adjust the voltage provided by the first power supply terminal according to the third detection voltage.

[0047] In some embodiments, the second detection circuit includes: a fifty-seventh transistor;

[0048] The control electrode of the fifty-seventh transistor is connected to the third acquisition control terminal, the first electrode of the fifty-seventh transistor is connected to the first voltage control node, and the second electrode of the fifty-seventh transistor is connected to the second signal detection line.

[0049] In some embodiments, the first signal detection line is multiplexed as the second signal detection line.

[0050] In some embodiments, the inverting circuit includes: a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, and a fortieth transistor;

[0051] The control electrode of the 37th transistor is connected to the third power supply terminal, the first electrode of the 37th transistor is connected to the control electrode of the 37th transistor, and the second electrode of the 37th transistor is connected to the control electrode of the 38th transistor.

[0052] The control terminal of the 38th transistor is connected to the first terminal of the 40th transistor, the first terminal of the 38th transistor is connected to the third power supply terminal, and the second terminal of the 38th transistor is connected to the pull-down node.

[0053] The control terminal of the 39th transistor is connected to the pull-up node, the first terminal of the 39th transistor is connected to the pull-down node, and the second terminal of the 39th transistor is connected to the fifth power supply terminal or the pull-down node.

[0054] The control terminal of the 40th transistor is connected to the pull-up node, and the second terminal of the 40th transistor is connected to the second power supply terminal.

[0055] In some embodiments, the inverting circuit further includes: a forty-first transistor, wherein the second terminal of the thirty-seventh transistor is connected to the control terminal of the thirty-eighth transistor via the forty-first transistor;

[0056] The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

[0057] In some embodiments, the inverting circuit includes: a twelfth transistor and a thirteenth transistor;

[0058] The control electrode of the twelfth transistor is connected to the third power supply terminal, the first electrode of the twelfth transistor is connected to the control electrode of the twelfth transistor, and the second electrode of the twelfth transistor is connected to the pull-down node.

[0059] The control terminal of the thirteenth transistor is connected to the pull-up node, the first terminal of the thirteenth transistor is connected to the pull-down node, and the second terminal of the thirteenth transistor is connected to the second power supply terminal.

[0060] In some embodiments, it also includes:

[0061] A sensing control circuit is connected to the sensing control node, the sensing signal input terminal, and the random signal input terminal. The sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the signal provided by the random signal input terminal.

[0062] The sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node, and the pull-up node. It is configured to write an effective level signal to the sensing intermediate node in response to the control of an effective level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of a signal provided by the clock control signal input terminal.

[0063] In a second aspect, embodiments of this disclosure provide a gate drive circuit, comprising: a plurality of cascaded shift registers, wherein at least one of the shift registers employs the shift registers provided in the first aspect.

[0064] In some embodiments, the cascaded plurality of shift registers includes: a plurality of active shift registers that provide drive signals to gate lines located within the display area and at least one virtual shift register other than the active shift registers;

[0065] At least one of the virtual shift registers employs the shift registers provided in the first aspect.

[0066] Thirdly, embodiments of this disclosure provide a display device, comprising: a display area and a non-display area surrounding the display area, wherein the non-display area is provided with the gate driving circuit as provided in the second aspect.

[0067] In some embodiments, it further includes: a plurality of pixel units arranged in an array and a plurality of signal readout lines, wherein the pixel unit includes: a pixel driving circuit with an external threshold compensation function, and the pixel driving circuit includes: a driving transistor and a sensing switch circuit;

[0068] The sensing switch circuit is connected to the second electrode of the driving transistor and the signal reading line. The sensing switch circuit is configured to read the electrical signal at the second electrode of the driving transistor to the corresponding signal reading line, so that the external second chip can perform external threshold compensation on the driving transistor based on the electrical signal at the second electrode of the driving transistor.

[0069] At least one of the signal readout lines is multiplexed as the first signal detection line.

[0070] In some embodiments, the second chip and the first chip are the same chip.

[0071] In some embodiments, the number of shift registers in the gate drive circuit that are provided with the first detection circuit is 1;

[0072] The signal readout line closest to the gate drive circuit in the display device is multiplexed as the first signal detection line.

[0073] In some embodiments, the first chip is further configured to control the voltage supplied by the third power supply terminal to switch from an effective level voltage to an ineffective level voltage in response to the display device switching to a power-off state.

[0074] In some embodiments, the first chip includes: an analog-to-digital conversion module and a voltage adjustment module;

[0075] The analog-to-digital conversion module is connected to the first signal detection line and is configured to perform analog-to-digital conversion processing on the signal obtained from the first signal detection line to obtain the corresponding digital voltage.

[0076] The voltage adjustment module is connected to the analog-to-digital conversion module and is configured to obtain the effective level voltage to be provided to the third power supply terminal based on a preset adjustment algorithm and the digital voltage provided by the analog-to-digital conversion module.

[0077] In some embodiments, the first chip further includes:

[0078] The power supply module is connected to the voltage adjustment module and is configured to output a corresponding effective voltage level to the third power supply terminal according to the effective voltage level determined by the voltage adjustment module.

[0079] In some embodiments, a switching circuit is provided between the first chip and the first signal detection line.

[0080] In some embodiments, the first signal detection line is further configured with an eleventh capacitor;

[0081] The first terminal of the eleventh capacitor is connected to the first detection line, and the second terminal of the eleventh capacitor is connected to the ground terminal. Attached Figure Description

[0082] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel.

[0083] Figure 2 for Figure 1 The diagram shows a timing sequence of one type of pixel circuit.

[0084] Figure 3 This is a schematic diagram of a circuit structure for a shift register involved in related technologies;

[0085] Figure 4A A schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0086] Figure 4B A schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure;

[0087] Figure 4C A schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure;

[0088] Figure 5 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0089] Figure 6 for Figure 5 The diagram shows a timing diagram of the voltage acquisition process performed by the first detection circuit in the shift register shown.

[0090] Figure 7 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0091] Figure 8 for Figure 7The diagram shows a timing diagram of the voltage acquisition process performed by the first detection circuit in the shift register shown.

[0092] Figure 9A and Figure 9B Two more circuit structure diagrams of the shift register provided in the embodiments of this disclosure;

[0093] Figure 10 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0094] Figure 11 for Figure 10 The diagram shows a timing sequence of the voltage acquisition process performed by the second detection circuit within the shift register.

[0095] Figure 12 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0096] Figure 13 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0097] Figure 14 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0098] Figure 15 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0099] Figure 16A and Figure 16B Two more circuit structure diagrams of the shift register provided in the embodiments of this disclosure;

[0100] Figure 17 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0101] Figure 18 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0102] Figure 19 for Figure 18 The diagram shows a timing diagram of a shift register used for display driving and sensor driving.

[0103] Figure 20 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0104] Figure 21 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0105] Figure 22This is a schematic diagram of a circuit structure for a gate drive circuit in a disclosed embodiment;

[0106] Figure 23 This is a schematic diagram of the structure of a display device in a disclosed embodiment;

[0107] Figure 24 This is a structural block diagram of the first chip in an embodiment of this disclosure. Detailed Implementation

[0108] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register, gate driving circuit and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0109] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0110] The transistors used in this embodiment can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In this embodiment, the coupling methods of the drain and source of each transistor are interchangeable; therefore, the drain and source of each transistor in this embodiment are actually indistinguishable. Here, one of the two terminals of the transistor (excluding the control terminal, i.e., the gate) is called the drain, and the other is called the source, simply to distinguish them. The thin-film transistors used in this embodiment can be N-type transistors or P-type transistors. In this embodiment, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain.

[0111] In this disclosure, "effective voltage level" refers to the voltage that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective voltage level" refers to the voltage that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level voltage is an effective voltage level, and a low-level voltage is an ineffective voltage level; for P-type transistors, a low-level voltage is an effective voltage level, and a high-level voltage is an ineffective voltage level.

[0112] In the following description, an N-type transistor will be used as an example. Here, the effective voltage level refers to a high-level voltage, and the ineffective voltage level refers to a low-level voltage. It is conceivable that when using a P-type transistor, the timing of the control voltage needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0113] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel. Figure 2 for Figure 1 The diagram shows a timing diagram of one possible operation of the pixel circuit. Figure 1 and Figure 2 As shown, for an organic light-emitting diode display panel with external compensation function, a frame can be divided into two stages: the display driving stage and the sensing stage. In the display driving stage, each row of pixel units in the display panel completes the display driving. In the sensing stage, a certain row of pixel units in the display panel completes current extraction (i.e., sensing).

[0114] See Figure 1 As shown, the pixel circuit includes a display switching transistor QTFT (with its control electrode connected to the first gate line G1), a driving transistor DTFT, a sensing switching transistor STFT (with its control electrode connected to the second gate line G2), and a Cst. When external compensation is required for the pixel circuit, the pixel circuit includes at least the following two stages during operation: a display driving stage (including the data voltage writing process) and a sensing driving stage (including the current reading process).

[0115] During the display driving phase, the data voltage Vdata in the data line Data needs to be written to the pixel unit. During the sensing driving phase, a test voltage Vsence needs to be written to the pixel unit via the data line Data, and the electrical signal at the drain of the driving transistor is read to the signal readout line RL via the sensing switch transistor STFT. During the current readout process, an effective level voltage needs to be written to the gate of the sensing switch transistor STFT via the corresponding second gate line G2. It should be noted that external compensation is performed on the pixel units in the OLED display panel; the specific compensation process and principle are not detailed here.

[0116] For the first gate line G1 used to control the display switching transistor QTFT and the second gate line G2 used to control the sensing switching transistor STFT, corresponding gate driving circuits are respectively configured in the peripheral area of ​​the display panel. The gate driving circuit includes multiple cascaded shift register units, which can provide driving signals to the corresponding gate lines.

[0117] Figure 3 This is a schematic diagram of a circuit structure for a shift register involved in related technologies. For example... Figure 3 As shown, the shift register includes a display input reset circuit 1, an inverting circuit 2, and at least one output circuit 5. Figure 1 Only one output circuit 5 is shown as an example. Output circuit 5 includes an output transistor and a pull-down transistor. The control electrode of the output transistor is connected to the pull-up node PU, and the control electrode of the pull-down transistor is connected to the pull-down node PD. The inverter circuit 2 is connected to the second power supply terminal and the third power supply terminal. The inverter circuit 2 is configured to invert the voltage of the pull-up node PU in response to the inactive voltage level provided by the second power supply terminal and the active voltage level provided by the third power supply terminal, and then output the inverted voltage to the pull-down node PD.

[0118] In practical applications, it has been found that the voltage at the pull-down node PD remains at a high level for a much longer period than the total time it is in a high-level state. This means that the voltage at the pull-down node PD remains at a high level for an extended period, which causes a positive shift in the threshold voltage of the pull-down transistor (the threshold voltage gradually increases).

[0119] Furthermore, the high-level voltage at the pull-down node PD is provided by the inverting circuit 2, and this high-level voltage is related to the high-level voltage (effective level voltage) provided by the third power supply terminal connected to the inverting circuit 2. The transistor in the inverting circuit 2 connected to the control electrode and the third power supply terminal will also experience forward drift due to the control electrode being continuously in a high-level state, which will also cause the voltage written by the inverting circuit 2 to the pull-down node PD to gradually decrease.

[0120] Therefore, in the relevant technology, as the usage time increases, the high-level voltage output from the inverter circuit 2 to the pull-down node PD will gradually decrease, while the threshold voltage of the pull-down transistor in the output circuit 5 will gradually increase. There is a risk that the high-level voltage output from the inverter circuit 2 to the pull-down node PD cannot control the pull-down transistor to conduct, resulting in a decrease in the reliability of the shift register.

[0121] To effectively improve at least one of the technical problems existing in the related technologies, embodiments of this disclosure provide a shift register.

[0122] Figure 4A This is a schematic diagram of a circuit structure for a shift register provided in an embodiment of this disclosure. Figure 4B This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. Figure 4C This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. For example... Figures 4A to 4C As shown, the shift register includes: a display input reset circuit 1, an inverting circuit 2, at least one output circuit 5, and a first detection circuit 100. The display input reset circuit 1, the inverting circuit 2, and the output circuit 5 are connected to the pull-up node PU, and the inverting circuit 2 and the output circuit 5 are connected to the pull-down node PD.

[0123] The display input reset circuit 1 is connected to the display signal input terminal INPUT1, the reset signal terminal RST, and the second power supply terminal. The display input reset circuit 1 is configured to write a valid level signal to the pull-up node PU in response to the control of the signal provided by the display signal input terminal INPUT1, and to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the reset signal terminal RST.

[0124] The inverter circuit 2 is connected to the second power supply terminal and the third power supply terminal. The inverter circuit 2 is configured to invert the voltage of the pull-up node PU in response to the inactive level voltage provided by the second power supply terminal and the active level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node PD.

[0125] Output circuit 5 is connected to pull-up node PU, pull-down node PD, corresponding signal output terminal OUT, corresponding output clock signal terminal CLKE, and corresponding fourth power supply terminal. Output circuit 5 is configured to write the signal provided by output clock signal terminal CLKE to corresponding signal output terminal OUT in response to voltage control at pull-up node PU, and to write the voltage provided by corresponding fourth power supply terminal to corresponding signal output terminal OUT in response to voltage control at pull-up node PU.

[0126] The first detection circuit 100 is connected to the signal acquisition point, the acquisition control terminal, and the first signal detection line SGD. The first detection circuit 100 is configured to control the acquisition of the voltage at the signal acquisition point in response to the signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line SGD, so that the external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal acquisition point includes at least one of the pull-down node PD and the signal output terminal OUT.

[0127] In this embodiment, the effective voltage level actually output by the inverting circuit 2 to the pull-down node PD can reflect the threshold voltage drift of the transistor connected to the control electrode and the third power supply in the inverting circuit 2. When the voltage at the pull-up node PU is an effective voltage level and the fourth power supply provides an effective voltage level, the voltage output by the signal output terminal OUT can reflect the overall threshold voltage drift of the transistor connected to the control electrode and the third power supply in the inverting circuit 2 and the pull-down transistor in the output circuit 5.

[0128] Therefore, in this disclosure, by setting a first detection circuit 100 to detect the effective voltage level at at least one of the pull-down node PD and the signal output terminal OUT, and outputting a corresponding detection voltage, the external first chip connected to the first signal detection line SGD can adjust (increase) the effective voltage level provided by the third power supply terminal according to the detection voltage, so that the effective voltage level output by the inverting circuit 2 to the pull-down node PD is always higher than the threshold voltage of the pull-down transistor, thereby ensuring that the pull-down transistor can always be in the conducting state when the inverting circuit 2 outputs an effective voltage level to the pull-down node PD, thereby improving the reliability of the shift register.

[0129] In some embodiments, the first detection circuit 100 includes at least one of a first detection sub-circuit 100a and a second detection sub-circuit 100b, and the acquisition control terminal includes either a first acquisition control terminal CL1 or a second acquisition control terminal CL2.

[0130] The first detection sub-circuit 100a is connected to the pull-down node PD, the first acquisition control terminal CL1, and the first signal detection line SGD. The first detection sub-circuit 100a is configured to acquire the voltage at the pull-down node PD in response to the control of the signal provided by the first acquisition control terminal CL1 and output a first detection voltage corresponding to the voltage at the pull-down node PD to the first signal detection line SGD.

[0131] The second detection sub-circuit 100b is connected to the signal output terminal OUT, the second acquisition control terminal CL2, and the first signal detection line SGD. The second detection sub-circuit 100b is configured to, in response to the control of the signal provided by the second acquisition control terminal CL2, acquire the voltage at the pull-down node PD and output a second detection voltage corresponding to the voltage at the signal output terminal OUT to the first signal detection line SGD.

[0132] in, Figure 4A An example is given where the first detection circuit 100 includes only the first detection sub-circuit 100a. Figure 4B An example is given where the first detection circuit 100 includes only the second detection sub-circuit 100b. Figure 4C An example is given where the first detection circuit 100 includes both a first detection sub-circuit 100a and a second detection sub-circuit 100b.

[0133] In this disclosure, the process of detecting the effective voltage level at the pull-down node PD using the first detection sub-circuit 100a is as follows: An effective voltage level signal is provided to the reset signal terminal RST, causing the display input reset circuit 1 to write the ineffective voltage level provided by the second power supply terminal to the pull-up node PU. At this time, under the action of the inverting circuit 2, the inverting circuit 2 pulls down the pull-down node PD and outputs an effective voltage level based on the effective voltage level provided by the third power supply terminal. Simultaneously, an effective voltage level signal is provided to the first acquisition control terminal CL1, causing the first detection sub-circuit 100a to acquire the effective voltage level at the pull-down node PD and output a first detection voltage corresponding to the voltage at the pull-down node PD to the first signal detection line SGD. In this embodiment, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD can be equal to or unequal to the effective voltage level at the pull-down node PD (in the case of unequal voltage levels, it is only necessary to ensure that the two satisfy a certain preset relationship). This will be described in detail below.

[0134] In this disclosure, the process of detecting the effective voltage level at the pull-down node PD using the second detection sub-circuit 100b is as follows: An effective voltage level signal is provided to the reset signal terminal RST, causing the display input reset circuit 1 to write the ineffective voltage level provided by the second power supply terminal to the pull-up node PU. At this time, under the action of the inverting circuit 2, the inverting circuit 2 pulls down the node PD to output an effective voltage level based on the effective voltage level provided by the third power supply terminal. Simultaneously, an effective voltage level signal is provided to the first acquisition control terminal CL1, and an effective voltage level is provided to the fourth power supply terminal corresponding to the output circuit 5 connected to the second detection sub-circuit 100b. This allows the second detection sub-circuit 100b to acquire the effective voltage level at the connected signal output terminal OUT and output a second detection voltage to the first signal detection line SGD corresponding to the effective voltage level at the signal output terminal OUT. In this embodiment, the second detection voltage output by the second detection sub-circuit 100b to the first signal detection line SGD can be equal to or unequal to the effective voltage level at the signal output terminal OUT (in the case of unequal voltage, it is sufficient to ensure that the two satisfy a certain preset relationship). This will be described in detail below.

[0135] Figure 5 This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. Figure 6 for Figure 5 The diagram shows a timing sequence of the voltage acquisition process performed by the first detection circuit 100 within the shift register. Figure 5 and Figure 6 As shown, this shift register is based on Figure 4AA specific alternative implementation of the shift register shown is provided. In some embodiments, the display input reset circuit 1 includes a ninth transistor M9 and a tenth transistor M10, the inverter circuit 2 includes a twelfth transistor M12 and a thirteenth transistor M13, and the output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17, wherein a first capacitor C1 may also be included in a portion of the output circuit 5.

[0136] Among them, the control electrode and the first electrode of the ninth transistor M9 are both connected to the display signal input terminal INPUT1, and the second electrode of the ninth transistor M9 is connected to the pull-up node PU.

[0137] The control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the pull-up node PU, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal.

[0138] The control electrode of the twelfth transistor M12 is connected to the third power supply terminal, the first electrode of the twelfth transistor M12 is connected to the control electrode of the twelfth transistor M12, and the second electrode of the twelfth transistor M12 is connected to the pull-down node PD.

[0139] The control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, the first electrode of the thirteenth transistor M13 is connected to the pull-down node PD, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

[0140] The control electrode of the fifth transistor M5 is connected to the pull-up node PU, the first electrode of the fifth transistor M5 is connected to the corresponding output clock signal terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the corresponding signal output terminal OUT.

[0141] The control electrode of the seventeenth transistor M17 is connected to the pull-down node PD, the first electrode of the seventeenth transistor M17 is connected to the corresponding signal output terminal OUT, and the second electrode of the seventeenth transistor M17 is connected to the corresponding fourth power supply terminal.

[0142] The first terminal of the first capacitor C1 is connected to the pull-up node PU, and the second terminal of the first capacitor C1 is connected to the corresponding signal output terminal OUT.

[0143] It should be noted that the specific circuit structures of the display input reset circuit 1, the inverter circuit 2, and the output circuit 5 exemplified above are only one optional implementation scheme in this disclosure, and they do not limit the technical solution of this disclosure.

[0144] In some embodiments, the first detection sub-circuit 100a includes: a fifty-first transistor M51; the control electrode of the fifty-first transistor M51 is connected to the first acquisition control terminal CL1, the first electrode of the fifty-first transistor M51 is connected to the pull-down node PD, and the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0145] The following will describe in detail the detection process of the first detection sub-circuit 100a and the principle of adjusting the effective level voltage output by the third power supply terminal based on the first detection voltage in the first signal detection line SGD, using specific examples.

[0146] Among them, the second power supply terminal provides a low-level voltage V2, the third power supply terminal provides a high-level voltage V3, and the fourth power supply terminal provides a high-level voltage V4, and the high-level voltage V4 is greater than or equal to the high-level voltage V3.

[0147] See Figure 6 As shown, the first acquisition period (the period during which the gate drive circuit does not need to drive the display device, such as the blanking period between two adjacent frames after the display device is powered on) includes: a first sub-stage d1 and a second sub-stage d2.

[0148] In the first sub-stage d1, the display reset signal input terminal RST provides a high-level signal, and the first acquisition control terminal CL1 provides a low-level signal. The tenth transistor M10 is turned on, and the fifty-first transistor M51 is turned off. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, putting PU in a low-level state. Correspondingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD through the twelfth transistor M12. At this time, the actual voltage written to the pull-down node PD is V3 - Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 during the first acquisition period. Correspondingly, the seventeenth transistor M17 is turned on, and the fourth power supply terminal charges the signal output terminal OUT. When the voltage at the signal output terminal OUT is charged to V3 - Vth_M12 - Vth_M17, the gate-source voltage of the seventeenth transistor M17 is equal to the current threshold voltage Vth_M17 of the seventeenth transistor M17, and the seventeenth transistor M17 switches to the off state.

[0149] In the second sub-stage d2, the first acquisition control terminal CL1 provides a high-level signal, the fifty-first transistor M51 is turned on, and the voltage at the pull-down node PD is written to the first signal detection line SGD through the fifty-first transistor M51. That is, the first detection voltage Vdtc11 = V3 - Vth_M12 is acquired through the first signal detection line SGD.

[0150] After a period of time (which can be preset according to actual conditions), the second acquisition period begins (the period when the gate drive circuit does not need to drive the display device, such as the blanking period between two adjacent frames after the display device is powered on). The second acquisition period also includes two sub-stages: the first sub-stage d1 and the second sub-stage d2. The specific process is the same as that of the first acquisition period, and will not be repeated here. In the second sub-stage d2 of the second acquisition period, the first detection voltage Vdtc12 = V3 - Vth_M12' acquired on the first signal detection line SGD, where Vth_M12' is the threshold voltage of the twelfth transistor M12 in the second acquisition period. Generally, the threshold voltage of the twelfth transistor M12 will drift positively under the action of the high-level voltage V3, that is, Vth_M12' > Vth_M12.

[0151] In this embodiment, the external first chip compares the first detection voltage Vdtc11 acquired during the first acquisition period with the first detection voltage Vdtc12 acquired during the second acquisition period to obtain the threshold voltage drift of the twelfth transistor M12. For example, by subtracting the two first detection voltages, Vdtc11-Vdtc12, the drift amount ΔVth_M12 of the threshold voltage of the twelfth transistor M12 from the first acquisition period to the second acquisition period can be obtained, where ΔVth_M12 = Vth_M12' - Vth_M12 = Vdtc11 - Vdtc12.

[0152] At this point, the effective voltage level provided by the third power supply terminal can be adjusted according to the threshold voltage drift of the twelfth transistor M12.

[0153] As an example, the effective voltage level V3' provided by the adjusted third power supply terminal is:

[0154] V3'=V3+2*△Vth_M12=V3+2*(Vdtc11-Vdtc12)

[0155] In practical applications, it was found that the threshold voltage drift of the seventeenth transistor M17 is basically the same as that of the twelfth transistor M12. That is, the drift amount ΔVth_M12 of the threshold voltage of the twelfth transistor M12 from the first acquisition period to the second acquisition period is equal to or approximately equal to the drift amount ΔVth_M17 of the threshold voltage of the seventeenth transistor M17 from the first acquisition period to the second acquisition period. Here, the threshold voltage of the seventeenth transistor M17 in the first acquisition period is denoted as Vth_M17, and the threshold voltage of the seventeenth transistor M17 in the second acquisition period is denoted as Vth_M17'. ΔVth_M17 = Vth_M17' - Vth_M17 ≈ ΔVth_M12.

[0156] During the first acquisition period, the difference between the control voltage (voltage at the pull-down node PD) of the seventeenth transistor M17 and its threshold voltage is V3 - Vth_M12 - Vth_M17. After the threshold voltage of the twelfth transistor M12 drifts to Vth_M12' and the threshold voltage of the seventeenth transistor M17 drifts to Vth_M17', in order to ensure that the seventeenth transistor M17 can still conduct normally, the effective level voltage provided by the third power supply terminal can be adjusted to V3', so that the difference between the control voltage (i.e., V3' - Vth_M12') and the threshold voltage (Vth_M17') of the seventeenth transistor M17 remains at V3 - Vth_M12 - Vth_M17.

[0157] That is, V3'-Vth_M12'-Vth_M17'=V3-Vth_M12-Vth_M17

[0158] At this point, V3' = V3 + (Vth_M12' - Vth_M12) + (Vth_M17' - Vth_M17) = V3 + △Vth_M12 + △Vth_M17;

[0159] Furthermore, since △Vth_M17≈△Vth_M12;

[0160] Therefore, V3'≈V3+2*△Vth_M12;

[0161] Furthermore, since △Vth_M12=Vdtc11-Vdtc12;

[0162] Therefore, V3'≈V3+2*(Vdtc11-Vdtc12);

[0163] Therefore, in this embodiment of the present disclosure, when adjusting the effective voltage level provided by the third power supply terminal based on the first detection voltage, the adjusted effective voltage level provided by the third power supply terminal can be adjusted to V3+2*(Vdtc11-Vdtc12).

[0164] Of course, the above adjustment method is only one optional implementation scheme in this disclosure, and it will not limit the technical solution of this disclosure. In practical applications, the corresponding adjustment algorithm can be set according to the actual needs based on the first detection voltage. In addition, in the above example, only the case where the first detection voltage is the same as the voltage at the pull-down node PD is given as an example.

[0165] Figure 7 This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. Figure 8 for Figure 7 The diagram shows a timing sequence of the voltage acquisition process performed by the first detection circuit within the shift register. Figure 7 and Figure 8 As shown, with Figure 5 The first detection sub-circuit 100a shown here differs from the one that only includes the fifty-first transistor M51. Figure 7 The first detection sub-circuit 100a shown includes a fifty-first transistor M51, a fifty-second transistor M52, a fifty-third transistor M53, and a fifty-fourth transistor M54.

[0166] Among them, the control electrode of the fifty-first transistor M51 is connected to the first acquisition control terminal CL1, the first electrode of the fifty-first transistor M51 is connected to the second electrode of the fifty-second transistor M52, and the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0167] The control electrode of transistor M52 is connected to the pull-down node PD, and the first electrode of transistor M52 is connected to the second electrode of transistor M53 and the first electrode of transistor M54.

[0168] The control electrode of the fifty-third transistor M53 is connected to the first switch control terminal J1, and the first electrode of the fifty-third transistor M53 is connected to the control electrode of the fifty-second transistor M52.

[0169] The control electrode of the 54th transistor M54 is connected to the second switch control terminal J2, and the second electrode of the 54th transistor M54 is connected to the seventh power supply terminal.

[0170] The seventh power supply terminal provides a low-level voltage V7. As an example, this low-level voltage V7 can be equal to the low-level voltage V2 provided by the second power supply terminal.

[0171] See Figure 8As shown, the period between the first acquisition period and the second acquisition period is a non-acquisition period (the gate drive circuit can drive the display device normally). Both the first acquisition period and the second acquisition period include: a first sub-stage d1 and a second sub-stage d2.

[0172] In the first sub-stage d1 of the first acquisition period, the display reset signal input terminal RST provides a high-level signal, the first acquisition control terminal CL1 provides a low-level signal, the first switch control terminal J1 provides a low-level signal, and the second switch control terminal J2 provides a high-level signal. At this time, the tenth transistor M10 is turned on, the fifty-first transistor M51 is turned off, the fifty-third transistor M53 is turned off, and the fifty-fourth transistor M54 is turned on. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, and the pull-up node PU is in a low-level state; correspondingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD through the twelfth transistor M12. At this time, the actual voltage written to the pull-down node PD is V3-Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 in the first acquisition period.

[0173] In the second sub-stage d2 of the first acquisition period, the first acquisition control terminal CL1 provides a high-level signal, the first switch control terminal J1 provides a high-level signal, and the second switch control terminal J2 provides a low-level signal. At this time, the fifty-first transistor M51 and the fifty-third transistor M53 are turned on, and the fifty-fourth transistor M54 is turned off.

[0174] Because the 53rd transistor M53 is turned on, the voltage at the pull-up node PU charges the first terminal of the 51st transistor through the 52nd transistor M52. When the voltage at the first terminal of the 51st transistor M51 is charged to V3 - Vth_M12 - Vth_M52, the gate-source voltage of the 52nd transistor M52 equals the current threshold voltage Vth_M52 of the 52nd transistor M52, and the 52nd transistor M52 switches to the off state. At this time, because the 51st transistor M51 is turned on, the first detection voltage Vdtc11 output to the first signal detection line SGD is V3 - Vth_M12 - Vth_M52.

[0175] During non-acquisition periods, the first acquisition control terminal CL1 provides a low-level signal, the first switch control terminal J1 provides a low-level signal, and the second switch control terminal J2 provides a high-level signal. That is, transistors M51 (51) and M53 (53) are both off, while transistor M54 (54) is on. This design ensures that during non-acquisition periods, the stress on transistor M52 is the same as that on transistor M17 in output circuit 5. In other words, the threshold voltage drift of transistor M52 is the same as that of transistor M17.

[0176] After the non-acquisition period ends, the second acquisition period begins. The specific working process is the same as that of the first acquisition period, and will not be repeated here. During the second acquisition period, the first detection sub-circuit 100a outputs the first detection voltage Vdtc12 = V3 - Vth_M12' - Vth_M52' to the first signal detection line SGD.

[0177] In this embodiment, the external first chip compares the first detection voltage Vdtc11 acquired during the first acquisition period with the first detection voltage Vdtc12 acquired during the second acquisition period to obtain the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the fifty-second transistor M52. For example, by subtracting the two first detection voltages Vdtc11-Vdtc12, the overall drift amount ΔVth_M12+ΔVth_M52 of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the fifty-second transistor M52 during the first acquisition period to the second acquisition period (i.e., the corresponding non-acquisition period) can be obtained.

[0178] ΔVth_M12+ΔVth_M52=(Vth_M12'-Vth_M12)+(Vth_M52'-Vth_M52)=Vdtc11-Vdtc12.

[0179] Since the threshold voltage drift ΔVth_M52 of the fifty-second transistor M52 is the same as that of the threshold voltage drift ΔVth_M17 of the seventeenth transistor M17, therefore ΔVth_M12 + ΔVth_M17 = Vdtc11 - Vdtc12.

[0180] During the first acquisition period, the difference between the control voltage (voltage at the pull-down node PD) of the seventeenth transistor M17 and its threshold voltage is V3 - Vth_M12 - Vth_M17. After the threshold voltage of the twelfth transistor M12 drifts to Vth_M12' and the threshold voltage of the seventeenth transistor M17 drifts to Vth_M17', in order to ensure that the seventeenth transistor M17 can still conduct normally, the effective level voltage provided by the third power supply terminal can be adjusted to V3', so that the difference between the control voltage (i.e., V3' - Vth_M12') and the threshold voltage (Vth_M17') of the seventeenth transistor M17 remains at V3 - Vth_M12 - Vth_M17.

[0181] That is, V3'-Vth_M12'-Vth_M17'=V3-Vth_M12-Vth_M17;

[0182] At this point, V3' = V3 + (Vth_M12' - Vth_M12) + (Vth_M17' - Vth_M17) = V3 + △Vth_M12 + △Vth_M17;

[0183] And because △Vth_M12+△Vth_M17=Vdtc11-Vdtc12;

[0184] Therefore, V3'=V3+(Vdtc11-Vdtc12).

[0185] Therefore, in this embodiment of the present disclosure, when adjusting the effective voltage level provided by the third power supply terminal based on the first detection voltage, the adjusted effective voltage level provided by the third power supply terminal can be adjusted to V3+(Vdtc11-Vdtc12).

[0186] In this embodiment, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD is different from the voltage at the pull-down node PD. Furthermore, the adjustment algorithm used in this embodiment to adjust the effective level voltage output by the third power supply terminal based on the first detection voltage is also different from that in previous embodiments.

[0187] Figure 9A and Figure 9B Two more circuit structure diagrams of the shift register provided in the embodiments of this disclosure are shown. Figure 9A and Figure 9B For based on Figure 7 A further improvement to the shift register shown, wherein the first detection sub-circuit 100a includes not only Figure 7 The 51st transistor M51 to the 54th transistor M54 shown in the figure also include the 55th transistor M55.

[0188] See Figure 9A As shown, as an example, the second terminal of the fifty-second transistor M52 is connected to the first terminal of the fifty-first transistor M51 through the fifty-fifth transistor M55. The control terminal and the first terminal of the fifty-fifth transistor M55 are both connected to the second terminal of the fifty-second transistor M52, and the second terminal of the fifty-fifth transistor M55 is connected to the first terminal of the fifty-first transistor M51.

[0189] See Figure 9B As shown, as an example, the second terminal of the fifty-first transistor M51 is connected to the first signal detection line SGD through the fifty-fifth transistor M55. The control terminal and the first terminal of the fifty-fifth transistor M55 are both connected to the second terminal of the fifty-first transistor M51, and the second terminal of the fifty-fifth transistor M55 is connected to the first signal detection line SGD.

[0190] for Figure 9A and Figure 9B The timing sequence for the voltage acquisition process of the first detection circuit 100 in the shift register shown can be adopted as described above. Figure 8 As shown, the specific working process can be described in the corresponding content of the previous embodiments, and will not be repeated here.

[0191] exist Figure 9A and Figure 9B In this circuit, by using the aforementioned diode-connected 55th transistor M55, the voltage value of the first detection voltage output from the first detection sub-circuit 100a to the first signal detection line SGD can be effectively reduced. Specifically, during the first acquisition period, the first detection voltage value Vdtc11 output by the first detection circuit 100 is V3 - Vth_M12 - Vth_M52 - Vth_M55; during the second acquisition period, the first detection voltage value Vdtc12 output by the first detection circuit 100 is V3 - Vth_M12' - Vth_M52' - Vth_M55. Here, Vth_M55 is the threshold voltage of the 55th transistor M55.

[0192] In practical applications, the first chip connected to the first signal detection line SGD often has certain requirements regarding the voltage value of the input signal, such as requiring the input signal voltage value to be less than or equal to 6V. However, the effective voltage level provided by the third power supply terminal is generally around 12V. In this case, there is a risk that the voltage output by the first detection sub-circuit 100a to the first signal detection line SGD will be greater than 6V, which may cause the first chip connected to the first signal detection line SGD to malfunction. By setting the aforementioned fifty-fifth transistor M55 and pre-designing the threshold voltage of the fifty-fifth transistor M55, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD can be controlled to always be less than 6V.

[0193] In addition, the configuration of the aforementioned fifty-fifth transistor M55 can effectively prevent the signal in the first signal detection line SGD from reverse charging the first detection sub-circuit 100a, which is beneficial to improving the service life of the transistors in the first detection sub-circuit 100a.

[0194] Figure 10 This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. Figure 11 for Figure 10The diagram shows a timing diagram of the voltage acquisition process of the second detection circuit in the shift register. In some embodiments, the second detection sub-circuit 100b includes: a fifty-sixth transistor M56; the control terminal of the fifty-sixth transistor M56 is connected to the corresponding second acquisition control terminal CL2, the first terminal of the fifty-first transistor M51 is connected to the pull-down node PD, and the second terminal of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0195] In this embodiment, the voltage V4 provided by the fourth power supply terminal connected to the output circuit 5 corresponding to the second detection circuit 200 is a high-level voltage, and the high-level voltage V4 ≥ the high-level voltage V3.

[0196] join Figure 11 As shown, the first acquisition period includes: a first sub-stage d1 and a second sub-stage d2. In the first sub-stage d1, the display reset signal input terminal RST provides a high-level signal, and the second acquisition control terminal CL2 provides a low-level signal. The tenth transistor M10 is turned on, and the fifty-first transistor M51 is turned off. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, and the pull-up node PU is in a low-level state; correspondingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD through the twelfth transistor M12. At this time, the actual voltage written to the pull-down node PD is V3 - Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 in the first acquisition period. Correspondingly, the seventeenth transistor M17 is turned on, and the fourth power supply terminal charges the signal output terminal OUT. When the voltage at the signal output terminal OUT is charged to V3-Vth_M12-Vth_M17, the gate-source voltage of the seventeenth transistor M17 is equal to the current threshold voltage Vth_M17 of the seventeenth transistor M17, and the seventeenth transistor M17 switches to the off state.

[0197] In the second sub-stage d2, the second acquisition control terminal CL2 provides a high-level signal, the fifty-sixth transistor M56 is turned on, and the voltage at the signal output terminal OUT is written to the first signal detection line SGD through the fifty-sixth transistor M56. That is, the second detection voltage Vdtc21 acquired through the first signal detection line SGD is V3-Vth_M12-Vth_M17.

[0198] After a certain period of time (which can be preset according to actual conditions), the second acquisition period begins. The second acquisition period also includes two sub-stages: the first sub-stage d1 and the second sub-stage d2. The specific process is the same as that of the first acquisition period, and will not be repeated here. In the second sub-stage d2 of the second acquisition period, the first detection voltage Vdtc22 = V3 - Vth_M12' - Vth_M17' is acquired on the first signal detection line SGD.

[0199] In this embodiment, the external first chip compares the second detection voltage Vdtc21 acquired during the first acquisition period with the second detection voltage Vdtc22 acquired during the second acquisition period to obtain the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the seventeenth transistor M17. For example, by subtracting the two second detection voltages Vdtc21-Vdtc22, the overall drift amount ΔVth_M12+ΔVth_M17 of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the seventeenth transistor M17 during the first acquisition period to the second acquisition period (i.e., the corresponding non-acquisition period) can be obtained.

[0200] With the previous Figure 8 The voltage adjustment scheme corresponding to the shift register shown is similar. In this embodiment, when adjusting the effective voltage level provided by the third power supply terminal based on the second detection voltage, the adjusted effective voltage level V3' provided by the third power supply terminal can be adjusted to V3 + (Vdtc21 - Vdtc22). For the specific adjustment principle, please refer to the corresponding content above, which will not be repeated here.

[0201] In some embodiments, the number of output circuits 5 is m, the number of second detection sub-circuits 100b is n, and the number of second acquisition control terminals CL2 is n. Each second detection sub-circuit 100b corresponds one-to-one with a second acquisition control terminal CL2, where m and n are both positive integers and m ≥ n. Different second detection sub-circuits 100b correspond to different output circuits 5, and each second detection sub-circuit 100b is connected to the signal output terminal OUT of its corresponding output circuit 5. A detailed description will follow with examples.

[0202] Figure 12 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 12 As shown, in some embodiments, the shift register includes multiple output circuits 5, which generally include one cascade output circuit 5 and at least one driving output circuit 5 (four driving output circuits 5 are illustrated in the figures). The signal output terminal of the cascade output circuit 5 is a cascade signal output terminal COUT, which is connected to other shift registers but not to the gate lines located in the display area. The signal output from the cascade signal output terminal COUT is used for cascading between shift registers. The signal output terminal of the driving output circuit 5 is a driving signal output terminal GOUT, which is connected to the corresponding gate line located in the display area but not to other shift registers. The signal output from the driving signal output terminal GOUT is used to drive the corresponding gate line.

[0203] The output clock signal terminal of the cascaded output circuit 5 is the cascaded output clock signal terminal CLKD, and the output clock signal terminals of the drive output circuit 5 are the drive output clock signal terminals CLKE1 to CLKE4. The cascaded output circuit 5 may or may not include the first capacitor C1.

[0204] Figure 12 The example diagram illustrates a shift register containing a second detection sub-circuit 100b, which is connected to the cascade signal output terminal COUT of the cascaded output circuit 5.

[0205] Of course, in some embodiments, the second detection sub-circuit 100b may also be selectively connected to the drive signal output terminal OUT of the drive output circuit 5.

[0206] Figure 13 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 13 As shown, with Figure 12 Unlike the diagram showing only one second detection sub-circuit 100b, in Figure 13 The illustrated embodiment shows a plurality of second detection sub-circuits 100b that correspond one-to-one with the output circuit 5.

[0207] Figure 13 The shift register shown includes a first sub-stage and a second sub-stage within a single acquisition period. A description of the first sub-stage can be found in the previous section. Figure 11 The content related to the first sub-stage is described below; only the second sub-stage will be described in detail below.

[0208] Specifically, in the second sub-stage, high-level signals are sequentially provided to each of the second acquisition control terminals CL2 to control the fifty-sixth transistor M56 in each of the second detection sub-circuits 100b to be turned on sequentially, thereby enabling each of the second detection sub-circuits 100b to sequentially write the corresponding second detection voltage to the first signal detection line SGD.

[0209] In practical applications, the threshold voltage drift of the seventeenth transistor M17 located in different output circuits 5 may differ. Therefore, multiple second detection sub-circuits 100b can be used to collect the signals output from the signal output terminal OUT of different output circuits 5, thereby obtaining the overall drift of the threshold voltage of the seventeenth transistor M17 and the threshold voltage of the twelfth transistor M12 in different output circuits 5. Then, based on the second detection voltage output by each second detection sub-circuit 100b, the adjustment scheme for the effective level voltage provided to the third power supply terminal can be determined.

[0210] As an example, the average value of multiple second detection voltages collected by multiple second detection sub-circuits 100b during the first acquisition period is calculated, and the average value of multiple second detection voltages collected by multiple second detection sub-circuits 100b during the second acquisition period is calculated. Then, the effective level voltage provided by the third power supply terminal is adjusted based on the two average values.

[0211] Those skilled in the art should know that when there are multiple output circuits 5, the number of second detection sub-circuits 100b set in the shift register can be one or more, as long as the number of second detection sub-circuits 100b is less than or equal to the number of output circuits 5.

[0212] Figure 14 This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. Figure 14 In the scheme shown, the detection circuit includes not only the first detection sub-circuit 100a, but also the second detection sub-circuit 100b, which can sequentially provide high-level signals to the first acquisition control terminal CL1 and each of the second acquisition control terminals CL2 to control the first detection sub-circuit 100a and each of the second detection sub-circuit 100b to sequentially provide detection voltage to the first signal detection line SGD.

[0213] The first detection voltage output by the first detection sub-circuit 100a reflects the threshold voltage drift of the transistor connected to the control electrode and the third power supply terminal in the inverting circuit 2 (e.g., the twelfth transistor M12 in the figure). The second detection voltage output by the second detection sub-circuit 100b reflects the overall threshold voltage drift of the transistor connected to the control electrode and the third power supply terminal in the inverting circuit 2 and the pull-down transistor in the output circuit 5 (e.g., the seventeenth transistor M17 in the figure). Therefore, based on the difference between the second detection voltage and the first detection voltage, the threshold voltage drift of the corresponding pull-down transistor in the output circuit 5 can be reflected. That is, when the first detection sub-circuit 100a and the second detection sub-circuit 100b are set simultaneously, the threshold voltage drift of the transistor connected to the control electrode and the third power supply terminal in the inverting circuit 2 and the threshold voltage drift of the pull-down transistor in the output circuit 5 can be obtained respectively. This allows for precise control of the threshold voltage drift of the pull-down transistor, facilitating precise adjustment of the voltage supplied to each terminal of the pull-down transistor according to actual needs.

[0214] Figure 15 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 15 As shown, Figure 15The shift register shown not only includes a first detection circuit 100, but also has a step-down circuit 6 between the first detection circuit 100 and the step-down circuit 6. The step-down circuit 6 is configured to step down the detection voltage output by the first detection circuit 100 and output the step-down detection voltage to the first signal detection line SGD.

[0215] Similar to the step-down function of the 55th transistor M55 set in the previous embodiment, in this embodiment of the disclosure, by setting the step-down voltage, the voltage range of the first detection circuit 100 output to the first signal detection line SGD can be effectively controlled, so as to avoid the situation where the output voltage of the first detection circuit 100 is too large, causing the external first chip to be unable to read it.

[0216] In practical applications, considering that the threshold voltage of the 55th transistor M55 (generally less than 3V) is not usually too large, the voltage reduction of the 55th transistor M55 is limited. Therefore, the above-mentioned step-down circuit 6 can be added in this disclosure.

[0217] In some embodiments, the step-down circuit 6 includes: a first resistor R1 and a second resistor R2; a first end of the first resistor R1 is connected to the first detection circuit 100, a second end of the first resistor R1 is connected to the first signal detection line SGD, a first end of the second resistor R2 is connected to the second end of the first resistor R1, and a second end of the second resistor R2 is connected to the ground terminal. Step-down can be achieved through the principle of resistor voltage division.

[0218] for Figure 15 For a detailed description of the first detection circuit 100, please refer to the content in the previous embodiments, which will not be repeated here.

[0219] Figure 16A and Figure 16B Two more circuit structure diagrams of the shift register provided in the embodiments of this disclosure are shown. Figure 16A and Figure 16B As shown, the circuit structure of the inverting circuit 2 shown in the previous embodiment, which includes the twelfth transistor M12 and the thirteenth transistor M13, is different. Figure 16A and Figure 16B The inverting circuit 2 in the shift register shown includes the thirty-seventh transistor M37, the thirty-eighth transistor M38, the thirty-ninth transistor M39, and the fortieth transistor M40.

[0220] The control electrode of the thirty-seventh transistor M37 is connected to the third power supply terminal, the first electrode of the thirty-seventh transistor M37 is connected to the control electrode of the thirty-seventh transistor M37, and the second electrode of the thirty-seventh transistor M37 is connected to the control electrode of the thirty-eighth transistor M38.

[0221] The control terminal of the thirty-eighth transistor M38 is connected to the first terminal of the fortieth transistor M40. The first terminal of the thirty-eighth transistor M38 is connected to the third power supply terminal. The second terminal of the thirty-eighth transistor M38 is connected to the pull-down node PD.

[0222] The control terminal of the 39th transistor M39 is connected to the pull-up node PU, the first terminal of the 39th transistor M39 is connected to the pull-down node PD, and the second terminal of the 39th transistor M39 is connected to the fifth power supply terminal. Figure 16A (as shown) or dropdown node PD ( Figure 16B (As shown in the diagram) connection.

[0223] The control electrode of the 40th transistor M40 is connected to the pull-up node PU, and the second electrode of the 40th transistor M40 is connected to the second power supply terminal.

[0224] When the inverter circuit 2 is as shown in Figure 16, the high-level voltage output by the inverter circuit 2 to the pull-up node PU is V3-Vth_M38, where Vth_M38 is the threshold voltage of the thirty-eighth transistor M38. The function of the thirty-eighth transistor M38 is similar to that of the twelfth transistor M12 in the previous embodiment, and will not be described again here.

[0225] In some embodiments, the inverter circuit 2 further includes: a forty-first transistor M41, wherein the second terminal of the thirty-seventh transistor M37 is connected to the control terminal of the thirty-eighth transistor M38 through the forty-first transistor M41;

[0226] The control electrode of the forty-first transistor M41 is connected to the control electrode of the thirty-seventh transistor M37, the first electrode of the forty-first transistor M41 is connected to the second electrode of the thirty-seventh transistor M37, and the second electrode of the forty-first transistor M41 is connected to the control electrode of the thirty-eighth transistor M38.

[0227] In practical applications, it has been found that when the 40th transistor M40 is in the off state and the 37th transistor M37 is in the on state, there will be a charging current with a short duration but a large current value between the control electrode of the 38th transistor M38 and the effective level supply terminal (used to charge the control electrode of the 38th transistor M38). This charging current can easily damage the 37th transistor M37, for example, by breaking it down.

[0228] To improve the above problems, in this embodiment of the present disclosure, a forty-first transistor M41 is provided between the second electrode of the thirty-seventh transistor M37 and the control electrode of the thirty-eighth transistor M38. The provision of the forty-first transistor M41 can effectively reduce the charging current between the control electrode of the thirty-eighth transistor M38 and the effective level supply terminal, so as to avoid the charging current from breaking down the thirty-seventh transistor M37.

[0229] Figure 17 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 17 As shown, in some embodiments, the display input reset circuit 1 includes a display input circuit 1a and a display reset circuit 1b.

[0230] The display input circuit 1a is connected to the display signal input terminal INPUT1 and the pull-up node PU. The display input circuit 1a is configured to write a valid level signal to the pull-up node PU in response to the control of the signal provided by the display signal input terminal INPUT1.

[0231] The display reset circuit 1b is connected to the display reset signal input terminal RST, the second power supply terminal, and the pull-up node PU. The display reset circuit 1b is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the display reset signal input terminal.

[0232] As an example, the display input circuit 1a includes the aforementioned ninth transistor M9, and the display reset circuit 1b includes the aforementioned tenth transistor M10.

[0233] In some embodiments, the shift register further includes at least one of the following: a pull-up noise reduction circuit 7 and a global reset circuit 6.

[0234] The pull-up noise reduction circuit 7 is connected to the second power supply terminal, the pull-up node PU, and the pull-down node PD. The pull-up noise reduction circuit 7 is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the effective level signal at the pull-down node PD.

[0235] The global reset circuit 6 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the pull-up node PU. The global reset circuit 6 is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the global reset signal input terminal T-RST.

[0236] In some embodiments, the pull-up noise reduction circuit 7 includes a fourteenth transistor M14; the control electrode of the fourteenth transistor M14 is connected to the pull-down node PD, the first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

[0237] In some embodiments, the global reset circuit 6 includes a seventh transistor M7; the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the pull-up node PU, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.

[0238] Figure 18This is a schematic diagram of another circuit structure of a shift register provided in an embodiment of this disclosure. Figure 19 for Figure 18 The diagram shows a timing diagram illustrating the operation of a shift register for display and sensor driving. Figure 18 and Figure 19 As shown, with Figure 17 The difference between the shift registers shown is that... Figure 18 The shift register shown also includes a sensing control circuit 11 and a sensing input circuit 12.

[0239] The sensing control circuit 11 is connected to the sensing control node H, the sensing signal input terminal INPUT2, and the random signal input terminal OE. The sensing control circuit 11 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE.

[0240] The sensing input circuit 12 is connected to the sensing control node H, the clock control signal input terminal CLKA, the sensing intermediate node N, and the pull-up node PU. The sensing input circuit 12 is configured to write an effective level signal to the sensing intermediate node N in response to the control of the effective level signal at the sensing control node H, and to form a path between the sensing intermediate node N and the pull-up node PU in response to the control of the effective level signal provided by the clock control signal input terminal CLKA.

[0241] In some embodiments, the sensing control circuit 11 includes a first transistor M1.

[0242] The control electrode of the first transistor M1 is connected to the random signal input terminal OE, the first electrode of the first transistor M1 is connected to the sensing signal input terminal INPUT2, and the second electrode of the first transistor M1 is connected to the sensing control node H.

[0243] In some embodiments, a holding capacitor C0 is configured at the sensing control node H; a first end of the holding capacitor C0 is connected to the sensing control node H, and a second end of the holding capacitor C0 is connected to a constant voltage supply terminal, such as a ground terminal or a power supply terminal. Figure 18 The example shown illustrates the case where the second terminal of the capacitor is grounded.

[0244] In some embodiments, the sensing input circuit 12 includes a second transistor M2 and a third transistor M3.

[0245] The control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA, and the second electrode of the second transistor M2 is connected to the sensing intermediate node N.

[0246] The control electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the sensing intermediate node N, and the second electrode of the third transistor M3 is connected to the pull-up node PU.

[0247] See Figure 19 As shown, the shift register includes the following processes during display driving and sensing driving: display driving process, sensing driving process, and global reset process s1. The display driving process includes: display input stage t1, display output stage t2, and display reset stage t3; the sensing driving process includes: sensing preparation stage p1, sensing input stage p2, sensing output stage p3, and sensing control reset stage p4.

[0248] for Figure 18 The operating states of each transistor in the shift register shown in the diagram at each stage can be referred to... Figure 19 The timing inference shown is obtained here, but the specific details are not described in detail here.

[0249] It should be noted that, in the embodiments of this disclosure, the order of the sensing control reset phase p4 and the global reset process s1 is not limited. For example, the sensing control reset phase p4 may be performed before the global reset process s1 (no corresponding figure is given), or it may be performed synchronously with the global reset process s1. Figure 13 As shown in the figure, it can also be located after the global reset process s1 (no corresponding figure is given). In the embodiments of this disclosure, it is only necessary to ensure that the sensing control reset stage p4 is located after the sensing input stage p2 and the global reset process s1 is located after the sensing output stage p3.

[0250] Figure 20 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 20 As shown, in some embodiments, the shift register further includes: a first voltage control circuit 14; the first voltage control circuit 14 is connected to a first power supply terminal, a pull-up node PU and a first voltage control node OFF1, and the first voltage control circuit 14 is configured to write the voltage provided by the first power supply terminal to the first voltage control node OFF1 in response to the control of the voltage at the pull-up node PU.

[0251] The shift register also includes at least one of the following: a first leakage protection circuit 15, a second leakage protection circuit 16, a third leakage protection circuit 17, and a display input leakage protection circuit 1a'.

[0252] The global reset circuit 6 is connected to the second power supply terminal through the first leakage protection circuit 15. The global reset circuit 6 and the first leakage protection circuit 15 are connected to the first leakage protection node Q1. The first leakage protection node Q1 is connected to the first voltage control node OFF1. The first leakage protection circuit 15 is connected to the global reset signal input terminal T-RST. The first leakage protection circuit 15 is configured to form a path between the first leakage protection node Q1 and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal T-RST, and to disconnect the circuit between the first leakage protection node Q1 and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal T-RST.

[0253] The display reset circuit 1b is connected to the second power supply terminal through the second leakage protection circuit 16. The display reset circuit 1b and the second leakage protection circuit 16 are connected to the second leakage protection node Q2. The second leakage protection node Q2 is connected to the first voltage control node OFF1. The second leakage protection circuit 16 is connected to the display reset signal input terminal RST. The second leakage protection circuit 16 is configured to form a path between the second leakage protection node Q2 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to disconnect the second leakage protection node Q2 and the second power supply terminal in response to the control of the invalid level signal provided by the display reset signal input terminal RST.

[0254] The pull-up noise reduction circuit 7 is connected to the second power supply terminal through the third leakage protection circuit 17. The pull-up noise reduction circuit 7 and the third leakage protection circuit 17 are connected to the third leakage protection node Q3. The third leakage protection node Q3 is connected to the first voltage control node OFF1. The third leakage protection circuit 17 is connected to the pull-down node PD. The third leakage protection circuit 17 is configured to form a path between the third leakage protection node Q3 and the second power supply terminal in response to the control of the effective level signal at the pull-down node PD, and to disconnect the circuit between the third leakage protection node Q3 and the second power supply terminal in response to the control of the ineffective level signal at the pull-down node PD.

[0255] The display input circuit 1a is connected to the pull-up node PU via the display input leakage protection circuit 1a'. The display input circuit 1a and the display input leakage protection circuit 1a' are connected to the display input leakage protection node XQ1. The display input leakage protection node XQ1 is connected to the first control voltage node OFF1 and the display signal input terminal INPUT1. The display input leakage protection circuit 1a' is configured to form a path between the display input leakage protection node XQ1 and the pull-up node PU in response to the control of the valid level signal provided by the display signal input terminal INPUT1, and to disconnect the circuit between the display input leakage protection node XQ1 and the pull-up node PU in response to the control of the invalid level signal provided by the display signal input terminal INPUT1.

[0256] In this embodiment of the present disclosure, by setting the first anti-leakage circuit 15, leakage current can be effectively prevented from occurring through the global reset circuit 6 by the voltage at the pull-up node PU; by setting the second anti-leakage circuit 16, leakage current can be effectively prevented from occurring through the display reset circuit 1b by the voltage at the pull-up node PU; by setting the third anti-leakage circuit 17, leakage current can be effectively prevented from occurring through the pull-up noise reduction circuit 7 by the pull-up node PU; and by setting the display input anti-leakage circuit 1a', leakage current can be effectively prevented from occurring through the display input circuit 1a by the pull-up node PU.

[0257] The accompanying drawings illustrate, for example, a shift register that includes a first leakage protection circuit 15, a second leakage protection circuit 16, a third leakage protection circuit 17, and a display input leakage protection circuit 1a'. This illustration is for illustrative purposes only.

[0258] In some embodiments, the shift register further includes a sensing input leakage protection circuit 12'; the sensing input circuit 12 is connected to the pull-up node PU through the sensing input leakage protection circuit 12', the sensing input circuit 12 and the sensing input leakage protection circuit 12' are connected to the sensing input leakage protection node SQ1, the sensing input leakage protection node SQ1 is connected to the first control voltage node OFF1, the sensing input leakage protection node SQ1 is connected to the clock control signal input terminal CLKA, and the sensing input leakage protection circuit 12' is configured to form a path between the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the valid level signal provided by the clock control signal input terminal CLKA, and to disconnect the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the invalid level signal provided by the clock control signal input terminal CLKA.

[0259] See Figure 20 As shown, in some embodiments, the first voltage control circuit 14 includes a twentieth transistor M20, the first leakage protection circuit 15 includes a twenty-first transistor M21, the second leakage protection circuit 16 includes a twenty-second transistor M22, the third leakage protection circuit 17 includes a twenty-third transistor M23, the display input leakage protection circuit 1a' includes a twenty-fourth transistor M24, and the sensing input leakage protection circuit 12' includes a twenty-fifth transistor M25.

[0260] The control electrode of the twentieth transistor M20 is connected to the pull-up node PU, the first electrode of the twentieth transistor M20 is connected to the first power supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0261] The control electrode of the twenty-first transistor M21 is connected to the global reset signal input terminal T-RST, the first electrode of the twenty-first transistor M21 is connected to the first leakage protection node Q1, and the second electrode of the twenty-second transistor M22 is connected to the second power supply terminal.

[0262] The control electrode of the 22nd transistor M22 is connected to the display reset signal input terminal RST, the first electrode of the 22nd transistor M22 is connected to the second leakage protection node Q2, and the second electrode of the 22nd transistor M22 is connected to the second power supply terminal.

[0263] The control electrode of the 23rd transistor M23 is connected to the pull-down node PD, the first electrode of the 23rd transistor M23 is connected to the third leakage protection node Q3, and the second electrode of the 23rd transistor M23 is connected to the second power supply terminal.

[0264] The control electrode of the 24th transistor M24 is connected to the display signal input terminal INPUT1, the first electrode of the 24th transistor M24 is connected to the display input leakage protection node XQ1, and the second electrode of the 24th transistor M24 is connected to the pull-up node PU.

[0265] Among them, the control electrode of the 25th transistor M25 is connected to the clock control signal input terminal CLKA, the first electrode of the 25th transistor M25 is connected to the sensing input leakage protection node SQ1, and the second electrode of the 25th transistor M25 is connected to the pull-up node PU.

[0266] Furthermore, in this embodiment, a sensing control leakage protection circuit 11' may also be provided. The sensing control circuit 11 is connected to the sensing control node H via the sensing control leakage protection circuit 11'. The sensing control leakage protection circuit 11' is connected to the sensing control leakage protection node GM. The sensing control leakage protection circuit 11' is also connected to the eighth power supply terminal, the sensing control node H, and the random signal input terminal. The sensing control leakage protection circuit 11' is configured to write the valid level signal provided by the eighth power supply terminal to the sensing control leakage protection node GM in response to the control of the valid level signal provided by the random signal input terminal OE. It is also configured to form a path between the sensing control leakage protection node GM and the sensing control node H in response to the control of the invalid level signal provided by the random signal input terminal OE, and to form an open circuit between the sensing control leakage protection node GM and the sensing control node H in response to the control of the invalid level signal provided by the random signal input terminal OE.

[0267] In some embodiments, the sensing control leakage protection circuit 11' includes a twenty-sixth transistor M26 and a twenty-seventh transistor M27.

[0268] The control electrode of the 26th transistor M26 is connected to the sensing control node H, the first electrode of the 26th transistor M26 is connected to the first power supply terminal, and the second electrode of the 26th transistor M26 is connected to the sensing control leakage protection node GM.

[0269] The control electrode of the 27th transistor M27 is connected to the random signal input terminal OE, the first electrode of the 27th transistor M27 is connected to the sensing control leakage protection node GM, and the second electrode of the 27th transistor M27 is connected to the sensing control node H.

[0270] In some embodiments, the shift register unit further includes at least one of a first pull-down noise reduction circuit 18 and a second pull-down noise reduction circuit 19.

[0271] The first pull-down noise reduction circuit 18 is connected to the pull-down node PD, the second power supply terminal, the sensing control node H, and the clock control signal input terminal CLKA. The first pull-down noise reduction circuit 18 is configured to write the ineffective level signal provided by the second power supply terminal to the pull-down node PD in response to the control of the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA, so as to perform noise reduction processing on the output voltage of the pull-down node PD.

[0272] The second pull-down noise reduction circuit 19 is connected to the pull-down node PD, the second power supply terminal, and the sensing signal input terminal INPUT2. The second pull-down noise reduction circuit 19 is configured to write the ineffective level signal provided by the second power supply terminal to the pull-down node PD in response to the control of the effective level signal provided by the sensing signal input terminal INPUT2, so as to perform noise reduction processing on the output voltage of the pull-down node PD.

[0273] In some embodiments, the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirtieth transistor M30, and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M30.

[0274] Among them, the control terminal of the twenty-ninth transistor M29 is connected to the clock control signal input terminal CLKA, the first terminal of the twenty-ninth transistor M29 is connected to the pull-down node PD, and the second terminal of the twenty-ninth transistor M29 is connected to the first terminal of the thirtieth transistor M30.

[0275] The control electrode of the thirtieth transistor M30 is connected to the sensing control node H, and the second electrode of the thirtieth transistor M30 is connected to the second power supply terminal.

[0276] The control electrode of the thirty-first transistor M30 is connected to the sensing signal input terminal INPUT2, the first electrode of the thirty-first transistor M30 is connected to the pull-down node PD, and the second electrode of the thirty-first transistor M30 is connected to the second power supply terminal.

[0277] Figure 21 This is a schematic diagram of another circuit structure of the shift register provided in an embodiment of this disclosure. For example... Figure 21As shown, in some embodiments, when a first voltage control circuit is provided in the shift register, the shift register may also include a second detection circuit 200; the second detection circuit 200 is connected to the first voltage control node OFF1, the third acquisition control terminal CL3, and the second signal detection line SGD', and is configured to acquire the voltage at the first voltage control node OFF1 in response to the signal provided by the third acquisition control terminal CL3, and output a third detection voltage corresponding to the voltage at the first voltage control node OFF1 to the second signal detection line SGD', so that the external first chip can adjust the voltage provided by the first power supply terminal according to the third detection voltage.

[0278] When the voltage at the pull-up node PU is high, the corresponding voltage is VPU_H. The voltage provided by the eighth power supply terminal is V8 ≥ VPU_H. At this time, the voltage at the first control node is VPU_H - Vth_M20, where Vth_M20 is the threshold voltage of the twentieth transistor M20 in the first control circuit. Therefore, by reading the voltage at the first control node, the threshold voltage drift of the twentieth transistor M20 can be obtained. Based on the threshold voltage drift of the twentieth transistor M20, the voltage provided by the first power supply terminal can be adjusted as needed. The specific adjustment method can be pre-designed according to actual needs, and will not be elaborated here.

[0279] In some embodiments, the second detection circuit 200 includes: a fifty-seventh transistor M57; the control electrode of the fifty-seventh transistor M57 is connected to the third acquisition control terminal CL3, the first electrode of the fifty-seventh transistor M57 is connected to the first control voltage node, and the second electrode of the fifty-seventh transistor M57 is connected to the second signal detection line SGD'.

[0280] To effectively reduce wiring, in some embodiments, the first signal detection line SGD is multiplexed as the second signal detection line SGD'. That is, the first signal detection line SGD can receive signals provided by the first detection circuit 100 and the second detection circuit 200 through time-division multiplexing.

[0281] Of course, in some embodiments, the shift register may include a second detection circuit 200 but not the first detection circuit 100 described above, and this situation should also fall within the protection scope of this disclosure.

[0282] It should be noted that in the above embodiments, different parts of different embodiments can be combined with each other, and the new technical solutions obtained by combining the embodiments should also fall within the protection scope of this disclosure.

[0283] Based on the same inventive concept, this disclosure also provides a gate driving circuit, which includes a plurality of cascaded shift registers, wherein at least one shift register is a shift register provided in the previous embodiment. For details, please refer to the content in the previous embodiment, which will not be repeated here.

[0284] Figure 22 This is a schematic diagram of a circuit structure for a gate drive circuit in a disclosed embodiment. For example... Figure 22 As shown, the gate drive circuit includes multiple shift registers, specifically including: multiple effective shift registers 300b that provide drive signals to the gate lines located in the display area, and at least one dummy shift register other than the effective shift registers 300b; wherein, at least one dummy shift register 300a adopts the shift register provided in the previous embodiment; that is, at least one dummy shift register 300a is provided with the first detection circuit 100 described above.

[0285] In practical applications, the shift registers located in the first two or last two stages of the gate drive circuit are generally virtual shift registers 300a, and the shift registers located in the third to third-to-last stages are effective shift registers 300b.

[0286] In this disclosure, the first detection circuit 100 can be configured in any virtual shift register 300a, or it can be configured in any virtual shift register 300a (with a first signal detection line SGD). This disclosure does not impose any limitations on this.

[0287] Based on the same inventive concept, this disclosure also provides a display device. Figure 23 This is a schematic diagram of the structure of a display device in a disclosed embodiment. Figure 24 This is a structural block diagram of the first chip in an embodiment of this disclosure. For example... Figure 23 and Figure 24 As shown, the display device 500 includes a display area 500a and a non-display area 500b surrounding the display area 500a. A gate driving circuit is disposed in the non-display area 500b. The gate driving circuit adopts the gate driving circuit provided in the previous embodiment. For a detailed description, please refer to the content of the previous embodiment, which will not be repeated here.

[0288] In some embodiments, the display device 500 further includes: a plurality of pixel units (PIX) arranged in an array and a plurality of signal readout lines. See again Figure 1As shown, in some embodiments, the pixel unit PIX includes a pixel driving circuit with an external threshold compensation function. The pixel driving circuit includes a driving transistor DTFT and a sensing switch circuit STFT. The sensing switch circuit STFT is connected to the second electrode of the driving transistor DTFT and the signal readout line RL. The sensing switch circuit STFT is configured to read the electrical signal at the second electrode of the driving transistor DTFT to the corresponding signal readout line RL, so that an external second chip (not shown) can perform external threshold compensation on the driving transistor DTFT based on the electrical signal at the second electrode of the driving transistor DTFT.

[0289] In some embodiments, at least one signal readout line RL is multiplexed as a first signal detection line SGD. This design can effectively reduce the number of wires in the display device and simplify the product structure.

[0290] In some embodiments, the second chip and the first chip 800 are the same chip.

[0291] In some embodiments, the number of shift registers in which the first detection circuit 100 is provided in the gate driving circuit is one; the signal readout line RL closest to the gate driving circuit in the display device is multiplexed as the first signal detection line SGD.

[0292] In some embodiments, the first chip 800 is further configured to control the voltage supplied by the third power supply terminal to switch from an effective level voltage to an ineffective level voltage in response to the display device switching to a power-off state. When the display device switches to a power-off state, the voltage supplied by the third power supply terminal can be controlled to switch from an effective level voltage to an ineffective level voltage, so as to eliminate the forward stress of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2, which helps to improve the forward drift problem of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2.

[0293] In some embodiments, the first chip 800 includes: an analog-to-digital converter module 801 and a voltage adjustment module 802; the analog-to-digital converter module 801 is connected to the first signal detection line SGD, and the analog-to-digital converter module 801 is configured to perform analog-to-digital conversion processing on the signal obtained from the first signal detection line SGD to obtain the corresponding digital voltage; the voltage adjustment module 802 is connected to the analog-to-digital converter module 801, and the voltage adjustment module 802 is configured to obtain the effective level voltage to be provided to the third power supply terminal according to a preset adjustment algorithm and the digital voltage provided by the analog-to-digital converter module 801.

[0294] In some embodiments, the first chip 800 further includes a power supply module 803; the power supply module 803 is connected to the voltage adjustment module, and the power supply module 803 is configured to output a corresponding effective level voltage to the third power supply terminal according to the effective level voltage to be provided to the third power supply terminal as determined by the voltage adjustment module 802.

[0295] In some embodiments, a switching circuit SW is provided between the first chip 800 and the first signal detection line SGD.

[0296] In some embodiments, the first signal detection line SGD is further configured with an eleventh capacitor C11; the first end of the eleventh capacitor C11 is connected to the first detection line SGD, and the second end of the eleventh capacitor C11 is connected to the ground terminal.

[0297] It should be noted that the above-described case, in which the signal readout line RL closest to the gate drive circuit in the display device is multiplexed as the first signal detection line SGD, is merely an optional embodiment of this disclosure and does not limit the disclosed technical solution. In this disclosure, one or more signal readout lines RL can also be randomly selected and multiplexed as the first signal detection line SGD, or the first signal detection line SGD can be added separately in the display device; all of these cases should fall within the protection scope of this disclosure.

[0298] The display device provided in this disclosure can be any product or component with display function, such as an OLED display panel, wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0299] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, wherein, include: The system includes a display input reset circuit, an inverting circuit, at least one output circuit, and a first detection circuit. The display input reset circuit, the inverting circuit, and the output circuit are connected to a pull-up node, and the inverting circuit and the output circuit are connected to a pull-down node. The display input reset circuit is connected to the display signal input terminal, the reset signal terminal, and the second power supply terminal. It is configured to write an effective level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal, and to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the reset signal terminal. The inverting circuit is connected to the second power supply terminal and the third power supply terminal, and is configured to invert the voltage of the pull-up node in response to the voltage provided by the second power supply terminal and the effective level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node. The output circuit is connected to the pull-up node, the pull-down node, the corresponding signal output terminal, the corresponding output clock signal terminal, and the corresponding fourth power supply terminal. It is configured to write the signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node, and to write the voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node. The first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line. It is configured to acquire the voltage at the signal acquisition point in response to the signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line, so that an external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal acquisition point includes at least one of the pull-down node and the signal output terminal. The first detection circuit includes at least one of a first detection sub-circuit and a second detection sub-circuit, and the acquisition control terminal includes either a first acquisition control terminal or a second acquisition control terminal. The first detection sub-circuit is connected to the pull-down node, the first acquisition control terminal, and the first signal detection line. The first detection sub-circuit is configured to, in response to the control of the signal provided by the first acquisition control terminal, acquire the voltage at the pull-down node and output a first detection voltage corresponding to the voltage at the pull-down node to the first signal detection line. The second detection sub-circuit is connected to the signal output terminal, the second acquisition control terminal, and the first signal detection line. The second detection sub-circuit is configured to, in response to the control of the signal provided by the second acquisition control terminal, acquire the voltage at the pull-down node and output a second detection voltage corresponding to the voltage at the signal output terminal to the first signal detection line.

2. The shift register according to claim 1, wherein, The first detection sub-circuit includes: the fifty-first transistor; The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

3. The shift register according to claim 1, wherein, The first detection sub-circuit includes: the fifty-first transistor, the fifty-second transistor, the fifty-third transistor, and the fifty-fourth transistor; The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-first transistor is connected to the first signal detection line. The control electrode of the fifty-second transistor is connected to the pull-down node, and the first electrode of the fifty-second transistor is connected to the second electrode of the fifty-third transistor and the first electrode of the fifty-fourth transistor; The control electrode of the fifty-third transistor is connected to the control terminal of the first switch, and the first electrode of the fifty-third transistor is connected to the control electrode of the fifty-second transistor. The control electrode of the fifty-fourth transistor is connected to the control terminal of the second switch, and the second electrode of the fifty-fourth transistor is connected to the power supply terminal of the seventh power supply.

4. The shift register according to claim 3, wherein, The first detection sub-circuit also includes: the fifty-fifth transistor; The second terminal of the fifty-second transistor is connected to the first terminal of the fifty-first transistor through the fifty-fifth transistor. The control terminal of the fifty-fifth transistor and the first terminal of the fifty-fifth transistor are both connected to the second terminal of the fifty-second transistor. The second terminal of the fifty-fifth transistor is connected to the first terminal of the fifty-first transistor. Alternatively, the second terminal of the fifty-first transistor is connected to the first signal detection line through the fifty-fifth transistor, and both the control terminal and the first terminal of the fifty-fifth transistor are connected to the second terminal of the fifty-first transistor, and the second terminal of the fifty-fifth transistor is connected to the first signal detection line.

5. The shift register according to claim 4, wherein, The number of output circuits is m, the number of second detection sub-circuits is n, the number of second acquisition control terminals is n, and the second detection sub-circuits and the second acquisition control terminals correspond one-to-one. m and n are both positive integers and m≥n. Different second detection sub-circuits correspond to different output circuits, and the second detection sub-circuit is connected to the signal output terminal of the corresponding output circuit.

6. The shift register according to claim 5, wherein, The second detection sub-circuit includes: the fifty-sixth transistor; The control electrode of the fifty-sixth transistor is connected to the corresponding second acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

7. The shift register according to claim 6, wherein, Also includes: Step-down circuit; The first detection circuit is connected to the first signal detection line through the step-down circuit. The step-down circuit is configured to step down the detection voltage output by the first detection circuit and output the step-down detection voltage to the first signal detection line.

8. The shift register according to claim 7, wherein, The step-down circuit includes: a first resistor and a second resistor; The first end of the first resistor is connected to the first detection circuit, the second end of the first resistor is connected to the first signal detection line, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the ground terminal.

9. The shift register according to claim 8, wherein, The display input reset circuit includes: The display input circuit is connected to the display signal input terminal and the pull-up node, and is configured to write a valid level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal; The display reset circuit is connected to the display reset signal input terminal, the second power supply terminal and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the display reset signal input terminal. The shift register further includes: a first voltage control circuit; The first voltage control circuit is connected to the first power supply terminal, the pull-up node, and the first voltage control node. The first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node. The shift register further includes at least one of a second leakage protection circuit and a display input leakage protection circuit; The display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal. The display input circuit is connected to the pull-up node via the display input leakage protection circuit. The display input circuit and the display input leakage protection circuit are connected to the display input leakage protection node. The display input leakage protection node is connected to the first voltage control node. The display input leakage protection node is connected to the display signal input terminal. The display input leakage protection circuit is configured to form a path between the display input leakage protection node and the pull-up node in response to the control of an effective level signal provided by the display signal input terminal, and to disconnect the circuit between the display input leakage protection node and the pull-up node in response to the control of an ineffective level signal provided by the display signal input terminal.

10. The shift register according to claim 9, wherein, The shift register further includes at least one of the following: a pull-up noise reduction circuit and a global reset circuit; The pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node, and the pull-down node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the effective level signal at the pull-down node. The global reset circuit is connected to the global reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the global reset signal input terminal.

11. The shift register according to claim 10, wherein, Also includes: First voltage control circuit; The first voltage control circuit is connected to the first power supply terminal, the pull-up node, and the first voltage control node. The first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node. The shift register circuit further includes at least one of a first leakage protection circuit and a third leakage protection circuit; The global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal. The pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the pull-down node.

12. The shift register according to claim 11, wherein, Also includes: The second detection circuit is connected to the first voltage control node, the third acquisition control terminal, and the second signal detection line. It is configured to acquire the voltage at the first voltage control node in response to the signal provided by the third acquisition control terminal and output a third detection voltage corresponding to the voltage at the first voltage control node to the second signal detection line, so that the external chip can adjust the voltage provided by the first power supply terminal according to the third detection voltage.

13. The shift register according to claim 12, wherein, The second detection circuit includes: a fifty-seventh transistor; The control electrode of the fifty-seventh transistor is connected to the third acquisition control terminal, the first electrode of the fifty-seventh transistor is connected to the first voltage control node, and the second electrode of the fifty-seventh transistor is connected to the second signal detection line.

14. The shift register according to claim 13, wherein, The first signal detection line is multiplexed as the second signal detection line.

15. The shift register according to claim 14, wherein, The inverting circuit includes: the thirty-seventh transistor, the thirty-eighth transistor, the thirty-ninth transistor, and the fortieth transistor; The control electrode of the 37th transistor is connected to the third power supply terminal, the first electrode of the 37th transistor is connected to the control electrode of the 37th transistor, and the second electrode of the 37th transistor is connected to the control electrode of the 38th transistor. The control electrode of the 38th transistor is connected to the first electrode of the 40th transistor, the first electrode of the 38th transistor is connected to the third power supply terminal, and the second electrode of the 38th transistor is connected to the pull-down node. The control terminal of the 39th transistor is connected to the pull-up node, the first terminal of the 39th transistor is connected to the pull-down node, and the second terminal of the 39th transistor is connected to the fifth power supply terminal or the pull-down node. The control terminal of the 40th transistor is connected to the pull-up node, and the second terminal of the 40th transistor is connected to the second power supply terminal.

16. The shift register according to claim 15, wherein, The inverting circuit further includes: a forty-first transistor, wherein the second terminal of the thirty-seventh transistor is connected to the control terminal of the thirty-eighth transistor through the forty-first transistor; The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

17. The shift register according to claim 16, wherein, The inverting circuit includes: a twelfth transistor and a thirteenth transistor; The control electrode of the twelfth transistor is connected to the third power supply terminal, the first electrode of the twelfth transistor is connected to the control electrode of the twelfth transistor, and the second electrode of the twelfth transistor is connected to the pull-down node. The control terminal of the thirteenth transistor is connected to the pull-up node, the first terminal of the thirteenth transistor is connected to the pull-down node, and the second terminal of the thirteenth transistor is connected to the second power supply terminal.

18. The shift register according to claim 17, wherein, Also includes: A sensing control circuit is connected to a sensing control node, a sensing signal input terminal, and a random signal input terminal. The sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the signal provided by the random signal input terminal. A sensing input circuit, connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node, and the pull-up node, is configured to write an effective level signal to the sensing intermediate node in response to the control of an effective level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of a signal provided by the clock control signal input terminal.

19. A gate driving circuit, wherein, include: A plurality of cascaded shift registers, wherein at least one of the shift registers is a shift register as described in any one of claims 1 to 18.

20. The gate drive circuit according to claim 19, wherein, The cascaded multiple shift registers include: multiple active shift registers that provide drive signals to the grid lines located in the display area, and at least one virtual shift register other than the active shift registers; At least one of the virtual shift registers is a shift register as described in any one of claims 1 to 15.

21. A display device, wherein, include: A display area and a non-display area surrounding the display area, wherein the non-display area is provided with a gate driving circuit as described in claim 19 or 20.

22. The display device according to claim 21, wherein, It also includes: multiple pixel units arranged in an array and multiple signal readout lines, wherein the pixel unit includes: a pixel driving circuit with external threshold compensation function, and the pixel driving circuit includes: a driving transistor and a sensing switch circuit; The sensing switch circuit is connected to the second electrode of the driving transistor and the signal reading line. The sensing switch circuit is configured to read the electrical signal at the second electrode of the driving transistor to the corresponding signal reading line, so that the external second chip can perform external threshold compensation on the driving transistor based on the electrical signal at the second electrode of the driving transistor. At least one of the signal readout lines is multiplexed as the first signal detection line.

23. The display device according to claim 22, wherein, The second chip is the same chip as the first chip.

24. The display device according to claim 23, wherein, The number of shift registers with the first detection circuit in the gate drive circuit is 1; The signal readout line closest to the gate drive circuit in the display device is multiplexed as the first signal detection line.

25. The display device according to claim 24, wherein, The first chip is also configured to control the voltage supplied by the third power supply terminal to switch from an effective level voltage to an ineffective level voltage in response to the display device switching to a power-off state.

26. The display device according to claim 25, wherein, The first chip includes: an analog-to-digital conversion module and a voltage regulation module; The analog-to-digital conversion module is connected to the first signal detection line and is configured to perform analog-to-digital conversion processing on the signal obtained from the first signal detection line to obtain the corresponding digital voltage. The voltage adjustment module is connected to the analog-to-digital conversion module and is configured to obtain the effective level voltage to be provided to the third power supply terminal based on a preset adjustment algorithm and the digital voltage provided by the analog-to-digital conversion module.

27. The display device according to claim 26, wherein, The first chip also includes: The power supply module is connected to the voltage adjustment module and is configured to output a corresponding effective voltage level to the third power supply terminal according to the effective voltage level determined by the voltage adjustment module.

28. The display device according to claim 27, wherein, A switching circuit is provided between the first chip and the first signal detection line.

29. The display device according to claim 28, wherein, The first signal detection line is also equipped with an eleventh capacitor; The first terminal of the eleventh capacitor is connected to the first signal detection line, and the second terminal of the eleventh capacitor is connected to the ground terminal.

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